Electrical connection substrate, chip packaging structure, and electronic device

Abstract

Embodiments of the present application relate to the technical field of chip packaging, and provide an electrical connection substrate, a chip packaging structure, and an electronic device, for use in reducing the probability of trace breakage within an electrical connection substrate due to inward propagation of cracks in the substrate. In the electrical connection substrate, a corresponding anti-pad is provided in a first surface metal layer around a first pad, and a corresponding anti-pad is provided around the vertical projection of the first pad on any first intermediate metal layer. A floating metal pattern is provided within the anti-pad in at least one first intermediate metal layer, and there is no metal connection between the floating metal pattern and a first via, nor between the floating metal pattern and the metal portion of the first intermediate metal layer other than the floating metal pattern. The floating metal pattern reduces the probabilities of formation and inward propagation of cracks in the electrical connection substrate, and is beneficial to ensuring the signal integrity and stability of high-speed signal links during high-speed signal transmission.

Description

An electrical connection substrate, a chip packaging structure, and an electronic device.

[0001] This application claims priority to Chinese Patent Application No. 202410817418.5, filed with the State Intellectual Property Office of China on June 21, 2024, entitled "An Electrical Connection Substrate, Chip Packaging Structure, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of chip packaging technology, and in particular to an electrical connection substrate, a chip packaging structure, and an electronic device. Background Technology

[0003] In the design of high-speed circuits in the field of chip packaging, as wiring density and signal transmission rate continue to increase, the requirements for signal integrity are becoming increasingly stringent. However, during temperature cycling reliability testing, chip packages are subject to stress mismatch and deformation, which can cause the substrate to crack. The propagation of these cracks can lead to the breakage of signal lines inside the substrate, resulting in the failure of the entire chip package structure. Summary of the Invention

[0004] This application provides an electrical connection substrate, a chip packaging structure, and an electronic device to reduce the probability of cracks in the electrical connection substrate propagating inward and causing internal wiring breakage.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] One aspect of this application provides an electrical connection substrate, which includes multiple metal layers and a first via. The multiple metal layers include a first surface metal layer, at least one first intermediate metal layer, a second intermediate metal layer, and a second surface metal layer stacked sequentially. The second intermediate metal layer includes metal traces. A corresponding dielectric layer is provided between adjacent metal layers in the multiple metal layers. Furthermore, the first via penetrates the first surface metal layer and at least one first intermediate metal layer, as well as the dielectric layer between the first surface metal layer and the second intermediate metal layer. A first end of the first via is electrically connected to the metal traces. The first surface metal layer includes a first pad, which is electrically connected to a second end of the first via. A corresponding anti-pad is provided around the first pad in the first surface metal layer, and a corresponding anti-pad is also provided around the first pad's vertical projection onto any one of the at least one first intermediate metal layers. The at least one first intermediate metal layer may include a floating metal pattern, and the floating metal pattern is located within the anti-pad in the first intermediate metal layer. A portion of an anti-pad is spaced between the metal portion other than the floating metal pattern in the first intermediate metal layer with the floating metal pattern, and between the floating metal pattern and the first via.

[0007] In summary, the first end of the first via is electrically connected to the metal trace, and the second end of the first via is electrically connected to the first pad, thus allowing the first pad to be electrically connected to the metal trace through the first via. In this configuration, when two electronic components are electrically connected to the metal trace and the first pad respectively, the two electronic components can transmit electrical signals through the electrical connection to the substrate. Furthermore, the anti-pads in the first surface metal layer are arranged around the first pad, thereby isolating the first pad from the rest of the metal in the first surface metal layer, preventing short circuits. Additionally, the anti-pads in the first intermediate metal layer can isolate the first via penetrating the first intermediate metal layer from the first intermediate metal layer, thus preventing short circuits in the first via.

[0008] Based on this, during the temperature cycling reliability test, the aforementioned electrical connection substrate is affected by stress mismatch. The metal material around the anti-pad stretches the anti-pad, resulting in significant stress at the interface between the anti-pad and the metal material (e.g., the interface between the anti-pad and the first pad, or the interface between the anti-pad and the first surface metal layer). Therefore, since the floating metal pattern is disposed within the anti-pad in the first surface metal layer, and the metal portion of the first intermediate metal layer containing the floating metal pattern is isolated from the floating metal pattern and the first via through the anti-pad of the first intermediate metal layer, the floating metal pattern can form a stress relief channel with the metal material on both sides of the anti-pad, such as the metal portion of the first intermediate metal layer excluding the floating metal pattern and the first pad. This stress relief channel can distribute the stress between the anti-pad and the first pad, and between the metal portion of the first surface metal layer excluding the floating metal pattern, thereby reducing the probability of cracks forming in the electrical connection substrate and the inward propagation of cracks. Furthermore, the aforementioned floating metal pattern, as a rigid structure, can block the extension trend of cracks, thereby reducing the inward propagation of cracks.

[0009] Furthermore, the floating metal pattern is disposed within an anti-pad in at least one first intermediate metal layer, and a portion of the anti-pad is spaced between the floating metal pattern and the metal portion of the first intermediate metal layer other than the floating metal pattern. This ensures that there is no electrical connection between the floating metal pattern, the metal portion of the first intermediate metal layer other than the floating metal pattern, and the first via, thereby reducing the coupling between the first pad and the floating metal pattern, or between the first pad and the first intermediate metal layer, and thus reducing the probability of impedance discontinuity caused by impedance drop. When the aforementioned electrical connection substrate transmits high-speed signals, it helps to ensure the signal integrity and stability of the high-speed signal link and reduces the impact on the characteristics of the high-speed signal link. Moreover, the anti-pad is spaced between the floating metal pattern and the first via, thus preventing short circuits in the first via.

[0010] In one optional embodiment, the dielectric layer is a first dielectric layer. The vertical projection of the floating metal pattern onto the first dielectric layer overlaps with the edge of the vertical projection of the first pad onto the first dielectric layer. In this case, the floating metal pattern can overlap with the edge of the first pad. Thus, when the metal material around the anti-pad stretches the anti-pad, causing the aforementioned crack to appear at the interface between the anti-pad and the first pad (e.g., the edge of the first pad), the floating metal pattern overlapping with the edge of the first pad is more likely to prevent the crack from further propagating into the interior of the electrical connection substrate.

[0011] In one optional embodiment, the dielectric layer is a first dielectric layer. The vertical projection of the floating metal pattern onto the first dielectric layer overlaps with the edge of the first surface metal layer (excluding the first pad) facing the first via, where the vertical projection of the metal portion onto the first dielectric layer is directed. In this case, the position of the floating metal pattern can overlap with the position of the edge of the first surface metal layer (excluding the first pad) facing the first via. Thus, when the metal material around the anti-pad stretches the anti-pad, causing the aforementioned crack to appear at the interface between the anti-pad and the metal portion of the first surface metal layer (excluding the first pad), the floating metal pattern overlapping with the edge of the metal portion of the first surface metal layer (excluding the first pad) more easily prevents the crack from further propagating into the interior of the electrical connection substrate.

[0012] In one optional implementation, the dielectric layer is a first dielectric layer. The vertical projection of the floating metal pattern onto the first dielectric layer does not overlap with the vertical projection of the metal trace onto the first dielectric layer. This reduces the coupling between the metal trace and the floating metal pattern, thereby reducing the impact on the impedance continuity of the passive link.

[0013] In one optional embodiment, the floating metal pattern includes a first metal ring. The vertical projection of the first metal ring onto the first dielectric layer is arranged around the circumference of the vertical projection of the first pad onto the first dielectric layer. A notch is formed on the first metal ring, penetrating both the inner and outer ring surfaces. The vertical projection of the metal trace onto the first dielectric layer lies within the range of the vertical projection of the notch onto the first dielectric layer. In this case, on the one hand, the location of the notch in the first metal ring overlaps with the location of the metal trace, thereby reducing the coupling between the first metal ring and the metal trace, and thus reducing the impact on the impedance continuity of the passive link. On the other hand, the arrangement of the first metal ring around the first pad increases the probability that the first metal ring is located on the crack propagation path.

[0014] In one optional embodiment, the dielectric layer is a first dielectric layer. At least one floating metal pattern includes a plurality of spaced-apart floating metal blocks. The vertical projections of these floating metal blocks onto the first dielectric layer are arranged in a ring around the vertical projection of the first pad onto the first dielectric layer. Based on this, since the plurality of floating metal blocks in the aforementioned floating metal pattern can be spaced around the first pad, the probability of the floating metal blocks being located on the crack propagation path can be increased, thereby reducing the probability of crack propagation in different directions and achieving the purpose of reducing crack propagation into the electrical connection substrate. Furthermore, the plurality of floating metal blocks are disposed co-layered with the same first intermediate metal layer. In this way, the plurality of co-layered floating metal blocks can be formed in a single photolithography process, thereby simplifying the fabrication process of the floating metal pattern.

[0015] In one optional embodiment, the floating metal pattern includes adjacent first floating metal blocks and second floating metal blocks. The vertical projection of the metal trace on the first dielectric layer lies between the vertical projections of the first floating metal block and the second floating metal block on the first dielectric layer, thereby ensuring that the positions of the metal trace and the first and second floating metal blocks in the floating metal pattern do not overlap, thus reducing the impact on the impedance continuity of the passive link.

[0016] In one optional embodiment, the dielectric layer is a first dielectric layer. The multilayer metal layer includes at least two first intermediate metal layers. The floating metal pattern of the at least two first intermediate metal layers each includes at least one floating metal block. In this way, the coupling between floating metal blocks arranged in different layers in the floating metal pattern is small, thereby reducing the impact on the impedance continuity on the passive link.

[0017] In one optional embodiment, the vertical projections of multiple floating metal blocks on different layers onto the first dielectric layer are arranged in a ring around the first vertical projection disk soldered onto the first dielectric layer. This reduces the coupling between the multiple floating metal blocks on different layers, thereby minimizing the impact on impedance continuity in the passive link. Furthermore, the multiple floating metal blocks on different layers can be arranged around the first pad, increasing the probability that the floating metal blocks are located along the crack propagation path, thus reducing the probability of crack propagation in different directions and ultimately reducing crack propagation into the electrical connection substrate.

[0018] In one optional embodiment, two adjacent floating metal blocks on different layers are designated as a third floating metal block and a fourth floating metal block, respectively. The vertical projections of the third and fourth floating metal blocks on the first dielectric layer at least partially overlap or are spliced ​​together. In this case, since the third and fourth floating metal blocks are respectively disposed on the same layer as different first intermediate metal layers, the coupling between the third and fourth floating metal blocks can be reduced, thereby reducing the impact on the impedance continuity of the passive link. Furthermore, since the vertical projections of the third and fourth floating metal blocks on the first dielectric layer at least partially overlap or are spliced ​​together, the probability that at least one of the third and fourth floating metal blocks is located on the crack propagation path is increased, thereby reducing the propagation of the crack into the electrical connection substrate.

[0019] In one optional embodiment, the vertical projections of the third and fourth floating metal blocks on the first dielectric layer completely overlap, thereby blocking the crack propagation at the point where the third and fourth floating metal blocks completely overlap, thus improving the effect of preventing further crack propagation. The technical effects of different layers of the third and fourth floating metal blocks are the same as described above, and will not be repeated here.

[0020] In one optional embodiment, the electrical connection substrate further includes a second via. The second via penetrates the metal layer and dielectric layer between the third and fourth floating metal blocks. A first end of the second via is connected to the third floating metal block, and a second end of the second via is connected to the fourth floating metal block. The vertical projection of the second via onto the first dielectric layer overlaps with the vertical projections of the third and fourth floating metal blocks onto the first dielectric layer, respectively. In this case, the overlapping third and fourth floating metal blocks can be connected together through the second via, thereby reducing the movement of at least one of the floating metal blocks relative to the dielectric layer during deformation of the electrical connection substrate, increasing the structural strength of the electrical connection substrate. This reduces coupling with other metal structures caused by the movement of the floating metal blocks, thus minimizing the impact on the impedance continuity of the passive link.

[0021] In one optional implementation, two adjacent floating metal blocks on different layers are designated as a third floating metal block and a fourth floating metal block, respectively. The vertical projection of the metal trace on the first dielectric layer lies between the vertical projections of the third floating metal block and the fourth floating metal block on the first dielectric layer, thereby reducing the impact on the impedance continuity of the passive link.

[0022] In one optional embodiment, the vertical projection of the floating metal block onto the first dielectric layer is fan-shaped. The fan shape has a first arc edge and a second arc edge. The first arc edge faces away from the first via, and the second arc edge faces the first via. The arc length of the first arc edge is greater than the arc length of the second arc edge. In this case, multiple fan-shaped floating metal blocks are more easily arranged around the first pad, making the arrangement of the multiple floating metal blocks more compact, which helps increase the probability that the floating metal blocks are located on the crack propagation path.

[0023] In one alternative embodiment, the dielectric layer is a first dielectric layer. The floating metal pattern includes a second metal ring, the vertical projection of which is arranged around the vertical projection of the first pad on the first dielectric layer.

[0024] In one optional embodiment, at least one first intermediate metal layer includes a lower first intermediate metal layer and an upper first intermediate metal layer stacked together, with the upper first intermediate metal layer located on the side of the lower first intermediate metal layer facing away from the first surface metal layer. No metal layer is disposed between the lower intermediate metal layer and the first surface metal layer, or between the lower intermediate metal layer and the upper intermediate metal layer. At least a portion of the floating metal pattern is disposed on the same layer as the upper intermediate metal layer. Therefore, when at least the upper intermediate metal layer includes the aforementioned floating metal pattern, the floating metal pattern can be separated from the first surface metal layer by a metal layer, namely the lower first intermediate metal layer. This reduces the distance between the floating metal pattern and the first pad, thereby minimizing the impact on impedance continuity in the passive link, improving signal quality, and forming a stress-relieving channel with strong stress-sharing capabilities.

[0025] In one optional embodiment, the electrical connection substrate is a packaging substrate, a circuit board, or a redistribution layer. The redistribution layer in the chip can be electrically connected to the bare chip. The packaging substrate is electrically connected to the chip located on the packaging substrate. The circuit board is electrically connected to the chip through the packaging substrate. Therefore, any one of the above-mentioned redistribution layer, packaging substrate, or circuit board can serve as an electrical connection substrate capable of being electrically connected to other electronic components to achieve signal transmission.

[0026] Another aspect of this application provides a chip packaging structure, including a chip and any of the electrical connection substrates described above. The electrical connection substrate is a packaging substrate, and the chip is disposed on the electrical connection substrate. The above-described chip packaging structure has the same technical effects as the electrical connection substrates provided in the foregoing embodiments, and will not be repeated here.

[0027] In one optional embodiment, the chip package structure further includes a first interconnect structure. The first interconnect structure is disposed on one side of the electrical connection substrate where a first pad is located, and the first interconnect structure is electrically connected to the first pad. The chip is disposed on the side of the electrical connection substrate opposite to the first interconnect structure, and the chip is electrically connected to a metal trace of the electrical connection substrate. In this case, the chip and the first pad are located on opposite sides of the electrical connection substrate.

[0028] In one alternative embodiment, the chip is disposed on one side of the electrical connection substrate where the first pad is located, and the chip is electrically connected to the first pad. In this case, the chip and the first pad are located on the same side of the electrical connection substrate.

[0029] Another aspect of this application provides an electronic device, including a circuit board and any of the chip packaging structures described above. The chip packaging structure is disposed on the circuit board and electrically connected to the circuit board. The above-described electronic device has the same technical effects as the chip packaging substrate provided in the foregoing embodiments, and will not be repeated here. Attached Figure Description

[0030] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0031] Figure 2 is a schematic diagram of an electrical connection substrate provided in an embodiment of this application;

[0032] Figure 3 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0033] Figure 4 is a cross-sectional view obtained by cutting along the dashed line O1-O2 in Figure 3;

[0034] Figure 5 is another sectional view obtained by cutting along the dashed line O1-O2 in Figure 3;

[0035] Figure 6 is a schematic diagram of an electrical connection substrate provided by related technologies;

[0036] Figure 7 is a schematic diagram of another electrical connection substrate provided by the related technology;

[0037] Figure 8 is another sectional view obtained by cutting along the dashed line O1-O2 in Figure 3;

[0038] Figure 9 is a schematic diagram of a connection structure between an electrical connection substrate, a chip, and a circuit board provided in an embodiment of this application;

[0039] Figure 10 is a schematic diagram of a connection structure between an electrical connection substrate and a chip provided in an embodiment of this application;

[0040] Figure 11 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0041] Figure 12 is a partial top view obtained along direction C in Figure 11;

[0042] Figure 13 is another partial top view obtained along direction C in Figure 11;

[0043] Figure 14 shows another partial top view obtained along direction C in Figure 11;

[0044] Figure 15 is another partial top view obtained along direction C in Figure 11;

[0045] Figure 16 is another partial top view obtained along direction C in Figure 11;

[0046] Figure 17 is a schematic diagram of the insertion loss of multiple electrical connection substrates transmitting signals below 30 GHz;

[0047] Figure 18 is a schematic diagram of the return loss when transmitting signals below 30 GHz on multiple electrical connection substrates.

[0048] Figure 19 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0049] Figure 20 is a partial top view obtained along direction E in Figure 19;

[0050] Figure 21 is another partial top view obtained along direction C in Figure 11;

[0051] Figure 22 is another partial top view obtained along direction C in Figure 11;

[0052] Figure 23 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0053] Figure 24 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0054] Figure 25 is a partial top view obtained along direction D in Figure 24;

[0055] Figure 26 is a schematic diagram of another electrical connection substrate provided in an embodiment of this application;

[0056] Figure 27 is a partial structural schematic diagram of the electrical connection substrate provided in an embodiment of this application.

[0057] Reference numerals: 01-Electronic device; 10-Chip package structure; 101-Chip; 1011-Bare chip; 1012-Redistribution layer; 102-Packaging substrate; 103-First interconnect structure; 11-Circuit board; 20-Electrically connected substrate; 201-Metal layer; 202-Dielectric layer; 203-First via; 204-First pad; 205-Anti-pad; 206-Floating metal pattern; 2011-First surface metal layer; 2012-First intermediate metal layer; 2013-Second intermediate metal layer; 2 0131 - Metal trace; 2014 - Second surface metal layer; 1101 - PCB trace; 100 - Crack; 212 - Core layer via; 211 - Core layer; 2021 - First dielectric layer; 2061 - Floating metal block; 2061a - First floating metal block; 2061b - Second floating metal block; 2062 - First metal ring; 300 - Notch; 2063 - Second metal ring; 2061c - Third floating metal block; 2061d - Fourth floating metal block; 301 - Second via. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. When describing a single component, device, or system, multiple such components, devices, or systems may perform related functions. For example, one or more processors may perform the functions described in relation to a processor.

[0059] In the following description, the terms "first," "second," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0060] The limitations mentioned in the embodiments of this application, such as parallel, perpendicular, orthogonal, and identical (e.g., identical length, identical width, etc.), are all relative to the current technological level, and not absolute and strict mathematical definitions. A predetermined angular deviation may exist between two mutually parallel or perpendicular components. In one embodiment, the predetermined threshold may be less than or equal to a threshold of 1 mm, for example, the predetermined threshold may be 0.5 mm or 0.1 mm. In one embodiment, the predetermined angle may be an angle within the range of ±10°, for example, a predetermined angular deviation of ±5°.

[0061] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed mechanical connection, a detachable mechanical connection, or an integral part; or, "connection" can be a direct connection or an indirect connection through an intermediate medium. Furthermore, unless otherwise expressly specified and limited, the term "coupling" should be interpreted broadly. For example, "coupling" can be a direct electrical connection, such as physical contact and electrical conduction between two components; it can also be understood as an electrical connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as copper foil or wires on a printed circuit board (PCB), to transmit electrical signals; or, "coupling" can be an indirect electrical connection between two components through an intermediate medium; or, "coupling" can be an electrical connection between two components in a non-contact manner, such as an electrical connection between two components using capacitive coupling to transmit electrical signals.

[0062] In the embodiments of this application, directional terms such as "up," "down," "left," and "right" may be defined relative to the orientation of the components shown in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation of the components in the accompanying drawings.

[0063] In the accompanying drawings of the embodiments of this application, components are represented by guide lines with arrows; parts are represented by guide lines only; openings, holes, and other openings are represented by guide lines with wavy lines at the ends.

[0064] This application provides an electronic device. This electronic device can be applied to various communication systems or protocols, such as Bluetooth (BT) communication technology, Global Positioning System (GPS) communication technology, Global System for Mobile Communication (GSM) communication technology, Wireless Fidelity (WiFi) communication technology, Wideband Code Division Multiple Access (WCDMA) communication technology, Long Term Evolution (LTE) technology, 5G communication technology, and other future communication technologies. The electronic device in this application can be a mobile phone, tablet computer, laptop computer, smart home device, smart wearable device (e.g., smartwatch, smart bracelet, smart glasses, smart helmet, smart headphones), virtual reality (VR) electronic device, augmented reality (AR) electronic device, etc. Electronic devices can also be servers, routers, switches, handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, vehicle-mounted devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc., and the embodiments of this application are not limited to these.

[0065] As shown in Figure 1, the aforementioned electronic device 01 may include a chip package (PKG) structure 10 and a circuit board 11. For example, the circuit board 11 may be a printed circuit board (PCB), a flexible printed circuit board (FPCB), or a rigid-flex printed circuit board (RFPCB). For ease of explanation, the following description uses a PCB as an example for the circuit board 11. The chip package structure 10 may be disposed on the circuit board 11, and the chip package structure 10 may be electrically connected to the circuit board 11.

[0066] In some embodiments of this application, continuing as shown in FIG1, the chip package structure 10 may include at least one chip 101 and a package substrate 102. The package substrate 102 has a first surface A1 and a second surface A2 disposed opposite to each other. The chip 101 is disposed on the first surface A1 of the package substrate 102. Based on this, in order to enable the chip package structure 10 to be electrically connected to the circuit board 11, the chip package structure 10 may further include a plurality of first interconnect structures 103 arranged in an array. For example, the first interconnect structures 103 may be disposed on the second surface A2 of the package substrate 102. The chip 101 can transmit signals with other chips or chip package structures on the circuit board 11 through the package substrate 102 and the first interconnect structures 103.

[0067] For example, the first interconnect structure 103 described above can be a solder ball, and multiple first interconnect structures 103 arranged in an array can form a ball grid array (BGA). Alternatively, the first interconnect structure 103 can be a copper pillar bump. This application does not limit the specific type of the first interconnect structure 103.

[0068] Figure 1 illustrates an example of a chip package structure 10 containing one chip 101. In other embodiments of this application, the chip package structure 10 can also be a multi-chip module (MCM). In this case, the chip package structure 10 can package at least two chips 101.

[0069] For example, the chip 101 described above can be a single die. Alternatively, in some embodiments, continuing as shown in FIG1, the chip 101 can be a structure using fan-out package (FOP) technology, with the single die 1011 disposed on a redistribution layer (RDL) 1012. In this case, the single die 1011 can be electrically connected to the package substrate 102 through the redistribution layer 1012. Or, in some embodiments, the chip 101 can be a structure using chip-on-wafer-on-substrate (COWOS) technology, with the single die disposed on an interposer. This application does not limit the specific type of chip 101.

[0070] For ease of explanation, an XYZ coordinate system is established in the accompanying drawings, as shown in Figure 1. The Z direction can be the stacking direction of the chip package structure 10 and the circuit board 11, or the thickness direction of the electronic device 01. The XY plane formed by the X and Y directions can be perpendicular to the Z direction. Therefore, this XY plane can be parallel to the surface of the circuit board 11.

[0071] As described above, as shown in Figure 1, the redistribution layer 1012 in the chip 101 can be electrically connected to the bare chip 1011. The packaging substrate 102 is electrically connected to the chip 101 located on the packaging substrate 102. The circuit board 11 is electrically connected to the chip 101 through the packaging substrate 102. Therefore, any one of the above-mentioned redistribution layer 1012, packaging substrate 102, or circuit board 11 can serve as an electrical connection substrate capable of being electrically connected to other electronic components to realize signal transmission.

[0072] When transmitting electrical signals, such as high-speed signals (for example, signals above 3Gbps), the aforementioned electrical connection substrate needs to have high impedance (IM) continuity to ensure the signal integrity (SI) and stability of the transmitted signal on the passive link of the electrical connection substrate. The following description uses the packaging substrate 102 in Figure 1 as an example to illustrate the structure of this electrical connection substrate. When the electrical connection substrate is the redistribution layer 1012 or the circuit board 11 shown in Figure 1, the structure and technical effects are similar and will not be elaborated further.

[0073] In some embodiments of this application, as shown in FIG2, the electrical connection substrate 20 may include multiple metal layers 201 and multiple dielectric layers 202. The multiple dielectric layers 202 may be disposed between the multiple metal layers 201, that is, between any two adjacent metal layers 201, a corresponding dielectric layer 202 may be disposed. The dielectric layer 202 may insulate adjacent metal layers 201 located on both sides of the dielectric layer 202. In this case, the electrical connection substrate 20 may be a structure consisting of multiple metal layers 201 and multiple dielectric layers 202 alternately stacked.

[0074] Furthermore, as shown in FIG3, the multilayer metal layers in the electrical connection substrate 20 may include a first surface metal layer 2011, at least one first intermediate metal layer 2012 (FIG3 illustrates this with three first intermediate metal layers 2012 as an example), a second intermediate metal layer 2013 including metal traces 20131 (FIG4), and a second surface metal layer 2014, which are stacked sequentially. The first surface metal layer 2011, the first intermediate metal layer 2012, the second intermediate metal layer 2013 including metal traces 20131 (FIG4), and the second surface metal layer 2014 may be patterned metal layers formed by photolithography. The metal traces 20131 may be part of the patterned second intermediate metal layer 2103 (FIG4) in which the metal traces 20131 are located.

[0075] The aforementioned patterned metal layer can include grounding patterns for grounding and metal traces for transmitting signal lines, depending on the circuit design requirements. This application does not limit the patterning design of the aforementioned patterned metal layer. For ease of explanation, the specific patterns of the first surface metal layer 2011, the first intermediate metal layer 2012, the second intermediate metal layer 2013 including the metal trace 20131, and the second surface metal layer 2014 are not shown in the accompanying drawings.

[0076] For example, continuing as shown in Figure 3, the materials of the first surface metal layer 2011, the first intermediate metal layer 2012, the metal trace 20131, and the second surface metal layer 2014 can be copper (Cu). In this case, the metal layer attached to the surface of the dielectric layer 202 (as shown in Figure 2) can be copper foil. By performing photolithography on different layers of copper foil, a multi-layer patterned metal layer is formed, thereby realizing the fabrication of the first surface metal layer 2011, the first intermediate metal layer 2012, the metal trace 20131, and the second surface metal layer 2014. Alternatively, as another example, the materials of the first surface metal layer 2011, the first intermediate metal layer 2012, the metal trace 20131, and the second surface metal layer 2014 can be aluminum (Al) or other metal materials with high conductivity.

[0077] Continuing with Figure 3, the first surface metal layer 2011 and the second surface metal layer 2014 can be the two outermost metal layers in a multilayer stacked metal layer 201 (as shown in Figure 2). For example, in the case where the electrical connection substrate 20 is the packaging substrate 102 shown in Figure 1, as shown in Figure 4 (a cross-sectional view obtained by cutting along the dashed line O1-O2 in Figure 3), the first surface metal layer 2011 can be the metal layer closest to the circuit board 11 in the multilayer stacked metal layers. The second surface metal layer 2014 can be the metal layer closest to the chip 101 in the multiple stacked metal layers. Furthermore, insulating film layers, such as solder resist layers or adhesive layers, can be provided on the surface of the first surface metal layer 2011 facing the circuit board 11 and the surface of the second surface metal layer 2014 facing the chip 101.

[0078] Alternatively, as another example, the first surface metal layer 2011 can be the metal layer closest to the chip 101 among multiple stacked metal layers. The second surface metal layer 2014 can be the metal layer closest to the circuit board 11 among multiple stacked metal layers. For ease of explanation, the following examples use the configuration shown in Figure 4, where the first surface metal layer 2011 is close to the circuit board 11 and the second surface metal layer 2014 is close to the chip 101.

[0079] Continuing with Figure 3, the first surface metal layer 2011 may include a first pad 204. For example, as shown in Figure 4, the dielectric layer 202 between the bottommost first intermediate metal layer 2012 and the first surface metal layer 2011 may have a surface B facing the circuit board 11, and the first surface metal layer 2011 with the first pad 204 may be located on the surface B. For example, if the electrical connection substrate 20 is the packaging substrate 102 shown in Figure 1, the first pad 204 may be electrically connected to the first interconnect structure 103.

[0080] Furthermore, continuing as shown in FIG3, the aforementioned electrical connection substrate 20 may further include a first via 203, which can penetrate the first surface metal layer 2011 and the aforementioned at least one first intermediate metal layer 2012 (i.e., the first via 203 can penetrate all of the first intermediate metal layers 2012). Furthermore, as shown in FIG4, the aforementioned first via 203 can also penetrate the dielectric layer 202 between the first surface metal layer 2011 and the second intermediate metal layer 2013. The first via 203 may include a plurality of sub-vias sequentially electrically connected along the Z-direction, each sub-via located between two adjacent metal layers and penetrating a dielectric layer 202 between the two adjacent metal layers. The axes of the plurality of sub-vias may overlap along the Z-direction. Alternatively, in some embodiments of this application, the axes of at least two of the plurality of sub-vias may not overlap.

[0081] Continuing as shown in Figure 3, the first end a1 (i.e., the upper end) of the first via 203 can be electrically connected to the metal trace 20131, and the second end a2 (i.e., the lower end) of the first via 203 can be electrically connected to the first pad 204. In this case, the first pad 204, the first via 203, and the metal trace 20131 can constitute at least a part of the passive link in the electrical connection substrate 20.

[0082] Based on this, to prevent the first pad 204 from being electrically connected to the metal portion of the first surface metal layer 2011 other than the first pad 204, thus causing a short circuit in the first pad 204, as shown in Figure 3, a corresponding anti-pad, such as anti-pad 205a, can be provided in the first surface metal layer 2011 around the first pad 204. This anti-pad 205a in the first surface metal layer 2011 is the corresponding anti-pad for the first pad 204. For example, a portion of the first surface metal layer 2011 surrounding the first pad 204 can be removed, forming a cavity around the first pad 204 in the first surface metal layer 2011. The area containing this cavity can be the aforementioned anti-pad 205a. This cavity can be filled with the same dielectric material as the aforementioned dielectric layer 202. For example, when the multilayer metal layer 201 and the multilayer dielectric layer 202 are laminated, some material from the dielectric layer 202 will flow into the cavity and fill it. Alternatively, the aforementioned cavity may not need to be filled with the aforementioned medium material; this application does not limit this.

[0083] Similarly, to prevent a short circuit between the first pad 204 and the first intermediate metal layer 2012 via the first via 203 electrically connected to the first pad 204, as shown in Figure 3, a corresponding anti-pad 205b is provided around the vertical projection of the first pad 204 onto any one of the at least one first intermediate metal layer 2012. The anti-pad 205a in any one of the first intermediate metal layers 2012 is the anti-pad corresponding to the vertical projection of the first pad 204 onto that first intermediate metal layer 2012. For example, a portion of the periphery of the vertical projection of the first pad 204 onto that first intermediate metal layer 2012 can be removed, and the area containing the resulting void is the aforementioned anti-pad 205b.

[0084] Figure 3 illustrates an example where the diameter of the anti-pad 205a on the first surface metal layer 2011 is the same as or approximately the same as the diameter of the anti-pad 205b on the first intermediate metal layer 2012. In other embodiments, the diameters of the anti-pads on at least two metal layers may be different. For example, the diameter of the anti-pad 205a on the first surface metal layer 2011 may be larger than the diameter of the anti-pad 205b on any one of the plurality of first intermediate metal layers 2012.

[0085] In this way, the anti-pad 205a in the first surface metal layer 2011 can isolate the first pad 204 from the other metal portions of the first surface metal layer 2011, thus preventing electrical connection between the first pad 204 and the other metal portions of the first surface metal layer 2011. Furthermore, the anti-pad 205b can isolate the first via 203 penetrating the first intermediate metal layer 2012 from the first intermediate metal layer 2012, preventing the first pad 204 from being electrically connected to the first intermediate metal layer 2012 through the first via 203. Therefore, the anti-pads 205a and 205b can also be referred to as isolation pads, which insulate the first pad 204 from the first intermediate metal layer 2012 and the other metal portions of the first surface metal layer 2011.

[0086] Based on this, as described above, when the electrical connection substrate 20 transmits signals, especially high-speed signals, it needs to have high impedance continuity to ensure the integrity and stability of the transmitted signals on the passive link of the electrical connection substrate 20. However, in Figure 4, the impedance of the first pad 204 and the first interconnect structure 103 is low, which causes an impedance drop at the location of the first pad 204 and the first interconnect structure 103 on the passive link, reducing the impedance continuity on the passive link, causing impedance mismatch, and thus leading to a decrease in signal quality (e.g., signal reflection or jitter).

[0087] In this case, since the first pad 204 and the first interconnect structure 103 can form a capacitor with the metal layer that is insulated from them, in order to improve the impedance continuity, the diameter of the plurality of anti-pads can be increased to increase the impedance at the location of the first pad 204 and the first interconnect structure 103 on the passive link, thereby achieving the purpose of improving impedance continuity.

[0088] Furthermore, continuing as shown in FIG3, at least one first intermediate metal layer 2012 may include a floating metal pattern 206. And, continuing as shown in FIG4, the floating metal pattern 206 may be located within the anti-pad 205b in the first intermediate metal layer 2012. The metal portions of the first intermediate metal layer 2012 having the floating metal pattern 206, excluding the floating metal pattern 206, and the floating metal pattern 206, as well as the first via 203, can be isolated by the anti-pad 205b, without any metal connection. This avoids the short circuit caused by the electrical connection between the first via 203 and the floating metal pattern 206. Here, "floating" means that there is no metal connection or electrical connection between the floating metal pattern 206 and the metal portions of the first intermediate metal layer 2012, excluding the floating metal pattern 206, and between the floating metal pattern 206 and the first via 203.

[0089] In summary, as shown in FIG4, in the electrical connection substrate 20 provided in this application embodiment, the first end a1 of the first via 203 penetrating all first intermediate metal layers 2012 is electrically connected to the metal trace 20131. For example, when the electrical connection substrate 20 is a packaging substrate, the chip 101 on the packaging substrate can be electrically connected to the aforementioned metal trace 20131 via solder balls. Furthermore, the second end a2 of the first via 203 is electrically connected to the first pad 204. The first pad 204 can be electrically connected to the PCB trace 1101 in the circuit board 11 via the first interconnect structure 103. In this way, the first pad 204 can be electrically connected to the metal trace 20131 via the first via 203. In this case, when two electronic components, such as the chip 101 and the circuit board 11, are electrically connected to the metal trace 20131 and the first pad 204 respectively, the two electronic components (e.g., the chip 101 and the circuit board 11) can transmit electrical signals through the electrical connection substrate 20.

[0090] Furthermore, in the first surface metal layer 2011, anti-pads 205a are arranged around the first pad 204, thereby isolating the first pad 204 from the metal portion of the first surface metal layer 2011 other than the first pad 204, preventing short circuits in the first pad 204. Additionally, in the first intermediate metal layer 2012, anti-pads 205b can isolate the first via 203 penetrating the first intermediate metal layer 2012 from the first intermediate metal layer 2012, thereby preventing short circuits in the first via 203.

[0091] Based on this, during the temperature cycling reliability test, the aforementioned electrical connection substrate 20 is affected by stress mismatch. As shown in Figure 5 (another cross-sectional view obtained by cutting along the dashed line O1-O2 in Figure 3), the metal material around the anti-pad 205 (hereinafter, for ease of explanation, both the anti-pad in the first surface metal layer 2011 and the anti-pad in the first intermediate metal layer 2012 are referred to as anti-pad 205) will exert a tensile force f on the anti-pad 205 to stretch it. This results in a large stress at the interface between the anti-pad 205 and the metal material (for example, at the interface between the anti-pad 205 and the first pad 204, or at the interface between the anti-pad 205 and the metal part of the first surface metal layer 2011 other than the first pad 204).

[0092] In this situation, as shown in Figure 6, the aforementioned stress can cause cracks 100 to form on the surface B of the electrical connection substrate 20 where the first pad 204 is located, at the interface between the anti-pad 205 and the metal material, for example, at the interface between the anti-pad 205 and the first pad 204. When the stress is high, the cracks 100 can propagate into the interior of the electrical connection substrate 20 and extend to the metal trace 20131, causing the metal trace 20131 to break, thereby causing the entire electrical connection substrate 20 to malfunction.

[0093] To alleviate the aforementioned crack 100, as described above, at least one first intermediate metal layer 2012 in the electrical connection substrate 20 provided in this application embodiment may include a floating metal pattern 206 as shown in FIG. 5. Since the floating metal pattern 206 is disposed within the anti-pad 205 in the first intermediate metal layer 2012, and the first intermediate metal layer 2012 having the floating metal pattern 206 is isolated between the metal portion other than the floating metal pattern 206 and the floating metal pattern 206, and between the floating metal pattern 206 and the first via 203 via the anti-pad 205 of the first intermediate metal layer 2012, the floating metal pattern 206 can form a stress relief channel (shown by dashed arrows in FIG. 5) with the metal material on both sides of the anti-pad 205, such as the metal portion other than the floating metal pattern 206 in the first intermediate metal layer 2012 and the first pad 204.

[0094] Based on this, continuing as shown in Figure 5, when the electrical connection substrate 20 is affected by stress mismatch, causing the metal material around the anti-pad 205 to exert a tensile force f on the anti-pad 205, resulting in a crack 100 on the surface B, when the crack 100 propagates into the electrical connection substrate 20 to the floating metal pattern 206, the floating metal pattern 206 can share the stress between the anti-pad 205 and the first pad 204, and between the anti-pad 205 and the metal portion of the first surface metal layer 2011 other than the floating metal pattern 206, through the stress relief channel formed by the anti-pad 205 and the metal material on both sides of the anti-pad 205. This can reduce the probability of crack 100 occurring and crack 100 further propagating into the electrical connection substrate 20.

[0095] Based on this, since the second intermediate metal layer 2013 with metal traces 20131 is located on the side of the plurality of first intermediate metal layers 2012 facing away from the first surface metal layer 2011, and the floating metal pattern 206 can be disposed in the same layer as at least one first intermediate metal layer 2012, the floating metal pattern 206 is located on the side of the metal traces 20131 facing the first surface metal layer 2011, that is, the metal traces 20131 are located above the floating metal pattern 206. In this way, since the floating metal pattern 206, as a rigid structure, can prevent the crack 100 from further propagating inward, it can prevent the crack 100 from extending to the metal traces 20131 located above the floating metal pattern 206, thereby reducing the probability of the inwardly propagating crack 100 causing the metal traces 20131 to break, and thus reducing the probability of the electrical connection substrate 20 failing.

[0096] Furthermore, in related technologies, to reduce the propagation tendency of crack 100 into the electrical connection substrate 20, as shown in Figure 7, the aperture of a portion of the anti-pad 205 is reduced, for example, the aperture D1 is reduced to aperture D2. In this way, the portion of metal layer 201 around aperture D2 can prevent crack 100 from propagating further inward. However, the portion of metal layer 201 around aperture D2 couples with pad P, causing an impedance drop at the coupling point between the portion of metal layer 201 around aperture D2 and pad P on the passive link, thereby reducing the impedance continuity on the passive link.

[0097] To address the aforementioned issues, as shown in Figure 5, in the electrical connection substrate 20 provided in this embodiment, the floating metal pattern 206 disposed within the anti-pad 205 in the first intermediate metal layer 2012 is spaced apart from the metal portions of the plurality of first intermediate metal layers 2012 other than the floating metal pattern 206 by anti-pads 205. This ensures that there is no electrical connection between the floating metal pattern 206 and the metal portions of the first intermediate metal layer 2012 other than the floating metal pattern 206, and between the floating metal pattern 206 and the first via 203. This reduces the coupling between the first pad 204 and the floating metal pattern 206, or between the first pad 204 and the first intermediate metal layer 2012. Furthermore, this reduces the probability of impedance discontinuities caused by impedance drops at the coupling positions of the first pad 204 and the floating metal pattern 206, or between the first pad 204 and the first intermediate metal layer 2012, on the passive link of the electrical connection substrate 20. When the aforementioned electrical connection substrate 20 transmits high-speed signals, it helps to ensure the signal integrity and stability of the high-speed signal link and reduces the impact on the characteristics of the high-speed signal link.

[0098] Figures 5, 6, and 7 illustrate the effect of stress mismatch on the electrical connection substrate 20, where the metal material surrounding the anti-pad 205 stretches the anti-pad 205, resulting in significant stress at the interface between the anti-pad 205 and the first pad 204, causing cracks 100 at this interface. In other embodiments of this application, when the metal material surrounding the anti-pad 205 stretches the anti-pad 205, causing significant stress at the interface between the anti-pad 205 and the first surface metal layer 2011, the aforementioned cracks may also occur at this interface. The floating metal pattern 206 mitigates the inward propagation of cracks at the interface between the anti-pad 205 and the first surface metal layer 2011 as described above, and will not be repeated here.

[0099] Figure 5 illustrates an example of an electrical connection substrate 20 with a first via 203, a metal trace 20131 electrically connected to the first via 203, and three first intermediate metal layers 2012 located below the metal trace 20131. In some embodiments of the application, as shown in Figure 8 (another cross-sectional view obtained by cutting along the dashed lines O1-O2 in Figure 3), the electrical connection substrate 20 needs to be electrically connected to multiple first interconnect structures 103 (e.g., solder balls). In this case, the electrical connection substrate 20 has multiple first vias, and each first via can be electrically connected to one first interconnect structure 103.

[0100] For example, continuing as shown in Figure 8, the aforementioned plurality of first vias may include first via 203a and first via 203b. Between the metal trace 20131a electrically connected to the first via 203a and the first surface metal layer 2011, three first intermediate metal layers 2012 may be provided. Between the metal trace 20131b electrically connected to the first via 203b and the first surface metal layer 2011, two first intermediate metal layers 2012 may be provided. In this case, the second intermediate metal layer 2013 containing the metal trace 20131b electrically connected to the first via 203b can be considered as the first intermediate metal layer 2012 closest to the metal trace 20131a below the metal trace 20131a electrically connected to the first via 203a (filled in black).

[0101] Therefore, since the depths of the multiple first vias are different, the first intermediate metal layer 2012 below one first via can also be the second intermediate metal layer 2013 where the metal trace electrically connected to another first via is located. In summary, any one of the first intermediate metal layer 2012 and the second intermediate metal layer 2013 can include metal traces for transmitting signals.

[0102] Figures 4, 5, and 8 above illustrate examples where the dielectric layer 202 between adjacent metal layers 201 in the electrical connection substrate 20 has the same thickness or a small difference in thickness. In other embodiments of this application, as shown in Figure 9, in order to improve the support performance of the electrical connection substrate 20, the thickness (dimension along the Z direction) of some dielectric layers, such as dielectric layer 202a, is greater than the thickness of other dielectric layers, such as dielectric layer 202b. Based on this, the dielectric layer 202a and the metal layers located on both sides of the dielectric layer 202a (e.g., the first intermediate metal layer 2012) can constitute a core layer 211. The floating metal pattern 206 can be located below the core layer 211. In this way, the floating metal pattern 206 can not only reduce the probability of the crack 100 spreading further inward to the metal trace 20131, but also reduce the probability of the crack 100 spreading into the dielectric layer 202a in the core layer 211, causing internal cracking of the dielectric layer 202a.

[0103] Based on this, continuing as shown in FIG9, the second intermediate metal layer 2013 can be disposed above the core layer 211. To enable the first via 203 to be electrically connected to the metal trace 20131 in the second intermediate metal layer 2013, the electrical connection substrate 20 can further include a core layer via 212 penetrating the core layer 211. This core layer via 212 can electrically connect the first via 203 and the metal trace 20131 in the second intermediate metal layer 2013, so that the first via 203 is electrically connected to the metal trace 20131 through the aforementioned core layer via 212. Alternatively, in some embodiments of this application, the second intermediate metal layer 2013 can also be located below the core layer 211. In this case, the metal trace 20131 in the second intermediate metal layer 2013 can also be electrically connected to other metal traces in the metal layer 201 above the core layer 211 through the core layer via, thereby realizing signal transmission between the chip 101 and the circuit board 11. The passive link described above will experience impedance reduction at the location of the core layer via 212. Similarly, the impedance at the locations of the first pad 204, the first interconnect structure 103, and the core layer via 212 can be increased by increasing the diameter of the multiple anti-pads 205, thereby improving impedance continuity.

[0104] When the electrical connection substrate 20 is a packaging substrate, Figures 4, 5, 8, and 9 are illustrative examples with the first interconnect structure 103 disposed on the side of the electrical connection substrate 20 where the first pad 204 is located, and the chip 101 disposed on the side of the electrical connection substrate 20 away from the first interconnect structure 103. In other embodiments of this application, as shown in Figure 10, the chip 101 can be disposed on the side of the electrical connection substrate 20 where the first pad 204 is located, and the chip 101 is electrically connected to the first pad 204. For example, the chip 101 can be electrically connected to the first pad 204 through a copper bump. Similarly, when a crack 100 occurs on the surface of the electrical connection substrate 20 on the side where the chip 101 is located, for example near the first pad 204, the floating metal pattern 206 can reduce the probability that the crack 100 will further propagate inward to the metal trace 20131, causing the metal trace 20131 to break.

[0105] For ease of explanation, the following example illustrates the arrangement of the floating metal pattern 206, using the electrical connection substrate 20 including the aforementioned core layer 211. As shown in FIG11, at least one first intermediate metal layer 2012 (as shown in FIG9) may include a lower first intermediate metal layer 20121 and an upper first intermediate metal layer 20122 stacked together. The upper first intermediate metal layer 20122 may be located on the side of the lower first intermediate metal layer 20121 that faces away from the first surface metal layer 2011.

[0106] In this configuration, no metal layer is disposed between the lower first intermediate metal layer 20121 and the first surface metal layer 2011, or between the lower first intermediate metal layer 20121 and the upper first intermediate metal layer 20122. That is, the lower first intermediate metal layer 20121 is the metal layer closest to the first surface metal layer 2011 among all metal layers 201, while the upper first intermediate metal layer 20122 is the metal layer closest to the lower first intermediate metal layer 20121 among all metal layers 201. Based on this, at least a portion of the floating metal pattern 206 can be disposed on the same layer as the upper intermediate metal layer 20122. Figure 11 provides an example where the entire floating metal pattern 206 is disposed on the same layer as the upper intermediate metal layer 20122.

[0107] As described above, the floating metal pattern 206 is made of metal. When the floating metal pattern 206 is close to the first pad 204, for example, when the floating metal pattern 206 is disposed on the same layer as the lower first intermediate metal layer 20121, the floating metal pattern 206 can couple with the first pad 204. This results in a decrease in impedance at the coupling position between the floating metal pattern 206 and the first pad 204 in the passive link, leading to a decrease in impedance continuity in the passive link. However, when the floating metal pattern 206 is far from the first pad 204, the stress relief channel formed by the floating metal pattern 206 and the metal materials on both sides of the anti-pad 205 has a weaker ability to share the stress between the anti-pad 205, the first pad 204, and the first surface metal layer 2011, making it easier for the crack 100 to propagate into the electrical connection substrate 20.

[0108] Therefore, continuing as shown in Figure 11, when at least the upper intermediate metal layer 20122 includes the floating metal pattern 206 in the same layer, the floating metal pattern 206 can be separated from the first surface metal layer 2011 by a metal layer, namely the lower first intermediate metal layer 20121. In this way, the distance between the floating metal pattern 206 and the first pad 204 can be reduced, which can reduce the impact on impedance continuity in the passive link, improve signal quality, and form a stress relief channel with strong stress sharing capability.

[0109] The following example illustrates the placement of the floating metal pattern 206 within the anti-pad 205 of the first intermediate metal layer 2012. For ease of explanation, the floating metal pattern 206 is illustrated using a vertical projection onto one of the dielectric layers in the multilayer dielectric layers, such as the first dielectric layer 2021 shown in FIG. 11. The above explanation uses the first dielectric layer 2021 as an example of the dielectric layer within the core layer 211. This application does not limit the position of the first dielectric layer 2021; it can be any dielectric layer between two adjacent metal layers in the electrical connection substrate 20.

[0110] As described above, the electrical connection substrate 20 is affected by stress mismatch. The metal material around the anti-pad 205 stretches the anti-pad 205, resulting in significant stress at the interface between the anti-pad 205 and the metal material, leading to the aforementioned crack 100. Therefore, to effectively prevent the crack 100 from further propagating into the electrical connection substrate 20, in some embodiments of this application, as shown in FIG12 (a partial top view along direction C in FIG11), the vertical projection of the floating metal pattern 206 on the first dielectric layer 2021 (as shown in FIG11) overlaps with the edge of the vertical projection of the first pad 204 on the first dielectric layer 2021. That is, the edges of the floating metal pattern 206 and the first pad 204 overlap in their vertical projections on the same dielectric layer (e.g., the aforementioned first dielectric layer 2021).

[0111] In this case, continuing as shown in Figure 12, along the Z direction, the position of the floating metal pattern 206 can overlap with the edge of the first pad 204. Thus, when the metal material around the anti-pad 205 stretches the anti-pad 205, causing the aforementioned crack 100 to appear at the junction of the anti-pad 205 and the first pad 204 (e.g., at the edge of the first pad 204), the floating metal pattern 206, overlapping with the edge of the first pad 204, more easily prevents the crack 100 from further propagating into the electrical connection substrate 20.

[0112] Figure 12 illustrates an example where the vertical projection of the floating metal pattern 206 onto the first dielectric layer 2021 (as shown in Figure 11) overlaps with the vertical projection of the metal trace 20131 onto the first dielectric layer 2021. In other embodiments of this application, as shown in Figure 13 (another partial top view along direction C in Figure 11), the vertical projection of the floating metal pattern 206 onto the first dielectric layer 2021 (as shown in Figure 11) and the vertical projection of the metal trace 20131 onto the first dielectric layer 2021 may not overlap. This reduces the coupling between the metal trace 20131 and the floating metal pattern 206, thereby reducing the impact on the impedance continuity of the passive link.

[0113] Alternatively, in some other embodiments of this application, as shown in FIG14 (another partial top view obtained along direction C in FIG11), the vertical projection of the floating metal pattern 206 on the first dielectric layer 2021 (as shown in FIG11) overlaps with the edge of the vertical projection of the metal portion of the first surface metal layer 2011 other than the first pad 204 on the first dielectric layer 2021 toward the first via 203.

[0114] In this case, continuing as shown in Figure 14, along the Z direction, the position of the floating metal pattern 206 can overlap with the edge of the metal portion of the first surface metal layer 2011 other than the first pad 204 facing the first via 203. Thus, when the metal material around the anti-pad 205 stretches the anti-pad 205, causing the aforementioned crack 100 to appear at the interface between the anti-pad 205 and the metal portion of the first surface metal layer 2011 other than the first pad 204, the floating metal pattern 206, which overlaps with the edge of the metal portion of the first surface metal layer 2011 other than the first pad 204, more easily prevents the crack 100 from further propagating into the electrical connection substrate 20.

[0115] Figure 14 illustrates an example where the vertical projection of the floating metal pattern 206 onto the first dielectric layer 2021 (as shown in Figure 11) does not overlap with the vertical projection of the metal trace 20131 onto the first dielectric layer 2021. In other embodiments of this application, the vertical projection of the floating metal pattern 206 onto the first dielectric layer 2021 (as shown in Figure 11) may overlap with the vertical projection of the metal trace 20131 onto the first dielectric layer 2021, and this application does not limit this.

[0116] As described above, in order to reduce the probability of crack 100 extending inward, the floating metal pattern 206 can overlap with the interface between the anti-pad 205 and the metal material. For ease of explanation, the following examples all use the overlap between the position of the floating metal pattern 206 and the edge of the anti-pad 205 in the Z direction as an example.

[0117] Figures 12, 13, and 14 above are illustrative examples illustrating that the floating metal pattern 206 may include a single floating metal block. This application does not limit the number of floating metal blocks in the floating metal pattern. In other embodiments of this application, as shown in Figure 15 (a partial top view along direction C in Figure 11), at least one of the aforementioned floating metal patterns 206 may include a plurality of spaced-apart floating metal blocks 2061. The vertical projection of these plurality of floating metal blocks 2061 onto the first dielectric layer 2021 (as shown in Figure 11) can be arranged in a ring around the vertical projection of the first pad 204 onto the first dielectric layer 2021. The spaced-apart arrangement of the plurality of floating metal blocks 2061 means that any two adjacent floating metal blocks 2061 are not connected and are spaced apart by a distance. This application does not limit the distance between any two adjacent floating metal blocks 2061.

[0118] In this case, the multiple floating metal blocks 2061 in the floating metal pattern 206 are disposed on the same layer as the first intermediate metal layer 2012. In this way, multiple floating metal blocks disposed on the same layer can be formed in a single photolithography process, thereby simplifying the manufacturing process of the floating metal pattern 206.

[0119] Figure 15 illustrates an example where the first intermediate metal layer 2012 includes a floating metal pattern 206. In other embodiments of this application, the first intermediate metal layer 2012 may include two or more floating metal patterns 206. Different floating metal patterns 206, arranged in a ring shape with multiple floating metal blocks spaced apart, may be nested.

[0120] In this case, when the crack 100 is generated at the junction of the anti-pad 205 and the metal material, such as at the junction of the anti-pad 205 and the first pad 204 (as shown in FIG. 11), the crack 100 can be located at any position around the first pad 204. Based on this, since the multiple floating metal blocks 2061 in the floating metal pattern 206 can be arranged around the first pad 204, the probability of the floating metal blocks 2061 being located on the extension path of the crack 100 can be increased, thereby reducing the probability of the crack 100 propagating inward in different directions, thereby achieving the purpose of reducing the propagation of the crack 100 into the electrical connection substrate 20.

[0121] For example, the multiple floating metal blocks 2061 in the aforementioned floating metal pattern 206 can be evenly arranged around the first pad 204. Furthermore, the multiple floating metal blocks 2061 in the floating metal pattern 206 can overlap with the edge of the anti-pad 205. Alternatively, the multiple floating metal blocks 2061 in the floating metal pattern 206 can overlap with the edge of the first surface metal layer 2011 facing the first via 203. The technical effects of the above solutions are similar and will not be elaborated further here.

[0122] Building upon this, as shown in Figure 15, the floating metal blocks 2061 in the floating metal pattern 206, when projected vertically onto the first dielectric layer 2021 (as shown in Figure 11), can be fan-shaped. This fan shape can have a first arc edge L1 and a second arc edge L2. The first arc edge L1 faces away from the first via 203, and the second arc edge L2 faces the first via 203. The arc length of the first arc edge L1 is greater than the arc length of the second arc edge L2. In this case, multiple fan-shaped floating metal blocks 2061 are more easily arranged around the first pad 204, making the arrangement of the multiple floating metal blocks 2061 more compact, which helps increase the probability that the floating metal blocks 2061 are located on the propagation path of the crack 100.

[0123] Figure 15 is an example of a floating metal block 2061 in a fan shape. In other embodiments of this application, the shape of the floating metal block 2061 can also be rectangular, circular, etc., and this application does not limit it.

[0124] Furthermore, as can be seen from the above, in order to reduce the coupling between the metal trace 20131 and the floating metal pattern 206, and thus reduce the impact on the impedance continuity of the passive link, the vertical projection of the floating metal pattern 206 on the first dielectric layer 2021 (as shown in Figure 11) and the vertical projection of the metal trace 20131 on the first dielectric layer 2021 can be non-overlapping. Therefore, when the floating metal pattern 206 includes multiple floating metal blocks 2061 spaced apart as shown in FIG. 15, as shown in FIG. 16 (another partial top view obtained along direction C in FIG. 11), the floating metal pattern 206 includes adjacent first floating metal blocks 2061a and second floating metal blocks 2061b. The vertical projection of the metal trace 20131 on the first dielectric layer 2021 (as shown in FIG. 11) is located between the vertical projection of the first floating metal block 2061a on the first dielectric layer 2021 and the vertical projection of the second floating metal block 2061b on the first dielectric layer 2021. This allows the position of the metal trace 20131 to not overlap with that of the floating metal pattern 206, thereby reducing the impact on the impedance continuity of the passive link.

[0125] For example, in Figure 17, scheme ①, in the related art, the electrical connection substrate 20 without the floating metal pattern shown in Figure 6, when transmitting a signal at a frequency of 30 GHz, has an insertion loss of approximately -1.2 dB. In Figure 17, scheme ②, in the related art, as shown in Figure 7, the electrical connection substrate 20 with a reduced anti-pad 205 portion size has an insertion loss of approximately -1.6 dB when transmitting a signal at a frequency of 30 GHz. In Figure 17, scheme ③, as provided in this embodiment of the application, the electrical connection substrate 20 with a floating metal pattern 206 composed of multiple floating metal blocks arranged in a ring, as shown in Figure 16, has an insertion loss of approximately -1.28 dB when transmitting a signal at a frequency of 30 GHz. The smaller the absolute value of the insertion loss, the smaller the signal attenuation and the higher the signal quality.

[0126] Therefore, as shown in Figure 17, the signal insertion loss of scheme ③ and scheme ① differs by only 0.08 dB. Although the electrical connection substrate 20 shown in Figure 16 has a floating metal pattern 206 that can reduce crack propagation, it has little impact on the continuity of passive link impedance, thus ensuring good signal transmission quality.

[0127] Furthermore, as shown in Figure 18, in the related art, the electrical connection substrate 20 without the floating metal pattern shown in Figure 6 has a return loss of approximately -9.8 dB when transmitting a signal at a frequency of 30 GHz. As shown in Figure 18, in the related art, as shown in Figure 7, the electrical connection substrate 20 with a reduced anti-pad 205 portion has a return loss of approximately -8 dB when transmitting a signal at a frequency of 30 GHz. As shown in Figure 18, in the embodiment of this application, the electrical connection substrate 20 with a floating metal pattern 206 composed of multiple floating metal blocks arranged in a ring, as shown in Figure 16, has a return loss of approximately -9.3 dB when transmitting a signal at a frequency of 30 GHz.

[0128] Therefore, as shown in Figure 18, the signal return loss of scheme ③ and scheme ① differs by only 0.5dB. Although the electrical connection substrate 20 shown in Figure 16 has a floating metal pattern 206 that can reduce crack propagation, it has little impact on the continuity of passive link impedance, thus ensuring good signal transmission quality.

[0129] In some embodiments of this application, as shown in FIG19, when the multilayer metal layers in the electrical connection substrate 20 include at least two first intermediate metal layers 2012, the floating metal patterns of the at least two first intermediate metal layers 2012 may each include at least one floating metal block, that is, the electrical connection substrate 20 may include multiple floating metal blocks of different layers. For example, two adjacent floating metal blocks of different layers may be a third floating metal block 2061c and a fourth floating metal block 2061d, respectively. In this way, the coupling between the third floating metal block 2061c and the fourth floating metal block 2061d disposed of on different layers is small, thereby reducing the impact on the impedance continuity on the passive link.

[0130] In other embodiments of this application, as shown in FIG20 (a partial top view along direction E in FIG19), similarly, in order to ensure that the positions of the metal trace 20131 and the floating metal pattern 206 do not overlap, the vertical projection of the metal trace 20131 on the first dielectric layer 2021 (as shown in FIG11) is located between the vertical projection of the third floating metal block 2061c on the first dielectric layer 2021 and the vertical projection of the fourth floating metal block 2061d on the first dielectric layer 2021, which can also achieve the purpose of reducing the impact on the continuity of passive link impedance.

[0131] The above description uses an example of a floating metal pattern 206 including at least one floating metal block 2061. In other embodiments of this application, as shown in FIG21 (a partial top view along direction C in FIG11), the floating metal pattern 206 may include a first metal ring 2062. The vertical projection of the first metal ring 2062 on the first dielectric layer 2021 may be arranged around the circumference of the vertical projection of the first pad 204 on the first dielectric layer 2021. Furthermore, a notch 300 is provided on the first metal ring 2062, and the notch 300 penetrates the inner ring surface S1 and the outer ring surface S2 of the first metal ring 2062. Also, the vertical projection of the metal trace 20131 on the first dielectric layer 2021 (as shown in FIG11) is located within the range of the vertical projection of the notch 300 on the first dielectric layer 2021. In this situation, on the one hand, the location of the notch 300 of the first metal ring 2062 overlaps with the location of the metal trace 20131, thereby reducing the coupling between the first metal ring 2062 and the metal trace 20131, and thus reducing the impact on the impedance continuity of the passive link. On the other hand, the arrangement of the first metal ring 2062 around the first pad 204 increases the probability that the first metal ring 2062 is located on the extension path of the crack 100.

[0132] Alternatively, in some other embodiments of this application, the floating metal pattern 206 may include a second metal ring 2063 as shown in FIG22 (another partial top view along direction C in FIG11), the second metal ring 2063 being disposed around the vertical projection of the first dielectric layer 2021 (as shown in FIG11) around the vertical projection of the first pad 204 on the first dielectric layer 2021. Similarly, this increases the probability that the second metal ring 2063 is located on the path of the crack 100.

[0133] As described above, Figure 19 or Figure 20 is an example illustrating the arrangement of at least two floating metal blocks at intervals on different layers, where the positions of the two spaced-apart floating metal blocks on different layers do not overlap. In other embodiments of this application, the positions of at least two floating metal blocks may overlap.

[0134] For example, as shown in FIG23, the multilayer metal layers in the electrical connection substrate 20 include at least two first intermediate metal layers 2012, and in the case that two adjacent floating metal blocks of different layers can be the third floating metal block 2061c and the fourth floating metal block 2061d respectively, the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 respectively at least partially overlap or splice.

[0135] In this case, since the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 of the different layers at least partially overlap or splice, the probability that at least one of the third floating metal block 2061c and the fourth floating metal block 2061d is located on the crack propagation path is increased, thereby reducing the propagation of the crack into the electrical connection substrate. Based on this, the electrical connection substrate 20 may also include a second via 301 as shown in FIG. 24. The second via 301 can penetrate the metal layer (e.g., the first intermediate metal layer 2012) and the dielectric layer 202 between the third floating metal block 2061c and the fourth floating metal block 2061d. The first end (e.g., the upper end) of the second via 301 is connected to the third floating metal block 2061c, and the second end (e.g., the lower end) of the second via 301 is connected to the fourth floating metal block 2061d. Furthermore, as shown in Figure 25 (a partial top view along direction D in Figure 24), the vertical projection of the second via 301 on the first dielectric layer 2021 (as shown in Figure 24) overlaps with the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021, respectively.

[0136] In this case, the overlapping third floating metal block 2061c and fourth floating metal block 2061d can be connected together through the second via 301. This reduces the movement of at least one of the floating metal blocks 2061c and 2061d relative to the dielectric layer during deformation of the electrical connection substrate 20, thereby increasing the structural strength of the electrical connection substrate 20. This also reduces coupling with other metal structures caused by the movement of the floating metal blocks, thus minimizing the impact on the impedance continuity of the passive link.

[0137] Figures 23, 24, and 25 illustrate examples where the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 overlap. In other embodiments of this application, as shown in Figure 26, the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 can completely overlap. This allows the two layers of floating metal blocks to block the spread of cracks at the point of complete overlap, improving the effect of preventing further crack propagation. The technical effects of different layers of the third floating metal block 2061c and the fourth floating metal block 2061d are the same as described above and will not be repeated here.

[0138] The above illustration uses the example of the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 partially overlapping or completely overlapping. In other embodiments of this application, as shown in FIG27, the vertical projections of the third floating metal block 2061c and the fourth floating metal block 2061d on the first dielectric layer 2021 are spliced ​​together. That is, the edge of the vertical projection of the third floating metal block 2061c on the first dielectric layer 2021 can overlap with the edge of the vertical projection of the fourth floating metal block 2061d on the first dielectric layer 2021, so that the positions of the third floating metal block 2061c and the fourth floating metal block 2061d can be spliced ​​together.

[0139] For example, the floating metal pattern 206 shown in Figure 27 may include multiple floating metal blocks (e.g., fan-shaped floating metal blocks) arranged in a ring around the first pad 204. In the above floating metal pattern, two adjacent floating metal blocks may be the third floating metal block 2061c and the fourth floating metal block 2061d, respectively. In this case, since the third floating metal block 2061c and the fourth floating metal block 2061d are on different layers and are spliced ​​(or overlapped), not only can the coupling between the third floating metal block 2061c and the fourth floating metal block 2061d be reduced, but the floating metal blocks can also be arranged around the first pad 204. This can reduce the impact on the continuity of passive link impedance while increasing the probability that the floating metal pattern 206 is located on the crack propagation path, thereby reducing the probability of crack propagation in different directions.

[0140] Figure 27 illustrates an example where multiple floating metal blocks 2061 of different layers are arranged in a ring around the vertical projection of the first dielectric layer 2021 (as shown in Figure 24), with adjacent floating metal blocks, such as the third floating metal block 2061c and the fourth floating metal block 2061d, joined together. In other embodiments of this application, the positions of two adjacent floating metal blocks of different layers can overlap. Furthermore, the second via 301 as shown in Figure 24 can be provided between the two overlapping floating metal blocks. The technical effects of the overlapping floating metal blocks of different layers and the second via 301 are the same as described above and will not be repeated here.

[0141] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An electrical connection substrate, characterized in that, include: A multilayer metal layer includes a first surface metal layer, at least one first intermediate metal layer, a second intermediate metal layer, and a second surface metal layer stacked sequentially; wherein the second intermediate metal layer includes metal traces, and a corresponding dielectric layer is provided between adjacent metal layers in the multilayer metal layer; A first via penetrates the first surface metal layer and the at least one first intermediate metal layer, as well as the dielectric layer between the first surface metal layer and the second intermediate metal layer; a first end of the first via is electrically connected to the metal trace. Wherein, the first surface metal layer includes a first pad, the first pad being electrically connected to the second end of the first via; a corresponding anti-pad is provided in the first surface metal layer around the first pad, and a corresponding anti-pad is provided around the first pad on any one of the at least one first intermediate metal layers for its vertical projection. At least one first intermediate metal layer includes a floating metal pattern, and the floating metal pattern is located within an anti-pad in the first intermediate metal layer; there is no metal connection between the metal portion of the first intermediate metal layer having the floating metal pattern other than the floating metal pattern and between the floating metal pattern and the first via.

2. The electrical connection substrate according to claim 1, characterized in that, The dielectric layer is a first dielectric layer; The vertical projection of the floating metal pattern on the first dielectric layer overlaps with the edge of the vertical projection of the first pad on the first dielectric layer.

3. The electrical connection substrate according to claim 1 or 2, characterized in that, The dielectric layer is a first dielectric layer; The vertical projection of the floating metal pattern on the first dielectric layer overlaps with the vertical projection of the metal portion of the first surface metal layer (excluding the first pad) on the first dielectric layer toward the edge of the first via.

4. The electrical connection substrate according to any one of claims 1-3, characterized in that, The dielectric layer is a first dielectric layer; The vertical projection of the floating metal pattern on the first dielectric layer does not overlap with the vertical projection of the metal trace on the first dielectric layer.

5. The electrical connection substrate according to claim 4, characterized in that, The floating metal pattern includes a first metal ring, the vertical projection of the first metal ring on the first dielectric layer is arranged around the circumference of the vertical projection of the first pad on the first dielectric layer; a notch is formed on the first metal ring, the notch penetrates the inner and outer ring surfaces of the first metal ring; The vertical projection of the metal trace onto the first dielectric layer is located within the range of the vertical projection of the notch onto the first dielectric layer.

6. The electrical connection substrate according to any one of claims 1-3, characterized in that, The dielectric layer is a first dielectric layer; At least one of the floating metal patterns includes a plurality of floating metal blocks spaced apart, the vertical projections of the plurality of floating metal blocks on the first dielectric layer being arranged in a ring around the vertical projection of the first pad on the first dielectric layer.

7. The electrical connection substrate according to claim 6, characterized in that, The floating metal pattern includes an adjacent first floating metal block and a second floating metal block; The vertical projection of the metal trace on the first dielectric layer is located between the vertical projection of the first floating metal block on the first dielectric layer and the vertical projection of the second floating metal block on the first dielectric layer.

8. The electrical connection substrate according to any one of claims 1-3, characterized in that, The dielectric layer is a first dielectric layer; The multilayer metal layer includes at least two first intermediate metal layers; the floating metal pattern of the at least two first intermediate metal layers each includes at least one floating metal block.

9. The electrical connection substrate according to claim 8, characterized in that, The vertical projections of the plurality of floating metal blocks on the first dielectric layer of different layers are arranged in a ring around the vertical projection of the first pad on the first dielectric layer.

10. The electrical connection substrate according to claim 8 or 9, characterized in that, Two adjacent floating metal blocks on different layers are the third floating metal block and the fourth floating metal block, respectively. The vertical projections of the third and fourth floating metal blocks on the first dielectric layer at least partially overlap or are spliced ​​together.

11. The electrical connection substrate according to claim 10, characterized in that, The electrical connection substrate further includes a second via; the second via penetrates the metal layer and the dielectric layer between the third floating metal block and the fourth floating metal block; a first end of the second via is connected to the third floating metal block, and a second end of the second via is connected to the fourth floating metal block; The vertical projection of the second via on the first dielectric layer overlaps with the vertical projections of the third floating metal block and the fourth floating metal block on the first dielectric layer.

12. The electrical connection substrate according to claim 8 or 9, characterized in that, Two adjacent floating metal blocks on different layers are the third floating metal block and the fourth floating metal block, respectively. The vertical projection of the metal trace on the first dielectric layer is located between the vertical projection of the third floating metal block on the first dielectric layer and the vertical projection of the fourth floating metal block on the first dielectric layer.

13. The electrical connection substrate according to claim 6 or 9, characterized in that, The vertical projection of the floating metal block onto the first dielectric layer is fan-shaped; the fan shape has a first arc edge and a second arc edge. The first arc edge is away from the first via, and the second arc edge is towards the first via; the arc length of the first arc edge is greater than the arc length of the second arc edge.

14. The electrical connection substrate according to any one of claims 1-4, characterized in that, The dielectric layer is a first dielectric layer; the floating metal pattern includes a second metal ring, the vertical projection of the second metal ring on the first dielectric layer being arranged around the circumference of the vertical projection of the first pad on the first dielectric layer.

15. The electrical connection substrate according to any one of claims 1-14, characterized in that, The at least one first intermediate metal layer includes a lower first intermediate metal layer and an upper first intermediate metal layer stacked together, wherein the upper first intermediate metal layer is located on the side of the lower first intermediate metal layer that is away from the first surface metal layer; no metal layer is disposed between the lower intermediate metal layer and the first surface metal layer, or between the lower intermediate metal layer and the upper intermediate metal layer. At least the upper intermediate metal layer includes the floating metal pattern.

16. The electrical connection substrate according to any one of claims 1-15, characterized in that, The electrical connection substrate is a packaging substrate, a circuit board, or a redistribution layer.

17. A chip packaging structure, characterized in that, include: chip; The electrical connection substrate as described in any one of claims 1-16, wherein the electrical connection substrate is a packaging substrate; and the chip is disposed on the electrical connection substrate.

18. The chip packaging structure according to claim 17, characterized in that, The chip packaging structure also includes a first interconnect structure; The first interconnect structure is disposed on one side of the first pad of the electrical connection substrate, and the first interconnect structure is electrically connected to the first pad; The chip is disposed on the side of the electrical connection substrate opposite to the first interconnect structure, and the chip is electrically connected to the metal traces of the electrical connection substrate.

19. The chip packaging structure according to claim 17, characterized in that, The chip is disposed on one side of the first pad of the electrical connection substrate, and the chip is electrically connected to the first pad.

20. An electronic device, characterized in that, include: Circuit board; The chip packaging structure as described in any one of claims 17-19, wherein the chip packaging structure is disposed on the circuit board and is electrically connected to the circuit board.

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