Micro-display chip based on multilayer stacking and manufacturing method therefor

Abstract

The present invention relates to a micro-display chip based on multi-layer stacking and a manufacturing method therefor. The micro-display chip comprises a driving wafer, a first pixel layer, and a second pixel layer; anode contacts are provided on the driving wafer; the first pixel layer is stacked on the driving wafer in a Z direction, anode connectors and auxiliary pixels are provided in the first pixel layer, and each anode connector passes through one auxiliary pixel and is then electrically connected to a corresponding anode contact; the second pixel layer is stacked on the first pixel layer in the Z direction, sub-pixels corresponding to the anode connectors are provided in the second pixel layer, and the sub-pixels in the second pixel layer are electrically connected to the corresponding anode connectors in the first pixel layer. The present invention also relates to a manufacturing method for the micro-display chip. The manufacturing method of the present invention is simple and convenient to operate, and effectively shortens the manufacturing period of the display chip.

Description

Multilayer stacked microdisplay chip and its fabrication method

[0001] Priority information: This application claims priority to Chinese Patent Application No. 2024110133978, filed on July 26, 2024, and Chinese Patent Application No. 2024107890402, filed on June 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of semiconductor technology, and in particular to a microdisplay chip based on multilayer stacking and its fabrication method. Background Technology

[0003] In the field of LED displays, micro-display technology has seen widespread development in recent years, especially Micro-LED display technology. It boasts advantages such as high efficiency, low power consumption, high density, and high stability, and is considered one of the most promising next-generation display and light-emitting devices. Micro-LED display technology is now widely used in near-eye display terminal products, including virtual reality (VR), augmented reality (AR), and mixed reality (MR). Existing micro-display chips typically have multiple pixel units arranged in an array in their display area. To further reduce the horizontal size of micro-display chips and increase pixel density, existing technologies can set the chips in a vertically stacked multi-layer structure, with each layer containing light-emitting pixel units. In this multi-layer structure, as shown in Figure 1, the upper-layer pixel units need to be connected to the anode of the driving wafer 10 through the lower-layer anode connector 306. To configure the anode connector 306, the layer containing the anode connector generally needs to be specially prepared to reserve space for the anode connector, avoiding the pixel units. This preparation method is cumbersome, cannot utilize the original single-layer pixel structure for stacking, increases the display chip preparation cycle, and cannot meet production requirements. Summary of the Invention

[0004] Therefore, the technical problem to be solved by the present invention is to overcome the defects of the existing technology in which the fabrication of multi-layer display chips is cumbersome and the fabrication cycle is long.

[0005] To address the aforementioned technical problems, this invention provides a microdisplay chip based on multilayer stacking, comprising:

[0006] A driving wafer, wherein an anode contact is provided on the driving wafer;

[0007] A first pixel layer is stacked on the driving wafer along the Z direction. The first pixel layer is provided with an anode connector and an auxiliary pixel. The anode connector passes through one of the auxiliary pixels and is electrically connected to the corresponding anode contact.

[0008] The second pixel layer is stacked on the first pixel layer along the Z direction. The second pixel layer has sub-pixels corresponding to the anode connectors. The sub-pixels in the second pixel layer are electrically connected to the corresponding anode connectors in the first pixel layer.

[0009] In one embodiment of the present invention, an anode hole is provided on the auxiliary pixel through which the anode connector penetrates, the anode hole is filled with the anode connector, and the cross-sectional area of ​​the portion of the anode hole that is relatively far away from the driving wafer is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer.

[0010] In one embodiment of the present invention, the anode hole is a cone shape with a cross-sectional area increasing toward the side away from the driving wafer, and the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90° to 120°.

[0011] In one embodiment of the present invention, each sub-pixel and auxiliary pixel includes a pixel body, and each pixel body is provided with a bonding metal member on the side near the driving wafer. The bonding metal member of the sub-pixel in the second pixel layer is electrically connected to the corresponding anode connector in the first pixel layer.

[0012] In one embodiment of the present invention, the driving wafer is further provided with a cathode contact, the first pixel layer and the second pixel layer both include an insulating body, the pixel body in the first pixel layer and the second pixel layer are all located inside the insulating body, the outer side of each pixel body is covered with an insulating passivation layer, the bonding metal member is located inside the insulating passivation layer, the upper part of the insulating passivation layer has an opening, the outer side of the insulating passivation layer of the sub-pixel is covered with a common cathode layer, the pixel body of the sub-pixel is electrically connected to the common cathode layer through the opening, and the common cathode layer is used to electrically connect with the cathode contact.

[0013] In one embodiment of the present invention, each pixel body includes a P-type semiconductor layer, an active layer and an N-type semiconductor layer arranged sequentially along the Z direction. The bonding metal element is disposed on the side of the P-type semiconductor layer near the driving wafer. The N-type semiconductor layer of the sub-pixel is electrically connected to the common cathode layer through the opening.

[0014] In one embodiment of the present invention, a cathode connector is further provided in the first pixel layer, the cathode connector passes through another auxiliary pixel and is electrically connected to the cathode contact, and the common cathode layer in the second pixel layer is electrically connected to the cathode connector.

[0015] In one embodiment of the present invention, a third pixel layer is further included, which is stacked on the second pixel layer along the Z direction. The third pixel layer is provided with sub-pixels, and the second pixel layer is also provided with auxiliary pixels. The common cathode layer in the third pixel layer is electrically connected to the cathode contact after passing through the corresponding auxiliary pixels in the second pixel layer and the first pixel layer in sequence through a cathode connector.

[0016] In one embodiment of the present invention, a third pixel layer is further included, which is stacked on the second pixel layer along the Z direction. The third pixel layer is provided with sub-pixels, and the second pixel layer is also provided with auxiliary pixels. The sub-pixels in the third pixel layer are electrically connected to the corresponding anode contacts after passing through the corresponding auxiliary pixels in the second pixel layer and the first pixel layer in sequence via an anode connector.

[0017] In one embodiment of the present invention, the pixel body is trapezoidal or cylindrical.

[0018] In one embodiment of the present invention, sub-pixels are also provided in the first pixel layer.

[0019] In one embodiment of the present invention, the light emitted by the sub-pixels in the first pixel layer and the second pixel layer are different.

[0020] In one embodiment of the present invention, a color transfer element is further provided in the second pixel layer, and an excitation pixel is provided in the first pixel layer. Each color transfer element corresponds to an excitation pixel, and the color transfer element is located on the light emission path of the corresponding excitation pixel.

[0021] In one embodiment of the present invention, the light-emitting color of the sub-pixel in the second pixel layer is different from the light-emitting color of the color transfer element.

[0022] In one embodiment of the present invention, the second pixel layer is provided with filling holes, and each filling hole is filled with the color transfer element.

[0023] In one embodiment of the present invention, an insulating layer is formed on the inner wall of the filling hole, the insulating layer being a metal reflective layer or a light-absorbing layer.

[0024] In one embodiment of the present invention, the thickness of the insulating layer is 50 nm to 2 μm.

[0025] This invention also relates to a method for fabricating a microdisplay chip based on multilayer stacking, comprising,

[0026] Step M1: Prepare a driving wafer, on which anode contacts are provided;

[0027] Step M2: A first pixel layer and a second pixel layer are stacked sequentially along the Z direction on the driving wafer, such that the first pixel layer is provided with an anode connector and an auxiliary pixel, the anode connector passes through one of the auxiliary pixels and is electrically connected to the corresponding anode contact, and the second pixel layer is provided with a sub-pixel corresponding to the anode connector, the sub-pixel in the second pixel layer and the corresponding anode connector in the first pixel layer are electrically connected.

[0028] The technical solution of the present invention has the following advantages compared with the prior art:

[0029] The microdisplay chip based on multilayer stacking and its fabrication method described in this invention are easier to fabricate, simpler to fabricate, and more convenient to operate, effectively shortening the fabrication cycle of the display chip. Attached Figure Description

[0030] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0031] Figure 1 is a schematic diagram of the structure of a display chip in the prior art;

[0032] Figure 2 is a comparative diagram of trapezoidal pixels and hemispherical pixels;

[0033] Figure 3 is a schematic diagram of the internal structure of a microdisplay chip based on multilayer stacking according to the present invention;

[0034] Figure 4 is a magnified view of part G in Figure 3;

[0035] Figure 5 is a partial flowchart of the chip fabrication process of the present invention;

[0036] Figure 6 is a flowchart of the preparation process of the structure shown in Figure 3;

[0037] Figure 7 is a schematic diagram of the internal structure of the second type of microdisplay chip based on multilayer stacking according to the present invention;

[0038] Figure 8 is a schematic diagram of the internal structure of the third type of microdisplay chip based on multilayer stacking according to the present invention;

[0039] Figure 9 is a schematic diagram of the internal structure of the fourth type of microdisplay chip based on multilayer stacking according to the present invention;

[0040] Figure 10 is a schematic diagram of the internal structure of the fifth type of microdisplay chip based on multilayer stacking according to the present invention;

[0041] Figure 11 is a schematic diagram (top view) of the arrangement of the common cathode layer of the present invention;

[0042] Explanation of reference numerals in the accompanying drawings: 10, driving wafer; 101, anode contact; 102, cathode contact; 20, sub-pixel; 201, pixel body; 2011, P-type ohmic contact layer; 2012, P-type semiconductor layer; 2013, active layer; 2014, N-type semiconductor layer; 2015, N-type ohmic contact layer; 30, first pixel layer; 301, insulating body; 302, bonding layer; 3021, bonding metal part; 303, insulating passivation layer; 3031, opening; 304, common cathode layer; 3041, auxiliary hole; 3042, first connection end; 3043, transition portion; 305, anode hole; 306, anode connector; 307, cathode hole; 308, cathode connector; 40, second pixel layer; 401, filling hole; 402, insulating layer; 50, auxiliary pixel; 60, excitation pixel; 70. Color transfer element; 80. Compound semiconductor; 801. Substrate; 90. Lens; 100. Third pixel layer. Detailed Implementation

[0043] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the present disclosure or its application or use.

[0044] In the description of this invention, it should be understood that the terms "vertical," "upper," "lower," "top," "side," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0045] The structure of this embodiment will be further described below with reference to Figures 2-8.

[0046] It should be noted that, for ease of description, the microdisplay chip in this invention has mutually perpendicular Z and X directions, wherein the Z direction is generally the direction away from the driving wafer. In this invention, "up" and "down" are relative terms in the Z direction, and similarly, "top" and "bottom" or "high" and "low" are also relative terms in the Z direction.

[0047] Example 1

[0048] Referring to Figures 3-7, this embodiment discloses a microdisplay chip based on multi-layer stacking, including a driving wafer 10, a first pixel layer 30 and a second pixel layer 40. The driving wafer 10 has a driving circuit inside, which is used to control the light emission of sub-pixels 20 in the pixel layer. The driving wafer 10 can be a CMOS driving wafer.

[0049] An anode contact 101 is provided on the driver wafer 10;

[0050] The first pixel layer 30 is stacked on the driving wafer 10 along the Z direction. The first pixel layer 30 is provided with an anode connector 306 and an auxiliary pixel 50. The anode connector 306 passes through an auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101.

[0051] The second pixel layer 40 is stacked on the first pixel layer 30 along the Z direction. The second pixel layer 40 is provided with a sub-pixel 20 corresponding to the anode connector 306. The sub-pixel 20 in the second pixel layer 40 is electrically connected to the corresponding anode connector 306 in the first pixel layer 30, which means that the sub-pixel 20 in the second pixel layer 40 is electrically connected to the anode contact 101 of the driving wafer 10 through the corresponding anode connector 306 in the lower layer.

[0052] The auxiliary pixel 50 in the above structure can be an existing pixel in the first pixel layer 30. This pixel can be used directly as an auxiliary pixel 50. When using it, it is only necessary to make the anode connector 306 in the first pixel layer 30 pass through an auxiliary pixel 50 and then electrically connect it to the corresponding anode contact 101 on the driving wafer 10. This method can avoid re-fabrication of the first pixel layer 30 and can directly use the original single-layer monochrome pixel product. That is, the second and higher pixel layers can be directly superimposed on the original single-layer product. The preparation method is faster and can reduce the cost of special and separate preparation of the first pixel layer 30. The operation is simpler and more convenient, and the preparation cycle of the display chip is shortened.

[0053] It should be noted that after the auxiliary pixel 50 is penetrated by the anode connector 306, the auxiliary pixel 50 cannot emit light normally and is only used as a connector.

[0054] In some embodiments, the top length (X direction) of the anode hole 305 is greater than the bottom length.

[0055] In some embodiments, an anode hole 305 is provided on the auxiliary pixel 50 through which the anode connector 306 penetrates, and the anode hole 305 is filled with an anode metal material to form the anode connector 306;

[0056] In some embodiments, the cross-sectional area of ​​the portion of the anode hole 305 that is relatively far from the driving wafer 10 is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer 10. This cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 305. That is, the anode hole has a shape that is wider at the top and narrower at the bottom, for example, it can be conical or Y-shaped.

[0057] In some preferred embodiments, as shown in Figure 8, the anode hole 305 is tapered with a cross-sectional area that increases toward the side away from the driving wafer. The aforementioned cross-sectional area refers to the area of ​​the cross section (section) obtained by cutting the anode hole with a plane perpendicular to the axis of the anode hole 305. The inclination angle φ of the inner wall of the anode hole 305 relative to the top surface of the driving wafer 10 is 90° to 120°.

[0058] The shape of the anode connector 306 is adapted to the shape of the anode hole 305, so that the anode connector 305 also has a structure that is wider at the top and narrower at the bottom. When the bottom length is the same, this shape can produce a thicker anode connector compared to the structure that is narrower at the top and wider at the bottom, thereby enhancing the anode electrical transmission capability.

[0059] In one embodiment, the length of the top end of the anode connector 306 in the X direction is greater than the length of the bottom end, that is, it presents a structure that is wider at the top and narrower at the bottom. When the length of the bottom end is the same, this shape structure can obtain a thicker anode connector 306 compared with the structure that is narrower at the top and wider at the bottom, thereby enhancing the anode electrical transmission capability.

[0060] In some embodiments, each sub-pixel 20 and auxiliary pixel 50 includes a pixel body 201. Each pixel body 201 is provided with a bonding metal member 3021 on the side near the driving wafer 10. The bonding metal member 3021 of the sub-pixel 20 in the second pixel layer 40 is electrically connected to the corresponding anode connector 306 in the first pixel layer 30. That is, the bonding metal member 3021 of the sub-pixel 20 in the second pixel layer 40 is electrically connected to the anode contact 101 of the driving wafer 10 through the anode connector 306.

[0061] Understandably, if the first pixel layer 30 is the bottom pixel layer and the first pixel layer 30 also has a sub-pixel 20, then the bonding metal part 3021 of the sub-pixel 20 can be directly electrically connected to the anode contact 101 of the driving wafer 10 through its bonding metal part 3021.

[0062] In some implementations, a cathode contact 102 is also provided on the driving wafer 10. The first pixel layer 30 and the second pixel layer 40 both include an insulating body 301. The pixel bodies 201 in the first pixel layer 30 and the second pixel layer 40 are all located inside the insulating body 301. Each pixel body 201 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031.

[0063] In each sub-pixel 20, the insulating passivation layer 303 of the pixel body 201 of the sub-pixel 20 is covered with a common cathode layer 304. The pixel body 201 of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 102 to realize the cathode connection between the sub-pixel 20 and the driving wafer 10.

[0064] Understandably, in the auxiliary pixel 50, the common cathode layer 304 may not be covered on the outside of the insulating passivation layer 303 of the pixel body 201 of the auxiliary pixel 50, or the common cathode layer 304 may be removed, in order to avoid short circuit between the common cathode layer 304 and the anode connector 306 in the auxiliary pixel 50. The anode connector 306 in the auxiliary pixel 50 may pass through the opening 3031 of the insulating passivation layer 303 and penetrate the auxiliary pixel.

[0065] Additionally, if the common cathode layer 304 still covers the outside of the insulating passivation layer 303 of the auxiliary pixel 50, an auxiliary hole 3041 for the anode connector 306 to pass through can be provided on the common cathode layer 304. In this case, the anode connector 306 needs to pass through the auxiliary hole 3041 of the common cathode layer 304 of the auxiliary pixel and the opening 3031 of the insulating passivation layer 303 in sequence, and then pass through the pixel body 201 and be electrically connected to the anode contact 101 of the driving wafer 10. In order to avoid the anode connector 306 from contacting the common cathode layer 304 outside the auxiliary pixel 50, an auxiliary hole 3041 is provided on the common cathode layer 304 outside the pixel body of the auxiliary pixel 50 for the anode connector 306 to pass through, as shown in stage d in Figure 6. The length L4 of the auxiliary hole 3041 in the X direction is greater than the length L5 of the opening 3031 of the top insulating passivation layer 303 of the auxiliary pixel 50.

[0066] As shown in Figure 4, each pixel body 201 includes a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction. The active layer 2013 is used to emit light. Each P-type semiconductor layer 2012 has a bonding metal element 3021 on the side near the driving wafer 10. The N-type semiconductor layer of the sub-pixel 20 is electrically connected to the common cathode layer 304 through the opening 3031 of the insulating passivation layer. The common cathode layer 304 is used to be electrically connected to the cathode contact 102. The P-type semiconductor layer of the sub-pixel 20 is used to be electrically connected to the anode contact 101 through the bonding metal element 3021.

[0067] The bonding metal part 3021 can correspond one-to-one with the anode contact 101, or multiple anode contacts 101 can correspond to one bonding metal part 3021.

[0068] In some embodiments, the pixel body 201 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, and an N-type semiconductor layer 2014 arranged sequentially along the Z direction;

[0069] The active layer 2013 is used to emit light. Each P-type semiconductor layer 2012 near the driving wafer 10 has a bonding metal element 3021. A P-type ohmic contact layer 2011 is provided between the P-type semiconductor layer 2012 and the bonding metal element 3021 to achieve better ohmic contact. This allows the P-type semiconductor layer 2012 of the sub-pixel 20 to be electrically connected to the corresponding anode contact 101 via the bonding metal element 3021, thus achieving anode connection. The N-type semiconductor layer of the sub-pixel 20 is exposed at the opening 3031, and the exposed portion is electrically connected to the common cathode layer 304. The common cathode layer 304 is used to connect to the cathode contact 102 of the driving wafer 10, thus achieving cathode connection. The insulating passivation layer 303 is used to insulate and isolate the N-type semiconductor layer 2014 and the P-type semiconductor layer 2012 in the pixel body 201 to prevent short circuits.

[0070] In some embodiments, the thickness of the P-type ohmic contact layer 2011 is 10 nm to 300 nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as AuBe or AnZn.

[0071] In some embodiments, the thickness of the insulating passivation layer 303 is 30nm to 500nm to better ensure insulation and passivation capabilities.

[0072] In some embodiments, the thickness of the common cathode layer 304 is 50nm to 500nm to maximize its transmittance while ensuring current spread capability. The thicker the common cathode layer 304 is, the better the current spread, but the lower the transmittance, which will cause greater light loss and increase the processing difficulty. If the thickness is too thin, it will affect the metal current spread capability.

[0073] In some embodiments, as shown in Figure 7, the common cathode layer 304 in the second pixel layer 40 can be laid as a whole layer, and each sub-pixel in this layer is electrically connected to the common cathode layer 40. The top surface of the N-type semiconductor layer of the pixel body 201 in each sub-pixel is completely covered by the common cathode layer 304. In other embodiments, only a part of the top surface of the N-type semiconductor layer of the sub-pixel is in contact with the common cathode layer, while the other part is still exposed, as shown in Figure 11. In this case, a conductive first connection terminal 3042 can be provided on the common cathode layer 304 corresponding to each sub-pixel, and the first connection terminal 3042 is in contact with a part of the top surface of the N-type semiconductor layer of the corresponding sub-pixel.

[0074] Figure 11 illustrates different configurations of the common cathode layer connection terminals of the three sub-pixels. Multiple circumferentially arranged first connection terminals 3042 can be provided at the common cathode layer 304 corresponding to the sub-pixel to better ensure the stability of electrical contact. Alternatively, a conductive transition portion 3043 can be provided between two opposing first connection terminals 3042, allowing them to connect through the transition portion 3043, further ensuring the stability of the cathode connection and enhancing cathode current conduction. In some embodiments, a cathode connector 308 is also provided in the first pixel layer 30. The cathode connector 308 passes through another auxiliary pixel 50 and is electrically connected to the cathode contact 102. The common cathode layer 304 in the second pixel layer 40 is electrically connected to the cathode connector 308.

[0075] A cathode hole 307 can be provided on the auxiliary pixel 50 where the cathode connector 308 needs to be set, and cathode metal material can be filled into the cathode hole 307 to form the cathode connector 308. The structure of the cathode connector 308 is the same as that of the anode connector 306, and will not be described in detail here.

[0076] For example, as shown in Figure 3, the first pixel layer 30 has two auxiliary pixels 50 and three sub-pixels 20 arranged in it. One of the auxiliary pixels 50 is provided with an anode connector 306, and the other auxiliary pixel 50 is provided with a cathode connector 308. The second pixel layer 40 has one sub-pixel 20. As shown in Figure 7, the first pixel layer 30 has four auxiliary pixels 50 and one sub-pixel 20 arranged in it. Three of the auxiliary pixels 50 are provided with an anode connector 306, and the other auxiliary pixel 50 is provided with a cathode connector 308. The second pixel layer 40 has three sub-pixels 20.

[0077] In some implementations, the pixel body 201 is trapezoidal or cylindrical.

[0078] As shown in Figure 3, the pixel body 201 is trapezoidal or cylindrical. Compared to pixels with hemispherical or semi-ellipsoidal structures, trapezoidal or cylindrical pixels can effectively increase the pixel's light-emitting area, thereby increasing the light-emitting intensity. Pixels generally have an active layer 2013 to emit light. As can be seen from Figure 2, with the same bottom size, the active layer area (the entire shaded area) of the trapezoidal pixel is larger than the active layer area (the shaded area inside the hemisphere) of the hemispherical pixel, thus effectively increasing the light-emitting intensity. Similarly, cylindrical pixels, compared to hemispherical pixels, can also increase the area of ​​the active layer 2013, thereby effectively increasing the light-emitting intensity.

[0079] In some embodiments, as shown in stage d of FIG6, the height D of the pixel body 201 in the Z direction is 0.3um to 5um; preferably, D is 0.3um to 1.5um; wherein, the height of the pixel body 201 is the distance between its P-type semiconductor layer 2012 and N-type semiconductor layer 2014 (including the thickness of the P-type semiconductor layer 2012 and N-type semiconductor layer 2014 themselves).

[0080] Furthermore, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 45° to 135°; it can be understood that the sidewall of the pixel body 201 here refers to the wall between the top and bottom surfaces of the pixel body 201.

[0081] The aforementioned tilt angle can reduce total internal reflection and facilitate light extraction. Exceeding this range will reduce light extraction efficiency. In addition, due to the limited horizontal space, a certain amount of space needs to be reserved for subsequent processes. If the tilt angle is too small, the bottom surface of the pixel will occupy too much horizontal space, which will increase the difficulty of pixel spacing arrangement.

[0082] Preferably, the tilt angle θ of the sidewall of the pixel body 201 relative to the driving wafer 10 is 75° to 105°, which has the best light extraction efficiency and the best pixel pitch design.

[0083] Furthermore, sub-pixels 20 are also provided in the first pixel layer 30.

[0084] In one approach, the emitted light color of sub-pixels 20 in the first pixel layer 30 and the second pixel layer 40 can be the same to achieve a multi-layer monochrome setting.

[0085] In another approach, the sub-pixels 20 in the first pixel layer 30 and the second pixel layer 40 emit different colors of light to achieve multi-layer, multi-color settings. For example, as shown in Figure 3, the sub-pixels 20 in the first pixel layer 30 emit red light and are arranged in 3 units, while the sub-pixels 20 in the second pixel layer 40 emit green light and are arranged in 1 unit. Alternatively, as shown in Figure 7, the sub-pixels 20 in the first pixel layer 30 emit green light and are arranged in 1 unit, while the sub-pixels 20 in the second pixel layer 40 emit red light and are arranged in 3 units. In actual operation, the specific pixel layer in which the different colored sub-pixels are located and the number of units can be selected as needed and are not limited here.

[0086] Based on the two pixel layers mentioned above, other pixel layers can be stacked to form a three-layer or higher arrangement. As shown in Figure 9, a total of three pixel layers are set, namely the first pixel layer 30, the second pixel layer 40, and the third pixel layer 100. These three pixel layers are stacked sequentially along the Z direction. Each layer is provided with sub-pixels. The emission colors of the sub-pixels in the three pixel layers can all be different to achieve a three-color configuration.

[0087] In the upper pixel layer, the anode connector 306 can penetrate multiple auxiliary pixels in the lower layer and be electrically connected to the corresponding anode contact 101, as shown in Figure 9. The third pixel layer 100 is stacked on the second pixel layer 40 along the Z direction. The third pixel layer 100 has sub-pixels, and the second pixel layer 40 also has auxiliary pixels 50. The sub-pixels in the third pixel layer 100 are electrically connected to the corresponding anode contact 101 through the anode connector 306, which penetrates two auxiliary pixels in the two layers below. Similarly, the cathode connector 308 can also penetrate multiple auxiliary pixels below and be electrically connected to the cathode contact 102, as shown in Figure 9. The common cathode layer in the third pixel layer 100 is electrically connected to the cathode contact 102 through the corresponding auxiliary pixels in the two layers below in sequence via a cathode connector 308.

[0088] In other embodiments, sub-pixels in the third pixel layer 100 can be sequentially connected to corresponding anode contacts 101 via anode connectors 306 in the layers below. Each anode connector in a pixel layer penetrates the corresponding auxiliary pixel. Anode connectors in adjacent pixel layers can be connected via conductive layers such as bonding metals, as shown in Figure 10. Both the second pixel layer 40 and the first pixel layer 30 have anode connectors 306 penetrating the auxiliary pixels. At the junction of the second pixel layer 40 and the first pixel layer 30, a P-type ohmic contact layer 2011 and a bonding metal 3021 for the second auxiliary pixel are retained, allowing the two anode connectors to be connected via this P-type ohmic contact layer 2011 and bonding metal 3021. Similarly, the common cathode layer in the third pixel layer 100 can also be sequentially connected to corresponding cathode contacts 102 via cathode connectors 308 in the layers below. Each cathode connector in a pixel layer penetrates the corresponding auxiliary pixel. Anode connectors in adjacent pixel layers can be connected via conductive layers such as bonding metals. Further details are omitted here.

[0089] Furthermore, the projections of all sub-pixels 20 onto the driving wafer 10 do not overlap, so as to minimize optical crosstalk or color noise caused by photoexcitation between sub-pixels 20, thereby controlling the light combining effect more precisely.

[0090] In some implementations, a lens 90 may also be connected to the upper part of the second pixel layer 40, with multiple sub-pixels 20 corresponding to one lens 90, or the lens 90 and the sub-pixel 20 corresponding one-to-one. This method is to better collimate the emitted light of each sub-pixel 20 and further reduce light interference.

[0091] This embodiment also discloses a method for fabricating a microdisplay chip based on multilayer stacking, including,

[0092] Step M1: Prepare a driving wafer 10 and set an anode contact 101 on the driving wafer 10;

[0093] Step M2: A first pixel layer 30 and a second pixel layer 40 are stacked sequentially along the Z direction on the driving wafer 10, such that the first pixel layer 30 is provided with an anode connector 306 and an auxiliary pixel 50, the anode connector 306 passes through an auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101, and the second pixel layer 40 is provided with a sub-pixel 20 corresponding to the anode connector 306, the sub-pixel 20 in the second pixel layer 40 and the corresponding anode connector 306 in the first pixel layer 30 are electrically connected.

[0094] In some embodiments, when the first pixel layer 30 is fabricated, an anode hole 305 is provided on the auxiliary pixel 50 through which the anode connector 306 penetrates, and the anode hole 305 is filled with anode metal material to form the anode connector 306.

[0095] In one embodiment, as shown in stage f of FIG6, after step M2, a dielectric layer is deposited on the upper part of the second pixel layer 40, and the dielectric layer is patterned and etched to form a lens 90, so that multiple sub-pixels 20 correspond to one lens 90, or each sub-pixel 20 corresponds to a lens 90, so as to better collimate the emitted light of each sub-pixel 20 and further reduce light interference.

[0096] In some implementations, step M2 includes:

[0097] Step M21: Bond a compound semiconductor 80 onto the driving wafer 10; for example, the compound semiconductor 80 can be bonded onto the driving wafer 10 through a bonding layer 302.

[0098] As shown in Figure 5, the compound semiconductor 80 includes a P-type ohmic contact layer 2011, a P-type semiconductor layer 2012, an active layer 2013, an N-type semiconductor layer 2014, and a substrate 801 arranged sequentially away from the direction of the driving wafer 10. After the compound semiconductor 80 is bonded to the driving wafer 10, the substrate 801 needs to be removed to expose the N-type semiconductor layer 2014. After removing the substrate 801, as shown in stage c of Figure 5, an N-type ohmic contact layer 2015 can also be disposed on the N-type semiconductor layer 2014.

[0099] Furthermore, the N-type ohmic contact layer 2015 has a thickness of 10nm to 300nm, and its material can be a transparent conductive film such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO), or a metal alloy film such as gold-germanium alloy (AuGe) or gold-nickel alloy (AuNi).

[0100] Preferably, the thickness of the N-type ohmic contact layer 2015 is 10nm to 100nm, so as to ensure ohmic contact while also giving it high transmittance, thereby reducing light loss.

[0101] Step M22: Pattern the compound semiconductor 80 to obtain at least one set of pixels, which includes auxiliary pixels 50. Each auxiliary pixel 50 includes a pixel body 201, and each pixel body 201 corresponds to a bonding metal element 3021. The bonding metal element 3021 can be obtained by etching the bonding layer 302.

[0102] Step M23: Deposit an insulating passivation layer 303 on the outside of the pixel body 201 of the auxiliary pixel 50, and provide an opening 3031 on the upper part of the insulating passivation layer 303;

[0103] Step M24: A through anode hole 305 is provided on the auxiliary pixel 50 where the anode connector 306 needs to be arranged. The anode hole 305 passes through the opening 3031 and is filled with anode metal material to form the anode connector 306, so that the anode connector 306 passes through the auxiliary pixel 50 and is electrically connected to the corresponding anode contact 101.

[0104] Step M25: Fill the insulating body 301 so that all pixel bodies 201 are located inside the insulating body 301, thereby obtaining the first pixel layer 30 as shown in stage d of Figure 6;

[0105] Step M26: Bond another compound semiconductor 80 to the top of the first pixel layer 30, and perform patterned etching on the compound semiconductor 80 to obtain a sub-pixel 20. The sub-pixel 20 also includes a pixel body 201. The pixel body 201 is electrically connected to the corresponding anode connector 306 through a bonding metal part 3021. Then, an insulating passivation layer 303 is deposited on the outside of the pixel body 201. An opening 3031 is provided on the upper part of the insulating passivation layer 303 to expose the N-type semiconductor layer 2014 or the N-type ohmic contact layer 2015 of the pixel body 201. A common cathode layer 304 is deposited on the outside of the insulating passivation layer 303, so that the pixel body 201 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect to the cathode contact 102. That is, the N-type semiconductor layer 2014 of the pixel body 201 is electrically connected to the cathode contact 102 through the common cathode layer 304 to achieve cathode connection.

[0106] An insulating body 301 is filled outside the common cathode layer 304, so that the pixel body 201 of this layer is located inside the insulating body 301, thereby obtaining the second pixel layer 40 as shown in stage e of FIG6.

[0107] Furthermore, during the fabrication of the first pixel layer 30, the compound semiconductor 80 is patterned and etched to obtain at least one set of pixels. In addition to auxiliary pixels 50, the set of pixels also includes sub-pixels 20. An insulating passivation layer 303 and a common cathode layer 304 are sequentially disposed on the outside of the pixel body 201 of the sub-pixel 20. The N-type semiconductor layer 2014 of the pixel body 201 of the sub-pixel 20 is electrically connected to the cathode contact 102 through the common cathode layer 304.

[0108] It is understandable that if the light emitted by sub-pixels 20 in two pixel layers is different, then the compound semiconductor 80 used in the fabrication of the two pixel layers is also different, so that the light emitted by the compound semiconductors used is different.

[0109] For example, in the compound semiconductor 80, the P-type semiconductor layer 2012 and the N-type semiconductor layer 2014 can both be made of materials such as gallium nitride (GaN), the substrate 801 can be made of materials such as gallium nitride (GaN), silicon (Si) or sapphire, and the active layer 2013 can be made of materials such as indium gallium nitride (InGaN).

[0110] In one embodiment, the insulating passivation layer 303 may be made of one or more of aluminum oxide, silicon dioxide, and silicon nitride.

[0111] In one embodiment, the insulating body 301 may be made of one or more of silicon oxide, silicon nitride, silicon carbide (SiC), silicon carbon nitride (SiCN), phosphate glass (PSG), and borosilicate glass (BPSG).

[0112] In one embodiment, the common cathode layer 304 includes one or more of indium tin oxide (ITO), indium zinc oxide (IZO), Al-doped zinc oxide (AZO), Al-doped indium tin oxide, Ag-doped indium tin oxide, and Au-doped indium tin oxide.

[0113] In one embodiment, the anode connector 306 may be made of one or more of aluminum, copper, and tungsten.

[0114] Furthermore, the cathode connector 308 can be made of the same material as the anode connector 306, which is a conductive material.

[0115] In one embodiment, the material of the bonding metal part 3021 can be one of Al, Au, Cu, or a stacked structure of Ni, Au, Cu and Sn, or a bonding stack of Au with In or Ge, or a bonding stack of Au with Si.

[0116] Furthermore, the aforementioned bonding metal part 3021 can adopt the following structural form: Cr2nm / Pt50nm / Ti10nm / Pt50nm / Au100nm / Sn150nm / Au50nm, wherein Cr is the adhesive layer and Pt / Ti / Pt is the barrier layer.

[0117] Example 2

[0118] Referring to Figure 8, the main difference between this embodiment and Embodiment 1 is that: a color transfer element 70 is also provided in the second pixel layer 40, and an excitation pixel 60 is provided in the first pixel layer 30. Each color transfer element 70 corresponds to an excitation pixel 60. The color transfer element 70 is located on the light emission path of the corresponding excitation pixel 60, so that the light emitted by the excitation pixel 60 is directed to the color transfer element 70 and excites the color transfer element 70 to emit light of a specific color.

[0119] Sub-pixels 20 are all electrically connected to the driving wafer 10, which has a driving circuit to control the light emission of sub-pixels 20. Understandably, excitation pixels 60 are also electrically connected to the driving wafer 10 to control the light emission of excitation pixels 60.

[0120] The structure of the excitation pixel 60 is the same as that of the sub-pixel 20. The excitation pixel 60 also includes a pixel body 201. Each pixel body 201 has a bonding metal part 3021 on the side near the driving wafer 10. The bonding metal part 3021 of the excitation pixel 60 is electrically connected to the anode contact 101 of the driving wafer 10. Each pixel body 201 is covered with an insulating passivation layer 303. The bonding metal part 3021 is located inside the insulating passivation layer 303. The upper part of the insulating passivation layer 303 has an opening 3031. The outer part of the insulating passivation layer 303 is covered with a common cathode layer 304. The pixel body 201 of the excitation pixel 60 is electrically connected to the common cathode layer 304 through the opening 3031. The common cathode layer 304 is used to electrically connect with the cathode contact 102 to realize the cathode connection between the excitation pixel 60 and the driving wafer 10.

[0121] In some implementations, the light-emitting color of sub-pixel 20 in the second pixel layer 40 is different from the light-emitting color of color transfer element 70.

[0122] In some implementations, the light emitted by sub-pixel 20 in the second pixel layer 40 is green, and the light emitted by the color converter 70 after being excited by the excitation pixel 60 is red; the light emitted by the excitation pixel 60 is also blue.

[0123] It should be noted that the light emission wavelength of the excitation pixel 60 needs to be shorter than the red light wavelength, so that the shorter wavelength light can be used to excite the color transfer element 70 to undergo color transfer and emit red light. The red light color transfer element is made of quantum dot material or red phosphor material.

[0124] Furthermore, a sub-pixel 20 is also provided in the first pixel layer 30. The light emitted by the sub-pixel 20 is blue and is emitted directly through the second pixel layer 40.

[0125] Furthermore, all pixels in the first pixel layer 30 can emit blue light to facilitate fabrication. This can be achieved by using some pixels in this layer as excitation pixels 60, some as sub-pixels 20, and others as auxiliary pixels 50. No other sub-pixels 20 are set on the light emission path above the sub-pixels 20 in the first pixel layer 30, so that blue light can be emitted through the second pixel layer 40. The light emitted through the second pixel layer 40 will then be three different colors: blue light emitted by the blue sub-pixel 20, green light emitted by the green sub-pixel 20, and red light emitted by the color converter 70, thus achieving a three-color configuration.

[0126] Similarly, a two-color configuration can also be achieved, which will not be elaborated here.

[0127] In some implementations, the red light transducer can be made of quantum dot materials, such as indium phosphide (InP); or it can be made of phosphor materials, such as fluoride-based phosphors, KSF red phosphor (K2SiF6:Mn4+), or nitride Eu2+ doped CaAlSiN3-based red phosphor, etc.

[0128] In some embodiments, the second pixel layer 40 is provided with filling holes 401, and each filling hole 401 is filled with color transfer material to form a color transfer element 70.

[0129] The material of the color transfer component 70 can be a quantum dot material or a phosphor material.

[0130] Furthermore, the filling hole 401 is formed in the insulating body 301 of the second pixel layer 40.

[0131] In some embodiments, the length Ls of the filling hole 401 along the X direction is not less than the maximum length of the excitation pixel 60 in the X direction, and the X direction is perpendicular to the Z direction. This method can provide a good light path for the excitation pixel 60 below and is less prone to light crosstalk, thereby maximizing the color conversion effect.

[0132] Furthermore, the inner wall of the filling hole 401 is inclined relative to the driving wafer 10, with an inclination angle C of 60° to 90°, to facilitate etching and ensure filling effect.

[0133] In some embodiments, an insulating layer 402 is formed on the inner wall of the filling hole 401; the insulating layer 402 is used to shield the light interference from the pixels below the non-filled space, so that the color transfer element 70 inside the filling hole 401 can have a better color transfer effect.

[0134] Among them, the insulating layer 402 is a metal reflective layer or a light-absorbing layer.

[0135] The metal reflective layer can be made of one or more metals such as Al, Ti, Pt, Au, Cr and Ni, to shield light interference through metal reflection; the light-absorbing layer can be made of light-absorbing materials such as carbon film, black glue, polycrystalline silicon, etc., to shield light interference through light absorption.

[0136] Furthermore, the thickness of the insulating layer 402 is 50nm to 2um. If the thickness is too thin, leakage is likely to occur, while if the thickness is too thick, the cost will increase.

[0137] Specifically, the required thickness for optical interference shielding can be achieved based on the different materials used, such as Al ≥ 50nm and black glue ≥ 1um.

[0138] In some implementations, a lens 90 is also connected to the upper part of the second pixel layer 40, with multiple sub-pixels 20 corresponding to one lens 90, or a one-to-one correspondence between the lens 90 and the sub-pixels 20. This method is to better collimate the emitted light of each sub-pixel 20 and further reduce light interference.

[0139] In some implementations, each color transfer element 70 also corresponds to a lens 90, or multiple color transfer elements 70 correspond to a lens 90.

[0140] The fabrication method of the microdisplay chip in this embodiment is roughly the same as that in Embodiment 1, except that the color transfer element 70 and the excitation pixel 60 need to be fabricated, which will not be described in detail here.

[0141] The microdisplay chips in the above embodiments can directly use the original pixels in the first pixel layer as auxiliary pixels. This method avoids the need to re-prepare the first pixel layer and can directly use the original single-layer pixel products. The preparation method is faster, reduces the cost of specially preparing the first pixel layer, and is simpler and more convenient to operate, thus shortening the preparation cycle of the display chip.

[0142] All the above-mentioned optional technical solutions can be combined in any way to form optional embodiments of the present invention. That is, any number of embodiments can be combined to meet the needs of different application scenarios. All of these are within the protection scope of this application and will not be described in detail here.

[0143] It should be noted that the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A microdisplay chip based on multilayer stacking, characterized in that: include, A driving wafer, wherein an anode contact is provided on the driving wafer; A first pixel layer is stacked on the driving wafer along the Z direction. The first pixel layer is provided with an anode connector and an auxiliary pixel. The anode connector passes through one of the auxiliary pixels and is electrically connected to the corresponding anode contact. The second pixel layer is stacked on the first pixel layer along the Z direction. The second pixel layer has sub-pixels corresponding to the anode connectors. The sub-pixels in the second pixel layer are electrically connected to the corresponding anode connectors in the first pixel layer.

2. The microdisplay chip based on multilayer stacking according to claim 1, characterized in that: An anode hole is provided on the auxiliary pixel through which the anode connector penetrates. The anode hole is filled with the anode connector. The cross-sectional area of ​​the portion of the anode hole that is relatively far from the driving wafer is larger than the cross-sectional area of ​​the portion that is relatively close to the driving wafer.

3. The microdisplay chip based on multilayer stacking according to claim 2, characterized in that: The anode hole is cone-shaped with a cross-sectional area that increases toward the side away from the driving wafer, and the inclination angle of the inner wall of the anode hole relative to the top surface of the driving wafer is 90° to 120°.

4. The microdisplay chip based on multilayer stacking according to claim 1, characterized in that: Each of the sub-pixels and auxiliary pixels includes a pixel body, and each pixel body has a bonding metal component on the side closest to the driving wafer. The bonding metal component of the sub-pixel in the second pixel layer is electrically connected to the corresponding anode connector in the first pixel layer.

5. The microdisplay chip based on multilayer stacking according to claim 4, characterized in that: The driving wafer is also provided with cathode contacts. The first pixel layer and the second pixel layer both include an insulating body. The pixel bodies in the first pixel layer and the second pixel layer are all located inside the insulating body. Each pixel body is covered with an insulating passivation layer. The bonding metal is located inside the insulating passivation layer. The upper part of the insulating passivation layer has an opening. The outer part of the insulating passivation layer of the sub-pixel is covered with a common cathode layer. The pixel body of the sub-pixel is electrically connected to the common cathode layer through the opening. The common cathode layer is used to electrically connect with the cathode contacts.

6. The microdisplay chip based on multilayer stacking according to claim 4, characterized in that: Each pixel body includes a P-type semiconductor layer, an active layer, and an N-type semiconductor layer arranged sequentially along the Z direction. The bonding metal element is disposed on the side of the P-type semiconductor layer near the driving wafer. The N-type semiconductor layer of the sub-pixel is electrically connected to the common cathode layer through the opening.

7. The microdisplay chip based on multilayer stacking according to claim 5, characterized in that: The first pixel layer is also provided with a cathode connector, which passes through another auxiliary pixel and is electrically connected to the cathode contact. The common cathode layer in the second pixel layer is electrically connected to the cathode connector.

8. The microdisplay chip based on multilayer stacking according to claim 7, characterized in that: It also includes a third pixel layer, which is stacked on the second pixel layer along the Z direction. The third pixel layer is provided with sub-pixels, and the second pixel layer is also provided with auxiliary pixels. The common cathode layer in the third pixel layer is electrically connected to the cathode contact after passing through the corresponding auxiliary pixels in the second pixel layer and the first pixel layer in sequence through a cathode connector.

9. The microdisplay chip based on multilayer stacking according to claim 1, characterized in that: It also includes a third pixel layer, which is stacked on the second pixel layer along the Z direction. The third pixel layer is provided with sub-pixels, and the second pixel layer is also provided with auxiliary pixels. The sub-pixels in the third pixel layer are electrically connected to the corresponding anode contacts after passing through the corresponding auxiliary pixels in the second pixel layer and the first pixel layer in sequence through an anode connector.

10. The microdisplay chip based on multilayer stacking according to claim 4, characterized in that: The pixel body is trapezoidal or cylindrical.

11. The microdisplay chip based on multilayer stacking according to claim 1, characterized in that: Sub-pixels are also set in the first pixel layer.

12. The microdisplay chip based on multilayer stacking according to claim 11, characterized in that: The sub-pixels in the first pixel layer and the second pixel layer emit different colors of light.

13. The microdisplay chip based on multilayer stacking according to claim 1, characterized in that: The second pixel layer is further provided with a color transfer component, and the first pixel layer is provided with an excitation pixel. Each color transfer component corresponds to an excitation pixel, and the color transfer component is located on the light emission path of the corresponding excitation pixel.

14. The microdisplay chip based on multilayer stacking according to claim 13, characterized in that: The light-emitting color of the sub-pixels in the second pixel layer is different from the light-emitting color of the color converter.

15. The microdisplay chip based on multilayer stacking according to claim 13, characterized in that: The second pixel layer is provided with filling holes, and each filling hole is filled with the color transfer element.

16. The microdisplay chip based on multilayer stacking according to claim 15, characterized in that: An insulating layer is formed on the inner wall of the filling hole, and the insulating layer is a metal reflective layer or a light-absorbing layer.

17. The microdisplay chip based on multilayer stacking according to claim 16, characterized in that: The thickness of the insulating layer is 50 nm to 2 μm.

18. The method for fabricating a microdisplay chip based on multilayer stacking as described in any one of claims 1-17, characterized in that: include, Step M1: Prepare a driving wafer, on which anode contacts are provided; Step M2: A first pixel layer and a second pixel layer are stacked sequentially along the Z direction on the driving wafer, such that the first pixel layer is provided with an anode connector and an auxiliary pixel, the anode connector passes through one of the auxiliary pixels and is electrically connected to the corresponding anode contact, and the second pixel layer is provided with a sub-pixel corresponding to the anode connector, the sub-pixel in the second pixel layer and the corresponding anode connector in the first pixel layer are electrically connected.

Images