Data reception method, apparatus, chip, optical module and device

Abstract

The present disclosure relates to the technical field of communications, and provides a data reception method, an apparatus, a chip, an optical module, and a device. The method comprises performing first FEC decoding processing on an acquired first sequence to obtain a second sequence, wherein the first FEC decoding processing is soft decision decoding processing; performing second FEC decoding processing on the second sequence to obtain a third sequence, wherein the second FEC decoding processing is hard decision decoding processing; and performing first FEC decoding processing on the first sequence on the basis of the third sequence to obtain a fourth sequence, wherein the fourth sequence is used to determine decoded data of the first sequence. The use of the method of the present disclosure can make cascaded FEC transmission scheme adapted to data reception over a plurality of transmission distances.

Description

Method, device, chip, optical module and equipment for data receiving

[0001] The present application claims priority from the Chinese patent application No. 202410782382.1 filed on June 17, 2024, and entitled "Method, device, chip, optical module and equipment for data receiving", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the field of communication technology, and in particular, to a method, device, chip, optical module and equipment for data receiving. BACKGROUND

[0003] With the continuous promotion of 5G, cloud computing, big data and artificial intelligence, optical communication systems are developing towards large capacity, packetization and intelligentization. Optical communication systems use the amplitude, phase, polarization or frequency of light waves to carry information. In optical communication systems, signal distortion may occur due to some reasons during transmission of optical signals, and as the transmission rate of Ethernet increases, the transmission error rate will also increase. Using forward error correction (FEC) encoding and decoding technology to correct errors in transmitted data can solve transmission errors and recover data sent by the sender device from the received data.

[0004] A cascaded FEC transmission scheme is currently proposed. The sender device and the sender processing module are connected through an attachment unit interface (AUI). The sender device performs first FEC encoding on the data to be transmitted and sends the first FEC encoded data to the sender processing module. The sender processing module performs second FEC encoding on the first FEC encoded data and transmits the second FEC encoded data to the receiver processing module through an optical fiber. The receiver processing module performs one FEC decoding on the second FEC encoded data to reduce the error introduced by the optical fiber link, and transmits the data after one FEC decoding to the receiver device through the AUI. The receiver device performs FEC decoding again to obtain the data sent by the sender device. Although the power consumption and time delay of the encoding and decoding algorithm of this scheme are relatively low, it is not suitable for long distance transmission scheme. SUMMARY

[0005] The present disclosure provides a method, device, equipment, chip, optical module and storage medium for data receiving, which can make the encoding and decoding algorithm suitable for various transmission distances. The technical solution is as follows:

[0006] In a first aspect, the present disclosure provides a method for data receiving, comprising: performing first FEC decoding processing on a first sequence to obtain a second sequence, wherein the first FEC decoding processing is soft decision decoding processing; performing second FEC decoding processing on the second sequence to obtain a third sequence, wherein the second FEC decoding processing is hard decision decoding processing; and performing the first FEC decoding processing on the first sequence according to the third sequence to obtain a fourth sequence, wherein the fourth sequence is used to determine the decoding data of the first sequence.

[0007] In the scheme shown in the present disclosure, when the transmission scheme of cascaded FEC is used at the sending end, the receiving end performs decoding by using iterative decoding when performing the first FEC decoding, at least two first FEC decoding processing and at least one second FEC decoding processing are performed, and when performing the first FEC decoding processing after the first time, the decoding result of the last second FEC decoding processing is also referred to, so that the decoding accuracy can be improved and the error codes introduced by transmission can be reduced. Moreover, the number of iterative decoding can be set according to actual needs, so that the accuracy of decoding is adapted to the transmission distance. Therefore, the method for data receiving can be suitable for various transmission distances.

[0008] In an optional manner, the first FEC decoding processing is performed on the first sequence according to the third sequence to obtain a fourth sequence, comprising: updating the first sequence according to the third sequence; and performing the first FEC decoding processing on the updated first sequence to obtain the fourth sequence.

[0009] In the scheme shown in the present disclosure, the first sequence is updated according to the third sequence, and then the first FEC decoding processing is performed.

[0010] In an optional manner, the first sequence is soft decision information corresponding to a plurality of received FEC code words, and the soft decision information of each bit in each received FEC code word is represented by m bits, and m is greater than 1.

[0011] In an optional manner, the first FEC decoding processing is Bose-Chaudhuri-Hocquenghem (BCH) soft decision decoding processing, or FEC (128, 120) soft decision decoding processing; and the second FEC decoding processing is Reed-Solomon (RS) hard decision decoding processing.

[0012] In an optional manner, before the second FEC decoding processing is performed on the second sequence, an aligment lock processing is performed on the second sequence, so as to determine the boundary of the outer code word and align the data streams of a plurality of channels.

[0013] In an optional mode, after the alignment flag locking processing is performed on the second sequence, one or more of the deskewing, channel reordering or de-channeling processing is performed on the second sequence after the alignment flag locking processing, so that the information bits belonging to one FEC codeword in the second sequence are continuous.

[0014] In an optional mode, before the first FEC decoding processing is performed on the first sequence according to the third sequence, the third sequence is subjected to channel distribution and channel ordering processing.

[0015] In an optional mode, the first sequence is the soft decision information corresponding to the received plurality of FEC codewords; and the updating the first sequence according to the third sequence comprises: if the second FEC decoding processing in which the first bit participates is successful, updating the soft decision information corresponding to the first bit in the first sequence to a specified value, the first bit being one information bit of the FEC codeword obtained by the first FEC decoding processing.

[0016] In the scheme shown in the disclosure, when the second FEC decoding processing in which a certain bit participates is successful, the soft decision information corresponding to the bit in the first sequence is updated to a specified value, the specified value being used to indicate that the decoding result of the bit is reliable, so that the soft decision information of the bit in the first sequence is not used, and soft decision information with higher decoding accuracy can be obtained.

[0017] In an optional mode, the method further comprises: if the number of times of performing the first FEC decoding processing on the first sequence reaches a target threshold, taking the fourth sequence as the decoding data of the first sequence; if the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, performing the second FEC decoding processing on the fourth sequence, taking the decoding result as the updated third sequence, and returning to perform the processing of performing the first FEC decoding processing on the first sequence according to the third sequence until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

[0018] In the scheme shown in the disclosure, when the two FEC encodings are performed at the sending end, the decoding data of the first FEC decoding processing is output at the receiving end when the iterative decoding is performed.

[0019] In an optional mode, after the fourth sequence is taken as the decoding data of the first sequence, the decoding data of the first sequence is subjected to de-interleaving processing. In this way, the de-interleaving processing is performed after the decoding data is obtained, and the anti-burst performance of the cascaded FEC transmission scheme can also be improved.

[0020] In an alternative manner, after the fourth sequence is taken as the decoded data of the first sequence, the second FEC decoding processing is performed on the decoded data of the first sequence to obtain a fifth sequence. In this way, when the receiver processing module is integrated with the receiver device, the second FEC decoding processing is also performed on the decoded data of the first sequence to obtain the final data.

[0021] In an alternative manner, the method further comprises: performing the second FEC decoding processing on the fourth sequence; if the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold, taking the result of the second FEC decoding processing on the fourth sequence as the decoded data of the first sequence; and if the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, taking the result of the second FEC decoding processing on the fourth sequence as an updated third sequence, and returning to perform the processing of performing the first FEC decoding processing on the first sequence according to the third sequence until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

[0022] In the scheme shown in the disclosure, the sender device performs one-time FEC encoding, sends the FEC encoded data to the sender processing module, the sender processing module performs one-time FEC decoding on the FEC encoded data, and then performs two-time concatenated FEC encoding. In this way, the receiver processing module iteratively decodes the output of the second FEC decoding processing.

[0023] In an alternative manner, after the decoded data corresponding to the updated third sequence is taken as the decoded data of the first sequence, the FEC encoding processing is performed on the decoded data of the first sequence to obtain a sixth sequence. In this way, the data received by the receiver device is FEC encoded data.

[0024] In an alternative manner, after the sixth sequence is obtained, the sixth sequence is subjected to interleaving processing. In this way, the anti-burst performance of the concatenated FEC transmission scheme can be improved.

[0025] In a second aspect, the disclosure provides a data receiving apparatus having the functions of the above-mentioned first aspect or any of the alternative manners of the first aspect. The apparatus comprises at least one module for implementing the method of data receiving provided in the above-mentioned first aspect or any of the alternative manners of the first aspect.

[0026] In a third aspect, the disclosure provides a chip for implementing the method of data receiving provided in the above-mentioned first aspect or any of the alternative manners of the first aspect.

[0027] In a fourth aspect, the present disclosure provides an optical module, comprising a processor and an interface for communicating with other devices, the processor being configured to perform the method for receiving data according to the first aspect or any of the optional modes of the first aspect.

[0028] In a fifth aspect, the present disclosure provides a communication device, comprising a host device and an optical module according to the fourth aspect, the optical module being configured to perform the method for receiving data according to the first aspect or any of the optional modes of the first aspect to obtain a first sequence of decoded data, and send the first sequence of decoded data to the host device.

[0029] In a sixth aspect, the present disclosure provides a computer readable storage medium, in which at least one computer instruction is stored, the computer instruction being read by a processor to cause an optical module to perform the method for receiving data according to the first aspect or any of the optional modes of the first aspect.

[0030] In a seventh aspect, the present disclosure provides a computer program product, comprising computer instructions stored in a computer readable storage medium. A processor in an optical module reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the optical module to perform the method for receiving data according to the first aspect or any of the optional modes of the first aspect. BRIEF DESCRIPTION OF DRAWINGS

[0031] Fig. 1 is a schematic diagram of a communication system according to an example embodiment of the present disclosure;

[0032] Fig. 2 is a schematic diagram of a process of data transmission according to an example embodiment of the present disclosure;

[0033] Fig. 3 is a schematic diagram of a process of data transmission according to another example embodiment of the present disclosure;

[0034] Fig. 4 is a schematic diagram of a communication system according to another example embodiment of the present disclosure;

[0035] Fig. 5 is a schematic diagram of a method for receiving data according to an example embodiment of the present disclosure;

[0036] Fig. 6 is a schematic diagram of a method for receiving data according to another example embodiment of the present disclosure;

[0037] Fig. 7 is a schematic diagram of a method for receiving data according to yet another example embodiment of the present disclosure;

[0038] Fig. 8 is a logic block diagram of iterative decoding according to an example embodiment of the present disclosure;

[0039] FIG. 9 is a flow diagram of a method of data reception according to another example embodiment of the disclosure;

[0040] FIG. 10 is a logic diagram of iterative decoding according to another example embodiment of the disclosure;

[0041] FIG. 11 is a logic diagram of performing two first FEC decoding processes according to an example embodiment of the disclosure;

[0042] FIG. 12 is a logic diagram of iterative decoding according to another example embodiment of the disclosure;

[0043] FIG. 13 is a logic diagram of decoding according to an example embodiment of the disclosure;

[0044] FIG. 14 is a diagram of second de-interleaving according to an example embodiment of the disclosure;

[0045] FIG. 15 is a logic diagram of second de-interleaving according to another example embodiment of the disclosure;

[0046] FIG. 16 is a logic diagram of de-convolution interleaving according to an example embodiment of the disclosure;

[0047] FIG. 17 is a logic diagram of a first data sub-process according to another example embodiment of the disclosure;

[0048] FIG. 18 is a logic diagram of a second data sub-process according to another example embodiment of the disclosure;

[0049] FIG. 19 is a logic diagram of interleaving according to an example embodiment of the disclosure;

[0050] FIG. 20 is a logic diagram of interleaving according to another example embodiment of the disclosure;

[0051] FIG. 21 is a logic diagram of interleaving according to another example embodiment of the disclosure;

[0052] FIG. 22 is a logic diagram of de-interleaving according to another example embodiment of the disclosure;

[0053] FIG. 23 is a logic diagram of interleaving according to another example embodiment of the disclosure;

[0054] FIG. 24 is a logic diagram of iterative decoding according to another example embodiment of the disclosure;

[0055] FIG. 25 is a logic diagram of iterative decoding according to another example embodiment of the disclosure;

[0056] FIG. 26 is a logic diagram of decoding according to another example embodiment of the disclosure;

[0057] FIG. 27 is a structural schematic diagram of a data receiving apparatus according to an example embodiment of the present disclosure;

[0058] FIG. 28 is a structural schematic diagram of an optical module according to an example embodiment of the present disclosure;

[0059] FIG. 29 is a structural schematic diagram of a communication device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] For the purpose, technical solutions and advantages of the present disclosure to be clearer, the embodiments of the present disclosure will be further described in detail below with reference to the drawings.

[0061] In the current transmission scheme of cascaded FEC, the coding algorithm and the time delay are relatively low, but it is not suitable for long distance transmission scheme.

[0062] The method for receiving data provided by the embodiments of the present disclosure can be applied to a receiving end processing module. When the receiving end processing module decodes, iterative decoding is performed to obtain decoded data sent to the receiving end device, more error codes can be corrected, and thus more reliable decoded data can be provided. Alternatively, the receiving end processing module and the receiving end device are integrated together, and the method can also be applied to the receiving end device. When the receiving end device performs first FEC decoding, iterative decoding is performed to obtain decoded data, more error codes can be corrected, and thus more reliable decoded data can be provided.

[0063] FIG. 1 is a schematic diagram of a communication system to which embodiments of the present disclosure are applied. As shown in FIG. 1, the communication system includes a sending device 01, a sending processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network, the sending device 01 and the receiving device 05 can be switches or routers, and the sending device 01 is also referred to as a client device at the sending end, and the receiving device 05 is also referred to as a client device at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client device is also referred to as a host device, a client chip, or a host chip. The connection interface between the sending device 01 and the sending processing module 02 can be connected through an AUI, and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The sending processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a long range (LR) optical module, such as a 1600LR module (a kind of coherent optical module), an extended range (ER) optical module, a Zebest range (ZR) optical module, or a ZR+ longer range optical module. In addition, the sending device 01, the sending processing module 02, the channel transmission medium 03, the receiving processing module 04, and the receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, and the specific implementation is not limited herein.

[0064] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, in the process of transmitting data from the sending device 01 to the receiving device 05, the sending device 01 performs outer code encoding (i.e. first FEC encoding, the outer code encoding mentioned hereinafter is first FEC encoding) on the data to obtain outer code encoded data including outer code codewords, and then transmits the outer code encoded data to the sending processing module 02. The sending processing module 02 performs inner code encoding (i.e. second FEC encoding, the inner code encoding mentioned hereinafter is second FEC encoding) on the outer code encoded data to obtain inner code encoded data including inner code codewords, and then transmits the inner code encoded data to the channel transmission medium 03 after sending processing (e.g. digital signal processor (DSP) framing). The channel transmission medium 03 transmits the inner code encoded data to the receiving processing module 04. The receiving processing module 04 performs receiving processing on the inner code encoded data, and then performs first iterative decoding (the first iterative decoding is inner code decoding, but not traditional inner code decoding, the iterative decoding includes at least two first FEC decoding processes and at least one second FEC decoding process, the output decoded data is the decoded data after the first FEC decoding process, the first FEC decoding process is soft decision decoding process, and the second FEC decoding process is hard decision decoding process), and transmits the first iterative decoding data to the receiving device 05. The receiving device 05 performs outer code decoding on the first iterative decoding data.

[0065] Figure 3 is a schematic diagram of another data transmission process in the communication system shown in Figure 1. As shown in Figure 3, in the process of transmitting data from the sending device 01 to the receiving device 05, the sending device 01 performs outer code encoding on the data, and then transmits the outer code encoded data to the sending processing module 02. The sending processing module 02 performs outer code decoding on the outer code encoded data to reduce the error code introduced by the connection unit interface link. The outer code decoded data is sequentially subjected to outer code encoding and inner code encoding to obtain outer code encoded and inner code encoded data. The outer code encoded data includes outer code codewords, and the outer code encoded and inner code encoded data includes inner code codewords. The outer code encoded and inner code encoded data is transmitted to the channel transmission medium 03 after being subjected to sending processing. The channel transmission medium 03 transmits the outer code encoded and inner code encoded data to the receiving processing module 04. The receiving processing module 04 performs receiving processing on the outer code encoded and inner code encoded data, and then performs second iteration decoding (the second iteration decoding includes at least two first FEC decoding processes and at least one second FEC decoding process, and the output decoded data is the decoded data after the second FEC decoding process. The first FEC decoding process is a soft decision decoding process, and the second FEC decoding process is a hard decision decoding process). The outer code decoded data is obtained. Then the outer code decoded data is subjected to outer code encoding, and the outer code encoded data is transmitted to the receiving device 05. The receiving device 05 performs outer code decoding on the outer code encoded data.

[0066] It should be understood that the "inner" in the inner code and the "outer" in the outer code are only distinguished based on the distance of the execution subject performing operation on the data relative to the channel transmission medium 03. The execution subject performing operation on the inner code is closer to the channel transmission medium 03, and the execution subject performing operation on the outer code is farther away from the channel transmission medium 03. In the embodiment of the present disclosure, since the data is transmitted from the sending device 01 to the channel transmission medium 03 through the sending processing module 02, and then transmitted from the channel transmission medium 03 to the receiving device 05 through the receiving processing module 04. The data encoded by the sending device 01 is farther away from the channel transmission medium 03 than the data encoded by the sending processing module 02, and the data decoded by the receiving device 05 is farther away from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the sending device 01 is referred to as outer code encoded data, the data encoded by the sending processing module 02 is referred to as inner code encoded data, the data decoded by the receiving device 05 is referred to as outer code decoded data, and the data decoded by the receiving processing module 04 is referred to as iteration decoded data.

[0067] The embodiments of the present disclosure do not limit the specific manners of outer code encoding and inner code encoding in the transmission scheme of concatenated FEC. For example, the sending device 01 can perform outer code encoding by using RS code, and the sending processing module 02 can perform inner code encoding by using Hamming code. For another example, the sending device 01 can perform outer code encoding by using RS code, and the sending processing module 02 can perform inner code encoding by using BCH code. The BCH code that can correct a single error is equivalent to Hamming code. For another example, the sending device 01 can perform outer code encoding by using RS code, and the sending processing module 02 can also perform inner code encoding by using Polar code.

[0068] FIG. 4 is another schematic diagram of a communication system to which the embodiments of the present disclosure are applied. As shown in FIG. 4, the communication system includes the sending device 01, the channel transmission medium 03 and the receiving device 05. The sending device 01 performs outer code encoding and inner code encoding on data, and the data after outer code encoding and inner code encoding is sent to the transmission medium 03. The receiving device 05 performs iterative decoding and outer code decoding on the data received from the transmission medium 03. Taking the communication system as a data center network for example, the sending device 01 and the receiving device 05 can be devices such as switches or routers, and the sending device 01 is also referred to as a client-side device or a host-side device at the sending end, and the receiving device 05 is also referred to as a client-side chip at the receiving end, and the channel transmission medium 03 can be an optical fiber. The client-side device is also referred to as a client-side chip or a host-side chip. The sending device 01, the channel transmission medium 03 and the receiving device 05 in the communication system can support bidirectional transmission, or can support unidirectional transmission, which is not limited here.

[0069] It should be noted that, as shown in FIGS. 2 to 4, in some specific applications, the data after inner code encoding is further subjected to sending processing, and then the data to be sent is obtained. The sending processing is different in different application scenarios. For example, when applied to a coherent scenario, the sending processing obtains a DSP frame, and the sending processing includes adding at least one sequence of a frame alignment word sequence (FAW Sequence), a training symbol sequence, a reserved symbol sequence and a pilot symbol sequence. When applied to a direct detection scenario, the sending processing includes symbol mapping and the like.

[0070] It should be noted that the above is an exemplary description of the application scenario of the data receiving method provided by the embodiments of the present disclosure, and does not constitute a limitation on the application scenario of the data receiving method. Those skilled in the art can know that with the change of business needs, the application scenario can be adjusted according to the application needs, and the embodiments of the present disclosure do not enumerate them one by one.

[0071] Next, the implementation process of the data receiving method provided by the embodiments of the present disclosure is introduced. The data receiving method is applied to a receiving end, for example, it can be implemented through the receiving end processing module 04 shown in FIG. 1, and for example, it can be implemented through the receiving end device 05 shown in FIG. 4. The following takes the application to the receiving end processing module 04 as an example for description. As shown in FIG. 5, the implementation process of the data receiving method includes steps 501 to 503.

[0072] Step 501, performing first FEC decoding processing on the obtained first sequence to obtain a second sequence, and the first FEC decoding processing is soft decision decoding processing.

[0073] Among them, the soft decision decoding processing is called soft decoding processing, the first FEC decoding processing is BCH (126, 110) soft decision decoding processing or FEC (128, 120) soft decision decoding processing, and the decoding algorithm in the first FEC decoding processing can include but is not limited to Chase algorithm or ordered statistic decoding (OSD) algorithm, and Chase is a person's name.

[0074] In the present embodiment, the receiving end processing module 04 receives the data transmitted by the channel transmission medium 03, and the receiving end processing module 04 performs receiving processing on the data to obtain a first sequence, the first sequence includes soft decision information corresponding to a plurality of received first FEC code words, the plurality of first FEC code words are initially obtained by the sending end processing module 02 by inner code encoding, but noise is introduced in the transmission process of the channel transmission medium, therefore, the received first FEC code word can also be called as a received inner code word.

[0075] The receiving end processing module 04 performs first FEC decoding processing on the first sequence, determines which bits have errors, flips the corresponding bits to correct errors, determines the decoded information bits, and thus obtains the information bits of the first FEC codeword, i.e., the information bits of the inner code codeword, after the first FEC decoding processing. For example, the first FEC decoding processing is BCH (126, 110) soft decision decoding processing, and the first FEC codeword uses BCH (126, 110), which means that the codeword length of the first FEC codeword is 126 bits, of which 110 bits are information bits and 16 bits are check bits. After performing the first FEC decoding processing on each BCH (126, 110), 110 bits of information bits corresponding to the corrected bits are output, and the 110 bits of information bits are taken as the second sequence. For another example, the first FEC decoding processing is FEC (128, 120) soft decision decoding processing, and the first FEC codeword uses FEC (128, 120), which means that the codeword length of the first FEC codeword is 128 bits, of which 120 bits are information bits and 8 bits are check bits. After performing the first FEC decoding processing on each FEC (128, 120), 120 bits of information bits corresponding to the corrected bits are output, and the 120 bits of information bits are taken as the second sequence.

[0076] It should be noted that, due to random distribution of errors, the number of error bits in each first FEC codeword is uncertain. It is possible that the received first FEC codeword at a certain moment has no errors, and no correction is performed during the first FEC decoding processing if it is determined that there are no errors, and thus the second sequence is the original information bits of the received first FEC codeword. It is also possible that the received first FEC codeword at a certain moment has many errors, which may cause the first FEC decoding processing to make a mistake and flip the bits that have no errors. In this case, the second sequence is the information bits of the first FEC codeword after the mistake correction. Or it is possible that the first FEC decoding processing fails, and no correction is performed in this case, and the second sequence is still the original information bits of the received first FEC codeword. Or it is possible that the first FEC decoding processing is correct and corrects all the error bits, and the second sequence is the information bits of the first FEC codeword after the correction. In this way, after the first FEC decoding processing, the errors that have not been corrected may still exist, and the information bits in the second sequence may still have errors and be inconsistent with the information bits sent by the sending end.

[0077] In an optional mode, the first sequence is soft decision information, which can also be referred to as soft value, and the soft decision information is corresponding to each bit of the received first FEC codeword, and for each bit in the first FEC codeword, the soft decision information corresponding to the bit includes an amplitude and a sign, the amplitude represents the reliability of the bit, and the sign represents whether the bit is 0 or 1, for example, when the sign is positive, the corresponding bit is 0, otherwise the corresponding bit is 1, or, when the sign is positive, the corresponding bit is 1, otherwise the corresponding bit is 0.

[0078] Optionally, the soft decision information of each bit is represented by m bits, and m is greater than 1.

[0079] Optionally, the soft decision information is log-likelihood ratio (LLR) information.

[0080] In an optional mode, in order to increase the burst performance of the transmission scheme of the concatenated FEC, the sender processing module 02 shown in FIG. 2 or the sender device 01 shown in FIG. 4 performs interleaving between the inner code codewords after the inner code encoding, and then sends to the channel transmission medium 03 for transmission, and correspondingly, after receiving the first sequence, performs deinterleaving processing and then executes step 501.

[0081] In an optional mode, the data receiving method is applied to a coherent scenario, and the receiving processing includes one or more of clock recovery, carrier phase recovery, equalization, symbol demodulation, DSP frame synchronization, and pilot sequence deletion, and the deinterleaving processing includes one or more of BCH deinterleaving and inverse circular shift, and the symbol demodulation is double polarization 16 quadrature amplitude modulation (DP-16QAM) demodulation, etc.

[0082] In an optional mode, the data receiving method is applied to a direct detection scenario, and the receiving processing includes one or more of clock recovery, BCJR equalization, symbol demodulation, inner code synchronization, and PMA4 deinterleaving, wherein the symbol demodulation is PAM4 demodulation, and the deinterleaving processing is PAM4 deinterleaving processing. The BCJR equalization algorithm is an algorithm defined on a trellis diagram to maximize the posterior probability of error correction coding. This algorithm is named after its inventors, Bahl, Cocke, Jelinek and Raviv.

[0083] Step 502, performing second FEC decoding processing on the second sequence to obtain a third sequence, and the second FEC decoding processing is hard decision decoding processing.

[0084] The second FEC decoding process can be a hard decision decoding process, and an algorithm of the second FEC decoding process includes a Berlekamp decoding algorithm or a Euclidean decoding algorithm, etc. Berlekamp is a person's name. The hard decision decoding process can also be referred to as a hard decoding process.

[0085] In the embodiment, the receiver processing module 04 performs the second FEC decoding process on each information bit in the second sequence to obtain a third sequence. The third sequence indicates whether each information bit is successfully decoded in the second FEC decoding process, whether the corresponding information bit is flipped or the result of the decision of the corresponding information bit if the decoding is successful, or an identifier of the decoding failure in the third sequence if the decoding is unsuccessful. For example, when the second FEC decoding process corresponds to RS (544, 514) FEC encoding, the RS (544, 514) decoding process is performed on the second sequence, and the third sequence indicates whether each information bit in the second sequence is successfully decoded, whether the corresponding information bit is flipped or the result of the decision of the corresponding information bit if the decoding is successful.

[0086] It should be understood that, for a certain information bit, the decoding failure in the second FEC decoding process is generally caused by exceeding the error correction capability of the decoder to make the code word uncorrectable, and the decoding failure is indicated. The decoder is a device for performing the decoding process, and is part of the receiver processing module 04. The decoding success includes two cases of correct error correction and incorrect error correction. For example, RS (544, 514) can correct less than or equal to 15 symbol errors in any combination. When the number of error symbols in the code word is greater than 15, the decoder can determine that the code word is uncorrectable.

[0087] In step 503, the first FEC decoding process is performed on the first sequence according to the third sequence to obtain a fourth sequence. The fourth sequence is used to determine the decoded data of the first sequence.

[0088] In the embodiment, after obtaining the third sequence, the receiver processing module 04 performs the first FEC decoding process on the first sequence again using the third sequence to obtain the information bits of the first FEC code word obtained by the first FEC decoding process, i.e., to obtain the fourth sequence. Although the second sequence and the fourth sequence both include the information bits of the first FEC code word obtained by the first FEC decoding process, they can be different, because the fourth sequence is obtained by performing the first FEC decoding process on the first sequence for the second time.

[0089] In an optional mode, the sink processing module 04 updates the first sequence according to the third sequence to obtain an updated first sequence. The sink processing module 04 performs first FEC decoding processing on the updated first sequence to obtain the fourth sequence. For example, the first sequence is the soft decision information corresponding to the received plurality of first FEC codewords, and the sink processing module 04 updates the soft decision information corresponding to the plurality of first FEC codewords in the first sequence according to the third sequence to obtain the updated soft decision information of the plurality of first FEC codewords. Then, the first FEC decoding processing is performed according to the updated soft decision information to obtain the fourth sequence.

[0090] Optionally, the process of obtaining the updated soft decision information is as follows:

[0091] For each first bit in each first FEC codeword, the sink processing module 04 determines whether the second FEC decoding processing participated by the first bit is successful. If the decoding is successful, the sink processing module 04 updates the soft decision information corresponding to the first bit in the first sequence to a specified value, for example, the soft decision information is the LLR information, and the sink processing module 04 updates the amplitude of the soft decision information corresponding to the first bit in the first sequence to the specified value, which is a preset value indicating that the reliability of the second FEC decoding processing is high. If the decoding fails, the sink processing module 04 does not update the soft decision information corresponding to the first bit in the first sequence.

[0092] Optionally, the range of the soft decision information represented by the first sequence is [-X, X], and the specified value is -X or X, where X is a positive number.

[0093] It should be noted that when updating the soft decision information, only the soft decision information of the information bits of the first FEC codeword in the first sequence is updated, and the soft decision information of the check bits is not updated.

[0094] In step 503, after the fourth sequence is determined, the fourth sequence is used to determine the decoded data of the first sequence. In different application scenarios, the determination mode is different, and the decoded data of the first sequence obtained is also different. When applied to the application scenario shown in FIG. 2, the data receiving process is as shown in FIG. 6, and as shown in steps 601 to 607 in FIG. 6. When applied to the application scenario shown in FIG. 3, the data receiving process is as shown in FIG. 7, and as shown in steps 701 to 708 in FIG. 7. In FIGS. 6 and 7, the sink processing module 04 is taken as an example for illustration.

[0095] In step 601, the first FEC decoding processing is performed on the obtained first sequence for the first time R=1 to obtain the second sequence, and the first FEC decoding processing is soft decision decoding processing.

[0096] Step 602, performing a second FEC decoding process on the second sequence to obtain a third sequence, the second FEC decoding process being a hard decision decoding process.

[0097] Step 603, performing an R+1th first FEC decoding process on the first sequence according to the third sequence to obtain a fourth sequence.

[0098] Step 604, judging whether the number of times of performing the first FEC decoding process on the first sequence reaches a target threshold value.

[0099] The target threshold value is greater than or equal to 2, and is set according to an empirical value. For example, when applied to a scenario with a long transmission distance, the target threshold value is set to be larger, and when applied to a scenario with a short transmission distance, the target threshold value is set to be smaller. Alternatively, the target threshold value is obtained through training. For example, an initial value of the target threshold value is set, encoding and transmission are performed on known training data, and then iterative decoding is performed according to the target threshold value to determine whether the performance of the concatenated FEC encoding is less than a threshold value. If yes, the target threshold value is determined as the initial value, otherwise, the target threshold value is adjusted until the performance of the concatenated FEC encoding is less than the threshold value, and a final target threshold value is obtained. Here, the performance of the concatenated FEC encoding can be the bit error rate of the decoded data.

[0100] Step 605, if the target threshold value is reached, the fourth sequence is taken as the decoded data of the first sequence.

[0101] In this embodiment, the decoded data of the first sequence is the information bits of the first FEC codeword after error correction.

[0102] Step 606, if the target threshold value is not reached, performing a second FEC decoding process on the fourth sequence, taking the obtained decoding result as an updated third sequence, and returning to step 603 with R=R+1 until the number of times of performing the first FEC decoding process on the first sequence reaches the target threshold value.

[0103] In this embodiment, the manner of performing the second FEC decoding process on the fourth sequence is the same as the manner of performing the second FEC decoding process on the second sequence in step 502, which will not be described herein.

[0104] Step 607, sending the decoded data of the first sequence to the receiving device 05.

[0105] In this embodiment, after obtaining the decoded data of the first sequence, the receiving processing module 04 sends the decoded data of the first sequence to the receiving device 05.

[0106] It should be noted that in the flow shown in FIG. 6, the number of times of the first FEC decoding process can be used as a basis for judging whether the fourth sequence is the decoded data of the first sequence, and the number of times of the second FEC decoding process can also be used as a basis for judging whether the fourth sequence is the decoded data of the first sequence.

[0107] In an optional manner, after the decoded data of the first sequence is obtained, the decoded data of the first sequence is subjected to data processing including de-interleaving convolution, to obtain a new sequence, and the data processing can also include other processing, which is not limited by the embodiments of the present disclosure. At this time, the new sequence is sent to the receiving end device 05.

[0108] For the convenience of understanding, FIG. 8 also provides a logical block diagram of iterative decoding corresponding to the flow shown in FIG. 6. As shown in FIG. 8, the decoder of the iterative decoding logically includes an inner code soft decoding module (corresponding to the first decoding module hereinafter), an outer code decoding module (corresponding to the second decoding module hereinafter), and an output selector. The first sequence output after the receiving processing is sent to the inner code soft decoding module, the inner code soft decoding module performs the first FEC decoding process on the first sequence, and outputs the second sequence. The output selection judges whether the number of times of the first FEC decoding process reaches the target threshold, and sends the second sequence to the outer code decoding module, the outer code decoding module performs the second FEC decoding process on the second data, and outputs the third sequence to the inner code soft decoding module. The inner code soft decoding module performs the first FEC decoding process on the first sequence again according to the third sequence, and outputs the fourth sequence, the output selection judges whether the number of times of the first FEC decoding process reaches the target threshold, and when the target threshold is not reached, the fourth sequence is sent to the outer code decoding module, otherwise the fourth sequence is output, and the fourth sequence is the decoded data of the first sequence.

[0109] In an optional manner, in order to increase the burst performance of the transmission scheme of the concatenated FEC, the sending end processing module 02 shown in FIG. 2 or the sending end device 01 shown in FIG. 4 performs data interleaving processing after the outer code encoding, before the inner code encoding, and after the inner code encoding. Correspondingly, as shown in the flow of FIG. 9, the first de-interleaving processing is performed on the first sequence before step 601, see step 6010, and the first data processing is performed after step 601 and before step 602, the first data processing includes alignment lock processing, see step 6020. The alignment lock is used to determine the boundary of the outer code word.

[0110] Optionally, the first data processing further comprises one or more of a deskew, a lane reorder, or a de-lane distribution. The deskew is performed after the alignment flag lock processing, and the lane reorder and the de-lane distribution are performed after the deskew. The lane reorder is used to reorder the data streams of the lanes to eliminate the data stream disorder caused by the transmission, and the de-lane distribution is used to correspond the information bits in the data stream to the codewords. The de-lane distribution can also be referred to as a de-symbol distribution or a de-interleaver.

[0111] In an optional manner, a second data processing is added after step 602 and before step 603. The second data processing includes, but is not limited to, interleaving processing, etc. See step 6021.

[0112] For the convenience of understanding, when the first data processing and the second data processing exist, FIG. 10 further provides a logic block diagram of the corresponding iterative decoding. Compared with FIG. 7, the decoder of the iterative decoding further includes a de-interleaver module, a first data processing module, and a second data processing module in logic. The de-interleaver module performs a first de-interleaving processing on the first sequence, the first data processing module performs a first data processing on the second sequence or the fourth sequence obtained after the first FEC decoding processing, and the second data processing module performs a second data processing on the third sequence obtained after the second FEC decoding processing.

[0113] In the flow shown in FIG. 6, considering that the more the number of iterations is, the better the performance of the error correction can be obtained, but the decoding delay, power consumption, and area will be larger, the target threshold is 2, that is, after the second first FEC decoding processing, the decoding data of the first sequence is output. FIG. 11 further provides a logic block diagram of the corresponding iterative decoding. As shown in FIG. 11, the decoder includes a first inner code soft decoding module, an outer code decoding module, a second inner code soft decoding module, and a delay module in logic. The first sequence output after the receiving processing is sent to the first inner code soft decoding module and the delay module. The first inner code soft decoding module performs a first FEC decoding processing on the first sequence, and outputs a second sequence. The delay module buffers the first sequence. The second sequence is sent to the outer code decoding module. The outer code decoding module performs a second FEC decoding processing on the second sequence, and outputs a third sequence. The third sequence is sent to the second inner code soft decoding module. The second inner code soft decoding module reads the first sequence from the delay module, performs a first FEC decoding processing on the first sequence according to the third sequence, and obtains a fourth sequence, that is, the decoding data of the first sequence, which is output.

[0114] When the target threshold value is 2, Fig. 12 further provides another logical block diagram of the iterative decoding, the decoder of which logically comprises a deinterleaving module, a first inner code soft decoding module, a first data processing module, an outer code decoding module, a second data processing module, a second inner code soft decoding module and a delay module. The first sequence output after the receiving processing is input into the first deinterleaving module, and after the deinterleaving processing, is output to the first inner code soft decoding module and the delay module. The first inner code soft decoding module performs the first FEC decoding processing on the first sequence, and outputs the second sequence, and the delay module buffers the first sequence. The second sequence is input into the first data processing module to perform the first data processing, and is output to the outer code decoding module. The outer code decoding module performs the second FEC decoding processing on the second sequence after the first data processing, and outputs the third sequence. The third sequence is input into the second data processing module, and the second data processing module performs the second data processing on the third sequence, and outputs to the second inner code soft decoding module. The first inner code soft decoding module reads the first sequence from the delay module, and performs the first FEC decoding processing on the first sequence according to the third sequence after the second data processing, to obtain the fourth sequence, i.e., the decoding data of the first sequence, which is output.

[0115] In order to better understand the method of data receiving, the method of data receiving is applied to a 1.6T coherent transmission scenario, the sending device 01 adopts a BCH (126, 110) code word, the code word length is 126 bits, the information bit length is 110 bits, the receiving processing module 04 adopts an RS (544, 514) code word, the code word length is 5440 bits (i.e., 544 symbols), and the information bit length is 5140 bits (i.e., 514 symbols), i.e., a KP4 code word. The data stream transmitted through the optical fiber is received and processed by the receiving processing module 04 and the first deinterleaving processing, to obtain P inner code decoding data streams. Each 126 soft decision information connected in the inner code decoding data stream is the soft decision information corresponding to all bits of an inner code word BCH (126, 110), and the inner code word is the first FEC code word mentioned above. In this way, the data of the inner code decoding data stream is the first sequence. The receiving processing includes but is not limited to clock recovery, carrier phase recovery, symbol demodulation, DSP frame synchronization, pilot sequence deletion, etc. The first deinterleaving processing includes but is not limited to BCH deinterleaving and de-cyclic shift processing. The first sequence is processed through the flow shown in Fig. 6, to obtain P iterative decoding data streams. The P iterative decoding data streams are deinterleaved to obtain N channel data streams, which are transmitted to the receiving device 05 after being processed by the physical medium attachment (PMA) to perform outer code decoding processing, to obtain the data sent by the sending device 01.

[0116] The first sequence is processed through the flow shown in Fig. 6 as follows, as shown in Fig. 13.

[0117] The receiving end processing module 04 respectively performs BCH (126, 110) soft decision decoding processing on each of the 126 soft decision information connected in the to-be-inner-code-decoded data stream, to obtain P inner code soft decoding data streams, each of which includes a plurality of information bits corresponding to the BCH (126, 110), and the second sequence includes 110 information bits of the BCH (126, 110) code word determined by the BCH (126, 110) soft decision decoding.

[0118] Then, the P inner code soft decoding data streams are processed by the first data processing to obtain W to-be-outer-code-decoded data streams. Specifically, the first data processing includes second de-interleaving processing and first data sub-processing. The P inner code soft decoding data streams are processed by the second de-interleaving processing to obtain N channel data streams, and then the N channel data streams are processed by the first data sub-processing to obtain the W to-be-outer-code-decoded data streams.

[0119] Among them, the second de-interleaving processing has multiple implementation manners, such as the following manner one and manner two.

[0120] Manner one, Fig. 14 provides an implementation manner of the second de-interleaving processing. The P de-convolution interleavers respectively perform de-convolution interleaving on the P inner code soft decoding data streams to obtain the N channel data streams.

[0121] Manner two: when P is a multiple of N, that is, P / N = f, Fig. 15 provides another implementation manner of the second de-interleaving processing. Compared with the scheme shown in Fig. 14, before de-convolution interleaving, each f inner code decoding data stream is block multiplexed to obtain a multiplexed data stream, and the size of the block is the length of the information bits of the inner code code word (i.e., the first FEC code word), such as 110 bits. Then, each multiplexed data stream is processed by de-convolution interleaving to obtain the N channel data streams.

[0122] Fig. 16 provides an implementation manner of the de-convolution interleaver, which includes three delay lines, i.e., delay line 0 to delay line 2. The delay line 0 includes 2Q delay units, the delay line 1 includes Q delay units, and the delay line 2 includes 0 delay units. Each delay unit stores D, which includes 4 KP4 code symbols, i.e., 40 bits, where Q = 12. According to the polling order from the delay line 0 to the delay line 2, the inner code soft decoding data stream is input to each delay line for 4 KP4 code symbols at a time, and 4 KP4 code symbols are output from each delay line at a time.

[0123] The first data sub-process aims to obtain the outer code codewords to be decoded from the N channel data streams. FIG. 17 shows one implementation of the first data sub-process. As shown in FIG. 17, the alignment flag is first locked for each channel data stream, and then the de-skew is performed according to the alignment flag locking, followed by channel reordering, and finally the de-channel distribution is performed to obtain W outer code decoding data streams. Each 544 RS symbols (5440 bits) in the outer code decoding data stream is an RS (544, 514) codeword.

[0124] The W outer code decoding data streams are then sent into W outer code decoding modules respectively to perform RS (544, 514) outer code decoding processing, and a third sequence is output to obtain W outer code decoding data streams. When the number of error symbols in the RS (544, 514) codeword to be decoded exceeds 15, the RS (544, 514) decoding process may detect that it cannot be decoded, and it is determined that the decoding fails. In this case, the output third sequence is the decoding failure information. If the number of error symbols is determined not to exceed 15 in the decoding process, the decoder successfully decodes and determines which bits are error, and in this case, the third sequence is the RS (544, 514) codeword determined by the RS (544, 514) decoding, or the third sequence is the bit flipping information determined by the decoding, i.e., which bits are corrected and which bits are not corrected.

[0125] The W outer code decoding data streams are then subjected to a second data processing to obtain P inner code information data streams. The second data processing includes a second data sub-process and a data interleaving processing. One possible implementation of the second data sub-process is shown in FIG. 18. First, the W outer code decoding data streams are subjected to channel distribution or symbol distribution to obtain N channel data streams, and then the N channel data streams are sorted to adjust the order between the N channel data streams. The order of the sorted channel data streams is consistent with the order before the reordering in the first data sub-process. Then, the N channel data streams are subjected to data interleaving processing to obtain P inner code information data streams, and the data in the inner code information data stream is the third sequence in which the transmission order is disturbed. The data interleaving processing is the inverse processing of the second de-interleaving processing. For example, when the second de-interleaving processing adopts the scheme shown in FIG. 14, the data interleaving processing adopts the scheme shown in FIG. 19, and when the second de-interleaving processing adopts the scheme shown in FIG. 15, the corresponding data interleaving processing adopts the scheme shown in FIG. 20. It should be noted that when the de-convolution interleaving in the second de-interleaving processing adopts the scheme shown in FIG. 16, the corresponding convolution interleaver in the data interleaving processing adopts the scheme shown in FIG. 21, or when the de-convolution interleaving in the second de-interleaving processing adopts the scheme shown in FIG. 21, the corresponding convolution interleaver in the data interleaving processing adopts the scheme shown in FIG. 16.

[0126] Then the third sequence and the delayed first sequence are sent to the inner code soft decoding module for inner code soft decoding. Specifically, first, according to the third sequence, the soft decision information of the first sequence for the plurality of received inner code code words is updated to obtain updated soft decision information of the plurality of received inner code code words. For the information bits of the received inner code code word, the information bits are simultaneously protected by the outer code, and therefore after outer code decoding, a decoding decision result of the information bits by the outer code decoding is obtained, and the decoding decision result is the third sequence. Therefore, when the third sequence indicates that the outer code code word in which the information bits participate is successfully decoded, the soft decision information corresponding to the information bits is adjusted to a specified value, and when the third sequence indicates that the outer code code word in which the information bits participate is unsuccessfully decoded, the soft decision information corresponding to the information bits is still the soft decision information indicated by the first sequence. For example, when the soft decision information indicated by the first sequence ranges from -X to X, the specified value is -X or X, where X is a positive number. Then, inner code soft decoding is performed according to the updated soft decision information, error bits are corrected, and information bits corresponding to the soft-decoded inner code code word are output to obtain P iterative decoding data streams.

[0127] Finally, the P iterative decoding data streams are subjected to third deinterleaving processing to obtain N channel data streams. The implementation manner of the third deinterleaving processing is consistent with that of the second deinterleaving processing. The N channel data streams mentioned above are referred to as N physical coding sublayer (PCS) channel data streams, and the N PCS channel data streams are subjected to PMA processing and finally transmitted to the receiving device 05.

[0128] In an optional manner, W=4, P=16, and N=16; or W=4, P=32, and N=16.

[0129] When the method of the embodiments of the present disclosure is applied to a 1.6T coherent transmission scenario, the outer code is a concatenated code of KP4 and BCH (126, 110), and simulation shows that compared with existing decoding schemes, the method can obtain a performance gain of at least 0.7 dB.

[0130] It should be noted that the data receiving scheme shown in FIG. 13, if used in a 1.6T direct detection transmission scheme, the sending device 01 uses an inner code codeword as an FEC (128, 120) codeword, that is, the code length of the inner code codeword is 120 bits, and the information bit length is 120 bits, and the sending processing device 02 uses an RS (544, 514) codeword, that is, a KP4 codeword. The data stream transmitted through the optical fiber is received and processed by the receiving processing module 04 and the first deinterleaving processing, to obtain P data streams to be decoded, and each connected 128 soft decision information in the data stream to be decoded is the soft decision information corresponding to each bit of an inner code codeword (128, 120), which is also called a first FEC codeword. Thus, the data stream to be decoded includes a first sequence. The receiving processing includes but is not limited to clock recovery, symbol demodulation, inner code synchronization, pad removal, etc. The first deinterleaving processing includes but is not limited to PAM4 deinterleaving processing. The first sequence is processed through the flow shown in FIG. 6 to obtain P decoded data streams, and the P decoded data streams are processed through the first data processing to obtain N channel data streams, which are transmitted to the receiving device 05 after PMA processing for outer code decoding processing to obtain the data sent by the sending device 01. An implementation of the corresponding second deinterleaving processing in this scenario is shown in FIG. 22. The implementation includes performing inverse circular shift on each inner code codeword information data in each inner code decoding data stream, then performing deconvolution interleaving processing, and finally performing 1:2 4 RS symbol demultiplexing. The corresponding data interleaving processing is shown in FIG. 23, which sequentially performs 2:1 4 RS symbol multiplexing, convolution interleaving, 120-bit block distribution, and circular shift processing.

[0131] As shown in FIG. 7, step 701, performing first FEC decoding processing on the first sequence for the first time R=1 to obtain a second sequence.

[0132] Step 702, performing second FEC decoding processing on the second sequence to obtain a third sequence.

[0133] Step 703, performing first FEC decoding processing on the first sequence for the second time R+1 according to the third sequence to obtain a fourth sequence.

[0134] Step 704, performing second FEC decoding processing on the fourth sequence.

[0135] Step 705, determining whether the number of times of performing first FEC decoding processing on the first sequence reaches a target threshold.

[0136] The definition of the target threshold has been described above and will not be repeated here.

[0137] In step 706, if the target threshold is reached, the decision result obtained by performing the second FEC decoding process on the fourth sequence is taken as the decoding data of the first sequence.

[0138] In this embodiment, the decoding data of the first sequence is the information bits of the outer code codeword after error correction.

[0139] In step 707, if the target threshold is not reached, the decoding result of performing the second FEC decoding process on the fourth sequence is taken as the updated third sequence, and R=R+1 is assigned and the step 703 is executed until the number of times of performing the first FEC decoding process on the first sequence reaches the target threshold.

[0140] In this embodiment, the manner of performing the second FEC decoding process on the fourth sequence is the same as the manner of performing the second FEC decoding process on the second sequence in step 503, which will not be repeated here.

[0141] In step 708, the decoding data of the first sequence is subjected to FEC encoding process to obtain a sixth sequence, and the sixth sequence is sent to the receiving device 05.

[0142] In this embodiment, after obtaining the decoding data of the first sequence, the receiving processing module 04 subjects the decoding data of the first sequence to FEC encoding process, which is the same as the outer code encoding performed by the sending device 01. Then the sixth sequence is sent to the receiving device 05.

[0143] It should be noted that when the decoding data of the first sequence is the information bits of the outer code after error correction, the error rate in the decoding data is extremely low, such as less than or equal to 1e-15.

[0144] In an optional manner, in order to improve the burst performance of the concatenated code, in step 709, after obtaining the sixth sequence, the sixth sequence is subjected to data interleaving process to obtain a data interleaving processed sequence, and the data interleaving processed sequence is sent to the receiving device 05.

[0145] For the convenience of understanding, Fig. 24 also provides a logic block diagram of the iterative decoding corresponding to the flow shown in Fig. 7. As shown in Fig. 24, the decoder logic of the iterative decoding includes an inner code soft decoding module and an outer code decoding module. The first sequence output by the DSP processing is input to the inner code soft decoding module, the inner code soft decoding module performs the first FEC decoding processing on the first sequence, and outputs a second sequence. The second sequence is input to the outer code decoding module, the outer code decoding module performs the second FEC decoding processing on the second sequence, and outputs a third sequence to the inner code soft decoding module. The inner code soft decoding module performs the first FEC decoding processing on the first sequence again according to the third sequence, and outputs a fourth sequence. The fourth sequence is input to the outer code decoding module, the outer code decoding module performs the second FEC decoding processing on the fourth sequence, and judges whether the number of times of the first FEC decoding processing reaches a target threshold. When the target threshold is not reached, the third sequence obtained by the second FEC decoding processing is input to the inner code decoding module, otherwise the decision result obtained by the second FEC decoding processing is taken as the decoding data of the first sequence.

[0146] In an optional manner, in order to increase the burst performance of the transmission scheme of the concatenated FEC, the sender processing module 02 shown in Fig. 3 performs data interleaving processing after the outer code encoding, before the inner code encoding, and after the inner code encoding. Correspondingly, the first deinterleaving processing is performed on the first sequence before the step 701, and the first data processing is performed before the step 701 after the step 701. The first data processing includes but is not limited to deinterleaving and alignment flag locking processing, and after the first data processing, the information bits of the first FEC codeword obtained by the first FEC decoding processing are continuous in the second sequence. The second data processing is added before the step 703 after the step 702, and the second data processing includes but is not limited to interleaving processing and scrambling processing, so that the information bits of the first FEC codeword subjected to the second FEC decoding processing are continuous.

[0147] For the convenience of understanding, when the first data processing and the second data processing exist, Fig. 25 also provides a corresponding logic block diagram of the iterative decoding. Compared with Fig. 24, the decoder also includes a deinterleaving module, a first data processing module and a second data processing module in logic. The deinterleaving module performs the first deinterleaving processing on the first sequence, the first data module performs the second data processing on the second sequence or the fourth sequence obtained after the first FEC decoding processing, and the second data module performs the second data processing on the third sequence obtained after the second FEC decoding processing.

[0148] In order to better understand the method of data reception shown in Fig. 7, the method of data reception will be applied to a 1.6T coherent transmission scenario below. The sender device 01 adopts a BCH (128, 110) codeword, and the sender processing device 02 adopts an RS (544, 514) codeword, that is, a KP4 codeword.

[0149] The difference between the method shown in FIG. 6 is that, as shown in FIG. 26, the second sequence in the P inner code information data stream output after the second time inner code decoding is sequentially subjected to the second number processing and outer code decoding, and the outer code word information bits determined after the outer code decoding are output, that is, after the outer code decoding of each RS (544, 514), the 514 information bit symbols of the outer code word determined after the decoding are output, and then the RS (544, 514) encoding is performed on each RS (544, 514) information bit symbol to obtain the RS (544, 514) code word, so as to obtain W outer code encoded data streams, and then the third data sub-processing is performed on the W outer code encoded data streams to obtain N PCS channel data streams, and the third data sub-processing is the channel distribution processing described above.

[0150] FIG. 27 is a structural schematic diagram of a data receiving apparatus in an embodiment of the present disclosure. As shown in FIG. 27, the data receiving apparatus includes a first decoding module 271 and a second decoding module 272.

[0151] The first decoding module 271 is configured to perform first FEC decoding processing on the first sequence to obtain a second sequence, wherein the first FEC decoding processing is soft decision decoding processing, and can be specifically configured to perform the first FEC decoding processing function of step 501 and the implicit steps included in step 501.

[0152] The second decoding module 272 is configured to perform second FEC decoding processing on the second sequence to obtain a third sequence, wherein the second FEC decoding processing is hard decision decoding processing, and can be specifically configured to perform the second FEC decoding processing function of step 502 and the implicit steps included in step 502.

[0153] The first decoding module 271 is further configured to perform the first FEC decoding processing on the first sequence according to the third sequence to obtain a fourth sequence, wherein the fourth sequence is used to determine the decoding data of the first sequence, and can be specifically configured to perform the first FEC decoding processing function of step 501 and the implicit steps included in step 503.

[0154] In an optional manner, the first decoding module 271 is further configured to:

[0155] update the first sequence according to the third sequence;

[0156] perform the first FEC decoding processing on the updated first sequence to obtain a fourth sequence.

[0157] In an optional manner, the first sequence is soft decision information corresponding to a plurality of FEC code words received;

[0158] The soft decision information of each bit in each received FEC code word is represented by m bits, where m is greater than 1.

[0159] In an alternative manner, the first FEC decoding process is a BCH (128, 110) soft decision decoding process, or an FEC (128, 120) soft decision decoding process; and the second FEC decoding process is an RS (544, 514) hard decision decoding process.

[0160] In an alternative manner, the apparatus further comprises a first data processing module configured to perform an alignment flag locking process on the second sequence before performing the second FEC decoding process on the second sequence.

[0161] In an alternative manner, the first data processing module is further configured to perform one or more of a deskew, channel reordering or de-channel distribution process on the second sequence after performing the alignment flag locking process on the second sequence.

[0162] In an alternative manner, the apparatus further comprises a second data processing module configured to perform a channel distribution and channel ordering process on the third sequence before performing the first FEC decoding process on the first sequence according to the third sequence.

[0163] In an alternative manner, the first sequence is soft decision information corresponding to a plurality of received FEC code words.

[0164] The first decoding module 2710 is further configured to, if the second FEC decoding process in which the first bit participates is successful, update the soft decision information corresponding to the first bit in the first sequence to a specified value, the first bit being one information bit of an FEC code word obtained by the first FEC decoding process.

[0165] In an alternative manner, the first decoding module 2710 is further configured to:

[0166] If the number of times of performing the first FEC decoding process on the first sequence reaches a target threshold, the fourth sequence is taken as the decoded data of the first sequence.

[0167] If the number of times of performing the first FEC decoding process on the first sequence does not reach the target threshold, the second FEC decoding process is performed on the fourth sequence, a decoding result is taken as an updated third sequence, and the process of performing the first FEC decoding process on the first sequence according to the third sequence is executed until the number of times of performing the first FEC decoding process on the first sequence reaches a target threshold.

[0168] In an alternative mode, the apparatus further comprises a de-interleaving module configured to:

[0169] perform de-interleaving processing on the decoded data of the first sequence after taking the fourth sequence as the decoded data of the first sequence.

[0170] In an alternative mode, the apparatus further comprises an FEC decoding module configured to:

[0171] perform the second FEC decoding processing on the decoded data of the first sequence after taking the fourth sequence as the decoded data of the first sequence to obtain a fifth sequence.

[0172] In an alternative mode, the second decoding module 2720 is further configured to:

[0173] perform the second FEC decoding processing on the fourth sequence;

[0174] if the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold, take the decision result of performing the second FEC decoding processing on the fourth sequence as the decoded data of the first sequence;

[0175] if the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, take the decoding result of performing the second FEC decoding processing on the fourth sequence as an updated third sequence, and return to perform the processing of performing the first FEC decoding processing on the first sequence according to the third sequence until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

[0176] In an alternative mode, the apparatus further comprises an FEC encoding module configured to:

[0177] perform FEC encoding processing on the decoded data of the first sequence after taking the updated third sequence as the decoded data of the first sequence to obtain a sixth sequence.

[0178] In an alternative mode, the apparatus further comprises an interleaving module configured to:

[0179] perform interleaving processing on the sixth sequence after obtaining the sixth sequence.

[0180] It should be understood that the apparatus for receiving data provided by the present disclosure can also be implemented in other manners. For example, the division of the modules in the apparatus described above is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of modules or components can be combined or integrated into another system, or some necessary modules or components can be omitted or not used. In addition, the various embodiments of the present disclosure can be implemented in a manner of an independent component, or two or more components can be integrated in a processing module. The integrated module can be implemented in a manner of hardware or software functional module.

[0181] FIG. 28 is a schematic diagram of a structure of an optical module in an embodiment of the present disclosure. As shown in FIG. 28, the optical module includes a processor 2801 and an interface 2802. The processor 2801 is configured to perform the operations performed by the apparatus for receiving data in the embodiments described above. The interface 2802 can be a transceiver or an input / output interface. The interface 2802 is configured to receive a signal from another apparatus and transmit the signal to the processor 2801, or transmit a signal from the processor 2801 to another apparatus. As an example, the processor 2801 performs FEC decoding to obtain decoded data, and transmits the decoded data through the interface 2802. In this example, the interface 2802 can specifically refer to an electrical interface. Optionally, the optical module can further include a memory 2803. The memory 2803 is configured to store program instructions and / or data.

[0182] Generally, an optical module is composed of optoelectronic devices, a processor, an interface, and the like. The optoelectronic devices include a transmitting device and a receiving device. The transmitting end of the optical module converts an electrical signal into an optical signal and transmits the optical signal through an optical fiber. The receiving end of the optical module receives an optical signal and converts the optical signal into an electrical signal.

[0183] It should be noted that the types of optical modules in the embodiments of the present disclosure include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules, etc. The functions that can be implemented by the normal optical modules include, but are not limited to, digital signal processing (DSP) and clock data recovery (CDR), etc. For example, the normal optical module converts an analog signal into a digital signal, performs DSP processing on the digital signal, and then converts the digital signal into an analog signal to be sent to a host-side device. Since DSP needs to be retimed, the normal optical module can also be referred to as a retimed module. The normal optical module is connected to the host-side device through an attachment unit interface (AUI). The NPO module and the CPO module do not have a pluggable optical module physical package form, and are closer to the host-side device. The NPO module and the CPO module can also be referred to as optical engines. The NPO technology or the CPO technology is a technology of "packaging" the host-side device (or the host-side chip) and the optical engine. When the host-side device and the optical engine are packaged by using the NPO technology, the optical engine can be referred to as an NPO module. When the host-side device and the optical engine are packaged by using the CPO technology, the optical engine can be referred to as a CPO module.

[0184] FIG. 29 is a schematic diagram of a structure of a communication device according to an embodiment of the present disclosure. As shown in FIG. 29, the communication device includes a host-side device 2901 and an optical module 2902. The host-side device 2901 is configured to send data to the optical module 2902, and the optical module 2902 generates an optical signal according to the data sent by the host-side device 2901 and sends the optical signal through a channel. For example, the host-side device can be a switch, a router, or a server, etc. The communication device can be a communication device including the host-side device 2901 and the optical module 2902.

[0185] The embodiments of the present disclosure also provide a chip. The chip integrates a circuit for implementing the functions of the processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, the chip can be connected to an external memory through an interface. The chip can complete the method steps of any one or more of the preceding embodiments. Alternatively, the chip implements the actions performed by the data receiving apparatus in the above embodiments according to program codes stored in the memory.

[0186] As an example, the processor in the embodiments of the present disclosure can be a central processing unit (CPU), and can also be other general-purpose processors, DSPs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor, or can be any conventional processor, and can also be a processing circuit implementing a specific function.

[0187] The embodiments of the present disclosure further provide a computer readable storage medium, including a program or instructions, which, when running on a communication device, causes the implementation of the method of data receiving as described in the above embodiments.

[0188] It should be understood that the processor mentioned in the embodiments of the present disclosure can be implemented by hardware or software. When implemented by hardware, the processor can be a logic circuit, an integrated circuit, etc. When implemented by software, the processor can be a general-purpose processor, which is implemented by reading software codes stored in a memory. The memory can exist independently of the processor, or the memory can be integrated with the processor.

[0189] As an example, the processor in the embodiments of the present disclosure can be a CPU, and can also be other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor can be a microprocessor, or can be any conventional processor, and can also be a processing circuit implementing a specific function.

[0190] The memory in the embodiments of the present disclosure can be random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), register, hard disk, mobile hard disk, CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Of course, the storage medium can be a component of the processor. The processor and the storage medium can be located in an ASIC. The ASIC can be located in a network device or a terminal device. Of course, the processor and the storage medium can also exist as discrete components in the network device or the terminal device.

[0191] In the above embodiments, the implementation can be entirely or partially realized by software, hardware, firmware, or any combination thereof.

[0192] When implemented by using hardware, the method of data receiving provided by the embodiments of the present disclosure can be realized without reading software codes or instructions, for example, by using a CPU, a DSP, an ASIC, an FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0193] When implemented by using software, the implementation can be entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on a computer, the processes or functions of the embodiments of the present disclosure are entirely or partially executed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable apparatus. The computer programs or instructions can be stored in or transmitted by a computer-readable storage medium. The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server integrating one or more available media. The available medium can be a magnetic medium, for example, a floppy disk, a hard disk, a magnetic tape; an optical medium, for example, a digital versatile disc (DVD); or a semiconductor medium, for example, a solid state disk (SSD).

[0194] It should be noted that the terms "first", "second", and the like, used in the description and in the claims of the present disclosure are intended to distinguish similar elements or steps in the disclosure and are not intended to be limiting. It should be understood that the use of these terms are not to indicate that a particular element is in any way inferior to or superior to the other elements or steps. It is also to be understood that the terms "comprising", "including", "having" and the like, are not intended to exclude many aspects, methodologies, procedures, components, materials and / or steps of the present disclosure. For example, a process, method, system, product or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements but can include other steps or elements not expressly listed or inherent to such process, method, system, product or apparatus.

[0195] Finally, it should be noted that the above merely illustrates the exemplary embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered by the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method of data reception, characterized by, The method comprises: performing first forward error correction (FEC) decoding processing on the obtained first sequence to obtain a second sequence, wherein the first FEC decoding processing is soft decision decoding processing; performing second FEC decoding processing on the second sequence to obtain a third sequence, wherein the second FEC decoding processing is hard decision decoding processing; performing the first FEC decoding processing on the first sequence according to the third sequence to obtain a fourth sequence, wherein the fourth sequence is used to determine the decoding data of the first sequence.

2. The method of claim 1, wherein, The performing of the first FEC decoding processing on the first sequence according to the third sequence to obtain a fourth sequence comprises: updating the first sequence according to the third sequence; performing the first FEC decoding processing on the updated first sequence to obtain the fourth sequence.

3. The method according to claim 1 or 2, characterized in that, The first sequence is soft decision information corresponding to a plurality of received FEC code words. The soft decision information of each bit in each received FEC code word is represented by m bits, and m is greater than 1.

4. The method of claim 3, wherein, The first FEC decoding processing is Bose-Chaudhuri-Hocquenghem (BCH) (126, 110) soft decision decoding processing, or FEC (128, 120) soft decision decoding processing. The second FEC decoding processing is Reed-Solomon (RS) (544, 514) hard decision decoding processing.

5. The method according to any one of claims 1 to 4, characterized in that, Before the performing of the second FEC decoding processing on the second sequence, the method further comprises: performing alignment flag locking processing on the second sequence.

6. The method of claim 5, wherein, After the performing of the alignment flag locking processing on the second sequence, the method further comprises: performing one or more of de-skew, channel reordering or de-channel distribution processing on the second sequence after the alignment flag locking processing.

7. The method according to any one of claims 1 to 6, characterized in that, Before the performing of the first FEC decoding processing on the first sequence according to the third sequence, the method further comprises: performing channel distribution and channel sorting processing on the third sequence.

8. The method of claim 2, wherein, The first sequence is soft decision information corresponding to a plurality of received FEC code words. The updating of the first sequence according to the third sequence comprises: if the second FEC decoding processing in which the first bit participates is successfully decoded, updating the soft decision information corresponding to the first bit in the first sequence to a specified value, the first bit being one information bit of an FEC code word obtained by the first FEC decoding processing.

9. The method according to any one of claims 1 to 8, characterized in that, The method further comprises: if the number of times of performing the first FEC decoding processing on the first sequence reaches a target threshold, taking the fourth sequence as the decoding data of the first sequence; if the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, performing the second FEC decoding processing on the fourth sequence, taking the decoding result as an updated third sequence, and returning to perform the processing of performing the first FEC decoding processing on the first sequence according to the third sequence until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

10. The method of claim 9, wherein, After the taking of the fourth sequence as the decoding data of the first sequence, the method further comprises: performing de-interleaving processing on the decoding data of the first sequence.

11. The method according to claim 9 or 10, characterized in that, The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence. The method further comprises:

12. The method according to any one of claims 1 to 9, characterized in that, processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold. The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence.

13. The method of claim 12, wherein, The method further comprises: processing the fourth sequence by the second FEC decoding process; 14. The method of claim 13, wherein, if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold.

15. An apparatus for data reception, the apparatus comprising: The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence. The method further comprises: processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; 16. The apparatus of claim 15, wherein, if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold. The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence. The method further comprises:

17. The apparatus of claim 15 or 16, wherein, processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; 18. The apparatus of claim 17, wherein, if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold. The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence.

19. The apparatus of any one of claims 15 to 18, wherein, The method further comprises:

20. The apparatus of claim 5, wherein, processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold. The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence. The method further comprises: processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold. The fourth sequence is further processed by the second FEC decoding process to obtain a fifth sequence. The method further comprises: processing the fourth sequence by the second FEC decoding process; if the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold, using the decision result of processing the fourth sequence by the second FEC decoding process as the decoded data of the first sequence; if the number of times of processing the first sequence by the first FEC decoding process does not reach the target threshold, using the decoding result of processing the fourth sequence by the second FEC decoding process as an updated third sequence, and returning to processing the first sequence by the first FEC decoding process according to the third sequence until the number of times of processing the first sequence by the first FEC decoding process reaches the target threshold.

21. The apparatus of any one of claims 15 to 20, wherein, The device further comprises a second data processing module configured to perform channel distribution and channel ordering processing on the third sequence before performing the first FEC decoding processing on the first sequence according to the third sequence.

22. The apparatus of claim 16, wherein, The first sequence is soft decision information corresponding to a plurality of received FEC code words. The first decoding module is further configured to update the soft decision information corresponding to the first bit in the first sequence to a specified value if the second FEC decoding processing in which the first bit participates is successful.

23. The apparatus of any one of claims 15 to 22, wherein, The first decoding module is further configured to: If the number of times of performing the first FEC decoding processing on the first sequence reaches a target threshold, the fourth sequence is taken as the decoded data of the first sequence. If the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, the second FEC decoding processing is performed on the fourth sequence, the decoding result is taken as an updated third sequence, and the processing of performing the first FEC decoding processing on the first sequence according to the third sequence is executed again until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

24. The apparatus of claim 23, wherein, The device further comprises a deinterleaving module configured to: perform deinterleaving processing on the decoded data of the first sequence after the fourth sequence is taken as the decoded data of the first sequence.

25. The apparatus of claim 23 or 24, wherein, The device further comprises an FEC decoding module configured to: perform the second FEC decoding processing on the decoded data of the first sequence after the fourth sequence is taken as the decoded data of the first sequence to obtain a fifth sequence.

26. The apparatus of any one of claims 15 to 25, wherein, The second decoding module is further configured to: perform the second FEC decoding processing on the fourth sequence; if the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold, the decoding result of performing the second FEC decoding processing on the fourth sequence is taken as the decoded data of the first sequence; if the number of times of performing the first FEC decoding processing on the first sequence does not reach the target threshold, the decoding result of performing the second FEC decoding processing on the fourth sequence is taken as an updated third sequence, and the processing of performing the first FEC decoding processing on the first sequence according to the third sequence is executed again until the number of times of performing the first FEC decoding processing on the first sequence reaches the target threshold.

27. The apparatus of claim 26, wherein, The device further comprises an FEC encoding module configured to: perform FEC encoding processing on the decoded data of the first sequence after the updated third sequence is taken as the decoded data of the first sequence to obtain a sixth sequence.

28. A chip, characterized by The chip is configured to execute the method in any one of claims 1 to 14.

29. An optical module characterized by comprising: The optical module comprises a processor and an interface, the interface is configured to communicate with other devices, and the processor is configured to execute the method in any one of claims 1 to 14.

30. A communications device, characterized by The communication device comprises a host-side device and the optical module as claimed in claim 29, the optical module being configured to perform the method as claimed in any one of claims 1 to 14 to obtain the first sequence of decoded data and transmit the first sequence of decoded data to the host-side device.

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