Circuit board and electronic device

Abstract

The present application relates to the technical field of circuit boards, and provides a circuit board and an electronic device. The circuit board comprises a prepreg layer, two circuit layer groups, a plurality of first vias, and a plurality of second vias. The two circuit layer groups are respectively disposed on opposite sides of the prepreg layer and are symmetrically arranged with respect to the prepreg layer, the plurality of first vias are disposed in one of the circuit layer groups, and the plurality of second vias are disposed in the other circuit layer group. A plurality of first pads are provided on the surface of one of the circuit layer groups, each first pad corresponds to one first via and is electrically connected to the corresponding first via, and each first via is adjacent to the corresponding first pad. A plurality of second pads are provided on the surface of the other circuit layer group, each second pad corresponds to one second via and is electrically connected to the corresponding second via, and each second via is adjacent to the corresponding second pad. The present application can reduce the difficulty of fan-out in a connector area on the circuit board and lower the costs of the circuit board.

Description

Circuit board and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410779903.8, filed on June 17, 2024, and entitled "Circuit board and electronic device", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of circuit boards, in particular to a circuit board and an electronic device. BACKGROUND

[0003] Servers and storage support data processing and storage of cloud computing and big data, and directly determine the stability of the entire system. As the core of the server, the design of the printed circuit board (PCB) directly determines the stability of the server.

[0004] In the related art, the circuit board assembly includes a printed circuit board, a chip and a plurality of connectors. The chip is electrically connected to the connectors through the printed circuit board. The connectors are double-sided 2x1 QSFP-DD (quad small form factor pluggable-doubledensity). Since the connectors are double-sided mounted on the printed circuit board, the front and back surfaces of the printed circuit board cannot simultaneously punch through-hole vias connected to the connectors. Moreover, the spacing between the adjacent two rows of pins of the QSFP-DD is not sufficient to simultaneously punch two pairs of differential vias. Therefore, the pins of the connectors on the front and back surfaces of the printed circuit board need to be connected to the peripheral vacant area of the connectors through deep micro-hole layer changing and then punched and changed layers, which will result in too many layers of the printed circuit board, thereby increasing the cost of the printed circuit board. SUMMARY

[0005] The present application provides a circuit board and an electronic device, which can reduce the number of layers of the circuit board and reduce the cost of the circuit board.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a circuit board, comprising a semi-cured layer, two circuit layer groups, a plurality of first vias and a plurality of second vias.

[0008] Each of the circuit layer groups comprises a plurality of circuit layers stacked, the two circuit layer groups are arranged on opposite sides of the semi-cured layer and symmetrically arranged with respect to the semi-cured layer, the plurality of first vias and the plurality of second vias are arranged on opposite sides of the semi-cured layer, the plurality of first vias are arranged in one of the circuit layer groups, and the plurality of second vias are arranged in the other circuit layer group.

[0009] The surface of one of the circuit layer groups is provided with a connector first pad area, the connector first pad area comprising a plurality of first pads, each of the first pads corresponding to one of the first vias and being electrically connected with the corresponding first via, and each of the first vias being close to the corresponding first pad;

[0010] The surface of another of the circuit layer groups is provided with a connector second pad area, the connector second pad area comprising a plurality of second pads, each of the second pads corresponding to one of the second vias and being electrically connected with the corresponding second via, and each of the second vias being close to the corresponding second pad.

[0011] In a possible implementation of the circuit board, the connector first pad area comprises a plurality of first connector regions arranged at intervals along a first direction, and the connector second pad area comprises a plurality of second connector regions arranged at intervals along the first direction; wherein the first direction is perpendicular to the thickness direction of the circuit board.

[0012] Each of the first connector regions corresponds to one of the second connector regions, and the first pads in the corresponding first connector region and the second pads in the corresponding second connector region are used to form one connector pad group.

[0013] In a possible implementation of the circuit board, each of the first connector regions comprises a plurality of first areas arranged at intervals along a second direction, and each of the first areas comprises a plurality of the first pads arranged at intervals along the first direction.

[0014] Each of the second connector regions comprises a plurality of second areas arranged at intervals along the second direction, and each of the second areas comprises a plurality of the second pads arranged at intervals along the first direction; wherein the first direction, the second direction, and the thickness direction of the circuit board are perpendicular to each other.

[0015] In a possible implementation of the circuit board, each of the first areas corresponds to one of the second areas, and the first pads in each of the first areas do not overlap with the second pads in the corresponding second areas in the thickness direction of the circuit board.

[0016] In the second direction, the first vias are arranged between adjacent two of the first areas, and the second vias are arranged between adjacent two of the second areas.

[0017] In a possible implementation of the circuit board, the number of the connector pad groups is multiple, and the multiple connector pad groups are arranged side by side and spaced apart in the first direction.

[0018] The surface of one of the circuit layer groups is further provided with a first chip pad area, a second chip pad area, a third chip pad area, and a fourth chip pad area, the first chip pad area and the second chip pad area are located between the third chip pad area and the fourth chip pad area, the second chip pad area is located between the first chip pad area and the connector pad group, and any one of the first chip pad area, the second chip pad area, the third chip pad area, and the fourth chip pad area includes multiple third pads.

[0019] The leftmost connector pad group of the multiple connector pad groups in the first direction is close to the third chip pad area and is used for electrical connection with the third pads in the third chip pad area, and the rightmost connector pad group of the multiple connector pad groups in the first direction is close to the fourth chip pad area and is used for electrical connection with the third pads in the fourth chip pad area.

[0020] In a possible implementation of the circuit board, all the circuit layers in the two circuit layer groups include multiple first signal circuit layers, multiple second signal circuit layers, and multiple power circuit layers, the first signal circuit layers are used for electrical connection with the third pads in the first chip pad area and the connector pad group, and the second signal circuit layers are used for electrical connection with the third pads in any one of the second chip pad area, the third chip pad area, and the fourth chip pad area and the connector pad group.

[0021] In a possible implementation of the circuit board, the first signal circuit layers include sixteen pairs of differential signal lines, and each pair of differential signal lines includes two differential signal lines.

[0022] In a possible implementation of the circuit board, the number of layers of the first signal circuit layers is four, the number of layers of the second signal circuit layers is eight, and the number of power circuit layers is four.

[0023] In a possible implementation of the circuit board, the circuit board further includes two dielectric groups, and each dielectric group includes multiple dielectric layers.

[0024] The dielectric layers in one of the dielectric layer groups are located between adjacent circuit layers in one of the circuit layer groups, and the dielectric layers in the other dielectric layer group are located between adjacent circuit layers in the other circuit layer group.

[0025] The material of the medium layer between the adjacent power supply circuit layers is different from the material of the medium layer between the adjacent first signal circuit layers, and the material of the medium layer between the adjacent power supply circuit layers is different from the material of the medium layer between the adjacent second signal circuit layers.

[0026] The present application also provides an electronic device comprising the circuit board according to any one of the first aspect.

[0027] The circuit board and the electronic device provided by the present application, the two circuit layer groups in the circuit board are symmetrically arranged with respect to the prepreg, so that the number of circuit layers on both sides of the prepreg is the same, and the structures of the corresponding circuit layers can be the same, for example, the materials or thicknesses of the corresponding circuit layers are the same, and then the two circuit layer groups can be pressed on both sides of the prepreg by one pressing process, which can reduce the difficulty of manufacturing the circuit board and the production cost, and also can improve the yield of the circuit board.

[0028] In addition, by using the stack design that the two circuit layer groups are symmetrically arranged with respect to the prepreg, the holes can be punched near the pads in the connector area on the front and back surfaces of the circuit board, for example, the first via in one of the circuit layer groups is punched near the first pad in the first pad area of the connector of the circuit board, and the second via in the other circuit layer group is punched near the second pad in the second pad area of the connector of the circuit board, so that the deep micro-hole layer changing in the related art is removed, and then the signal does not need to be led to the empty area outside the connector area of the circuit board, which can reduce the number of layers of the circuit board and reduce the cost of the circuit board. At the same time, the fan-out difficulty of the connector area on the circuit board can also be reduced, for example, the fan-out difficulty of the connector area in the circuit board in the application scenario of a double-sided 2x1 QSFP-DD connector. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor.

[0030] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present application;

[0031] FIG. 2 is a front view of the circuit board shown in FIG. 1;

[0032] FIG. 3 is a back view of the circuit board shown in FIG. 1;

[0033] FIG. 4 is a schematic view of the circuit board shown in FIG. 1 from a top perspective;

[0034] Fig. 5 is an enlarged schematic view of A in Fig. 4;

[0035] Fig. 6 is an enlarged schematic view of A in Fig. 5;

[0036] Fig. 7 is a simulation schematic diagram of a circuit board provided by an embodiment of the present application;

[0037] Fig. 8 is a simulation schematic diagram of a circuit board provided by an embodiment of the present application.

[0038] Legend: 100, circuit layer group; 110, circuit layer; 120, connector first pad area; 121, first connector area; 122, first area; 130, connector second pad area; 131, second connector area; 132, second area; 140, connector pad group; 150, first chip pad area; 160, second chip pad area; 170, third chip pad area; 180, fourth chip pad area; 200, semi-cured layer; 300, dielectric layer; 10, first pad; 20, second pad; 30, first via; 40, second via; 50, third pad; X, first direction; Y, second direction; Z, thickness direction. DETAILED DESCRIPTION

[0039] With the advent of the 5G and interconnection era, faster and more data processing requirements also bring higher requirements for communication technology bandwidth. At present, the Tomahawk fifth-generation switch chip (hereinafter referred to as TH5) with a throughput of 51.2Tbps has been launched to meet the current demand. Among them, the TH5 chip includes 64 800Gbps ports, and the single-channel signal rate has reached 100Gbps. This means that if the optical module selected is QSFP-DD (800G), 64 need to be configured, and if the QSFP112 (400G) package is used, 128 need to be configured. Usually, 64 ports need one layer of printed circuit board (PCB), and 128 ports need at least 2 layers of PCB. The more layers of PCB, the more expensive the cost of the PCB, and the 100G super-speed signal needs to be connected across the board, which is very detrimental to signal quality.

[0040] In the related art, the connector interface on the PCB adopts a 2x1 and belly to belly architecture (single column 4 ports), a total of 64 connector interfaces, arranged in 16 columns, to realize single-layer PCB to pass through the signal line number of TH5.

[0041] However, the double-sided 2x1 QSFP-DD is double-sidedly mounted on the front and back surfaces of the PCB, so that the pin near the QSFP-DD on the front and back surfaces of the PCB cannot be punched at the same time, and the distance between the two adjacent rows of pins of the QSFP-DD is not enough to simultaneously accommodate two pairs of differential vias. Therefore, the pins of the QSFP-DD on the front and back surfaces of the PCB need to be punched through deep micro-holes to lead the signals to the peripheral vacant area of the connector and then change layers, which increases the number of layers of the PCB, thereby increasing the cost of the PCB. In addition, 2-stage deep micro design is required, and the number of PCB pressing times is increased, which increases the cost of the PCB. In addition, the vacant area on the front and back surfaces of the PCB needs to be punched more differential layer holes, which means that the devices on the main chip and other paths need to be moved upward as a whole, which means that the length of the high-speed signal will increase, the attenuation will increase, and the signal quality will be deteriorated.

[0042] Therefore, the circuit board and the electronic device provided in the embodiments of the present application can reduce the difficulty of preparation and the production cost of the circuit board, improve the yield of the circuit board, punch the holes near the pins of the connector on the front and back surfaces of the circuit board without leading the signals to the vacant area outside the connector area of the circuit board, reduce the number of layers of the circuit board, reduce the cost of the circuit board, reduce the difficulty of fan-out of the connector area on the circuit board, shorten the length of the high-speed signal line of TH5, and improve the signal quality.

[0043] The circuit board and the electronic device provided in the embodiments of the present application will be described below with reference to the accompanying drawings.

[0044] FIG. 1 is a cross-sectional view of the circuit board provided in the embodiments of the present application, FIG. 2 is a front view of the circuit board shown in FIG. 1, FIG. 3 is a back view of the circuit board shown in FIG. 1, FIG. 4 is a schematic view of the circuit board shown in FIG. 1 from a top perspective, FIG. 5 is an enlarged view of A in FIG. 4, and FIG. 6 is an enlarged view of A in FIG. 5.

[0045] Referring to FIG. 1, the circuit board of the embodiment of the present application comprises a prepreg layer 200, two circuit layer sets 100, a plurality of first vias 30 and a plurality of second vias 40. The prepreg layer 200 is composed of resin and reinforcing material. The reinforcing material can be glass cloth, paper-based or other composite materials. For example, a thin material made of treated glass fiber cloth is impregnated with resin glue and pre-baked, so that the resin glue enters a semi-cured state. When the prepreg layer 200 is heated and pressed in the subsequent lamination process, it will soften and the resin will be fully cross-linked to bond and fix the two circuit layer sets 100 on both sides of the prepreg layer 200.

[0046] Referring to FIG. 1, each circuit layer set 100 comprises a plurality of circuit layers 110 stacked in sequence along a direction perpendicular to the prepreg layer 200 (e.g., the Z direction in FIG. 1). For example, each circuit layer set 100 comprises 16 circuit layers 110, i.e., the circuit board comprises 32 circuit layers 110. The number of layers of the circuit board is reduced, which reduces the production cost and difficulty of manufacturing the circuit board.

[0047] The two circuit layer sets 100 are arranged symmetrically on opposite sides of the prepreg layer 200, so that the corresponding circuit layers 110 are the same. For example, the circuit board comprises 32 circuit layers 110. The first circuit layer 110 is the same as the 32nd circuit layer 110, the second circuit layer 110 is the same as the 31st circuit layer 110, and so on, until the 16th circuit layer 110 is the same as the 17th circuit layer 110. It should be understood that in this example, the corresponding circuit layers 110 can refer to the structure, material and thickness of the two circuit layers 110 being the same.

[0048] Since the two circuit layer sets 100 are arranged symmetrically with respect to the prepreg layer 200, the number of layers of the circuit layers 110 on both sides of the prepreg layer 200 is the same, and the structure of the corresponding circuit layers 110 can be the same, for example, the material or thickness of the corresponding circuit layers 110 is the same. Therefore, the two circuit layer sets 100 can be laminated on both sides of the prepreg layer 200 by one lamination process, which reduces the difficulty of manufacturing the circuit board and the production cost, and improves the yield of the circuit board.

[0049] Continuing to refer to FIG. 1, the first vias 30 and the second vias 40 are respectively arranged on opposite sides of the prepreg 200, that is, the first vias 30 and the second vias 40 are arranged in a direction perpendicular to the prepreg 200 (for example, the Z direction in FIG. 1). The first vias 30 are arranged in one of the circuit layer groups 100, and the second vias 40 are arranged in the other circuit layer group 100. For example, when the circuit board includes 32 circuit layers 110, the first vias 30 are arranged from the first circuit layer 110 to the sixteenth circuit layer 110, and the second vias 40 are arranged from the thirty-second circuit layer 110 to the seventeenth circuit layer 110.

[0050] The surface of one of the circuit layer groups 100 is provided with the connector first pad area 120. The surface of the circuit layer group 100 can be understood as the front surface of the circuit board, and the connector first pad area 120 is located on the front surface of the circuit board (as shown in FIG. 2). The connector first pad area 120 includes a plurality of first pads 10. Each first pad 10 corresponds to a first via 30 and is electrically connected to the corresponding first via 30. Each first via 30 is close to the corresponding first pad 10, that is, the first via 30 is located near the corresponding first pad 10 (as shown in FIG. 5 or FIG. 6), and does not need to be electrically connected to the first pad 10 through a deep micro-hole layer change.

[0051] The surface of the other circuit layer group 100 is provided with the connector second pad area 130. The surface of the circuit layer group 100 can be understood as the back surface of the circuit board, and the connector second pad area 130 is located on the back surface of the circuit board (as shown in FIG. 3). The connector second pad area 130 includes a plurality of second pads 20. Each second pad 20 corresponds to a second via 40 and is electrically connected to the corresponding second via 40. Each second via 40 is close to the corresponding second pad 20, that is, the second via 40 is located near the corresponding second pad 20 (as shown in FIG. 5 or FIG. 6), and does not need to be electrically connected to the second pad 20 through a deep micro-hole layer change.

[0052] In view of the fact that, with the design of the two circuit layer groups 100 being symmetrically arranged relative to the prepreg 200, the via holes can be punched near the pads in the connector area on the front and back surfaces of the circuit board, for example, the first via hole 30 in one of the circuit layer groups 100 is punched near the first pad 10 in the connector first pad area 120 of the circuit board, and the second via hole 40 in the other circuit layer group 100 is punched near the second pad 20 in the connector second pad area 130 of the circuit board, thereby removing the deep micro-hole layer changing in the related art, and further without the need to lead the signals to the empty area outside the connector area of the circuit board, the number of layers of the circuit board can be reduced, and the cost of the circuit board is reduced. At the same time, the fan-out difficulty of the connector area on the circuit board can also be reduced, for example, the fan-out difficulty of the connector area in the circuit board in the application scenario of a double-sided 2x1 QSFP-DD connector. Wherein, the connector area refers to the connector first pad area 120 and the connector second pad area 130.

[0053] It can be understood that the first via hole 30 and the second via hole 40 are respectively located on different circuit layer groups 100, and one pair of differential signal via holes (the first via hole 30 or the second via hole 40) is accommodated through the spacing between the two adjacent rows of pins on the front or back surface of the connector of the circuit board, so that the first via hole 30 or the second via hole 40 can be arranged near the corresponding pad, thereby without the need to lead the signals to the empty area outside the connector area on the circuit board. In addition, the orthographic projection of the first via hole 30 and the second via hole 40 in the thickness direction Z of the circuit board can overlap or not overlap, but the first via hole 30 and the second via hole 40 are arranged in the thickness direction Z of the circuit board, which ensures that the first via hole 30 and the second via hole 40 can be arranged near the corresponding pad, and realizes the near punching.

[0054] In some possible implementations, the connector first pad area 120 includes a plurality of first connector areas 121 arranged in the first direction X and spaced apart, and the connector second pad area 130 includes a plurality of second connector areas 131 arranged in the first direction X and spaced apart. For example, as shown in FIG. 2, the connector first pad area 120 can include 16 first connector areas 121 arranged side by side and spaced apart in the first direction X, and as shown in FIG. 3, the connector second pad area 130 can include 16 second connector areas 131 arranged side by side and spaced apart in the first direction X. Each first connector area 121 corresponds to a second connector area 131, that is, the corresponding first connector area 121 and the second connector area 131 are arranged opposite to each other in the first direction X, and the first pad 10 in the corresponding first connector area 121 and the second pad 20 in the second connector area 131 are used to form a connector pad group 140 (as shown in FIG. 4 or FIG. 5), and the pads in the connector pad group 140 are used to be connected with the connector.

[0055] In the embodiments of the present application, the first direction X, the second direction Y and the thickness direction Z of the circuit board are perpendicular to each other.

[0056] Exemplarily, as shown in FIG. 4, the number of the connector pad groups 140 is 16 and the connector pad groups 140 are arranged side by side and spaced apart along the first direction X, each of the connector pad groups 140 can constitute four connector interfaces, thereby forming 64 interfaces to realize the connection with the TH5, and the number of layers of the circuit board can be reduced and the cost of the circuit board can be reduced.

[0057] In some possible implementation manners, as shown in FIG. 2, each of the first connector regions 121 includes a plurality of first regions 122 arranged spaced apart along the second direction Y, and each of the first regions 122 includes a plurality of first pads 10 arranged spaced apart along the first direction X. As shown in FIG. 3, each of the second connector regions 131 includes a plurality of second regions 132 arranged spaced apart along the second direction Y, and each of the second regions 132 includes a plurality of second pads 20 arranged spaced apart along the first direction X.

[0058] Exemplarily, each of the first connector regions 121 includes eight first regions 122 arranged side by side and spaced apart along the second direction Y, and from top to bottom along the second direction Y, the first first region 122 to the fourth first region 122 are used to constitute one connector interface, and the fifth first region 122 to the eighth first region 122 are used to constitute one connector interface, so that each of the first connector regions 121 forms two connector interfaces.

[0059] Exemplarily, each of the second connector regions 131 includes eight second regions 132 arranged side by side and spaced apart along the second direction Y, and from top to bottom along the second direction Y, the first second region 132 to the fourth second region 132 are used to constitute one connector interface, and the fifth second region 132 to the eighth second region 132 are used to constitute one connector interface, so that each of the second connector regions 131 forms two connector interfaces.

[0060] Therefore, the connector pad groups 140 constituted by the corresponding first connector regions 121 and the second connector regions 131 can form four connector interfaces to realize the connection with the TH5.

[0061] Exemplarily, each of the first regions 122 includes four first pads 10 arranged side by side and spaced apart along the first direction X, and each of the second regions 132 includes four second pads 20 arranged side by side and spaced apart along the first direction X.

[0062] In some possible implementation manners, referring to FIG. 5 and FIG. 6, each first region 122 corresponds to a second region 132, and the orthographic projection of the first pads 10 in each first region 122 on the thickness direction Z of the circuit board does not overlap with the orthographic projection of the second pads 20 in the corresponding second region 132 on the thickness direction Z of the circuit board. Along the second direction Y, a first via 30 is arranged between two adjacent first regions 122, and a second via 40 is arranged between two adjacent second regions 132, and the space between the two adjacent first regions 122 and the space between the two adjacent second regions 132 can be used for local punching to realize the fan-out of the connector interface.

[0063] In some possible implementation manners, the number of the connector pad groups 140 is multiple, and the multiple connector pad groups 140 are arranged side by side and spaced apart along the first direction X. Referring to FIG. 2 or FIG. 5, the surface of one of the line layer groups 100 is further provided with a first chip pad region 150, a second chip pad region 160, a third chip pad region 170 and a fourth chip pad region 180, the first chip pad region 150 and the second chip pad region are located between the third chip pad region 170 and the fourth chip pad region 180, and the second chip pad region 160 is located between the first chip pad region 150 and the connector pad group 140. Any one of the first chip pad region 150, the second chip pad region 160, the third chip pad region 170 and the fourth chip pad region 180 includes multiple third pads 50. The leftmost connector pad group 140 of the multiple connector pad groups 140 along the first direction X is close to the third chip pad region 170 and is used for electrically connecting the third pads 50 in the third chip pad region 170, and the rightmost connector pad group 140 of the multiple connector pad groups 140 along the first direction X is close to the fourth chip pad region 180 and is used for electrically connecting the third pads 50 in the fourth chip pad region 180.

[0064] In order to realize the connection between the TH5 and the circuit board, the front surface or the back surface of the circuit board is provided with a chip connection region, and the chip connection region includes the first chip pad region 150, the second chip pad region 160, the third chip pad region 170 and the fourth chip pad region 180, and is used for electrically connecting the TH5. For example, as shown in FIG. 5, the chip connection region is arranged on the front surface of the circuit board. Wherein, the TH5 adopts a BGA (ball grid array, ball grid array package) package, therefore, the TH5 includes a chip body and multiple solder balls located at the bottom of the chip body, and the multiple solder balls form a rectangular ring shape, and correspondingly, the shape of the chip connection region is also a rectangular ring shape.

[0065] As shown in FIG. 5, since the connector pad groups 140 and the chip connecting areas are arranged along the second direction Y, in the second direction Y, the first chip pad area 150 is farthest from the connector pad groups 140. In the related art, in order to connect the high-speed signals of the TH5 to the connector in the most direct path, the first chip pad area 150 needs to be connected to the connector pad groups 140 that are leftmost and / or rightmost in the first direction X, so that the high-speed signals of the area above the TH5 are connected to the leftmost / rightmost connector, so that the number of layers of the circuit board stack is the least, but this causes the high-speed signal lines to be very long, and in order to meet the use requirements, the PCB board material needs to be upgraded, resulting in an increase in the cost of the circuit board.

[0066] However, in the embodiment of the present application, the high-speed signals of the area above the TH5 are connected to the connector that is closest to the TH5 in the first direction X, that is, the first chip pad area 150 is not connected to the leftmost and rightmost connector pad groups 140 in the first direction X, at this time, the leftmost connector pad group 140 is used to be connected to the third chip pad area 170, and the rightmost connector pad group 140 is used to be connected to the fourth chip pad area 180, so that the maximum length of the high-speed signal lines of the TH5 is shortened.

[0067] In addition, the BGA area of the TH5 can take advantage of the fact that the two circuit layer groups 100 are symmetrically arranged with respect to the prepreg 200, and the via holes connected to the third pad 50 on the circuit board are arranged in the upper half of the circuit board, and the lower half of the circuit board opposite the BGA area of the TH5 will no longer have via holes, so that the current carrying capacity can be increased.

[0068] The first chip pad area 150 can be connected to one or more connector pad groups 140.

[0069] There is no limitation on which connector pad group 140 the first chip pad area 150 is connected to. Exemplarily, the number of connector pad groups 140 is 16, along the first direction X, from left to right, the first chip pad area 150 is connected to the sixth connector pad group 140 and the eleventh connector pad group 140, at this time, the leftmost connector pad group 140 is connected to the third chip pad area 170, and the rightmost connector pad group 140 is connected to the fourth chip pad area 180.

[0070] It should be noted that the connector pad group 140 connected to the first chip pad area 150 can also be connected to the third chip pad area 170, the second chip pad area 160, or the fourth chip pad area 180.

[0071] In some possible implementations, all the circuit layers 110 in the two circuit layer groups 100 include a plurality of first signal circuit layers, a plurality of second signal circuit layers, and a plurality of power circuit layers, the first signal circuit layers are configured to electrically connect the third pads 50 in the first chip pad area 150 and the connector pad group 140, and the second signal circuit layers are configured to electrically connect the third pads 50 in any one of the second chip pad area 160, the third chip pad area 170, and the fourth chip pad area 180 and the connector pad group 140.

[0072] Exemplarily, the total number of the circuit layers 110 in the two circuit layer groups 100 is 32, the number of the first signal circuit layers is four, the number of the second signal circuit layers is eight, and the number of the power circuit layers is four, that is, the total number of the first signal circuit layers, the second signal circuit layers, and the power circuit layers is 16, and the remaining 16 layers can include ground layers (GND) and other layers.

[0073] It should be noted that the distribution of the plurality of first signal circuit layers, the plurality of second signal circuit layers, and the plurality of power circuit layers in the two circuit layer groups 100 can be various, but the positions of the circuit layers 110 in the two circuit layer groups 100 are symmetrically arranged relative to the prepreg 200. Exemplarily, taking four first circuit layers 110 as an example, two of the four first circuit layers 110 can be arranged in the circuit layer group 100 above the prepreg 200, and the remaining two first circuit layers 110 can be arranged in the circuit layer group 100 below the prepreg 200 and symmetrically arranged relative to the prepreg 200.

[0074] Exemplarily, the first signal circuit layers include sixteen pairs of differential signal line pairs, each differential signal line pair includes two differential signal lines, and the fan-out of the high-speed signals in the area above the TH5 is implemented.

[0075] The specific positions of the first signal circuit layers and the second signal circuit layers are not limited herein. Exemplarily, the total number of the circuit layers 110 in the two circuit layer groups 100 is 32, along the thickness direction Z of the circuit board, from top to bottom, the third circuit layer 110, the thirteenth circuit layer 110, the twentieth circuit layer 110, and the thirtieth circuit layer 110 are configured to be the first signal circuit layers of the high-speed signal lines in the area above the fan-out TH5, and each layer includes sixteen pairs of differential signal line pairs. The fifth circuit layer 110, the seventh circuit layer 110, the ninth circuit layer 110, the eleventh circuit layer 110, the twenty-second circuit layer 110, the twenty-fourth circuit layer 110, the twenty-sixth circuit layer 110, and the twenty-eighth circuit layer 110 are configured to be the second signal circuit layers of the high-speed signal lines in the remaining area of the fan-out TH5.

[0076] The power supply circuit layer is used to supply power to the TH5. The specific position of the power supply circuit layer is not limited herein. Exemplarily, the circuit layer 110 of the seventeenth layer, the circuit layer 110 of the eighteenth layer, the circuit layer 110 of the fifteenth layer and the circuit layer 110 of the thirty-second layer can be used as the power supply circuit layer. Exemplarily, the circuit layer 110 of the seventeenth layer and the circuit layer 110 of the eighteenth layer are used as the power supply circuit layer to lay a complete large plane, the circuit layer 110 of the fifteenth layer is used as the power supply circuit layer to lay a 0.75V analog TSC TRVDD (70.57A) with a large current, and the circuit layer 110 of the thirty-second layer is used as the power supply circuit layer to lay a 0.9V analog TSC TRVDD (141A) with a large current.

[0077] It should be noted that, in addition to using these layers as the power supply circuit layer, other circuit layers 110 can also be used to lay current lines for reinforcement. For example, the 0.9V analog TSC TRVDD (141A) with a large current can also be laid in the circuit layer 110 of the thirteenth layer and the circuit layer 110 of the twentieth layer, and other circuit layers 110 can be used for reinforcement. Similarly, other circuit layers 110 can also be used to reinforce the 0.75V power supply layout.

[0078] In some possible implementations, referring to FIG. 1, the circuit board further includes two medium groups, the two medium groups are symmetrically arranged relative to the prepreg 200, and each medium group includes a plurality of medium layers 300. The medium layers 300 in one of the medium layer groups are located between adjacent circuit layers 110 of one of the circuit layer groups 100. The medium layers 300 in the other of the medium layer groups are located between adjacent circuit layers 110 of the other of the circuit layer groups 100. The medium layers 300 between adjacent power supply circuit layers have different materials from the medium layers 300 between adjacent first signal circuit layers. The medium layers 300 between adjacent power supply circuit layers have different materials from the medium layers 300 between adjacent second signal circuit layers. In this way, the cost of the circuit board can be reduced.

[0079] Exemplarily, each circuit layer group 100 includes 16 circuit layers 110, and each medium layer group includes 15 medium layers 300, and each medium layer 300 is located between adjacent circuit layers 110.

[0080] In the embodiment, the structure, material and thickness of the medium layer 300 of the first layer and the medium layer 300 of the last layer are completely same from top to bottom as shown in Fig. 1, so that each layer above the semi-cured layer 200 and each layer below the semi-cured layer 200 can be completely symmetrical, and the yield of the circuit board can be improved when the two circuit layer groups 100 are respectively pressed on the two sides of the semi-cured layer 200 in the one-time pressing process.

[0081] For example, the medium layer 300 between the adjacent power circuit layers is prepared by the mixed pressing process, so that the grade of the medium layer 300 between the adjacent power circuit layers is less than the grade of the medium layer 300 between the adjacent first signal circuit layers and the grade of the medium layer 300 between the adjacent second signal circuit layers. In this way, the quality and performance of the circuit board can be ensured, and the production cost of the circuit board can be saved, for example, compared with the related art in which the grade of the medium layer 300 in the circuit board is all M8N, the production cost can be saved by 20%-30%.

[0082] As an example, the six medium layers 300 of the plurality of medium layers 300 can be prepared by the mixed pressing process, so that the grade of the six medium layers 300 is less than the grade of the remaining medium layers 300. For example, the material grade of the medium layer 300 between the adjacent first signal circuit layers is M8N, and the material grade of the medium layer 300 between the adjacent power circuit layers can be M7 / M7GN / M6 / M4 / M2 / FR4 and other different board material grades. It should be noted that M8N / M7 / M7GN / M6 / M4 / M2 / FR4 are common materials of the medium layer 300, which can be found in the related art, and this embodiment will not be described here.

[0083] Fig. 7 is a simulation diagram of the circuit board provided by the embodiment of the application, and Fig. 8 is another simulation diagram of the circuit board provided by the embodiment of the application.

[0084] In Fig. 7, E1 represents the insertion loss curve obtained by simulating the 8.5 inches high-speed line of the circuit board of the application, and F1 represents the insertion loss curve obtained by simulating the 11.5 inches high-speed line of the circuit board in the related art. In addition, in Fig. 7, the material grade of the medium layer of the circuit board of the application and the circuit board in the related art is M8N.

[0085] In FIG. 8, E2 represents the insertion loss curve of the circuit board of the present application obtained by simulation of high-speed wiring of 8.5 inches, and F2 represents the insertion loss curve of the circuit board of the related art obtained by simulation of high-speed wiring of 11.5 inches. In addition, in FIG. 8, the material grade of the dielectric layer of the circuit board of the present application and the circuit board of the related art is M7GN.

[0086] As is apparent from the curve of FIG. 7, at a frequency of 26.56 GHz, the insertion loss of the circuit board of the present application is -6.852 dB, and the insertion loss of the circuit board of the related art is -8.954 dB, with a difference of more than 2 dB. As is apparent from the curve of FIG. 8, at a frequency of 26.56 GHz, the insertion loss of the circuit board of the present application is -7.898 dB, and the insertion loss of the circuit board of the related art is -10.413 dB, with a difference of more than 2 dB. Therefore, the circuit board provided by the present application, which is designed with the two circuit layer groups 100 symmetrically arranged with respect to the prepreg layer 200, can shorten the longest high-speed signal line connected to TH5 by 3 inches, thereby significantly reducing the insertion loss and improving the performance of the circuit board. In addition, the circuit board, which uses a low-grade dielectric layer 300, can also meet the design requirement of the insertion loss of LP0. It should be noted that dB in this embodiment only represents a unit of measurement.

[0087] The present application also provides an electronic device comprising the circuit board described above.

[0088] The electronic device provided by the present application, due to the use of the circuit board described above, which is designed with the two circuit layer groups 100 symmetrically arranged with respect to the prepreg layer 200, can punch holes near the pins of the connector, thereby reducing the difficulty of fan-out in the connector area. In addition, the longest high-speed signal line of TH5 can be shortened, thereby improving the signal quality. In addition, the cost of the circuit board can be greatly reduced.

[0089] The parallel, perpendicular, numerical values and numerical ranges involved in the embodiments of the present application are approximate values, and there may be a certain range of errors due to the manufacturing process, which can be considered negligible by those skilled in the art.

[0090] In the description of the embodiments of the present application, it should be understood that the terms (if any) "top", "bottom", "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0091] In the description of the embodiments of the present application, it should be understood that the terms "including", "containing" and "having" and any change thereof used herein are intended to cover the process of not excluding any technical feature, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0092] Unless otherwise clearly specified and limited, the terms "mounting", "connecting", "connecting", "fixing" and the like should be understood broadly, for example, can be fixed connection, can also be detachable connection, or become an integral part; can be directly connected, can also be indirectly connected through an intermediate medium, can make two elements inside the communication or the interaction relationship of two elements. For those skilled in the art, the specific meaning of the above terms in the embodiments of the present application can be understood according to the specific circumstances. In addition, the terms "first", "second" and the like are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated.

[0093] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A circuit board, characterized in that, It includes a prepreg layer, two circuit layer groups, multiple first vias, and multiple second vias; Each of the circuit layer groups includes a plurality of circuit layers stacked together. The two circuit layer groups are respectively disposed on opposite sides of the prepreg layer and are symmetrically disposed with respect to the prepreg layer. The plurality of first vias and the plurality of second vias are respectively disposed on opposite sides of the prepreg layer. The plurality of first vias are disposed in one of the circuit layer groups and the plurality of second vias are disposed in the other circuit layer group. One of the circuit layer groups has a connector first pad area on its surface. The connector first pad area includes a plurality of first pads, each first pad corresponding to a first via and electrically connected to the corresponding first via. Each first via is close to the corresponding first pad. Another circuit layer group has a connector second pad area on its surface, the connector second pad area including a plurality of second pads, each second pad corresponding to a second via and electrically connected to the corresponding second via, each second via being close to the corresponding second pad.

2. The circuit board according to claim 1, characterized in that, The first pad area of ​​the connector includes a plurality of first connector areas spaced apart along a first direction, and the second pad area of ​​the connector includes a plurality of second connector areas spaced apart along the first direction; wherein, the first direction is perpendicular to the thickness direction of the circuit board; Each of the first connector regions corresponds to one of the second connector regions, and the first pads in the corresponding first connector region and the second pads in the corresponding second connector region are used to form a connector pad group.

3. The circuit board according to claim 2, characterized in that, Each of the first connector regions includes a plurality of first regions spaced apart along a second direction, and each of the first regions includes a plurality of first pads spaced apart along the first direction. Each of the second connector regions includes a plurality of second regions spaced apart along a second direction, and each of the second regions includes a plurality of second pads spaced apart along the first direction; wherein the first direction, the second direction, and the thickness direction of the circuit board are perpendicular to each other.

4. The circuit board according to claim 3, characterized in that, Each first region corresponds to one second region, and the orthographic projection of the first pad in each first region onto the thickness direction of the circuit board does not overlap with the orthographic projection of the second pad in the corresponding second region onto the thickness direction of the circuit board. Along the second direction, a first via is provided between two adjacent first regions, and a second via is provided between two adjacent second regions.

5. The circuit board according to any one of claims 2-4, characterized in that, The number of connector pad groups is multiple, and the multiple connector pad groups are arranged side by side and spaced apart along the first direction; The surface of one of the circuit layer groups is further provided with a first chip pad area, a second chip pad area, a third chip pad area, and a fourth chip pad area. The first chip pad area and the second chip pad are located between the third chip pad area and the fourth chip pad area. The second chip pad area is located between the first chip pad area and the connector pad group. Any one of the first chip pad area, the second chip pad area, the third chip pad area, and the fourth chip pad area includes a plurality of third pads. The leftmost connector pad group in the first direction is close to the third chip pad area and is used for electrical connection with the third pad in the third chip pad area. The rightmost connector pad group in the first direction is close to the fourth chip pad area and is used for electrical connection with the third pad in the fourth chip pad area.

6. The circuit board according to claim 5, characterized in that, All the circuit layers in the two circuit layer groups include multiple first signal circuit layers, multiple second signal circuit layers, and multiple power circuit layers. The first signal circuit layer is used to electrically connect the third pad in the first chip pad area and the connector pad group. The second signal circuit layer is used to electrically connect the third pad in any one of the second chip pad area, the third chip pad area, and the fourth chip pad area and the connector pad group.

7. The circuit board according to claim 6, characterized in that, The first signal line layer includes sixteen pairs of differential signal lines, and each of the differential signal line pairs includes two differential signal lines.

8. The circuit board according to claim 6, characterized in that, The first signal line layer has four layers, the second signal line layer has eight layers, and the power line layer has four layers.

9. The circuit board according to claim 6, characterized in that, The circuit board also includes two dielectric groups, each of which includes multiple dielectric layers; In one of the dielectric layer groups, the dielectric layer is located between adjacent line layers in one of the line layer groups; in another dielectric layer group, the dielectric layer is located between adjacent line layers in the other line layer group. The material of the dielectric layer between adjacent power line layers is different from the material of the dielectric layer between adjacent first signal line layers; the material of the dielectric layer between adjacent power line layers is different from the material of the dielectric layer between adjacent second signal line layers.

10. An electronic device, characterized in that, Includes the circuit board as described in any one of claims 1 to 9.

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