Forming method for semiconductor substrate layer and preparation method for heterojunction cell

Abstract

The present invention relates to the technical field of preparation of solar cells, and specifically provides a forming method for a semiconductor substrate layer and a preparation method for a heterojunction cell. The forming method for a semiconductor substrate layer comprises: providing a semiconductor substrate layer; performing texturing treatment on the surface of at least one side of the semiconductor substrate layer, so that the surface of the at least one side of the semiconductor substrate layer is a textured surface, wherein the textured surface comprises a plurality of microstructure units; and by means of an acid treatment solution in combination with an ozonizing means or an electrochemical means, performing corrosion treatment on the textured surface of the side of the semiconductor substrate layer, so as to form a plurality of pores structures on the surfaces of the microstructure units. In the forming method for a semiconductor substrate layer provided by the present invention, the plurality of pore structures are formed on the surfaces of part of the microstructure units, thereby further reducing the reflectivity of the surface of the semiconductor substrate layer.

Description

Method for forming semiconductor substrate layer and method for preparing heterojunction cell

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410811364.1, filed on June 21, 2024, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of solar cell preparation, in particular to a method for forming a semiconductor substrate layer and a method for preparing a heterojunction cell. BACKGROUND

[0004] In improving the efficiency of heterojunction cells, how to obtain a good substrate layer texture to improve the absorption of incident light by the heterojunction cell, and how to match with subsequent film layer processes to avoid problems such as scratching caused by the sharp protruding microstructure units constituting the texture, have always been a concern. The current heterojunction solar cell texturing process needs to smooth the texture to facilitate subsequent passivation improvement. However, although smoothing can make the tips of the microstructure units constituting the texture no longer sharp, but smooth, improve the uniformity of the subsequent passivation layer deposition, and improve the passivation effect, it will also make the surface of the microstructure units smoother and more flat, reducing the roughness and increasing the reflectivity of the silicon wafer, ultimately reducing the light absorption of the cell. As shown in FIG. 5, the tips of the microstructure units after smoothing are smooth, but the sidewall surface is also smooth and flat. SUMMARY

[0005] Therefore, to solve the problem that smoothing the texture will increase the reflectivity of the silicon wafer and reduce the light absorption of the cell, the present application provides a method for forming a semiconductor substrate layer and a method for preparing a heterojunction cell.

[0006] The first aspect of the present application provides a method for forming a semiconductor substrate layer, comprising: providing a semiconductor substrate layer; performing a texturing treatment on at least one side surface of the semiconductor substrate layer to make the at least one side surface of the semiconductor substrate layer present a texture; the texture comprises a plurality of microstructure units; performing etching treatment on the side surface of the semiconductor substrate layer present with the texture by an acid treatment liquid in combination with an oxidation method or an electrochemical method to form a plurality of hole structures on the surface of the microstructure units.

[0007] Optionally, the step of etching the textured side of the semiconductor substrate with an acidic treatment solution in conjunction with oxidation or electrochemical means includes: mixing a metal salt solution, a first oxidant, and hydrofluoric acid to prepare a first etching solution; placing the semiconductor substrate in the first etching solution to perform a first reaction; the temperature of the first reaction is 25℃-80℃; the time of the first reaction is 1s-150s; the molar ratio of the metal salt to the first oxidant in the metal salt solution is 0.01-5; and the molar ratio of the first oxidant to the hydrofluoric acid is 0.001-2.

[0008] Optionally, the metal salt in the metal salt solution includes one or more combinations of gold salt, silver salt, platinum salt, copper salt, and nickel salt; the first oxidant includes one or more combinations of hydrogen peroxide, potassium permanganate, and concentrated nitric acid.

[0009] Optionally, the step of etching the textured side of the semiconductor substrate with an acidic treatment solution in conjunction with oxidation or electrochemical means includes: forming a metal layer on the textured side of the semiconductor substrate; after forming the metal layer, annealing the metal layer; after annealing the metal layer, mixing a second oxidant and hydrofluoric acid to prepare a second etching solution, and placing the semiconductor substrate in the second etching solution to perform a second reaction; the temperature of the second reaction is 25℃-80℃; the time of the second reaction is 1s-150s; the temperature of the annealing treatment is 200℃-800℃; the time of the annealing treatment is 60s-600s; and the molar ratio of the second oxidant to the hydrofluoric acid is 0.001-2.

[0010] Optionally, the thickness of the metal layer is 5nm-20nm; the metal layer includes one or more of gold, silver, platinum, copper, and nickel; the second oxidant includes one or more of potassium permanganate, nitric acid, and hydrogen peroxide.

[0011] Optionally, the method further includes: etching the textured side of the semiconductor substrate layer with an acidic treatment solution in conjunction with oxidation or electrochemical means, followed by cleaning the semiconductor substrate layer; the cleaning process uses nitric acid or aqua regia; the mass percentage concentration of the nitric acid is 30wt%-50wt%; and the cleaning time is 60s-900s.

[0012] Optionally, the step of etching the textured side of the semiconductor substrate with an acidic treatment solution in conjunction with oxidation or electrochemical means includes: providing a cathode and a third etching solution; the semiconductor substrate serving as the anode; placing the cathode and the semiconductor substrate in the third etching solution and applying an electric current to perform a third reaction; the cathode comprising graphite; the third etching solution comprising HF solution, the mass percentage concentration of the third etching solution being 0.1wt%-30wt%; the time of the third reaction being 1s-150s; and the temperature of the third reaction being 25℃-60℃.

[0013] Optionally, the depth of the pore structure is 0.5nm-20nm.

[0014] Optionally, the depth of the pore structure is 1nm-10nm.

[0015] Optionally, the shape of the microstructure unit includes an upright pyramid shape, an inverted pyramid shape, or a micron-sized frustum shape;

[0016] Preferably, the height of the microstructure unit is 0.5-5 μm.

[0017] A second aspect of the present invention provides a method for preparing a heterojunction solar cell, wherein the semiconductor substrate is prepared by the semiconductor substrate formation method described in the first aspect of the present invention; the method further includes: sequentially forming an intrinsic semiconductor layer, a doped semiconductor layer, a transparent conductive film, and a gate electrode on at least one side surface of the semiconductor substrate, wherein the conductivity types of the doped semiconductor layers on opposite sides of the semiconductor substrate are opposite.

[0018] A third aspect of the present invention provides a heterojunction solar cell, the heterojunction solar cell comprising a semiconductor substrate layer, at least one surface of the semiconductor substrate layer being textured; the textured surface comprising a plurality of microstructure units; and the surface of the microstructure units forming a plurality of pore structures.

[0019] Optionally, the heterojunction cell meets at least one of the following criteria:

[0020] a. The depth of the pore structure is 0.5nm-20nm;

[0021] b. The depth of the pore structure is 1nm-10nm;

[0022] c. The shape of the microstructure unit includes an upright pyramid, an inverted pyramid, or a micron-sized frustum;

[0023] d. The height of the microstructure unit is 0.5μm-5μm.

[0024] The beneficial effects of this invention are as follows:

[0025] The method for forming a semiconductor substrate provided by this invention involves etching the textured side of the semiconductor substrate using an acidic treatment solution combined with oxidation or electrochemical methods to form a plurality of porous structures on the surface of the microstructure unit. On one hand, the textured surface itself increases the reflection path of sunlight and enhances its light-trapping ability. Furthermore, the formation of a porous structure on the surface of the microstructure unit further increases the reflection path of sunlight and enhances its light-trapping ability, thereby further reducing the reflectivity of the semiconductor substrate surface. The porous structure also facilitates band bending and widening of the band gap, promoting carrier separation and converting some high-energy radiation from sunlight into low-energy light, which is then more effectively absorbed by the semiconductor substrate, improving the photoelectric conversion efficiency of the heterojunction solar cell. On the other hand, during the formation of the porous structure, the structural integrity of the tip portion of the microstructure unit is disrupted, causing the tip to break off and be removed during the formation of the holes. Even if a new tip forms at the opening edge of the hole structure, its size and sharpness are greatly reduced, achieving an effect essentially the same as smoothing the textured surface. This removes sharp portions from the surface of the microstructure unit, improving the uniformity of the subsequent passivation layer deposition and enhancing the passivation effect. Furthermore, the semiconductor substrate formation method provided by this invention can be combined with existing conventional passivation processes to achieve good reflectivity. No additional passivation process needs to be developed to match the semiconductor substrate of this invention, making subsequent processes simple and practical.

[0026] The reflectivity of the substrate obtained by the texturing and smoothing process in the prior art is 11.08%, while the present invention can reduce it to as low as 7.30%. The resulting heterojunction cell can improve the photoelectric conversion efficiency by about 1.7-2.8%.

[0027] Furthermore, the semiconductor substrate formation method provided by this invention employs a first etching solution prepared by mixing a first oxidant and hydrofluoric acid, along with metal ions, for chemical etching treatment. Compared to the prior art using alkaline solutions for smoothing or using acid solutions alone, alkaline solutions exhibit isotropic etching of the texturized silicon wafer with a fast reaction rate, primarily serving a polishing function on the textured surface, thus increasing its reflectivity. In contrast, acid solutions alone are difficult to react with silicon and thus difficult to etch it. They typically only smooth the textured surface in conjunction with an oxidant, but cannot form numerous pores, thus failing to further reduce reflectivity. The semiconductor substrate formation method provided by this invention utilizes a metal salt solution combined with a first etching solution formed by mixing a first oxidant and hydrofluoric acid to smooth the textured surface while simultaneously forming nanoscale pores. This increases the reflection path of incident light on the textured surface, thereby further reducing reflectivity. Simultaneously, it achieves the same effect as smoothing treatment in reducing the sharpness of microstructure unit tips on the textured surface. Attached Figure Description

[0028] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0029] Figure 1 is a flowchart of the method for forming a semiconductor substrate layer in Embodiment 1 of the present invention;

[0030] Figure 2 is a schematic diagram of the first structure of the semiconductor substrate layer in Embodiment 1 of the present invention;

[0031] Figure 3 is a schematic diagram of the second structure of the semiconductor substrate layer in Embodiment 1 of the present invention;

[0032] Figure 4 is a schematic diagram of the third structure of the semiconductor substrate layer in Embodiment 1 of the present invention;

[0033] Figure 5 is an electron microscope image of the microstructure unit after the textured surface has been smoothed in the prior art.

[0034] Figure labeling: 1-Semiconductor substrate; 2-Microstructure unit; 3-Vacuum structure. Detailed Implementation

[0035] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0036] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0038] Example 1

[0039] This invention provides a method for forming a semiconductor substrate layer 1. Referring to FIG1, and FIGS. 2 to 4, the method includes:

[0040] S1: Provides semiconductor substrate layer 1;

[0041] S2: At least one surface of the semiconductor substrate is texturized to make at least one surface of the semiconductor substrate textured; the textured surface includes a plurality of microstructure units 2;

[0042] S3: The textured side of the semiconductor substrate is etched using an acidic treatment solution combined with oxidation or electrochemical methods to form several pore structures 3 on the surface of the microstructure unit 2.

[0043] In this embodiment, the textured surface of the semiconductor substrate is etched using an acidic treatment solution combined with oxidation or electrochemical methods to form a plurality of porous structures on the surface of the microstructure unit 2. On one hand, the textured surface itself increases the reflection path of sunlight and enhances its light-trapping ability. Furthermore, the formation of a porous structure on the surface of the microstructure unit further increases the reflection path of sunlight and enhances its light-trapping ability, thereby further reducing the reflectivity of the semiconductor substrate surface. The porous structure also facilitates band bending and widening of the band gap, promoting carrier separation. It can also convert some high-energy radiation from sunlight into low-energy light, which is then more effectively absorbed by the semiconductor substrate, improving the photoelectric conversion efficiency of the heterojunction cell. On the other hand, during the formation of the porous structure, the structural integrity of the tip portion of the microstructure unit is disrupted, causing the tip to break off and be removed during the hole formation process. Even if a new tip forms at the opening edge of the porous structure, its size and sharpness are greatly reduced, achieving essentially the same effect as rounding the textured surface. This removes sharp portions from the surface of microstructure unit 2, improving the uniformity of the subsequent passivation layer deposition and enhancing the passivation effect. Furthermore, the semiconductor substrate formation method provided by this invention can be combined with existing conventional passivation processes to achieve good reflectivity. No additional passivation process needs to be developed to match the semiconductor substrate of this invention, making subsequent processes simple and practical.

[0044] In one embodiment, the shape of the microstructure unit 2 includes an upright pyramid, an inverted pyramid, or a micron-sized frustum. Specifically, in different embodiments, it can be: referring to Figure 2, the shape of the microstructure unit 2 is an upright pyramid; referring to Figure 3, the shape of the microstructure unit 2 is an inverted pyramid; referring to Figure 4, the shape of the microstructure unit 2 is a micron-sized frustum, where "micron-sized frustum" refers to a frustum with both its diameter and height on the order of micrometers.

[0045] In one embodiment, the texturing process for at least one surface of the semiconductor substrate includes one or a combination of wet processes. In other embodiments, the texturing process for at least one surface of the semiconductor substrate includes other processes.

[0046] In this embodiment, the perforated structure 3 is distributed on the surface of each of the microstructure units 2. Since the amount of incident sunlight reflected from the surface of the microstructure unit 2 is low, the perforated structure 3 can increase the reflection path of sunlight, enhance the light-trapping ability of the microstructure unit 2, and thus further reduce the reflectivity of the semiconductor substrate layer 1.

[0047] In one embodiment, the height of the microstructure unit 2 is 0.5 μm-5 μm. "Height of microstructure unit 2" refers to the distance from the top of the microstructure unit to its bottom surface. "Bottom surface of microstructure unit" refers to a cross-section parallel to the substrate layer in the direction where the deepest part of the void adjacent to the microstructure unit is located. If multiple cross-sections exist, the cross-section closest to the top of the microstructure unit is used as the bottom surface of the microstructure unit. For example, it can be 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm, or any combination thereof. The heights of the various microstructure units 2 may be the same or different. The height of "microstructure unit 2" is tested using SEM.

[0048] In one embodiment, the depth of the hole structure 3 is 0.5nm-20nm, preferably 1nm-10nm, for example, 0.5nm, 1nm, 5nm, 10nm, 20nm, or any combination thereof; "the depth of the hole structure 3" refers to the distance from the deepest point of the hole structure to the plane where the opening of the hole structure is located, and the depths of each hole structure 3 may be the same or different. The test method for "the depth of the hole structure 3" is to use SEM for testing. If the depth of the hole structure 3 is too large, the effect of subsequent deposition of the passivation layer is poor, the carrier recombination on the surface of the semiconductor substrate layer 1 is serious, and the effect of improving the photoelectric conversion efficiency of the heterojunction cell is weak; if the depth of the hole structure 3 is too small, the effect of enhancing the light-trapping ability of the textured surface is weak, and the effect of reducing the reflectivity of the surface of the semiconductor substrate layer 1 is small.

[0049] In one embodiment, the step of etching the textured side of the semiconductor substrate 1 using an acidic treatment solution combined with oxidation or electrochemical methods includes: mixing a metal salt solution, a first oxidant, and hydrofluoric acid to prepare a first etching solution; and placing the semiconductor substrate in the first etching solution to undergo a first reaction. In the metal salt solution, metal ions contacting the textured surface of the semiconductor substrate are reduced, the textured surface is oxidized by the first oxidant, and the formed oxide layer is etched by hydrofluoric acid. While the above processes occur simultaneously, metal particles create pores on the surface of the microstructure units, forming at least a portion of the microstructure unit's surface with a plurality of porous structures.

[0050] The first etching solution, prepared by mixing a first oxidant and hydrofluoric acid, is used in conjunction with metal ions for chemical etching. Compared to existing technologies that use alkaline solutions for smoothing or acid solutions alone, the alkaline solution exhibits an isotropic etching reaction on the texturized silicon wafer, with a fast reaction rate, primarily serving a polishing effect on the textured surface, thus increasing its reflectivity. In contrast, acid solutions alone are difficult to react with silicon and thus difficult to etch it. They typically only smooth the textured surface in conjunction with the oxidant, but cannot form sufficient pores to further reduce reflectivity. The semiconductor substrate formation method provided by this invention utilizes a metal salt solution combined with the first etching solution formed by mixing a first oxidant and hydrofluoric acid. This creates nanoscale pores, increasing the reflection path of incident light on the textured surface, thereby further reducing reflectivity. Simultaneously, it achieves the same effect as smoothing treatment in reducing the sharpness of microstructural unit tips on the textured surface.

[0051] In one embodiment, the temperature of the first reaction is 25°C-80°C, for example, 25°C, 30°C, 45°C, 50°C, 60°C or 80°C, or any combination thereof; the time of the first reaction is 1s-150s, for example, 1s, 20s, 40s, 60s, 80s, 100s, 120s or 150s, or any combination thereof.

[0052] In one embodiment, the molar ratio of the metal salt to the first oxidant in the metal salt solution is 0.01-5, and the "metal salt solution" is an aqueous solution of the metal salt, for example, 0.01, 1, 2, 3, 4 or 5, or any combination thereof; the molar ratio of the first oxidant to the hydrofluoric acid is 0.001-2, for example, 0.001, 0.5, 1, 1.5 or 2, or any combination thereof.

[0053] In one embodiment, the metal salt in the metal salt solution includes one or more combinations of gold salt, silver salt, platinum salt, copper salt, and nickel salt; the first oxidant includes one or more combinations of hydrogen peroxide, potassium permanganate, and concentrated nitric acid.

[0054] The method for forming a semiconductor substrate further includes: etching the textured side of the semiconductor substrate using an acidic treatment solution combined with oxidation or electrochemical methods, followed by cleaning the semiconductor substrate 1. The purpose of cleaning is to remove metal particles from the textured side of the semiconductor substrate. Specifically, after the first reaction, the semiconductor substrate 1 is cleaned.

[0055] In one embodiment, the cleaning treatment uses nitric acid or aqua regia; the mass percentage concentration of the nitric acid is 30wt%-50wt%, for example, 30wt%, 40wt%, or 50wt%, or any combination thereof; the cleaning treatment time is 60s-900s, for example, 60s, 200s, 400s, 600s, 800s, or 900s, or any combination thereof.

[0056] To demonstrate the beneficial effects of the present invention, Comparative Example 1 is provided for comparison with several Examples 1 (Examples 1A to 1D).

[0057] Comparative Example 1

[0058] The method for forming a semiconductor substrate in Comparative Example 1 differs from that in Example 1 in that step S3 of Example 1 is omitted: the textured side of the semiconductor substrate is etched using an acidic solution combined with oxidation or electrochemical methods. Instead, the textured side is smoothed, specifically including:

[0059] (1) Pre-cleaning the original silicon wafer: Use a mixed solution containing 1 wt% sodium hydroxide and 10 wt% hydrogen peroxide, treat at 65°C for 4 min, and then use a 10 wt% sodium hydroxide solution, treat at 75°C for 2 min to remove the damaged layer.

[0060] (2) A texturing solution containing 1 wt% sodium hydroxide and 1 wt% texturing additive is used to texture at 80°C for 480 s to form a textured surface on one side of the silicon wafer.

[0061] (3) Perform RCA1 cleaning: Use a cleaning solution containing 2wt% sodium hydroxide and 10wt% hydrogen peroxide, and clean at 65°C for 2 minutes. Then perform RCA2 cleaning: Use a cleaning solution containing 10wt% hydrogen peroxide and 5wt% hydrochloric acid, and clean at 65°C for 2 minutes.

[0062] (4) Remove the silicon oxide layer in 10wt% HF for 2 min. The surface of the microstructure units of the prepared silicon wafer does not have a porous structure.

[0063] In the semiconductor substrate layer obtained in Example 1A: the height of the microstructure unit 2 is 0.5 μm; the depth of the hole structure 3 is 0.5 nm;

[0064] In the semiconductor substrate layer obtained in Example 1B: the height of the microstructure unit 2 is 2 μm; the depth of the hole structure 3 is 5 nm;

[0065] In the semiconductor substrate layer obtained in Example 1C: the height of the microstructure unit 2 is 3 μm; the depth of the hole structure 3 is 10 nm;

[0066] In the semiconductor substrate layer obtained in Example 1D: the height of the microstructure unit 2 is 5 μm; the depth of the hole structure 3 is 20 nm.

[0067] In Examples 1A to 1D:

[0068] The height of the microstructural units was obtained by SEM testing. Specifically, 100 microstructural units were randomly selected within the field of view, and their heights were measured, with the mode being used as the height value.

[0069] The depth of the hole structure was obtained by SEM testing. Specifically, 100 holes were randomly selected within the field of view, the depth was measured, and the mode was used as the hole depth value.

[0070] The reflectivity of the semiconductor substrates obtained in Examples 1A to 1D and Comparative Example 1 was tested, and the results are shown in Table 1 below:

[0071] Table 1 Comparison of reflectivity of semiconductor substrates

[0072] In Table 1, the reflectance is tested using a spectrophotometer.

[0073] As can be seen from the table, the semiconductor substrate obtained by the method of Example 1, which involves etching the textured side of the semiconductor substrate with an acidic treatment solution in conjunction with oxidation or electrochemical means, has a significantly lower reflectivity than the semiconductor substrate obtained by the method of Comparative Example 1.

[0074] Using the semiconductor substrates obtained in Example 1 and Comparative Example 1, heterojunction solar cells with identical structures (excluding the semiconductor substrate) were fabricated using the same method. Photoelectric conversion efficiency and related parameters were tested, and the results are shown in Table 2 below.

[0075] Table 2 Comparison of Battery Performance

[0076] In Table 2, all electrical performance parameter test methods use I-V test equipment.

[0077] As can be seen from the table, the method of Example 1 involves etching one side of the textured semiconductor substrate with an acidic treatment solution combined with oxidation or electrochemical methods to form a series of pores on the textured surface, and then smoothing the textured surface to obtain a heterojunction cell. Compared with the heterojunction cell obtained by the semiconductor substrate of Comparative Example 1, the short-circuit current, fill factor, and photoelectric conversion efficiency are all improved. The final photoelectric conversion efficiency is about 1.7-2.8% higher than that of Comparative Example 1 (i.e., the prior art method of smoothing after texturing).

[0078] Example 2

[0079] The difference between this embodiment and Embodiment 1 is that:

[0080] The step of etching the textured side surface of the semiconductor substrate 1 using an acidic treatment solution in conjunction with oxidation or electrochemical means includes: forming a metal layer on the textured side surface of the semiconductor substrate 1; after forming the metal layer, annealing the metal layer; after annealing the metal layer, mixing a second oxidant and hydrofluoric acid to prepare a second etching solution, and placing the semiconductor substrate in the second etching solution to carry out a second reaction.

[0081] The process for forming the metal layer includes one of sputtering, vapor deposition, and deposition. After forming the metal layer, the metal layer is annealed to form a metal particle layer on the textured side surface of the semiconductor substrate 1; that is, the flat metal layer is transformed into a layer composed of metal particles. Subsequently, during the second reaction in the second etching solution, the metal particles oxidize upon contact with the textured surface of the semiconductor substrate, and the resulting oxide layer is etched by hydrofluoric acid. Simultaneously, the metal particles create pores on the surface of the microstructure units, forming at least a portion of the surface of the microstructure units with several pore structures.

[0082] In one embodiment, the temperature of the second reaction is 25°C-80°C, for example, 25°C, 30°C, 45°C, 50°C, 60°C or 80°C, or any combination thereof; the time of the second reaction is 1s-150s, for example, 1s, 20s, 40s, 60s, 80s, 100s, 120s or 150s, or any combination thereof.

[0083] In one embodiment, the annealing temperature is 200℃-800℃, for example, 200℃, 400℃, 600℃ or 800℃, or any combination thereof; the annealing time is 60s-600s, for example, 60s, 100s, 200s, 300s, 400s, 500s or 600s, or any combination thereof.

[0084] In one embodiment, the molar ratio of the second oxidant to the hydrofluoric acid is 0.001-2, for example, 0.001, 0.05, 1 or 2, or any combination thereof.

[0085] In one embodiment, the thickness of the metal layer is 5nm-20nm, for example, 5nm, 10nm, 15nm, 20nm, or any combination thereof. The metal layer includes one or more of gold, silver, platinum, copper, and nickel; the second oxidant includes one or more of potassium permanganate, nitric acid, and hydrogen peroxide.

[0086] It should be noted that after the second reaction, the semiconductor substrate 1 is cleaned. In this embodiment, the process requirements for the cleaning process are the same as in Embodiment 1. In other embodiments, the process requirements for the cleaning process are different from those in Embodiment 1.

[0087] Example 3

[0088] The difference between this embodiment and Embodiment 1 is that:

[0089] The steps of etching the textured side of the semiconductor substrate 1 using an acidic treatment solution combined with oxidation or electrochemical methods include: providing a cathode and a third etching solution; the semiconductor substrate 1 serving as the anode; placing the cathode and anode in the third etching solution and applying an electric current to initiate a third reaction. Electrochemical etching primarily utilizes the principle of chemical bond breaking and bonding during the electrochemical reaction between the third etching solution and the silicon wafer to modify and etch the silicon wafer surface. For example, when hydrofluoric acid is used as the third etching solution (i.e., the electrolyte), fluoride ions in the hydrofluoric acid continuously break silicon-hydrogen bonds under the influence of the electric current, thereby forming SiF4 and H2. Subsequently, the SiF4 falling into the third etching solution continuously etches, creating pores on the surface of the microstructure units.

[0090] In one embodiment, the cathode comprises graphite; the third etching solution comprises an HF solution, and the mass percentage concentration of the third etching solution is 0.1 wt% to 30 wt%, for example, 0.5 wt%, 10 wt%, 15 wt%, 30 wt%, or any combination thereof; the time of the third reaction is 1 s to 150 s, for example, 1 s, 20 s, 40 s, 60 s, 80 s, 100 s, 120 s, or 150 s, or any combination thereof; the temperature of the third reaction is 25°C to 60°C, for example, 25°C, 40°C, 50°C, 60°C, or any combination thereof.

[0091] It should be noted that, in this embodiment, there is no need to clean the semiconductor substrate after the third reaction.

[0092] Example 4

[0093] This embodiment provides a method for preparing a heterojunction solar cell, which uses the semiconductor substrate layer 1 formation method described in any one of Embodiments 1 to 3 to prepare the semiconductor substrate layer; it further includes: sequentially forming an intrinsic semiconductor layer, a doped semiconductor layer, a transparent conductive film and a gate electrode on at least one side surface of the semiconductor substrate layer 1, wherein the conductivity types of the doped semiconductor layers on opposite sides of the semiconductor substrate layer 1 are opposite.

[0094] Specifically, after etching the textured surface of the semiconductor substrate 1 using an acidic treatment solution combined with oxidation or electrochemical methods, a first intrinsic semiconductor layer is formed on the first side surface of the semiconductor substrate, and a second intrinsic semiconductor layer (not shown in the figure) is formed on the second side surface of the semiconductor substrate. A first doped semiconductor layer is formed on the side surface of the first intrinsic semiconductor layer facing away from the semiconductor substrate 1, and a second doped semiconductor layer is formed on the side surface of the second intrinsic semiconductor layer facing away from the semiconductor substrate 1 (not shown in the figure). A first transparent conductive film is formed on the side surface of the first doped semiconductor layer facing away from the semiconductor substrate 1, and a second transparent conductive film is formed on the side surface of the second doped semiconductor layer facing away from the semiconductor substrate 1 (not shown in the figure). A first gate electrode is formed on the side surface of the first transparent conductive film facing away from the semiconductor substrate 1, and a second gate electrode is formed on the side surface of the second transparent conductive film facing away from the semiconductor substrate 1 (not shown in the figure). The conductivity type of the second doped semiconductor layer is opposite to that of the first doped semiconductor layer.

[0095] In one embodiment, the first doped semiconductor layer is N-type and the second doped semiconductor layer is P-type, as an example.

[0096] The present invention provides a semiconductor substrate prepared by the semiconductor substrate formation method of the present invention.

[0097] The present invention provides a semiconductor substrate layer, wherein at least one surface of the semiconductor substrate layer is textured; the textured surface includes a plurality of microstructure units; and a plurality of hole structures are formed on the surface of the microstructure units.

[0098] The present invention provides a heterojunction solar cell, the heterojunction solar cell comprising a semiconductor substrate layer, at least one surface of the semiconductor substrate layer being textured; the textured surface comprising a plurality of microstructure units; and the surface of the microstructure units forming a plurality of pore structures.

[0099] In one embodiment, the heterojunction solar cell meets at least one of the following criteria:

[0100] a. The depth of the pore structure is 0.5nm-20nm;

[0101] b. The depth of the pore structure is 1nm-10nm;

[0102] c. The shape of the microstructure unit includes an upright pyramid, an inverted pyramid, or a micron-sized frustum;

[0103] d. The height of the microstructure unit is 0.5μm-5μm.

[0104] In one embodiment, the heterojunction cell further includes: an intrinsic semiconductor layer, a doped semiconductor layer, a transparent conductive film, and a gate electrode sequentially stacked on at least one side surface of the semiconductor substrate 1, wherein the doped semiconductor layers on opposite sides of the semiconductor substrate 1 have opposite conductivity types.

[0105] In one embodiment, a heterojunction solar cell includes a first gate electrode, a first transparent conductive film, a first doped semiconductor layer, a first intrinsic semiconductor layer, a semiconductor substrate layer, a second intrinsic semiconductor layer, a second doped semiconductor layer, a second transparent conductive film, and a second gate electrode, which are sequentially stacked.

[0106] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A method for forming a semiconductor substrate layer, comprising: Provide semiconductor substrate layer; At least one surface of the semiconductor substrate is texturized to give at least one surface of the semiconductor substrate a textured surface; the textured surface includes a plurality of microstructure units. The feature is that the textured side of the semiconductor substrate is etched by an acidic treatment solution combined with oxidation or electrochemical means to form a plurality of pore structures on the surface of the microstructure unit.

2. The method for forming a semiconductor substrate layer according to claim 1, characterized in that, The step of etching the textured side of the semiconductor substrate layer using an acidic treatment solution combined with oxidation or electrochemical methods includes: mixing a metal salt solution, a first oxidant, and hydrofluoric acid to prepare a first etching solution; and placing the semiconductor substrate layer in the first etching solution to perform a first reaction. The temperature of the first reaction is 25℃-80℃; the time of the first reaction is 1s-150s; The molar ratio of the metal salt to the first oxidant in the metal salt solution is 0.01-5; the molar ratio of the first oxidant to the hydrofluoric acid is 0.001-2.

3. The method for forming a semiconductor substrate layer according to claim 2, characterized in that, The metal salt in the metal salt solution includes one or more of gold salt, silver salt, platinum salt, copper salt, and nickel salt; the first oxidant includes one or more of hydrogen peroxide, potassium permanganate, and concentrated nitric acid.

4. The method for forming a semiconductor substrate layer according to claim 1, characterized in that, The step of etching the textured side surface of the semiconductor substrate with an acidic treatment solution in conjunction with oxidation or electrochemical means includes: forming a metal layer on the textured side surface of the semiconductor substrate; after forming the metal layer, annealing the metal layer; after annealing the metal layer, mixing a second oxidant and hydrofluoric acid to prepare a second etching solution, and placing the semiconductor substrate in the second etching solution to carry out a second reaction; The temperature of the second reaction is 25℃-80℃; the time of the second reaction is 1s-150s; The annealing temperature is 200℃-800℃; the annealing time is 60s-600s; The molar ratio of the second oxidant to the hydrofluoric acid is 0.001-2.

5. The method for forming a semiconductor substrate layer according to claim 4, characterized in that, The thickness of the metal layer is 5nm-20nm; the metal layer includes one or a mixture of gold, silver, platinum, copper, and nickel; the second oxidant includes one or a combination of potassium permanganate, nitric acid, and hydrogen peroxide.

6. The method for forming a semiconductor substrate layer according to any one of claims 1-5, characterized in that, Also includes: After etching the textured side of the semiconductor substrate layer using an acidic treatment solution combined with oxidation or electrochemical methods, the semiconductor substrate layer is then cleaned. The cleaning process uses nitric acid or aqua regia; the nitric acid has a mass percentage concentration of 30wt%-50wt%; and the cleaning time is 60s-900s.

7. The method for forming a semiconductor substrate layer according to claim 1, characterized in that, The step of etching the textured side of the semiconductor substrate layer using an acidic treatment solution combined with oxidation or electrochemical methods includes: providing a cathode and a third etching solution; the semiconductor substrate layer serving as the anode; placing the cathode and the semiconductor substrate layer in the third etching solution and applying an electric current to carry out a third reaction; The cathode component comprises graphite; the third etching solution comprises HF solution, and the mass percentage concentration of the third etching solution is 0.1wt%-30wt%; the time of the third reaction is 1s-150s; and the temperature of the third reaction is 25℃-60℃.

8. The method for forming a semiconductor substrate layer according to any one of claims 1-7, characterized in that, The depth of the pore structure is 0.5nm-20nm.

9. The method for forming a semiconductor substrate layer according to any one of claims 1-7, characterized in that, The depth of the pore structure is 1nm-10nm.

10. The method for forming a semiconductor substrate layer according to any one of claims 1-9, characterized in that, The shape of the microstructure unit includes an upright pyramid, an inverted pyramid, or a micron-sized frustum; Preferably, the height of the microstructure unit is 0.5μm-5μm.

11. A method for preparing a heterojunction solar cell, characterized in that, The semiconductor substrate layer is prepared by the method for forming a semiconductor substrate layer according to any one of claims 1 to 10; It also includes: forming an intrinsic semiconductor layer, a doped semiconductor layer, a transparent conductive film, and a gate electrode sequentially on at least one side surface of the semiconductor substrate, wherein the doped semiconductor layers on opposite sides of the semiconductor substrate have opposite conductivity types.

12. A heterojunction solar cell, said heterojunction solar cell comprising a semiconductor substrate layer, characterized in that, At least one surface of the semiconductor substrate is textured; the textured surface includes a plurality of microstructure units; the surface of the microstructure units forms a plurality of hole structures.

13. The heterojunction solar cell according to claim 12, characterized in that, The heterojunction solar cell meets at least one of the following criteria: a. The depth of the pore structure is 0.5nm-20nm; b. The depth of the pore structure is 1nm-10nm; c. The shape of the microstructure unit includes an upright pyramid, an inverted pyramid, or a micron-sized frustum; d. The height of the microstructure unit is 0.5μm-5μm.

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