Pixel circuit and image sensor

Abstract

A pixel circuit (100) comprises a floating diffusion (102) configured to be connected to a photosensitive element (11), the photosensitive element (11) being configured to generate charges in response to incident electromagnetic radiation (15). The pixel circuit (100) further comprises a first transistor (110), a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) and a terminal (112) of the first transistor (110) being connected to a first node (118). The pixel circuit (100) further comprises a capacitor arrangement (120) comprising a first capacitor (121) and a second capacitor (123). A first terminal of the first capacitor (121) is configured to be connected to the first node (118), and a second terminal of the first capacitor (121) being connected to a capacitor voltage supply. A first terminal of the second capacitor (123) is configured to be connected to the first node (118), and a second terminal of the second capacitor (123) being connected to the capacitor voltage supply. The capacitor voltage supply is configured to be operated at a first level (126) during a global operation (S100) and at a second level (127) different from the first level (126) during a local operation (S200).

Description

[0001] PIXEL CIRCUIT AND IMAGE SENSOR

[0002] Voltage domain global shutter image sensors are used in a variety of applications , including e . g . machine vision applications . Due their fast read out , their low parasitic light sensitivity ( PLS ) and the possibility of pipelining integration and read out , these image sensors are increasingly employed .

[0003] Generally, attempts are being made to improve the performance of these image sensors .

[0004] It is an obj ect of the present invention to provide an improved pixel circuit and improved image sensor .

[0005] SUMMARY

[0006] According to embodiments , the above obj ects are achieved by the claimed matter according to the independent claims . Further developments are defined in the dependent claims .

[0007] According to embodiments , a pixel circuit comprises a floating di f fusion configured to be connected to a photosensitive element , the photosensitive element being configured to generate charges in response to incident electromagnetic radiation . The pixel circuit may further comprise a reset transistor connected to the floating di f fusion for resetting the floating di f fusion to a predetermined voltage . The pixel circuit further comprises a first transistor, a gate electrode of the first transistor being electrically connected to the floating di f fusion, and a terminal of the first transistor being connected to a first node . The pixel circuit further comprises a capacitor arrangement comprising a first capacitor and a second capacitor . A first terminal of the first capacitor is configured to be connected to the first node , and a second terminal of the first capacitor is connected to a capacitor voltage supply . A first terminal of the second capacitor is configured to be connected to the first node , and a second terminal of the second capacitor is connected to the capacitor voltage supply . The capacitor voltage supply is configured to be operated at a first level during a global operation and at a second level di f ferent from the first level during a local operation .

[0008] For example , an output of the capacitor arrangement is connected to a gate electrode of a second transistor, a first terminal of the second transistor being connectable to a column output .

[0009] According to further embodiments , the first terminal of the first capacitor may be configured to be connected to the first node via a first sampling transistor and the first terminal of the second capacitor may be configured to be connected to a second node via a second sampling transistor . The pixel circuit may further comprise a third transistor between the first node and a node connected to the first sampling transistor and to the second node .

[0010] According to embodiments , the pixel circuit may further comprise a first sampling transistor between the first node and a node connected to the first terminal of the first capacitor, and a second sampling transistor between the node connected to the first terminal and a second node connected to the first terminal of the second capacitor .

[0011] For example , the pixel circuit may further comprise a precharge transistor electrically connected to the first node .

[0012] A method of manufacturing a pixel circuit as described above comprises measuring a DC dark level of a pixel and determining the second level based on the DC dark level and the first level , wherein the DC dark level corresponds to a voltage signal when no electromagnetic radiation is incident .

[0013] According to further embodiments , an image sensor comprises an array of pixels . Each of the pixels comprises a photosensitive element and a pixel circuit . At least one of the pixel circuit is implemented as has been described above .

[0014] For example , the image sensor may further comprise a memory for storing the second level .

[0015] According to embodiments , the image sensor may further comprise a temperature sensor for measuring a temperature of the image sensor, wherein the second level is determined additionally based on the measured temperature .

[0016] A method of manufacturing an image sensor as has been described above comprises measuring a DC dark level of the array of pixel circuits and determining the second level based on the DC dark level and the first level , wherein the DC dark level corresponds to a voltage signal when no electromagnetic radiation is incident .

[0017] The method may further comprise storing the second level in a memory .

[0018] For example , the second level may be stored in dependence from an operating temperature .

[0019] BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorpo- rated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles. Other embodiments of the invention and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numbers designate corresponding similar parts.

[0021] Fig. 1A shows an example of an equivalent circuit diagram of a pixel circuit according to embodiments.

[0022] Fig. IB shows a timing for sampling global shutter signals when operating the pixel circuit illustrated e.g. in Fig. 1A.

[0023] Fig. 2 shows an example of voltage levels of a pixel.

[0024] Fig. 3 shows an example of an equivalent circuit diagram of a pixel circuit according to further embodiments.

[0025] Fig. 4 shows an example of an image sensor according to embodiments .

[0026] DETAILED DESCRIPTION

[0027] In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as "top", "bottom", "front", "back", "over", "on", "above", "leading", "trailing" etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be posi- tioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims.

[0028] The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

[0029] The pixel circuit 100 of Fig. 1A comprises a floating diffusion 102 that is configured to be connected to a photosensitive element 11. The photosensitive element 11 is configured to generate charges in response to incident radiation 15.

[0030] For example, the photosensitive element 11 may comprise a photodiode, for example a pinned photodiode, or any other suitable photosensitive element. The floating diffusion 102 may be connected to the photosensitive element 11 e.g. via a transfer transistor 107. The transfer transistor 107 may also be a component of the pixel circuit 100. According to implementations, the floating diffusion 102 may be implemented as a capacitor and may implement a sense node. For example, charges generated by the photosensitive element 11 due to irradiation with incident radiation 15 may be transferred to the floating diffusion 102 via the transfer transistor 107.

[0031] The pixel circuit 100 may further comprise a reset transistor 105 which is connected to the floating diffusion 102. The reset transistor 105 is configured to reset the floating diffusion 102 to a predetermined voltage, e.g. VDDPIX.

[0032] The pixel circuit 100 further comprises a first transis- tor 110. A gate electrode 111 of the first transistor 110 is electrically connected to the floating diffusion 102. A first terminal 113, e.g. a drain terminal of the first transistor 110 may be electrically connected to a supply voltage e.g. VDDPIX. A second terminal 112, e.g. a source terminal of the first transistor 110 is electrically connected to a capacitor arrangement 120 for storing charges. As is illustrated in Fig. 1A, the second terminal 112 may be electrically connected to a first node 118 that may be electrically connected to the capacitor arrangement 120. The first transistor 110 implements a source follower, e.g. a source follower 1.

[0033] As is further illustrated in Fig. 1A, the pixel circuit 100 may further comprise a precharge transistor 116. A first terminal 117, e.g. a drain region of the precharge transistor 116 is connected to the first node 118. A second terminal, e.g. a source terminal, of the precharge transistor 116 may be connected to VL or GND. The precharge transistor 116 is biased to discharge the capacitor arrangement 120. As a result, the correct voltages on the capacitors of the capacitor arrangement

[0034] 120 may be sampled.

[0035] The capacitor arrangement 120 may comprise a first capacitor

[0036] 121 and a second capacitor 123. For example, the capacitor arrangement 120 may further comprises a first sampling transistor 122 which is arranged between the first capacitor 121 and a node that is connected to the first node 118. For example, a third transistor 125 may be arranged between the first node 118 and the node connected to the first sampling transistor 122. Moreover, a second sampling transistor 124 may be arranged between the second capacitor 123 and a second node 119. The second node 119 is connected to the node connected to the first sampling transistor 122. As is illustrated in Fig. 1A, a first terminal of the first capacitor 121 is configured to be connected to the first node 118 and a second terminal of the first capacitor 121 is connected to a capacitor voltage supply VSSPC.

[0037] Further, a first terminal of the second capacitor 123 is configured to be connected to the first node 118, e.g. via the second node 119. Further, a second terminal of the second capacitor 123 is connected to the capacitor voltage supply VSSPC.

[0038] As will be explained below with reference to Fig IB, the capacitor voltage supply VSSPC is configured to be operated at a first level 126 during a global operation, e.g. during exposure and charge carrier integration. Further, the capacitor voltage supply VSSPC is configured to be operated at a second level 127 different from the first level during a local operation, e.g. a readout process.

[0039] An output of the capacitor arrangement 120 may be electrically connected to a gate electrode 134 of a second transistor 135. For example, as is illustrated in Fig. 1A, the second node 119 may be connected to the gate electrode 134. A first terminal 136, e.g. a source terminal, of the second transistor 135 may be electrically connected to a column output 16, e.g. via a selection transistor 138. A second terminal, e.g a drain terminal of the second transistor 135 may be electrically connected to VDDPIX.

[0040] For example, the second transistor 135 may implement a second source follower, e.g. source follower 2. The selection transistor 138 may be arranged between the second transistor 135 and the column output 16. For example, a first terminal 139, e.g. a source terminal of the selection transistor 138 may be electrically connected to the first terminal 136 of the second transistor 135. A second terminal 140, e.g. a drain terminal of the selection transistor 138 may be electrically connected to the column output 16. The gate electrode of the selection transistor 138 may be supplied with a selection signal.

[0041] As will be explained below with reference to Fig. IB, during readout, charges corresponding to a black level or dark reference level may be stored in the second capacitor 123, while charges corresponding to the sum of detected light and the black level may be stored in the first capacitor 121 or vice versa, depending on the timing diagram. By subtracting e.g. a digital signal corresponding to the charges stored in the second capacitor 123 from a digital signal corresponding to the charges stored in the first capacitor 121, a digital signal corresponding to the detected light may be determined. Due to process variations when manufacturing the first transistor 110, the threshold voltage of the first transistor 110 may largely vary. Moreover, due to process variations when manufacturing the second transistor 135, the threshold voltage of the second transistor 135 may largely vary.

[0042] Due to the presence of the capacitor voltage supply VSSPC that is configured to be operated at a first level during a global operation and at a second level different from the first level during a local operation, these variations may be compensated in an easy manner.

[0043] Fig. IB shows waveforms of signals supplied to the single transistors during different phases of a sampling global shutter process. S100 in Fig. IB denotes a global operation, e.g. an exposure and integration process, whereas S200 denotes a local operation, e.g. a row readout process. During exposure to incident radiation 15, electrons are generated and collected in the photosensitive element 11. At the same time, between tO and tl the floating diffusion 102 is reset to VDDPIX. At t=tl, the reset transistor 105 is switched off. At t=t2, the precharge transistor 116, the first sampling transistor 122, and the third transistor 125 are switched on, resulting in a discharge of the first capacitor 121. After switching off the precharge transistor 116, the reset level corresponding to the dark signal is stored in the first capacitor 121.

[0044] At t=t3, the transfer transistor 107 is switched on and the charges collected in the photosensitive element 102 are transferred to the floating diffusion 102.

[0045] At t=t4, the precharge transistor 116, the second sampling transistor 124, and the third transistor 125 are switched on, resulting in a discharge of the second capacitor 123. At t=t5, the precharge transistor 116 is switched off. Accordingly, charges corresponding to signal charges stored in the floating diffusion 102 are stored in the second capacitor 123.

[0046] At t=t6, the selection transistor 138 is switched on. At t=t7, the first sampling transistor 122 is switched on resulting in a readout of the charges stored on the first capacitor 121. At t=t8, after switching off the first sampling transistor 122, the second sampling transistor 124 is switched on resulting in a readout of the charges stored on the second capacitor 123.

[0047] Fig. 2 illustrates an example of a voltage level corresponding to charges stored on the second capacitor 123 and to a difference between charges stored on the first capacitor 121 and on the second capacitor 123. The output dark level, e.g. the voltage level corresponding to charges stored on the second capacitor 123 may vary considerably between different image sensors. This variation (indicated by the arrow shown in Fig. 2) may be particularly due to variations of the threshold voltage of the first and / or the second transistors 110, 135.

[0048] According to embodiments, as is illustrated in Fig. IB, the capacitor voltage supply VSSPC may be operated at different levels. In particular, during the global operation S100, the capacitor voltage supply VSSPC may be at a first level 126, and during the local operation S200, the capacitor voltage supply VSSPC may be at a second level 127. For example, the capacitor voltage supply VSSPC may be at the second level during a readout process. According to implementations, the capacitor voltage supply VSSPC may be at the second level while the selection transistor 138 is switched on. For example, the capacitor voltage supply VSSPC may be maintained at the second level during the local operation S200. For example, the capacitor voltage supply VSSPC may be maintained at the second level while the selection transistor 138 is switched on.

[0049] For example, the first level 126 may be fixed, e.g. a small value of more than 500 mV. For example, the first level 126 may be less than 1500 mV, for example IV. The second level 127 may be determined in dependence from the first level 126 and a DC voltage level of the dark or reset signal. For example, the DC voltage level of the dark or reset signal may be determined for a specific pixel or may correspond to an average value for a pixel array.

[0050] For example, the desired dark level voltage at the column output 16 is determined to be VI, e.g. 1.5 V. The actual dark level voltage, V2, e.g. 1.2 V, at the column output 16 is measured. The difference between the second level 127 and the first level 126 of the capacitor voltage supply VSSPC may correspond to the difference between VI and V2, e.g. 0.3 V. Accordingly, the second level 127 may be equal to the sum of the first level 126 and the difference between VI and V2, e.g. 1.3 V. By shifting the voltage applied to the second terminal of the first capacitor 121 and the second capacitor 123, the voltage variation illustrated in Fig. 2 may be reduced.

[0051] According to embodiments, the DC level of the dark signal of a pixel or a pixel array may be measured during wafer sort and / or a final test. Based on the measured DC level or an average of the measured DC levels, the second level 127 may be determined with respect to the first level 126. The second level 127 may be stored in a permanent on-chip memory of the image sensor, e.g. in a one time programmable memory.

[0052] According to further implementations, an image sensor 20 (illustrated in Fig. 4) may be operable in a calibration mode. For example, the calibration mode may be automatically or manually performed with a set frequency during use. For example, when operated in the calibration mode, the DC level of the dark signal of a pixel or a pixel array may be measured. Based on the measured DC level or an average of the measured DC levels, the second level 127 may be determined with respect to the first level 126. The second level 127 may be stored in a memory .

[0053] According to further implementations, the second level 127 may further depend on the temperature. Accordingly, the second level may additionally be determined in dependence from an operating temperature. For example, the memory 154 of the image sensor 20 (illustrated in Fig. 4) may store a look-up table storing the second level 127 or difference between the first level 126 and the second level 127 in dependence from an operating temperature .

[0054] Due to the feature that the capacitor voltage supply is configured to be operated at a first level and at a second level , it is possible to reduce the variation of the dark level of the pixel ( array) . As a result , there is no need to provide additional circuitry, e . g . analog CDS ("correlated double sampling" ) circuitry, to compensate large variations , resulting in power and area savings . Further, black sun protection failures may be reduced without the need of complex black sun protection circuitry . For example , the capacitor voltage supply VSSPC may comprise a voltage regulator, e . g . an LDO ( low- dropout regulator ) which may provide 2 supply voltages . According to further implementations , the capacitor voltage supply VSSPC may be generated by a VDAC (voltage digital analog converter ) which toggles from one analog voltage to another .

[0055] Fig . 3 shows an equivalent circuit diagram of a pixel circuit 100 according to further embodiments . The pixel circuit 100 may comprise similar or identical components as the pixel circuit 100 illustrated in Fig . 1A. Di f fering from embodiments illustrated in Fig . 1A, the first sampling transistor 122 is arranged between the node 118 and the further node that is connected to the first capacitor 121 . Moreover, the second sampling transistor 124 is arranged between the node that is connected to the first capacitor 121 and the second node 119 that is connected to the second capacitor 123 . The second capacitor 123 is operable to store charges representing the dark reference . The first capacitor 121 is operable to store charges representing the signal .

[0056] Fig . 4 shows a schematic diagram of an image sensor 20 . The image sensor 20 comprises an array of pixels 10 . To be more specific, each of the pixels 10 of the array of pixels comprises a photosensitive element (not shown in Fig. 4, illustrated in Figs. 1A and 3) and a pixel circuit 100 (not shown in Fig. 4, illustrated in Figs. 1A and 3) . Each of the pixel circuits 100 may be implemented in the manner as has been described above. The image sensor 20 may further comprise a row selection line drive 150 for selecting a line to be read out and a controller 151. The controller 151 may e.g. be configured to generate the signals illustrated in Fig. IB. The image sensor 20 may further comprise a column processing device 152 and a pixel data processing device 153.

[0057] Moreover, the image sensor 20 may comprise a memory 154 for storing the second values 127 or the differences between the second values 127 and the first values 126. In addition, the image sensor 20 may comprise a temperature sensor 155. For example, based on a temperature measured by the temperature sensor 154, the second values 127 or the differences between the second values 127 and the first values 126 may be assessed, e.g. using a look-up table stored in the memory 154.

[0058] As a result of the processing, image data 17 may be output.

[0059] While embodiments of the invention have been described above, it is obvious that further embodiments may be implemented. For example, further embodiments may comprise any subcombination of features recited in the claims or any subcombination of elements described in the examples given above. Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein . LIST OF REFERENCES pixel photosensitive element incident radiation column output image data image sensor pixel circuit floating di f fusion reset transistor trans fer transistor first transistor gate electrode second terminal of first transistor first terminal of first transistor precharge transistor first terminal of precharge transistor first node second node capacitor arrangement first capacitor first sampling transistor second capacitor second sampling transistor third transistor first level second level gate electrode second transistor first terminal selection transistor first terminal second terminal 150 row selection line driver

[0060] 151 controller

[0061] 152 column processing device

[0062] 153 pixel data processing device 154 memory

[0063] 155 temperature sensor

[0064] S 100 global operation

[0065] S200 local operation

Claims

CLAIMS1. A pixel circuit (100) comprising: a floating diffusion (102) configured to be connected to a photosensitive element (11) , the photosensitive element (11) being configured to generate charges in response to incident electromagnetic radiation (15) ; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) ; a terminal (112) of the first transistor (110) being connected to a first node (118) ; a capacitor arrangement (120) comprising a first capacitor (121) and a second capacitor (123) , a first terminal of the first capacitor (121) being configured to be connected to the first node (118) , a second terminal of the first capacitor (121) being connected to a capacitor voltage supply; a first terminal of the second capacitor (123) being configured to be connected to the first node (118) , a second terminal of the second capacitor (123) being connected to the capacitor voltage supply, wherein the capacitor voltage supply is configured to be operated at a first level (126) during a global operation (S100) and at a second level (127) different from the first level (126) during a local operation (S200) .

2. The pixel circuit (100) according to claim 1, wherein the capacitor voltage supply is configured to be operated at the second level (127) during a readout process.

3. The pixel circuit (100) according to claim 2, wherein the capacitor voltage supply is configured to be operated ex-clusively at the second level (127) during the readout process.

4. The pixel circuit (100) according to any of the preceding claims, wherein an output of the capacitor arrangement(120) is connected to a gate electrode (134) of a second transistor (135) , a first terminal (136) of the second transistor (135) being connectable to a column output (16) .

5. The pixel circuit (100) according to any of the preceding claims, wherein the first terminal of the first capacitor(121) is configured to be connected to the first node (118) via a first sampling transistor (122) and the first terminal of the second capacitor (123) is configured to be connected to a second node (119) via a second sampling transistor (124) , further comprising a third transistor (125) between the first node (118) and a node connected to the first sampling transistor (122) and to the second node (119) .

6. The pixel circuit (100) according to any of claims 1 to 4, further comprising a first sampling transistor (122) between the first node (118) and a node connected to the first terminal of the first capacitor (121) , and a second sampling transistor (124) between the node connected to the first terminal of the first capacitor (121) and a second node (119) connected to the first terminal of the second capacitor (123) .

7. The pixel circuit (100) according to any of the preceding claims, further comprising a precharge transistor (116) electrically connected to the first node (118) .

8. A method of manufacturing a pixel circuit (100) comprising :a floating diffusion (102) configured to be connected to a photosensitive element (11) , the photosensitive element (11) being configured to generate charges in response to incident electromagnetic radiation (15) ; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) ; a terminal (112) of the first transistor (110) being connected to a first node (118) ; a capacitor arrangement (120) comprising a first capacitor (121) and a second capacitor (123) , a first terminal of the first capacitor (121) being configured to be connected to the first node (118) , a second terminal of the first capacitor (121) being connected to a capacitor voltage supply; a first terminal of the second capacitor (123) being configured to be connected to the first node (118) , a second terminal of the second capacitor (123) being connected to the capacitor voltage supply, wherein the capacitor voltage supply is configured to be operated at a first level (126) during a global operation (S100) and at a second level (127) different from the first level (126) during a local operation (S200) , the method comprising measuring a DC dark level of a pixel (10) and determining the second level (127) based on the DC dark level and the first level (126) , wherein the DC dark level corresponds to a voltage signal when no electromagnetic radiation (15) is incident .

9. An image sensor (20) comprising: an array of pixels (10) , each of the pixels (10) comprising : a photosensitive element (11) , and a pixel circuit (100) ,at least one of the pixel circuits (100) comprising: a floating diffusion (1029 configured to be connected to the photosensitive element (11) , the photosensitive element being (11) configured to generate charges in response to incident electromagnetic radiation (15) ; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) ; a terminal (112) of the first transistor (110) being connected to a first node (118) ; a capacitor arrangement (120) comprising a first capacitor (121) and a second capacitor (123) , a first terminal of the first capacitor (121) being configured to be connected to the first node (118) , a second terminal of the first capacitor (121) being connected to a capacitor voltage supply; a first terminal of the second capacitor (123) being configured to be connected to the first node (118) , a second terminal of the second capacitor (123) being connected to the capacitor voltage supply, wherein the capacitor voltage supply is configured to be operated at a first level (126) during a global operation(S100) and at a second level (127) different from the first level (126) during a local operation (S200) .

10. The image sensor (20) according to claim 9, further comprising a memory (154) for storing the second level (127) .

11. The image sensor (20) according to claim 9 or 10, further comprising a temperature sensor (155) for measuring a temperature of the image sensor (20) , wherein the second level (127) is determined additionally based on the measured temperature .

12. A method of manufacturing an image sensor (20) comprising an array of pixels (10) , each of the pixels (10) comprising : a photosensitive element (11) , and a pixel circuit (100) , at least one of the pixel circuits (100) comprising: a floating diffusion (102) configured to be connected to the photosensitive element (11) , the photosensitive element (11) being configured to generate charges in response to incident electromagnetic radiation (15) ; a first transistor (110) , a gate electrode (111) of the first transistor (110) being electrically connected to the floating diffusion (102) ; a terminal (112) of the first transistor (110) being connected to a first node (118) ; a capacitor arrangement (120) comprising a first capacitor (121) and a second capacitor (123) , a first terminal of the first capacitor (121) being configured to be connected to the first node (118) , a second terminal of the first capacitor (121) being connected to a capacitor voltage supply; a first terminal of the second capacitor (123) being configured to be connected to the first node (118) , a second terminal of the second capacitor (123) being connected to the capacitor voltage supply, wherein the capacitor voltage supply is configured to be operated at a first level (126) during a global operation (S100) and at a second level (127) different from the first level (126) during a local operation (S200) , the method comprising measuring a DC dark level of the array of pixel circuits and determining the second level (127) based on the DC dark level and the first level (126) , wherein the DC dark level corresponds to a voltage signal when no electromagnetic radiation is incident.

13. The method according to claim 12, further comprising storing the second level (127) in a memory (154) .

14. The method according to claim 13, wherein the second level (127) is stored in dependence from an operating temperature .

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