Fan-out panel-level packaging with direct bonded copper

Abstract

A method of packaging semiconductor dies and semiconductor die packages formed via the same, the method comprising: providing a substrate comprising at least one insulating layer and at least one conductive layer; attaching a plurality of dies to the conductive layer of the substrate in a face up configuration; encapsulating the substrate and dies with a molding compound, wherein an electrical connection for the dies is at least partially exposed from the encapsulation layer; forming an electrical or thermal connection to the conductive layer, wherein the electrical or thermal layer is at least partially exposed from the encapsulation layer; forming at least one electrical interconnect connected to each of the one or more dies; and singulating the encapsulated substrate into a plurality of semiconductor die packages, each of the packages comprising one or more of the plurality of dies.

Description

[0001] Fan-out Panel-level Packaging with Direct Bonded Copper

[0002] Field of the Disclosure

[0003] The present disclosure relates to power semiconductor devices and packaging of power semiconductor devices. Particularly, but not exclusively, the disclosure relates to the packaging of hetero-structure AIGaN / GaN high electron mobility transistors.

[0004] Background of the Disclosure

[0005] Gallium Nitride (GaN) is a wide band gap material suitable for power and RF semiconductor devices. GaN technology allows the design of transistors with high electron mobility and a high saturation velocity, both of which are, generally, useful traits in the field of power and Radio-Frequency (RF) electronics. The use of GaN material has additional advantages in power devices. For example, the wide band gap of the material (Eg=3.39eV) results in high critical electric field (Ec=3.3MV / cm), which can allow the design of devices with a shorter drift region (and therefore a lower on-state resistance) compared to silicon-based devices with the same breakdown voltage.

[0006] The use of an Aluminium Gallium Nitride (AIGaN) / GaN heterostructure also allows the formation of a two-dimensional electron gas (2DEG) at the hetero-interface where carriers can reach very high carrier mobility values (e.g. p=2000cm2 / (Vs)). In addition, the piezopolarization charge present at the AIGaN / GaN heterostructure can result in a high electron density in the 2DEG layer (e.g. 1e13cm-2). These properties allow the development of High Electron Mobility Transistors (HEMTs) and Schottky barrier diodes with very competitive performance parameters.

[0007] With the increasing adoption of power devices in various applications, the demand of higher current carrying capability, reliability and thermal efficiency of the power devices has increased. This led to a boom in advanced packaging technologies.

[0008] Traditionally, packaging of GaN dies for RF applications is done either by using expensive ceramic housing with air cavities and metal flanges or by assembly in an overmolded lead frame package. Ceramic packages are used for higher power applications, whereas the less expensive plastic packages are found for lower power solutions, such as in Schwantuschke et al., “Fan-out Wafer Level Packaging of GaN Traveling Wafer Amplifier,” 2022 IEEE / MTT-S International Microwave Symposium - IMS 2022, Denver, CO, USA, 2022, pp. 579-582.

[0009] The Fan-out Wafer Level Packaging (FOWLP) technology is one of the latest trends in microelectronics packaging. In FOWLP, multiple die units are placed face down on a temporary tape carrier. The multiple die units and temporary tape carrier are overmolded with a molding compound using a compression molding process. After molding the tape carrier is removed, leaving the active surface of the multiple die units exposed in a structure commonly referred to as a reconstituted wafer. Subsequently, a wafer level chip scale package (WLCSP) build-up structure is formed on top of the reconstituted wafer. Ball grid array (BGA) balls are attached to the reconstituted wafer and then the reconstituted wafer is saw singulated to form individual packages.

[0010] US8922021 B2 illustrates another method of die up fully molded fan-out wafer level packaging. All these methods attach multiple dies on a tape carrier, typically using equipment such as a tape laminator. After a series of processing steps such as overmolding, the tape carrier is removed to expose the dies. This removal of the carrier is executed by a device such as a debonder.

[0011] In the printed circuit board industry, over the past decade direct bonded copper (DBG) substrates have become popular electronic circuit boards for multichip power semiconductor modules. They are replacing complicated assemblies based on leadframes and metallized organic substrates due to ease of assembly, low thermal resistance and the low coefficient of thermal expansion (GTE) of DBG which matches silicon inspite of thick copper metallization (see Schulz-Harde, “Advantages and new development of direct bonded copper substrates”, Microelectronics Reliability, Volume 43, Issue 3, 2003, Pages 359-365). Direct bonded copper (DBG) substrates consist of a ceramic isolator, AI2O3 (aluminium oxide) or AIN (aluminium nitride), onto which pure copper is bonded to one or both sides in a high temperature melting and diffusion process. The coefficient of thermal expansion (GTE) of AI2O3 (7.1 ppm / K) and AIN (4.7 ppm / K) is close to that of silicon (4 ppm / K). Therefore, DBG is a suitable substrate for robust packaging of bare dice since such assemblies are not likely to experience wear out due to GTE mismatch during the product operating life. Furthermore, the low thermal resistance of the DBG substrate provides a thermally conductive path for enhanced cooling of high power devices. The top copper layer can be patterned prior to bonding or chemically etched after bonding using printed circuit board (PCB) technology to form a pattern including die pads for wirebond packages, leads, and traces for an electrical circuit, while the bottom copper layer usually remains un-patterned, as generally discussed in US2023 / 0307314A1. However, DBC is not used for wafer-level or panellevel package developments.

[0012] The Applicant has therefore recognised a need for improved single or multi-die packages that are easy to manufacture, have better reliability and thermal efficiency while enhancing the package density and reducing unwanted resistance, capacitance and inductance parasitics from the package to enhance device performance.

[0013] Summary

[0014] It is an object of this invention to provide a power semiconductor device package or module and a method of packaging power devices using fan-out panel-level packaging methodology. A metal on insulator substrate panel, for example Direct Bonded Copper (DBC) substrate with copper on topside or both sides, is used as the base panel to directly attach multiple dies.

[0015] According to a first aspect of the present disclosure there is provided a method of packaging semiconductor dies, the method comprising: providing a substrate comprising at least one insulating layer and at least one conductive layer; attaching a plurality of dies to the conductive layer of the substrate in a face up configuration; encapsulating the substrate and the plurality of dies with a molding compound, wherein an electrical connection for the plurality of dies is at least partially exposed from the encapsulation layer; forming an electrical or thermal connection to the conductive layer, wherein the electrical or thermal layer is at least partially exposed from the encapsulation layer; forming at least one electrical interconnect connected to each of the one or more dies; and after encapsulating, singulating the substrate into a plurality of substrates, each of the plurality of substrates comprising one or more of the plurality of dies and forming a semiconductor die package.

[0016] The substrate may be a DBC, for example such that the insulating layer comprises a ceramic layer and / or the conductive layer comprises a copper layer. The dies may be attached to the substrate in a face up configuration, e.g. such that the electrical pads of the die face away from the substrate.

[0017] In one example, a die (e.g. GaN, SiC, IGBT, Si, IPD etc.) with conductive pillars, such as pre-plated copper pillars may be attached face up to a substrate panel through, for example, a silver sinter die attach process. In other implementations, the dies may be attached to the substrate with a mixture or combination of electrically conductive and electrically non conductive materials. The die may be a thin die. The DBG panel is then overmolded with an encapsulant, and the top surface is ground to expose the copper pillar tips and provide a coplanar surface for subsequent processing. The encapsulating mold compound in the field region may be etched to create vias, and the vias filled with metal to provide front to back electrical or thermal connectivity. This could also be achieved by attaching copper studs or plating copper pillars to the DBG prior to molding. As an optional step, a polyimide (PI) layer may be added with a following step to open vias in the PI, for enhanced connectivity. A redistribution layer (RDL) may be provided to provide interconnections between the dies and the package pinout or module SMT components. The RDL may be formed through a semi additive process of copper seeding, masking, copper plating, mask removal and seed etching. Further PI and RDL layers may be added as required.

[0018] The packages are then singulated, for example by mechanical saw or any other suitable method. The singulation of the packages may comprise cutting or otherwise separating the substrate into multiple sections, such that each package comprise a section of the substrate and one or more of the plurality of semiconductor dies.

[0019] Optionally, the packages can be probe tested prior to singulation. In implementations, a heat sink may be attached to the back-side of the substrate for improved thermal conductivity. Optional double sided metallisation of the substrate may provide a low thermal resistance contact between the heatsink and the substrate, to further enhance the cooling capacity of the package. Thus, methods according to the present disclosure may result in high thermal conductivity single or multi die package with electrical isolation between substrate / source and heatsink.

[0020] While other substrates may be used, a direct bonded copper (DBG) substrate with copper on ceramic provides both isolation and low capacitance. These factors are advantageous for e.g. half-bridge and multi-switch topologies, in which the substrates of different dies can be at very different potentials. For example, the capacitance between the substrate and the heat sink may be important when the high-side devices are switching from high-voltage to ground. The addition of an insulating layer in the substrate assists in creating this low capacitance to the heatsink, and thereby in maintaining different potential levels for the high-side and low-side devices. Implementations of the disclosure may therefore utilise a DBC substrate, optionally with the semiconductor dies arranged in a half-bridge or multi-switch topology.

[0021] Thus, in implementations the insulating layer comprises a ceramic layer. Additionally or alternatively, the conductive layer comprises a metal layer such as a copper layer.

[0022] In implementations, the substrate is a direct bonded copper (DBC) substrate.

[0023] The dies may be attached to the substrate via any suitable means. In implementations, at least some of the dies are attached to the substrate using a silver sinter process. In other implementations, at least some of the dies are attached to the substrate using a combination of electrically conductive and electrically non-conductive materials. It will be understood that the plurality of dies may be attached to the substrate via different means. For example, some of the plurality of dies may be attached to the substrate using a silver sinter process, while others of the plurality of dies may be attached to the substrate using a combination of electrically conductive and electrically non-conductive materials.

[0024] In implementations, the method comprises removing part of the encapsulation layer to at least partially expose the electrical connection for the dies. The electrical connections for the dies may be e.g. die pads, conductive (e.g. copper) pillars connected or attached to the dies, or any other suitable electrical connection point or means.

[0025] In implementations, forming the electrical or thermal connection to the conductive layer comprises: prior to encapsulating, attaching a conductive pillar or stud to the conductive layer; and encapsulating the substrate such that the conductive pillar or stud is at least partially exposed from the encapsulation layer. Optionally, the method may comprise removing part of the encapsulation layer to partially expose the conductive pillar or stud.

[0026] In other implementations, forming the electrical or thermal connection to the conductive layer comprises: etching the encapsulation layer to form one or more vias; and filling the one or more vias with an electrically conductive material. It will be understood that the method may comprise forming the electrical or thermal connection to the conductive layer via various means. For example, multiple such connections may be formed (e.g. one or more for each eventual singulated package), and some of the connections may be formed via conductive pillars or studs, while others of the connections may comprise (metal filled) vias in the encapsulation layer. In implementations, the conductive layer of the substrate may be patterned to enable selective connections to some conductive structures, and / or to isolate other conductive structures. For example, the conductive layer on the substrate may be patterned to provide electrical isolation between the die substrate and the front to back electrical or thermal connections or between adjacent die in a multi die configuration. This can allow the package to be designed with Copper pillars / studs that thermally connect the front and back sides while being at at a different voltage potential other than the substrate voltage (i.e. which may be at the Source potential). This can allow even lateral devices such as GaN packaged device to have a drain as a bottom side thermal pad, and enable full pin-to-pin compatibility with traditional vertical Si / SiC packages.

[0027] In implementations, one or more heatsinks may be attached to the substrate. For example, a separate heatsink may be attached to the substrate corresponding to each of the singulated packages. The heatsinks may be attached to the substrate via any suitable means, and may be attached before or after the singulation of the packages. Optionally, the substrate, may comprise a second conductive layer on an opposite side of the insulating layer to the first conductive layer, and wherein the one or more heatsinks are attached to the second conductive layer. For example, the substrate may be a double sided DBG substrate. This may facilitate the provision of a dual side cooled package, for example a dual side cooled GaN package which can be pin-to-pin footprint compatible with a standard vertical Si / SiC device package.

[0028] In implementations, the method comprises forming a polyimide (PI) layer above the encapsulation layer, wherein the PI layer comprises one or more openings corresponding to the electrical connection for the dies and / or to the electrical or thermal connection to the conductive layer.

[0029] In implementations, the method comprises forming a redistribution layer, the redistribution layer electrically connected to each of the electrical connections for the dies. In some examples the redistribution layer may be formed on or above the PI layer. Optionally, the method may comprise forming multiple polyimide and redistribution layers to provide a network of electrical connections between a plurality of dies or terminals. For example, the method may comprise forming alternating PI and redistribution layers.

[0030] In implementations, the method comprises attaching one or more of the semiconductor die packages to a printed circuit board (PCB).

[0031] Optionally, the method may comprise integrating one or more of the semiconductor die packages into semiconductor power module.

[0032] The proposed method of packaging semiconductor dies may be implemented with power devices such as GaN power devices. However, it will be understood that the disclosure is not restricted to use with power devices. The packaging method and resulting packages are applicable to any semiconductor devices, such as semiconductor power devices and / or any combination of semiconductor power devices and companion devices or memories, and may additionally or alternatively include passive devices such as Integrated Passive Devices (IPDs) or passive structures such as RDL defined coils and capacitors.

[0033] According to a second aspect of the disclosure, there is provided a semiconductor die package formed via any of the methods according to the first aspect.

[0034] Brief Description of the Drawings

[0035] The present disclosure will be understood more fully from the accompanying drawings, which however, should not be taken to limit the disclosure to the specific embodiments shown, but are for explanation and understanding only.

[0036] Figure 1 shows an example fan-out wafer level packaging process flow for face down dies with a heatsink.

[0037] Figure 2 shows an example fan-out wafer level packaging process flow for face up dies.

[0038] Figure 3 depicts an example structure of a direct bonded copper (DBG) substrate

[0039] Figure 4 shows an example method of fan-out panel level packaging according to the present disclosure. Figures 5a- 5f depict example packaging at various stages of an example method according to the present disclosure.

[0040] Figures 6a-6f depict example packaging at various stages of another example method according to the present disclosure.

[0041] Figure 7 shows another example method of fan-out panel level packaging according to the present disclosure.

[0042] Figures 8a-8g depict example packaging at various stages of another example method according to the present disclosure.

[0043] Figure 9 depicts an example package according to the present disclosure.

[0044] Detailed Description of the Preferred Embodiments

[0045] One method of semiconductor dies packaging is fan-out wafer level packaging. Generally speaking, in this process, multiple die units are placed on a temporary tape carrier, with gaps and / or isolation features between them. The multiple die units and temporary tape carrier are overmolded with a molding compound. After molding the tape carrier is removed, leaving the active surface of the multiple die units exposed. This structure may be referred to as a reconstituted wafer. Subsequently, conductive tracks are formed on top of the reconstituted wafer, along with conductive (e.g. solder) balls. The reconstituted wafer is divided or singulated to form individual packages.

[0046] Figure 1 depicts an example process 100 for a fan-out wafer level packaging process flow, for packaging of face-down dies. In step 101 , a thermal release tape is applied to a carrier. In step 102, semiconductor dies are assembled face-down on the carrier, and a heat sink is attached to the dies. In step 103, a wafer overmolding step is performed, e.g. with epoxy resin or other molding compound. In step 104, the carrier is released or debonded from the reconstituted wafer. In step 105, the heat sink is exposed via grinding of the molding compound. In step 106, a redistribution layer (RDL) structure and copper interconnects are applied to a top side of the packaging, for connection to and / or use as routing pads. Finally, in step 107, solder balls are attached to the RDL, and the dies are singulated. Figure 2 depicts an alternative example process 200 for a fan-out wafer level packaging process flow, for packaging of face-up dies. At step 201 , an RDL structure is applied to the native semiconductor device wafer. At step 203 where one or more conductive interconnects are added over the RDL structure or coupled directly to die bond pads of the semiconductor dies. In step 205, the native device wafer is thinned and diced. In step 207, the semiconductor die units are placed with the active side upward (i.e. with bond pads facing away from the carrier) on a carrier using an adhesive, such as a sacrificial double-sided mounting tape or an epoxy film.

[0047] In step 209 of packaging process 200, a molding process is performed to encapsulate the die units within an encapsulant. In step 211 , the molded wafer panel is removed from the carrier and in step 212 an encapsulant layer, such as an epoxy film, is added to the unencapsulated back side of the die units. In step 213 of Figure 2, material is removed from the active surface of the molded wafer to expose the conductive interconnects. In step 215, a fan-out RDL structure is constructed on the active surface of the molded wafer panel, and electrically connected to the conductive interconnects. In step 217 solder balls are applied to the fan-out RDL structure. Finally, in step 219, the molded wafer panel is singulated into individual device packages.

[0048] In both example processes, the dies must be attached (and later separated from) a carrier. This process complicates the manufacturing processes and increases waste, costs and production time. Additionally, traditional packaging processes can result in performance issues for devices packages at an edge of the wafer. As a result, traditional processes typical utilise circular wafers with dies positioned away from the wafer edge, to reduce these “edge effects”. However, the empty, unused edge region of the wafer further increases waste and reduces manufacturing efficiency.

[0049] Figure 3 depicts a conventional structure of a direct bonded copper (DBG) substrate 300. The substrate 300 comprises an insulating layer 301 such as a ceramic layer and copper layers 302a, b. It will be understood that a DBG board may be provided with only one of the top 302a and bottom 302b copper layers, or with both. In implementations of the disclosure, a printed circuit may be formed directly on the DBG substrate 300. It will be understood that a DBG substrate such as substrate 300 is one example of a substrate suitable for use with the packaging method according to the present disclosure. More generally, any substrate comprising an insulating layer and one or more conductive (e.g. metal) layers may be provided. While below descriptions may refer to a DBG substrate, it will be appreciated that these references are provided for illustrative purposes, and are not intended to be limiting in nature.

[0050] Methods according to the present disclosure provide a process for packaging power devices using fan-out panel-level packaging methodology on a substrate such as a DBC substrate.

[0051] Figure 4 depicts one example process or method 2000 according to the present disclosure. It will be understood that the process steps depicted in Figure 4 are examples only, and various steps may be changed or omitted. For example, some or all of the steps may be performed in a different order to that depicted in process 2000.

[0052] In step 2001 , a die is attached to the substrate. The substrate comprises an insulating layer and one or more conductive (e.g. metal) layers. For example, the substrate may be a DBC substrate such as substrate 300, with an insulating ceramic layer and one or more conductive copper layers. The substrate may comprise a metal layer on only one side (e.g. a top side) to which the die is attached, or on both the top and bottom side, as depicted on Figure 3.

[0053] The use of a direct bonded copper substrate with copper on ceramic provides good isolation and low capacitance, which is advantageous in half-bridge and multi-switch topologies. This is because the substrates of different dies in these topologies may be at very different potentials, and as the high-side devices switch from high-voltage to ground the capacitance from the substrate to the heatsink may become an important factor. The provision of an insulator in the substrate may further assist in maintaining different potential levels for substrates of high-side and low-side devices.

[0054] In implementations, multiple dies are attached to the substrate. One or more of the dies may comprise conductive pillars (e.g. pre-plated copper pillars), conductive (e.g. copper) studs or other conductive structures to provide more accessible electrical connection points. For example, the dies may comprise conductive pillars electrically connected to the various die terminals, to thereby provide an extended electrical connection point for the die. The multiple dies may be attached to the substrate in a single process step, e.g. such that the dies are attached to the substrate simultaneously or substantially simultaneously. The die or dies may be a thin semiconductor die. In examples, the die may be a GaN, SiC, IGBT or IPD die. The die may be attached to the substrate via any suitable means. For example, a silver sinter die attach process may be used to connect the dies face-up to the substrate, such that the electrical contact pads of the dies face away from the substrate. It will be understood that the method is applicable to any semiconductor power devices and any combination of semiconductor power devices and companion devices or memories (e.g. GaN, SiC, IGBT, Si) and / or passive devices such as Integrated Passive Devices (IPDs), or other passive structures such as RDL defined coils and capacitors.

[0055] Other components, such as pre-plated conductive (e.g. copper) pillars and / or studs may additionally be attached to the top metal layer of the substrate.

[0056] In some implementations, a printed circuit may be formed on the substrate, e.g. by using printed circuit board (PCB) technology to form a pattern comprising one or more of die pads for wirebond packages, leads, and traces for an electrical circuit. Where a bottom metal layer is provided, this may remain un-patterned. In this way, the semiconductor dies and / or other components may be provided with a circuit connections formed directly on the substrate.

[0057] In step 2002, the substrate is overmolded with an encapsulant to form an encapsulating layer. The encapsulant may be any suitable molding compound, such as epoxy resin. The top surface of the encapsulating layer may be removed to provide a coplanar surface for subsequent processing. Removing the top surface of the encapsulating layer may comprise e.g. grinding, polishing, etching, etc. Where conductive pillars or studs have been provided, the tips of the conductive pillars may be exposed from the molding compound. This may occur and during or as part of the removal process, or as a separate step that occurs before or after the removal of the top layer of the encapsulation. Similarly, the removal of the surface of the encapsulating layer may partially expose the electrical connections of the dies, and / or the electrical connections for the dies may be exposed in a separate step.

[0058] In step 2003, the encapsulating layer in the field region (e.g. between the semiconductor dies) may be etched to create one or more vias. The vias may be filled with a metal or other electrically and / or thermally conductive material, to provide front to back electrical and / or thermal connectivity. Additionally or alternatively, and prior to the overmolding step, conductive (e.g. copper) studs may be attached to the substrate, and / or the conductive pillars may be plated to the substrate, to thereby provide front to back electrical and / or thermal connectivity. The vias may provide electrical connections directly to the conductive layer of the substrate, or may otherwise connect to the conductive pillars / studs.

[0059] It will be understood that the vias may be etched at the same time as or before the encapsulant is removed in step 2002. For example, where etching is used to remove the surface of the etching layer, the vias may be etched during the same process step. Alternatively, the vias may be formed after step 2002.

[0060] In an optional step 2004, a polyimide (PI) layer may be added. One or more openings may be provided in the PI layer corresponding to the vias, conductive pillars / studs, and / or the electrical connection points of the dies. These openings in the PI layer may enhance the connectivity of the packages, and thereby further enhance the reliability of the front to back electrical and / or thermal connections.

[0061] In step 2005, one or more redistribution layers (RDL) structures are formed, to provide electrical interconnections from the die or dies to the package pinout or module surface mount technology (SMT) components. In one example, the RDL may be formed through a semi additive process of copper seeding, masking, copper plating, mask removal and seed etching. Steps 2004 and 2005 may be repeated, to add further PI layers and RDL layers as required. It will be understood that an RDL may electrically connect one part of the semiconductor package to another. For example, the RDL may comprise one or more copper metal interconnects.

[0062] In step 2006, the packages are singulated by mechanical saw or other suitable method. Singulating the packages may comprise sawing, cutting or otherwise separating the substrate into one or more sections, such that each package comprises one or more of the semiconductor devices. Optionally, the packages may be probe tested prior to singulation. It will be understood that each package may comprise a single die, or multiple dies. Additionally, different packages may comprise different numbers of dies. Before or after singulation, a heat sink may be attached to the back side of the substrate, for enhanced thermal conductivity. It will be understood that a substrate with double sided metalisation (i.e. with top and bottom metal layers) may advantageously provide a low thermal resistance contact between the heatsink and the substrate. Thus, the method 2000 may provide a high thermal conductivity single or multi die package with electrical isolation between substrate / source and heatsink. The singulated packages may be subsequently attached to a printed circuit board (PCB) to provide a power supply. Alternatively, the singulated packages may form part of a module, e.g. an intelligent power module, which may include surface mount components directly attached to the module or connectors for further integration.

[0063] Figures 5a-5f illustrate the process flow and package development according to the example method proposed in Figure 4.

[0064] In Figure 5a, one or more dies 5002 are attached to a substrate 5000. The substrate 5000 comprises an insulating layer 5001b and a conductive top metal layer 5001a. It will be understood that a second metal layer may also be provided on an opposite (bottom) side of the substrate 5000. The substrate 5000 may be a DBC substrate, comprising an insulating ceramic layer (5001b) and a conductive copper layer (5001a).

[0065] In Figure 5b, the substrate 5000 is overmolded with a molding compound, to form an encapsulant layer 5003. Part of the molding compound may be removed to partially expose a conductive connection point of the one or more dies, such as electrical pads 5002a.

[0066] In Figure 5c, the molding compound is etched to provide one or more vias 5004. The vias may be filled with a metal or other (thermally or electrically) conductive material. Alternatively, one or more conductive pillars may be attached to the conductive layer 5001a prior to forming the encapsulant layer 5003, and the encapsulant layer may be etched or partially removed to expose a tip of the conductive pillars.

[0067] Figure 5d depicts the package with an additional PI layer 5005. It will be understood that the PI layer is optional, and the method may instead proceed without the addition of this layer, e.g. by applying an RDL structure directly onto the molding compound 5003. Openings 5005a, b may be formed in the PI layer for the vias, conductive pillars and / or electrical pads of the dies respectively.

[0068] In Figure 5e, an RDL structure 5007 is formed, electrically connected to the vias and / or die pads. Conductive (e.g. copper) connections 5006 may be provided as part of the RDL structure, or otherwise to interconnect various sections of the RDL structure. It will be understood that multiple PI layers and RDL structures may be provided. Alternatively, the copper interconnects may connect directly to the electrical die connectors 5002a, without an intervening redistribution layer.

[0069] In Figure 5f, the packages are singulated, e.g. by mechanical saw or other suitable method, thereby separating 5008 the packages from one another. Before or after singulation, additional layers may be provided to assist in connecting the packages to external modules, such as electrically isolating layer 5009 and external connection point 5010.

[0070] Figures 6a-6f illustrate a process flow and package development according to another example based on the method proposed in Figure 4. Many steps of this example process correspond to steps shown in Figure 5a-5f, and like reference numerals are used.

[0071] In Figure 6a, one or more dies 5002 are attached to a substrate 5000. The substrate 5000 comprises an insulating layer 5001 b, a conductive first or top metal layer 5001a, and a conductive second or bottom metal layer 5001c. The first and second conductive metal layers are provided on opposite sides of the insulating layer 5001 b. The substrate 5000 may be a DBC substrate, comprising an insulating ceramic layer (5001 b) and two conductive copper layers (5001a, 5001c), and such that the insulating ceramic layer 5001b is sandwiched between the first and second copper layers 5001a and 5001c. It will be understood that references to positional terms such as “top” and “bottom” are not intended to be limiting in nature, and instead are used for clarity with reference to the orientation of the packages as depicted in the accompanying figures.

[0072] In Figure 6b, the substrate 5000 is overmolded with a molding compound, to form an encapsulant layer 5003. Part of the molding compound may be removed to partially expose a conductive connection point of the one or more dies, such as electrical pads 5002a.

[0073] In Figure 6c, the molding compound is etched to provide one or more vias 5004. The vias may be filled with a metal or other (thermally or electrically) conductive material. Alternatively, one or more conductive pillars may be attached to the conductive layer 5001a prior to forming the encapsulant layer 5003, and the encapsulant layer may be etched or partially removed to expose a tip of the conductive pillars.

[0074] Figure 6d depicts the package with an additional PI layer 5005. It will be understood that the PI layer is optional, and the method may instead proceed without the addition of this layer, e.g. by applying an RDL structure directly onto the molding compound 5003. Openings 5005a, b may be formed in the PI layer for the vias, conductive pillars and / or electrical pads of the dies respectively.

[0075] In Figure 6e, an RDL structure 5007 is formed, electrically connected to the vias and / or die pads. Conductive (e.g. copper) connections 5006 may be provided as part of the RDL structure, or otherwise to interconnect various sections of the RDL structure. It will be understood that multiple PI layers and RDL structures may be provided. Alternatively, the copper interconnects may connect directly to the electrical die connectors 5002a, without an intervening redistribution layer.

[0076] In Figure 6f, the packages are singulated, e.g. by mechanical saw or other suitable method, thereby separating 5008 the packages from one another. Before or after singulation, additional layers may be provided to assist in connecting the packages to external modules, such as electrically isolating layer 5009 and external connection point 5010.

[0077] Figure 7 depicts another example process or method 7000 according to the present disclosure. It will be understood that the process steps depicted in Figure 7 are examples only, and various steps may be changed or omitted. For example, some or all of the steps may be performed in a different order to that depicted in process 7000.

[0078] In step 7001 , a substrate is patterned. The substrate may comprise an insulating layer, a conductive first or top metal layer, and optionally a conductive second or bottom metal layer. Where two conductive layers are provided, the first and second conductive metal layers may be provided on opposite sides of the insulating layer. In an example, the substrate may be a DBG substrate, comprising an insulating ceramic layer and one or more conductive copper layers. For example, the insulating ceramic layer may be sandwiched between the first and second copper layers. It will be understood that references to positional terms such as “top” and “bottom” are not intended to be limiting in nature, and instead are used for clarity with reference to the orientation of the packages as depicted in the accompanying figures.

[0079] The die-side of the substrate (for example, the top metal layer or other metal layer to which the dies are to be subsequently attached) is patterned. The die-side conductive layer of the substrate is patterned to facilitate selective connections to some conductive structures and the isolation of other conductive structures. Patterning the substrate can provide electrical isolation between, for example, the die substrate and the front to back electrical connections, and / or between adjacent die in a multi die configuration. This isolation may be particularly advantageous in certain topologies, such as half-bridge topologies.

[0080] In another example, by patterning the substrate any Copper pillars / studs or other connections that thermally connect front and back side may be placed at a different voltage potential than the substrate voltage. This means that even lateral devices such as a GaN packaged device can provide a terminal that is (for example) drain connected to a bottom side thermal pad, and / or enable full pin-to-pin compatibility with a traditional vertical Si / SiC packages.

[0081] In step 7002, a die is attached to the substrate. This step corresponds to step 2001 of method 2000, and discussions above relating to step 2001 apply equally to step 7002.

[0082] As discussed above, the use of a direct bonded copper substrate with copper on ceramic may provide good isolation and low capacitance, which is particularly advantageous in some topologies such as half-bridge and multi-switch topologies. This is because the substrates of different dies in these topologies may be at very different potentials. As a result, when the high-side devices switch from high-voltage to ground, the capacitance from the substrate to the heatsink may become an important or relevant factor to the operations of the device. The provision of an insulator in the substrate may further assist in maintaining different potential levels for substrates of high-side and low-side devices.

[0083] In implementations, multiple dies are attached to the substrate. One or more of the dies may comprise conductive pillars (e.g. pre-plated copper pillars), conductive (e.g. copper) studs or other conductive structures to provide more accessible electrical connection points. For example, the dies may comprise conductive pillars electrically connected to the various die terminals, to thereby provide an extended electrical connection point for the die. The multiple dies may be attached to the substrate in a single process step, e.g. such that the dies are attached to the substrate simultaneously or substantially simultaneously.

[0084] The die or dies may be a thin semiconductor die. In examples, the die may be a GaN, SiC, IGBT or IPD die. The die may be attached to the substrate via any suitable means. For example, a silver sinter die attach process may be used to connect the dies face-up to the substrate, such that the electrical contact pads of the dies face away from the substrate. It will be understood that the method is applicable to any semiconductor power devices and any combination of semiconductor power devices and companion devices or memories (e.g. GaN, SiC, IGBT, Si) and / or passive devices such as Integrated Passive Devices (IPDs), or other passive structures such as RDL defined coils and capacitors.

[0085] Other components, such as pre-plated conductive (e.g. copper) pillars and / or studs may additionally be attached to the top metal layer of the substrate.

[0086] In some implementations, a printed circuit may be formed on the substrate, e.g. by using printed circuit board (PCB) technology to form a pattern comprising one or more of die pads for wirebond packages, leads, and traces for an electrical circuit. Where a bottom metal layer is provided, this may remain un-patterned. In this way, the semiconductor dies and / or other components may be provided with a circuit connections formed directly on the substrate.

[0087] In step 7003, the substrate is overmolded with an encapsulant to form an encapsulating layer. This step corresponds to step 2002 of method 2000, and discussions above relating to step 2002 apply equally to step 7003.

[0088] The encapsulating layer in the field region (e.g. between the semiconductor dies) may be etched to create one or more vias. This etching process corresponds to step 2003 of method 2000, and discussions above relating to step 2003 apply equally to step 7004.

[0089] In an optional step 7005, a polyimide (PI) layer may be added. This step corresponds to step 2004 of method 2000, and discussions above relating to step 2004 apply equally to step 7005.

[0090] In step 7006, one or more redistribution layers (RDL) structures are formed, to provide electrical interconnections from the die or dies to the package pinout or module surface mount technology (SMT) components. This step corresponds to step 2005 of method 2000, and discussions above relating to step 2005 apply equally to step 7006.

[0091] In step 7007, the packages are singulated by mechanical saw or other suitable method. Singulating the packages may comprise sawing, cutting or otherwise separating the substrate into one or more sections, such that each package comprises one or more of the semiconductor devices. This step corresponds to step 2006 of method 2000, and discussions above relating to step 2006 apply equally to step 7007.

[0092] Figures 8a-8f illustrate the process flow and an example package development according to the example method depicted in Figure 7.

[0093] In Figure 8a, a substrate 8000 is patterned. The substrate 8000 comprises an insulating layer 8001 b, a conductive first or top metal layer 8001a, and a conductive second or bottom metal layer 8001c. The first and second conductive metal layers are provided on opposite sides of the insulating layer 8001 b. The substrate 8000 may be a DBC substrate, comprising an insulating ceramic layer (8001b) and two conductive copper layers (8001a, 8001c), and such that the insulating ceramic layer 8001b is sandwiched between the first and second copper layers 8001a and 8001c. It will be understood that references to positional terms such as “top” and “bottom” are not intended to be limiting in nature, and instead are used for clarity with reference to the orientation of the packages as depicted in the accompanying figures.

[0094] The conductive layer may be patterned (e.g. according to the process step 7001), wherein the patterned structures 8011 are formed in the die-side conductive layer of the substrate panel. These patterns may isolate the die terminals, as can be seen in the final package formed in e.g. Figure 8f in which terminals 8012 and 8013 are electrically isolated from each other through the patterned structures 8011.

[0095] In Figure 8b, one or more dies 8002 are attached to the substrate 8000. Where multiple dies are provided, they may be attached to the substrate in a single process step, e.g. such that the dies are attached to the substrate simultaneously or substantially simultaneously.

[0096] In Figure 8c, the substrate 8000 is overmolded with a molding compound, to form an encapsulant layer 8003. Part of the molding compound may be removed to partially expose a conductive connection point of the one or more dies, such as electrical pads 8002a.

[0097] In Figure 8d the molding compound is etched to provide one or more vias 8004. The vias may be filled with a metal or other (thermally or electrically) conductive material. Alternatively, one or more conductive pillars may be attached to the conductive layer 8001a prior to forming the encapsulant layer 8003, and the encapsulant layer may be etched or partially removed to expose a tip of the conductive pillars.

[0098] Figure 8e depicts the package with an additional PI layer 8005. It will be understood that the PI layer is optional, and the method may instead proceed without the addition of this layer, e.g. by applying an RDL structure directly onto the molding compound 8003. Openings 8005a, b may be formed in the PI layer for the vias, conductive pillars and / or electrical pads of the dies respectively.

[0099] In Figure 8f, an RDL structure 8007 is formed, electrically connected to the vias and / or die pads. Conductive (e.g. copper) connections 8006 may be provided as part of the RDL structure, or otherwise to interconnect various sections of the RDL structure. It will be understood that multiple PI layers and RDL structures may be provided. Alternatively, the copper interconnects may connect directly to the electrical die connectors 8002a, without an intervening redistribution layer.

[0100] In Figure 8g, the packages are singulated, e.g. by mechanical saw or other suitable method, thereby separating 8008 the packages from one another. Before or after singulation, additional layers may be provided to assist in connecting the packages to external modules, such as electrically isolating layer 8009 and external connection point 8010.

[0101] Figure 9 illustrates another example package according to the present disclosure. The die in this package may be, for example, a GaN-on-Si power HEMT device, while the substrate may be a DBG substrate, e.g. comprising an Si layer and one or more conductive copper layers. Terminals 9002 and 9003 may form the drain and source pads of the packaged device, respectively. Due to the design of the package, the optimal thermal path for GaN-on-Si Power HEMT is through the Si substrate. Conventionally, an Si substrate must be connected to source voltage potential for optimum performance of GaN HEMTs. The arrows 9004 illustrate example heat dissipation paths through the package. Because of the presence of the conductive metal (e.g. copper) layer 9001 at the bottom of the substrate, the bottom conductive layer acts as an isolated thermal pad resulting in a larger thermal pad for improved thermal performance.

[0102] The top pad terminals 9002, 9003 can be connected to the drain and / or source, facilitating a full pin match with standard Si / SiC MOSFET package with a drain tab. This package may therefore be footprint compatible with a Standard Si / SiC MOSFET power package. Further, the drain pad can be extended in size to provide a greater surface area for heat dissipation, due to the drain pad acting as the top thermal pad. The patterning of the top conductive layer of the DBC may facilitate the provision of copper pillars at different voltage potentials. Therefore, the Cu pillars can be electrically connected to the drain, and still offer good thermal coupling from the top to the bottom of the package.

[0103] Advantageously, the proposed methods may utilise rectangular substrate panels, providing an increased yield over traditional packaging panels that typically utilise circular wafers. This is due to the more reliable performance provided by edge devices and higher packing density on a rectangular panel. Additionally, the proposed methods simplify existing packaging processes, for example by removing the need to attach dies on (and subsequently separate them from) a carrier layer.

[0104] The skilled person will understand that in the preceding description and appended claims, positional terms such as ‘top’ and ‘bottom’ are made with reference to conceptual illustrations such as those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to the positioning of the components as shown in the accompanying schematic drawings.

[0105] Although the disclosure has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the disclosure, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

[0106] Many other effective alternatives will occur to the person skilled in the art. It will be understood that the disclosure is not limited to the described embodiments, but encompasses all the modifications which fall within the spirit and scope of the disclosure.

Claims

CLAIMS:

1. A method of packaging semiconductor dies, the method comprising: providing a substrate comprising at least one insulating layer and at least one conductive layer; attaching a plurality of dies to the conductive layer of the substrate in a face up configuration; encapsulating the substrate and the plurality of dies with a molding compound, wherein an electrical connection for the plurality of dies is at least partially exposed from the encapsulation layer; forming an electrical or thermal connection to the conductive layer, wherein the electrical or thermal layer is at least partially exposed from the encapsulation layer; forming at least one electrical interconnect connected to each of the one or more dies; and after encapsulating the substrate, singulating the substrate into a plurality of substrates, each of the plurality of substrates forming a semiconductor die package comprising one or more of the plurality of dies.

2. The method of claim 1 , wherein the insulating layer comprises a ceramic layer.

3. The method of claim 1 or 2, wherein the conductive layer comprises a copper layer.

4. The method of claim 3, wherein the conductive layer comprises two conductive layers positioned on opposite sides of the at least one insulating layer.

5. The method of any preceding claim, wherein the substrate is a direct bonded copper substrate.

6. The method of any preceding claim, wherein the dies are attached to the substrate using a silver sinter process.

7. The method of any preceding claim, wherein the dies are attached to the substrate using a combination of electrically conductive and electrically non-conductive materials.

8. The method of any preceding claim, the method comprising removing part of the encapsulation layer to at least partially expose the electrical connection for the dies.

9. The method of any preceding claim, wherein forming the electrical or thermal connection to the conductive layer comprises: prior to encapsulating, attaching a conductive pillar or stud to the conductive layer; and encapsulating the substrate such that the conductive pillar or stud is at least partially exposed from the encapsulation layer.

10. The method of claim 9, the method comprising removing part of the encapsulation layer to partially expose the conductive pillar or stud.

11. The method of claim 9 or 10, comprising, prior to attaching the conductive pillar or stud, patterning the conductive layer of the substrate to thereby electrically isolate the conductive pillar or stud from a remaining part of the substrate.

12. The method of any one of claims 9 to 11 , wherein the conductive pillar or stud forms a heat dissipation path to the at least one conductive layer, such that the at least one conductive layer is configured to act as a thermal pad.

13. The method of any preceding claim, wherein at least part of the electrical or thermal connection to the conductive layer that is exposed from the encapsulation layer is configured to act as a thermal pad.

14. The method of claim 13 when dependent upon claim 12, wherein the at least one conductive layer and the at least part of the electrical or thermal connection are configured to act respectively as first and second thermal pads on opposite sides of the semiconductor die package, such that the semiconductor package is a dual-side cooled semiconductor die package.

15. The method of any preceding claim, comprising, prior to attaching the plurality of dies, patterning the conductive layer of the substrate to thereby electrically isolate the plurality of dies from a remaining part of the substrate.

16. The method of any preceding claim, wherein forming the electrical or thermal connection to the conductive layer comprises:etching the encapsulation layer to form one or more vias; and filling the one or more vias with an electrically conductive material.

17. The method of any preceding claim, comprising attaching one or more heatsinks to the substrate.

18. The method of claim 17, wherein the substrate comprises a second conductive layer on an opposite side of the insulating layer to the first conductive layer, and wherein the one or more heatsinks are attached to the second conductive layer.

19. The method of any preceding claim, comprising forming a polyimide (PI) layer above the encapsulation layer, wherein the PI layer comprises one or more openings corresponding to the electrical connection for the dies and / or to the electrical or thermal connection to the conductive layer.

20. The method of any preceding claim comprising forming a redistribution layer, the redistribution layer electrically connected to each of the electrical connections for the dies.

21. The method of any preceding claim, comprising forming multiple polyimide and redistribution layers to provide a network of electrical connections between a plurality of dies or terminals.

22. The method of claim 20 when dependent upon claim 19, comprising forming the redistribution layer on the PI layer.

23. The method of any preceding claim, comprising attaching one or more of the semiconductor die packages to a printed circuit board (PCB).

24. The method of any preceding claim, comprising integrating one or more of the semiconductor die packages into semiconductor power module.

25. The method of any preceding claim, comprising simultaneously attaching the plurality of dies to the conductive layer of the substrate in a single process step.

26. A semiconductor die package formed via any of the methods of claims 1 to 25.

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