Storage device, electronic equipment, and method for controlling storage device

Abstract

A storage device capable of further improving operational reliability is provided. The present invention provides a storage device comprising: a memory cell array unit that comprises a plurality of memory cells, each including a magnetoresistive element having a resistance value that is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array unit that has a similar configuration to the memory cell array unit and comprises a plurality of reference cells; a sense amplifier that is connected to the plurality of memory cells and detects the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells on the basis of a reference resistance value; and a control unit that is capable of selecting, from the plurality of reference cells, a reference cell which is referenced in order to read the reference resistance value, and changing the value of the reference resistance value within a predetermined range. An upper limit of the predetermined range is larger than the high resistance value, and a lower limit of the predetermined range is smaller than the low resistance value.

Description

Storage device, electronic device, and storage device control method

[0001] The present disclosure relates to a storage device, an electronic device, and a method for controlling a storage device.

[0002] Magnetoresistive random access memories (MRAMs) that use magnetoresistive elements retain the magnetization state of the ferromagnetic material inside the magnetoresistive elements, and are therefore nonvolatile, meaning that recorded data is retained even when the power is turned off. Examples of MRAMs include STT-MRAMs that use spin transfer torque (STT) and VC-MRAMs that use voltage-controlled magnetic anisotropy (VCMA).

[0003] In such an MRAM, the resistance state of the magnetoresistive element of the memory cell is read as memory cell data by a sense amplifier based on a reference voltage generated by a reference resistor, for example, the resistance of the magnetoresistive element in the reference cell.

[0004] Japanese Patent Application Laid-Open No. 2021-96887

[0005] In the prior art, the resistance range of the magnetoresistive element of the reference cell is limited to a range from a low resistance value to a high resistance value, which corresponds to the two resistance states of the magnetoresistive element. Therefore, in the prior art, the sense amplifier cannot detect defective memory cells having resistance values ​​lower than the low resistance value or higher than the high resistance value. Furthermore, since the defective memory cells cannot be detected, the sense amplifier cannot operate while excluding the defective memory cells, which limits the improvement of the reliability of the memory device.

[0006] Furthermore, in the prior art, if the value of the reference resistor deviates significantly from the target value due to the manufacturing process or the like, the sense amplifier may not be able to correctly read data from the memory cell, which has limited the ability to further improve the reliability of the memory device's operation.

[0007] Therefore, the present disclosure proposes a storage device, an electronic device, and a control method for a storage device that can further improve the reliability of operation.

[0008] According to the present disclosure, there is provided a memory device comprising: a memory cell array section consisting of a plurality of memory cells, each of which includes a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section that selects, from the plurality of reference cells, the reference cell that is referenced to read the reference resistance value, and can change the value of the reference resistance value within a predetermined range, wherein the upper limit of the predetermined range is greater than the high resistance value and the lower limit of the predetermined range is less than the low resistance value.

[0009] Furthermore, according to the present disclosure, there is provided an electronic device comprising: a memory device for storing data, the memory device having a memory cell array section consisting of a plurality of memory cells, each of which includes a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section that selects the reference cell from the plurality of reference cells to be referenced to read the reference resistance value, and changes the value of the reference resistance value within a predetermined range, wherein the upper limit of the predetermined range is greater than the high resistance value and the lower limit of the predetermined range is less than the low resistance value.

[0010] Furthermore, according to the present disclosure, there is provided a control method for a memory device comprising: a memory cell array section consisting of a plurality of memory cells, each of which includes a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control unit that selects a reference cell from the plurality of reference cells to be referenced to read the reference resistance value, and changes the value of the reference resistance value within a predetermined range, wherein the control unit changes the value of the reference resistance value within the predetermined range, and the upper limit of the predetermined range is greater than the high resistance value and the lower limit of the predetermined range is less than the low resistance value.

[0011] 1 is a diagram illustrating a configuration example of a memory device 10 according to an embodiment of the present disclosure; FIG. 2 is a diagram illustrating a configuration example of a memory cell 202 according to an embodiment of the present disclosure; FIG. 3 is an explanatory diagram for explaining the background of an embodiment of the present disclosure; FIG. 4 is a schematic configuration diagram of a memory device 10 (common reference system) according to a comparative example; FIG. 5 is a circuit diagram of a reference cell array unit 100a (1SL1BL type) of a memory device 10 (common reference system) according to a comparative example; FIG. 6 is a circuit diagram (column number change pattern) of a reference cell array 100 unit (1SL1BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during low resistance expansion; FIG. 7 is a circuit diagram (column number change pattern) (part 1) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during low resistance expansion. FIG. 2 is a circuit diagram (column number change pattern) (part 2) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during low resistance expansion. FIG. 3 is a circuit diagram (word line number change pattern) of a reference cell array 100 portion (1SL1BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during low resistance expansion. FIG. 4 is a circuit diagram (word line number change pattern) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during low resistance expansion. FIG. 5 is a circuit diagram (column number change pattern) of a reference cell array 100 portion (1SL1BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. FIG. 6 is a circuit diagram (column number change pattern) (part 1) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. 1 is a circuit diagram (column number change pattern) (part 2) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. FIG. 2 is a circuit diagram (adjacent SL / BL connection pattern) of a reference cell array 100 portion (1SL1BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion.FIG. 1 is a circuit diagram (adjacent SL / BL connection pattern) (part 1) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. FIG. 2 is a circuit diagram (adjacent SL / BL connection pattern) (part 2) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. FIG. 3 is a circuit diagram (adjacent SL / BL connection pattern) (part 3) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (common reference system) according to a first embodiment of the present disclosure during high resistance expansion. FIG. 4 is a circuit diagram of a reference cell array unit 100a of a memory device 10 (individual reference system) according to a comparative example. FIG. 5 is a circuit diagram (series number change pattern) of a reference cell array 100 portion (1SL1BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during low resistance expansion. FIG. 10 is a circuit diagram (series number change pattern) (part 1) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during low resistance expansion. FIG. 11 is a circuit diagram (series number change pattern) (part 2) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during low resistance expansion. FIG. 12 is a circuit diagram (parallel number change pattern) of a reference cell array 100 unit (1SL1BL type / 1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during low resistance expansion. FIG. 13 is a circuit diagram (parallel number change pattern) of a reference cell array 100 unit (1SL1BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during high resistance expansion. FIG. 10 is a circuit diagram (parallel number change pattern) (part 1) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during high resistance expansion; FIG. 11 is a circuit diagram (parallel number change pattern) (part 2) of a reference cell array 100 portion (1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during high resistance expansion; and FIG. 12 is a circuit diagram (series number change pattern) of a reference cell array 100 portion (1SL1BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during high resistance expansion.FIG. 1 is a circuit diagram (series number change pattern) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (individual reference system) according to a second embodiment of the present disclosure during high resistance expansion. FIG. 2 is a circuit diagram (part 1) of a reference cell array 100 unit (1SL1BL type) of a memory device 10 (common reference system) according to a third embodiment of the present disclosure. FIG. 3 is a circuit diagram (part 1) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (common reference system) according to a third embodiment of the present disclosure. FIG. 4 is a circuit diagram (part 1) of a reference cell array 100 unit (1SL1BL type / 1SL2BL type) of a memory device 10 (individual reference system) according to a third embodiment of the present disclosure. FIG. 5 is a circuit diagram (part 2) of a reference cell array 100 unit (1SL1BL type) of a memory device 10 (common reference system) according to a third embodiment of the present disclosure. FIG. 10 is a circuit diagram (part 2) of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (common reference system) according to a third embodiment of the present disclosure. FIG. 11 is a circuit diagram (part 2) of a reference cell array 100 unit (1SL1BL type / 1SL2BL type) of a memory device 10 (individual reference system) according to a third embodiment of the present disclosure. FIG. 12 is a circuit diagram of a reference cell array 100 unit (1SL1BL type) of a memory device 10 (common reference system) according to a fourth embodiment of the present disclosure. FIG. 13 is a circuit diagram of a reference cell array 100 unit (1SL2BL type) of a memory device 10 (common reference system) according to a fourth embodiment of the present disclosure. FIG. 14 is a circuit diagram of a reference cell array 100 unit (1SL1BL type / 1SL2BL type) of a memory device 10 (individual reference system) according to a fourth embodiment of the present disclosure. FIG. 15 is a circuit diagram showing a configuration example of a memory device 10 according to a fifth embodiment of the present disclosure. FIG. 16 is a diagram showing a configuration example of a cell to be destroyed 103 according to a fifth embodiment of the present disclosure. FIG. 10 is a diagram showing an example configuration of a to-be-destroyed cell 103 according to a fifth embodiment of the present disclosure. FIG. 11 is a diagram showing an example configuration of a to-be-destroyed cell 103 according to a fifth embodiment of the present disclosure. FIG. 12 is a circuit diagram showing another example configuration of a storage device 10 according to a fifth embodiment of the present disclosure. FIG. 13 is a circuit diagram showing another example configuration of a storage device 10 according to a sixth embodiment of the present disclosure. FIG. 14 is a circuit diagram showing another example configuration of a storage device 10 according to a sixth embodiment of the present disclosure. FIG. 15 is a diagram showing an example of processing of a storage device 10 according to the sixth embodiment of the present disclosure.28A is a diagram showing an example of processing of a storage device 10 according to a sixth embodiment of the present disclosure. FIG. 28B is a circuit diagram showing an example configuration of a storage device 10 according to a seventh embodiment of the present disclosure. FIG. 28C is a diagram showing an overview of a system in which a storage device 10 according to an embodiment of the present disclosure is installed. FIG. 28D is a diagram showing an example operation of the system of FIG. 28A. FIG. 28E is a diagram showing a result when the value of a reference resistor is changed in a storage device 10 of an individual reference system. FIG. 28F is a diagram showing an example of a schematic configuration of an imaging device 400.

[0012] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and redundant description will be omitted. Furthermore, in this specification and the drawings, multiple components having substantially the same or similar functional configurations may be distinguished by adding different letters after the same reference numeral. However, when there is no particular need to distinguish between multiple components having substantially the same or similar functional configurations, only the same reference numerals will be used.

[0013] In the following description of circuits (electrical connections), unless otherwise specified, "electrically connected" or "connection" means connecting multiple elements so that electricity (signals) is conducted between them. In addition, "electrically connected" or "connection" in the following description includes not only cases where multiple elements are directly and electrically connected, but also cases where elements are indirectly and electrically connected via other elements.

[0014] The description will be given in the following order: 1. Storage device configuration example 2. Background 3. First embodiment 3.1 Comparative example 3.2 Example 4. Second embodiment 4.1 Comparative example 4.2 Example 5. Third embodiment 6. Fourth embodiment 7. Fifth embodiment 8. Sixth embodiment 9. Seventh embodiment 10. Eighth embodiment 11. Summary 12. Application example 13. Supplementary information

[0015] <<1. Configuration Example of Storage Device>> A configuration example of a storage device 10 according to an embodiment of the present disclosure will be described with reference to Fig. 1A. Fig. 1A is a diagram showing a configuration example of a storage device 10 according to an embodiment of the present disclosure.

[0016] As shown in FIG. 1A , the memory device 10 according to this embodiment is an example of a memory device that stores data based on the magnetization direction of a magnetic material, and includes a memory cell array unit 200. The memory cell array unit 200 includes a plurality of memory cells 202 arranged two-dimensionally. These memory cells 202 are connected to bit lines BL, source lines SL, and word lines WL, respectively. For example, the plurality of word lines WL extend along the horizontal direction (row direction) in FIG. 1A , and the plurality of bit lines BL and the plurality of source lines SL extend along the vertical direction (column direction) in FIG. 1A . These bit lines BL, source lines SL, and word lines WL each function as control lines.

[0017] As will be described later, each memory cell 202 has a magnetoresistive element 11 and a selection element 12. As the magnetoresistive element 11, for example, a magnetoresistive element such as an MTJ (Magnetic Tunnel Junction) can be used. The selection element 12 is connected to one end of the magnetoresistive element 11 and controls the application of voltage, current, etc. to the magnetoresistive element 11. As this selection element 12, for example, various types of transistors can be used.

[0018] In addition to the memory cell array section 200, the memory device 10 has an I / O 21, a control circuit (control section) 22, an address decoder 26, multiple bit line control circuits 27A, 27B, multiple source line control circuits 28A, 28B, a word line address decoder 29, multiple word line control circuits 30A, 30B, a sense amplifier circuit 31, and a reference cell array section 100.

[0019] Here, the memory cell array section 200 and the reference cell array section 100 are arranged so as to sandwich the sense amplifier circuit 31 etc. Corresponding to the memory cell array section 200 and the reference cell array section 100, there are provided respective bit line control circuits 27A, 27B, respective source line control circuits 28A, 28B, and respective word line control circuits 30A, 30B.

[0020] The I / O 21 enables the transfer of commands related to reading and writing data, addresses of memory cells 202 to be accessed, data, etc. between an external circuit of the memory device 10 (e.g., a Central Processing Unit (CPU)) and the control circuit 22 of the memory device 10.

[0021] In response to commands, the control circuit 22 controls writing and reading of data to and from the memory cells 202. Furthermore, in the embodiment of the present disclosure, the control circuit 22 controls the reference cell array unit 100 to obtain reference resistances having various values ​​used to read the memory cells 202. In particular, the control circuit 22 can select a reference cell 102 to be referenced to read the reference resistance value from among the multiple reference cells 102 in the reference cell array unit 100, and change the value of the reference resistance value within a predetermined range.

[0022] The address decoder 26 obtains addresses of the bit lines BL, source lines SL, etc. corresponding to the addresses received by the I / O 21. The address decoder 26 has a column switch selection circuit 32. The column switch selection circuit 32 controls the bit line control circuits 27A and 27B and the source line control circuits 28A and 28B.

[0023] Each bit line control circuit 27A, 27B is connected to a corresponding bit line BL. These bit line control circuits 27A, 27B select and control the bit line BL corresponding to the address of the address decoder 26.

[0024] Each of the source line control circuits 28A and 28B is connected to a corresponding one of the source lines SL. Each of the source line control circuits 28A and 28B selects and controls a source line SL corresponding to an address of the address decoder 26.

[0025] The word line address decoder 29 obtains the address of the word line WL corresponding to the address received at the I / O 21 described above.

[0026] Each of the word line control circuits 30A and 30B is connected to a corresponding word line WL, and each of the word line control circuits 30A and 30B selects and controls a word line WL corresponding to an address of the word line address decoder 29.

[0027] The sense amplifier circuit 31 is connected to the source line SL via the source line control circuits 28 A and 28 B. The sense amplifier circuit 31 detects data read from the memory cell 202 , specifically, the resistance value of the magnetoresistive element 11 .

[0028] Specifically, the sense amplifier circuit 31 has a plurality of sense amplifiers (SA) 300 (not shown). Each sense amplifier 300 may be, for example, a variety of sense amplifiers that use a reference voltage (reference current). Furthermore, a sense amplifier 300 is provided for each predetermined number of columns of memory cells 202.

[0029] When reading data from each memory cell 202, the sense amplifier 300 detects the resistance state (e.g., low resistance state or high resistance state) of the memory cell 202 based on a reference resistance value, which is the combined resistance value of each reference cell 102 in the reference cell array unit 100 (described later). For example, the sense amplifier 300 refers to a reference voltage (reference current) based on the reference resistance value, compares the reference voltage with the voltage of the memory cell 202, and reads the resistance state of the memory cell 202 based on the comparison result. The sense amplifier 300 outputs data (e.g., 0 or 1) corresponding to the read resistance state, i.e., a read voltage corresponding to the read data.

[0030] The reference cell array section 100, like the memory cell array section 200, includes a plurality of reference cells 102 arranged two-dimensionally. These reference cells 102 are connected to bit lines BL, source lines SL, and word lines WL, respectively. For example, the plurality of word lines WL extend in the horizontal direction (row direction) in FIG. 1A, and the plurality of bit lines BL and the plurality of source lines SL extend in the vertical direction (column direction) in FIG. 1A. These bit lines BL, source lines SL, and word lines WL each function as control lines.

[0031] Like the memory cells 202, each reference cell 102 has a magnetoresistive element 11 and a selection element 12. The magnetoresistive element 11 may be, for example, a magnetoresistive element such as an MTJ. The selection element 12 is connected to one end of the magnetoresistive element 11 and controls the application of voltage, current, etc. to the magnetoresistive element 11. The selection element 12 may be, for example, any of various transistors.

[0032] The reference cell array unit 100 can change the reference resistance value, which is the combined resistance value of the individual resistance values ​​of the reference cells 102, by adjusting the combination of the multiple reference cells 102 (the connection pattern of the reference cells 102) and the individual resistance values ​​of the reference cells 102. The reference resistance value is a resistance value that the sense amplifier 300 refers to when detecting the resistance value of the magnetoresistive element 11 from the memory cell 202.

[0033] Next, a configuration example of the memory cell 202 according to an embodiment of the present disclosure will be described with reference to Fig. 1B. Fig. 1B is a diagram showing a configuration example of the memory cell 202 according to an embodiment of the present disclosure.

[0034] 1B, the memory cell 202 includes a magnetoresistive element 11 and a selection element 12. The magnetoresistive element 11 and the selection element 12 are connected in series between a bit line BL and a source line SL.

[0035] The magnetoresistive element 11 has, for example, a sandwich structure in which a non-magnetic thin insulating film is sandwiched between two magnetic layers (a fixed layer and a recording layer) made of magnetic thin films. This structure is called a magnetic tunnel junction (MTJ). Because the insulating thin film is very thin, about a few nanometers thick, a tunnel current flows when a voltage is applied to both ends of the element. The magnitude of this tunnel current is characterized by its dependence on the relative angle of the magnetization of the two magnetic layers. This is called the tunnel magnetoresistance (TMR) effect.

[0036] In MRAM, the magnetization of one of the two magnetic layers (the fixed layer) is fixed, and the magnetization direction of the other magnetic layer (the recording layer) is controlled. For example, methods for controlling the direction of magnetization include a method using spin transfer torque (STT), which directly passes a current through the MTJ, and a method using voltage controlled magnetic anisotropy (VCMA). In addition, in MRAM, the TMR effect is used to read the state of the internal magnetic material. Examples of MRAM include STT-MRAM, which uses spin transfer torque, and VC-MRAM, which uses magnetic anisotropy control.

[0037] By switching the resistance state (resistance value) of such a magnetoresistive element 11 between a low resistance state (low resistance value) and a high resistance state (high resistance value), data (e.g., 0 or 1) is written to the memory cell 202. In the low resistance state, the magnetizations of the fixed layer and recording layer are parallel to each other, and in the high resistance state, the magnetizations of the fixed layer and recording layer are antiparallel to each other.

[0038] The selection element 12 is, for example, a field effect transistor (FET). One of the drain terminal and source terminal of the selection element 12 is connected to the magnetoresistive element 11. The other of the drain terminal and source terminal of the selection element 12 is connected to a source line SL. The gate terminal of the selection element 12 is connected to a word line WL. A voltage signal from the word line WL is applied to the gate of the selection element 12, turning on the selection element 12 (the drain and source become conductive), thereby connecting the magnetoresistive element 11 to the bit line BL and the source line SL, and applying a voltage, current, etc. to the magnetoresistive element 11.

[0039] In the embodiment of the present disclosure, the reference cell 102 of the reference cell array unit 100 also has a configuration similar to that of the memory cell 202 shown in FIG. 1B.

[0040] <<2. Background>> Next, the background that led the inventor to create the embodiment of the present disclosure will be described with reference to Fig. 2. Fig. 2 is an explanatory diagram for explaining the background of the embodiment of the present disclosure.

[0041] As described above, when reading data from each memory cell 202, the sense amplifier 300 detects the resistance state (e.g., low resistance state or high resistance state) of the memory cell 202 based on a reference resistance value, which is a combined resistance value of each reference cell 102 in the reference cell array unit 100 (described later). Specifically, the sense amplifier 300 references a reference voltage (reference current) based on the reference resistance value, compares the reference voltage with the voltage of the memory cell 202, and reads the resistance state of the memory cell 202 based on the comparison result. For example, as shown on the left side of FIG. 2 , the sense amplifier 300 can read two resistance states of the memory cell 202 by comparing the resistance value (MTJ resistance) of the magnetoresistive element 11 of the memory cell 202 with the reference resistance.

[0042] In a memory device 10 configured with a common reference system, each of the sense amplifiers 300 is connected to a plurality of reference cells 102 in the reference cell array section 100 and is also wired to adjacent sense amplifiers 300 (details of the common reference system will be described later). Furthermore, in the memory device 10, the individual reference potentials generated by the plurality of reference cells 102 corresponding to each sense amplifier 300 are shared by the plurality of sense amplifiers 300 via their wired connections, thereby making it possible to average these reference potentials. Therefore, in the common reference system, this average value can be used as a reference potential common to these sense amplifiers 300. The reference resistance, i.e., the reference potential, is determined depending on whether the magnetoresistive elements 11 of the reference cells 102 shared by these sense amplifiers 300 are set to one of two resistance states (low resistance state or high resistance state).

[0043] In the prior art, the setting range of the reference resistance is limited to a range from a low resistance value to a high resistance value corresponding to the two resistance states of the magnetoresistive element 11 .

[0044] Therefore, when reading the resistance state of the magnetoresistive element 11 of the memory cell 202, for example, as shown in the upper right section of FIG. 2 , the sense amplifier 300 cannot distinguish a memory cell 202 that is a defective bit, having a resistance value smaller than the low resistance value or larger than the high resistance value, from a normal bit. If such a defective bit could be identified during a test operation of the memory device 10, it would be possible to address the issue by excluding the defective bit or setting up redundancy, thereby improving the manufacturing yield of the memory device 10 and further improving the operational reliability of the memory device 10. Furthermore, even if a memory cell 202 that is an outlier, having a resistance value smaller than the low resistance value or larger than the high resistance value, operates normally in the initial stage of use of the memory device 10, it is likely to break down at an early stage. Therefore, if such an outlier could be identified during operation of the memory device 10, it would be possible to address the issue by excluding the outlier bit or setting up redundancy, thereby further improving the operational reliability of the memory device 10.

[0045] 2, for example, the value of the reference resistance may deviate significantly from the target value (the center of the detection window of the sense amplifier 300, specifically, between the low resistance value and the high resistance value) due to circuit design, manufacturing process, etc. In such a case, the sense amplifier 300 will not be able to correctly detect the resistance state of the magnetoresistive element 11 of the memory cell 202, which is a normal bit. As a result, all of the memory cells 202 detected by the sense amplifier 300 will be recognized as defective bits, which will increase the cost per memory capacity of the memory device 10 and impair the reliability of the operation of the memory device 10.

[0046] In light of this situation, the inventors have devised the following embodiments of the present disclosure. While utilizing the configuration of a memory device 10 according to the prior art, the embodiments of the present disclosure allow the reference resistance to be set in a range greater than the high resistance value and less than the low resistance value. For example, as shown in the upper right panel of FIG. 2 , by extending the reference resistance range to a range greater than the high resistance value and less than the low resistance value, the sense amplifier 300 according to this embodiment can distinguish defective memory cells 202, which have resistance values ​​less than the low resistance value or greater than the high resistance value, from normal memory cells. As a result, this embodiment can identify such defective memory cells during test operations of the memory device 10 and further address the issue by excluding the defective memory cells or setting redundancy, thereby improving the manufacturing yield of the memory device 10 and further improving the operational reliability of the memory device 10. Furthermore, in this embodiment, the sense amplifier 300 can detect defective memory cells 202, which have resistance values ​​less than the low resistance value or greater than the high resistance value. Therefore, according to this embodiment, since such outlier bits can be identified during operation of the memory device 10, it is possible to address the issue by excluding the outlier bits or setting redundancy, thereby improving the reliability of the operation of the memory device 10. Furthermore, in the embodiment of the present disclosure, even if the value of the reference resistor significantly deviates from the target value due to circuit design, manufacturing process, etc., the value of the reference resistor can be brought closer to the target value, as shown in the lower right section of FIG. 2 , while utilizing the configuration of the memory device 10 of the prior art. As a result, according to this embodiment, the sense amplifier 300 can correctly detect the resistance state of the magnetoresistive element 11 of the memory cell 202 that is a normal bit, and all of the memory cells 202 detected by the sense amplifier 300 will not be recognized as defective bits. Therefore, according to this embodiment, it is possible to suppress an increase in the cost per memory capacity of the memory device 10 and further improve the reliability of the operation of the memory device 10. Below, details of the embodiment of the present disclosure created by the present inventor will be described in order.

[0047] <<3. First Embodiment>> <3.1 Comparative Example> First, referring to FIGS. 3A and 3B, the configuration of a memory device 10 using a common reference system according to a comparative example will be described. FIG. 3A is a schematic diagram of the memory device 10 (common reference system) according to the comparative example. FIG. 3B is a circuit diagram of a reference cell array unit 100a (1SL1BL type) of the memory device 10 (common reference system) according to the comparative example, and FIG. 3C is a circuit diagram of a reference cell array unit 100a (1SL2BL type) of the memory device 10 (common reference system) according to the comparative example. Note that the comparative example here refers to a memory device 10 that the inventors of the present disclosure had studied extensively before developing the embodiments of the present disclosure. Furthermore, the bold lines in FIGS. 3B and 3C indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0048] 3A, the common reference type memory device 10 may be, for example, an open bit line type having a reference cell array section 100 and a memory cell array section 200 sandwiching a sense amplifier 300. For example, in FIG. 3A, when reading a memory cell 202 in the memory cell array section 200, a word line WL connected to the reference cell array section 100 is selected, and a reference resistance (reference potential) is generated by the reference cell 102 connected to the selected word line WL.

[0049] As shown in FIG. 3A , the common reference memory device 10 includes a plurality of sense amplifiers 300. Each sense amplifier 300 is connected to a plurality of memory cells 202 in the memory cell array unit 200 and a plurality of reference cells 102 in the reference cell array unit 100 a. Specifically, as shown in FIGS. 3B and 3C , the reference cell array unit 100 a includes a plurality of reference columns 122. Each of the reference columns 122 includes a plurality of reference cells 102 constituting one or more columns, a source line 120 connected to one terminal of the plurality of reference cells 102, and a bit line 124 connected to the other terminal of the plurality of reference cells 102. Furthermore, each reference column 122 includes a column header switch 126 connecting the source line 120 to the sense amplifier 300, a column footer switch 128 a connected to the source line 120 on the opposite side of the column header switch 126, and a column footer switch 128 b connected to the bit line 124. In the reference cell array section 100a, multiple reference cells 102 located in the same row are connected to the same word line 112. The column header switch 126 and the column footer switches 128a and 128b are, for example, FETs, and the reference cells 102 have the same configuration as the memory cells 202 shown in FIG.

[0050] Furthermore, in a memory device 10 employing the common reference method, as shown in FIG. 3B , each sense amplifier 300 is connected to an adjacent sense amplifier 300 by a common wiring 110. In the common reference method, the individual reference potentials generated by the reference cells 102 corresponding to each sense amplifier 300 are shared by the wiring of the multiple sense amplifiers 300, thereby making it possible to take an average value of these reference potentials. Then, in the common reference method, this average value can be used as a reference potential common to these sense amplifiers 300. In the common reference method, the reference resistance, i.e., the reference potential, is determined depending on whether the magnetoresistive elements 11 of the reference cells 102 shared by these sense amplifiers 300 are set to one of two resistance states (low resistance state or high resistance state).

[0051] Furthermore, when focusing on the source lines 120 and bit lines 124 of the reference cell array section 100a, the common reference type memory device 10 has, for example, two configurations: a 1SL1BL type and a 1SL2BL type. The configuration shown in Figure 3B is a 1SL1BL type configuration in which a reference column 122 made up of a plurality of reference cells 102 arranged in a row is connected to one sense amplifier 300. In the 1SL1BL type configuration, each of the plurality of reference columns 122 has a plurality of reference cells 102 forming a row, one source line 120 connected to one terminal of the reference cells in the row, and one bit line 124 connected to the other terminal of the reference cells in the row. Furthermore, in the 1SL1BL type configuration, each of the multiple reference columns 122 has a column header switch 126 that connects the source line 120 to the sense amplifier 300, a column footer switch 128a connected to the opposite side of the source line 120 from the column header switch 126, and a column footer switch 128b connected to the bit line 124.

[0052] 3C is a 1SL2BL type configuration in which a reference column 122 composed of two columns of reference cells 102 is connected to one sense amplifier 300. In the 1SL2BL type configuration, each of the reference columns 122 has two columns of reference cells 102, one source line 120 connected to one terminal of the two columns of reference cells, and two bit lines 124 connected to the other terminals of the two columns of reference cells. Furthermore, in the 1SL2BL type configuration, each of the reference columns 122 has a column header switch 126 connecting the source line 120 to the sense amplifier 300, a column footer switch 128a connected to the source line 120 on the opposite side of the column header switch 126, and two column footer switches 128b connected to the two bit lines 124.

[0053] 3B and 3C, one reference cell 102 is activated for each sense amplifier 300 by selecting one word line 112. In this way, the reference potential generated by the reference resistance value of the activated reference cell 102 can be shared by the multiple sense amplifiers 300 via the common wiring 110.

[0054] In the case of the reference cell array section 100a shown in Figures 3B and 3C, since the number of sense amplifiers 300 is equal to the number of reference cells 102 to be referenced, the setting range of the averaged reference resistance (reference potential) is limited to a range from a low resistance value to a high resistance value corresponding to the two resistance states of the magnetoresistive element 11.

[0055] Therefore, as explained above, when reading the resistance state of the magnetoresistive element 11 of the memory cell 202, the sense amplifier 300 cannot distinguish a memory cell 202 that is a defective bit, having a resistance value smaller than the low resistance value or larger than the high resistance value, from a normal bit. Furthermore, for example, if the value of the reference resistance deviates significantly from the target value due to the manufacturing process or the like, the sense amplifier 300 cannot correctly detect the resistance state of the magnetoresistive element 11 of the memory cell 202 that is a normal bit.

[0056] Therefore, the present inventor has come up with a first embodiment of a common reference type storage device 10. The first embodiment of the present disclosure created by the present inventor will be described in detail below.

[0057] 3.2 Example (1SL1BL, Low Resistance 1, Column Number Change Pattern) First, referring to FIG. 4A, the configuration of a 1SL1BL type memory device 10 using a common reference method according to a first embodiment of the present disclosure and its operation when expanded to the low resistance side will be described. FIG. 4A is a circuit diagram (column number change pattern) of the reference cell array unit 100 (1SL1BL type) of the memory device 10 (common reference method) according to this embodiment when expanded to low resistance. Note that the bold lines in FIG. 4A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0058] 4A, in this embodiment, the 1SL1BL type memory device 10 of the common reference system also has a plurality of sense amplifiers 300. The reference cell array section 100 is composed of a plurality of reference columns 122. A reference column 122 composed of a plurality of reference cells 102 arranged in a column is connected to one sense amplifier 300. In detail, in the example of FIG. 4A, each of the plurality of reference columns 122 has a plurality of reference cells 102 forming one column, one source line 120 connected to one terminal of the reference cells in the column, and one bit line 124 connected to the other terminal of the reference cells in the column. 4A , each of the plurality of reference columns 122 includes a column header switch (first column switch) 126 that connects the source line 120 to the sense amplifier 300, a column footer switch (second column switch) 128 a that is connected to the source line 120 on the opposite side of the column header switch 126, and a column footer switch (third column switch) 128 b that is connected to the bit line 124. The column header switch 126 and the column footer switches 128 a, 128 b are, for example, FETs, and the reference cells 102 have a configuration similar to that of the memory cells 202 shown in FIG. 1B as described above. In the reference cell array section 100, the plurality of reference cells 102 located in the same row are connected to the same word line 112.

[0059] 4A, in the memory device 10 employing the common reference system, each sense amplifier 300 is connected to an adjacent sense amplifier 300 by a common wiring 110. Also in this embodiment, due to the common reference system, the individual reference potentials generated by the multiple reference cells 102 corresponding to each sense amplifier 300 are shared by the wiring of the multiple sense amplifiers 300, thereby making it possible to obtain an average value of these reference potentials. Also in this embodiment, this average value can be used as a reference potential common to these sense amplifiers 300.

[0060] 4A , in order to extend the reference resistance value toward the low resistance side, the column header switch 126 and the column footer switch 128b are controlled to increase the number of active reference columns 122 corresponding to one sense amplifier 300 from one to multiple. In this manner, as shown in FIG. 4A , the reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in parallel, thereby lowering the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is reduced, the value of the reference resistance shared by multiple sense amplifiers 300 can be extended to a range smaller than the low resistance value.

[0061] (1SL2BL, Low Resistance 1, Column Number Change Pattern) Next, with reference to Figures 4B and 4C, the configuration of a 1SL2BL type memory device 10 with a common reference system according to a first embodiment of the present disclosure and its operation when expanded to the low resistance side will be described. Figures 4B and 4C are circuit diagrams (column number change pattern) of the reference cell array 100 portion (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to low resistance. Note that the thick lines in Figures 4B and 4C indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0062] In this embodiment, as shown in FIGS. 4B and 4C , the 1SL2BL type memory device 10 of the common reference system has a plurality of sense amplifiers 300. The reference cell array section 100 is composed of a plurality of reference columns 122. Furthermore, as shown in FIGS. 4B and 4C , a reference column 122 composed of a plurality of reference cells 102 arranged in two columns is connected to one sense amplifier 300. Specifically, in the example of FIGS. 4B and 4C , each of the plurality of reference columns 122 has a plurality of reference cells 102 forming two columns, one source line 120 connected to one terminal of the two columns of reference cells, and two bit lines 124 connected to the other terminal of the reference cells in each column. 4B and 4C , each of the multiple reference columns 122 has a column header switch (first column switch) 126 that connects the source line 120 to the sense amplifier 300, a column footer switch (second column switch) 128 a connected to the source line 120 on the opposite side of the column header switch 126, and two column footer switches (third column switches) 128 b connected to the two bit lines 124. The column header switch 126 and the column footer switches 128 a, 128 b are, for example, FETs, and the reference cells 102 have a configuration similar to that of the memory cells 202 shown in FIG. 1B as described above. Furthermore, in the reference cell array section 100, multiple reference cells 102 located in the same row are connected to the same word line 112.

[0063] Furthermore, since this embodiment also uses the common reference system, each sense amplifier 300 is connected to an adjacent sense amplifier 300 by a common wiring 110, as shown in Figures 4B and 4C. In this embodiment, too, the individual reference potentials generated by the multiple reference cells 102 corresponding to each sense amplifier 300 are shared by the multiple sense amplifiers 300 through the wiring connections, thereby making it possible to take an average value of these reference potentials. Then, in this embodiment, too, this average value can be used as a reference potential common to these sense amplifiers 300.

[0064] Furthermore, in the example of FIG. 4B , in order to extend the reference resistance value toward the low resistance side, the column header switch 126 and the column footer switch 128 b are controlled to change the number of columns of active reference cells 102 corresponding to one sense amplifier 300 from one to two. In this way, as shown in FIG. 4B , the reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in parallel, thereby lowering the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is reduced, the value of the reference resistance shared by the multiple sense amplifiers 300 can also be extended to a range smaller than the low resistance value.

[0065] In the example of FIG. 4C , to extend the reference resistance value toward the low resistance side, the column header switch 126 and the column footer switch 128b are controlled to increase the number of active reference columns 122 corresponding to one sense amplifier 300 from one to multiple. In this manner, as shown in FIG. 4C , the reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in parallel, thereby lowering the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is reduced, the value of the reference resistance shared by multiple sense amplifiers 300 can also be extended to a range smaller than the low resistance value. That is, in FIGS. 4B and 4C , two columns of reference cells 102 in one reference column 122 may be used per sense amplifier 300, or one column of reference cells 102 in two different reference columns 122 may be used.

[0066] 4A to 4C, the control circuit 22 can expand the value of the reference resistance to a range smaller than the low resistance value by increasing the number of reference columns 122 to be referenced from one to more than one, or by increasing the number of columns consisting of multiple reference cells 102 to be referenced from one to more than one. That is, in these examples, although an additional operation is required in the control logic of the column switch selection circuit 32 described above, the value of the reference resistance can be expanded to a range smaller than the low resistance value without changing the configuration of the reference cell array 100 of the memory device 10 of the prior art.

[0067] (1SL1BL, low resistance 2, word line number change pattern) Next, referring to Figure 5A, the operation of the 1SL1BL type memory device 10 of the common reference system according to this embodiment when expanded to the low resistance side will be described. Figure 5A is a circuit diagram (word line number change pattern) of the reference cell array unit 100 (1SL1BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to low resistance. Note that the thick lines in Figure 5A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0068] The example of FIG. 5A has the same circuit configuration as the 1SL1BL type memory device 10 of the common reference system according to this embodiment shown in FIG. 4A, and therefore a description of the circuit configuration will be omitted.

[0069] In the example of Figure 5A, in order to expand the reference resistance value toward the low resistance side, the word line control circuit 30 is controlled to activate two word lines 112, thereby increasing the number of active reference cells 102 corresponding to one sense amplifier 300 from one to multiple. In this way, as shown in Figure 5A, the reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in parallel, thereby lowering the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is reduced, the value of the reference resistance shared by multiple sense amplifiers 300 can also be expanded to a range smaller than the low resistance value.

[0070] (1SL2BL, Low Resistance 2, Word Line Number Change Pattern) Next, referring to Figure 5B, the operation of the 1SL2BL type memory device 10 of the common reference system according to this embodiment when expanded to the low resistance side will be described. Figure 5B is a circuit diagram (word line number change pattern) of the reference cell array unit 100 (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to low resistance. Note that the thick lines in Figure 5B indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0071] The example of FIG. 5B has the same circuit configuration as the 1SL2BL type memory device 10 of the common reference system according to this embodiment shown in FIGS. 4B and 4C, and therefore a description of the circuit configuration will be omitted.

[0072] In the example of Figure 5B, in order to expand the reference resistance value toward the low resistance side, the word line control circuit 30 is controlled to activate two word lines 112, thereby increasing the number of active reference cells 102 corresponding to one sense amplifier 300 from one to multiple. In this way, as shown in Figure 5B, the reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in parallel, thereby lowering the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is reduced, the value of the reference resistance shared by multiple sense amplifiers 300 can also be expanded to a range smaller than the low resistance value.

[0073] 5A and 5B, the control circuit 22 can expand the value of the reference resistance to a range smaller than the low resistance value by driving multiple word lines 112 to increase the number of reference cells 102 to be referenced. That is, in these examples, although two word lines 112 are controlled, the value of the reference resistance can be expanded to a range smaller than the low resistance value without changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art.

[0074] (1SL1BL, High Resistance 1, Column Number Change Pattern) Next, referring to Figure 6A, the operation of the 1SL1BL type memory device 10 of the common reference system according to this embodiment when expanded to the high resistance side will be described. Figure 6A is a circuit diagram (column number change pattern) of the reference cell array unit 100 (1SL1BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to a high resistance. Note that the thick lines in Figure 6A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0075] The example of FIG. 6A has the same circuit configuration as the 1SL1BL type memory device 10 of the common reference system according to this embodiment shown in FIG. 4A, and therefore description of the circuit configuration will be omitted.

[0076] 6A , in order to extend the reference resistance value toward the high resistance side, the column header switch 126 and the column footer switch 128 b are controlled to reduce the number of reference columns 122 shared by multiple sense amplifiers 300. In this way, as shown in FIG. 6A , the number of parallel reference cells 102 shared by multiple sense amplifiers 300 is reduced, and the value of the reference resistance can be extended to a range larger than the high resistance value.

[0077] (1SL2BL, high resistance 1, column number change pattern) Next, with reference to Figures 6B and 6C, the operation of the 1SL2BL type memory device 10 of the common reference system according to this embodiment when expanded to the high resistance side will be described. Figures 6B and 6C are circuit diagrams (column number change pattern) of the reference cell array unit 100 (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to a high resistance. Note that the thick lines in Figures 6B and 6C indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0078] The examples of FIGS. 6B and 6C have the same circuit configuration as the 1SL1BL type memory device 10 of the common reference system according to this embodiment shown in FIGS. 4B and 4C, and therefore description of the circuit configuration will be omitted.

[0079] 6B and 6C , in order to extend the reference resistance value toward the high resistance side, the column header switch 126 and the column footer switch 128b are controlled to reduce the number of reference columns 122 shared by multiple sense amplifiers 300. In this way, as shown in FIGS. 6B and 6C , the number of parallel reference cells 102 shared by multiple sense amplifiers 300 is reduced, so that the reference resistance value can be extended to a range greater than the high resistance value. The difference between FIGS. 6B and 6C is the number of columns of reference cells 102 in the reference column 122 to be activated.

[0080] 6A to 6C, the control circuit 22 can expand the value of the reference resistor to a range larger than the high resistance value by reducing the number of reference columns 122 shared by multiple sense amplifiers 300. That is, in these examples, although an additional operation is required in the control logic of the column switch selection circuit 32 described above, the value of the reference resistor can be expanded to a range larger than the high resistance value without changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art.

[0081] (1SL1BL, High Resistance 2, Adjacent SL / BL Connection Pattern) Next, referring to Figure 7A, the operation of the 1SL1BL type memory device 10 of the common reference system according to this embodiment when expanded to the high resistance side will be described. Figure 7A is a circuit diagram (adjacent SL / BL connection pattern) of the reference cell array section 100 (1SL1BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to a high resistance. Note that the thick lines in Figure 7A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0082] The example in Fig. 7A has the same circuit configuration as the 1SL1BL memory device 10 with a common reference system according to this embodiment shown in Fig. 4A, but differs from the circuit configuration of the 1SL1BL memory device 10 with a common reference system according to this embodiment shown in Fig. 4A in the following respects. As shown in Fig. 7A, the reference cell array unit 100 has a switch (third switch) 104 that connects the bit line 124 of one reference column 122 of a plurality of adjacent reference columns 122 to the source line 120 of the other reference column 122. The switch 104 is, for example, a FET.

[0083] In the example of FIG. 7A , to extend the reference resistance value toward the high resistance side, the column header switch 126, the column footer switch 128b, and the switch 104 are controlled to increase the number of active reference columns 122 corresponding to one sense amplifier 300 from one to two, and the two reference columns 122 are connected in series. In this manner, as shown in FIG. 7A , two reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in series, thereby increasing the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 increases, the value of the reference resistance shared by multiple sense amplifiers 300 can also be extended to a range greater than the high resistance value.

[0084] (1SL2BL, High Resistance 2, Adjacent SL / BL Connection Pattern) Next, with reference to Figures 7B to 7D, the operation of the 1SL2BL type memory device 10 of the common reference system according to this embodiment when expanded to the high resistance side will be described. Figures 7B to 7D are circuit diagrams (adjacent SL / BL connection pattern) of the reference cell array 100 portion (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment when expanded to a high resistance. Note that the thick lines in Figures 7B to 7D indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0085] The examples of Figures 7B to 7D have the same circuit configuration as the 1SL2BL type memory device 10 with a common reference system according to this embodiment shown in Figures 4B and 4C, but differ from the circuit configuration of the 1SL1BL type memory device 10 with a common reference system according to this embodiment shown in Figures 4B and 4C in the following respects.

[0086] 7B, each reference column 122 has a switch (fourth switch) 106 that connects the bit line 124 of one of the two columns of the plurality of reference cells 102 to the sense amplifier 300. The switch 106 is, for example, a FET.

[0087] In the example of Figure 7B, to expand the reference resistance value toward the high resistance side, the column footer switch 128b and the switch 106 are controlled to change the number of columns of active reference cells 102 corresponding to one sense amplifier 300 from one to two, and the two columns are connected in series. In this way, as shown in Figure 7B, two reference cells 102 that are referenced by the reference resistance per sense amplifier 300 are connected in series, thereby increasing the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is increased, the value of the reference resistance shared by multiple sense amplifiers 300 can also be expanded to a range greater than the high resistance value.

[0088] 7C, each reference column 122 has a switch (fourth switch) 106 that connects the bit line 124 of one of the two columns of reference cells 102 to the sense amplifier 300. Furthermore, as shown in FIG. 7C, the reference cell array unit 100 has a switch (fifth switch) 108 that connects the bit line 124 of one of the adjacent reference columns 122 to the bit line 124 of the other reference column 122. The switch 108 is, for example, a FET.

[0089] In the example of Figure 7C, to expand the reference resistance value toward the high resistance side, the column footer switch 128b and the switches 106 and 108 are controlled to increase the number of active reference columns 122 corresponding to one sense amplifier 300 from one to two, and to connect the two reference columns 122 in series. In this manner, as shown in Figure 7C, four reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in series, thereby increasing the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 increases, the value of the reference resistance shared by multiple sense amplifiers 300 can also be expanded to a range greater than the high resistance value.

[0090] As shown in FIG. 7D, the reference cell array section 100 also has a switch 108 that connects the bit line 124 of one of a plurality of adjacent reference columns 122 to the bit line 124 of the other reference column 122 .

[0091] In the example of FIG. 7D , to extend the reference resistance value toward the high resistance side, the column header switch 126, the column footer switch 128b, and the switch 108 are controlled to increase the number of active reference columns 122 corresponding to one sense amplifier 300 from one to two, and to connect the two reference columns 122 in series. In this manner, as shown in FIG. 7D , two reference cells 102 referenced by the reference resistance per sense amplifier 300 are connected in series, thereby increasing the effective resistance value. Therefore, since the reference resistance (reference potential) per sense amplifier 300 is increased, the value of the reference resistance shared by multiple sense amplifiers 300 can also be extended to a range greater than the high resistance value. That is, in FIGS. 7B to 7D , two columns of reference cells 102 in one reference column 122 may be used per sense amplifier 300, one column of reference cells 102 in two different reference columns 122 may be used, or two different reference columns 122 may be used.

[0092] 7A to 7D , the control circuit 22 changes the number of reference columns 122 to be referenced from one to multiple, and the number of columns consisting of multiple reference cells 102 to be referenced from one to multiple. Furthermore, the control circuit 22 controls the column header switch 126, the column footer switch 128b, and the switches 104, 106, and 108 to serially connect the reference columns 122 and the columns of reference cells 102, thereby expanding the value of the reference resistor to a range greater than the high resistance value. In other words, although these examples require the addition of switches 104, 106, 108, etc., the value of the reference resistor can be expanded to a range greater than the high resistance value without changing the configuration of the reference cell array 100 of the memory device 10 of the prior art.

[0093] <<4. Second Embodiment>> <4.1 Comparative Example> First, the configuration of a memory device 10 using an individual reference method according to a comparative example will be described with reference to FIG. 8 . FIG. 8 is a circuit diagram of a reference cell array unit 100a of a memory device 10 (using an individual reference method) according to a comparative example. Note that the comparative example here refers to a memory device 10 that the inventors of the present disclosure had studied extensively before developing the embodiment of the present disclosure. In addition, the thick lines in FIG. 8 indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0094] The memory device 10 using the individual reference system has a plurality of sense amplifiers 300, similar to the memory device 10 using the common reference system, but each sense amplifier 300 is not connected to adjacent sense amplifiers 300 by a common wiring 110. That is, in the memory device 10 using the individual reference system, each sense amplifier 300 reads data from each memory cell 202 by referring to a reference potential generated by a plurality of reference cells 102 connected to each sense amplifier 300.

[0095] 8, the reference cell array unit 100a of the memory device 10 using the individual reference method according to the comparative example has a plurality of magnetoresistive elements 132 and a selection element 130 as the reference cell 102. In detail, the magnetoresistive elements 132 and the selection element 130 are connected in series between the source line 120 and the bit line 124. Furthermore, the plurality of magnetoresistive elements 132 are connected in parallel to each other in a plurality of columns, each column including a predetermined number of magnetoresistive elements 132 connected in series.

[0096] In the case of the reference cell array section 100a shown in Figure 8, the number of series and parallel connections of the magnetoresistive elements 132 are equal, and as explained above, the setting range of the reference resistance (reference potential) is limited to a range from a low resistance value to a high resistance value corresponding to the two resistance states of the magnetoresistive element 132.

[0097] Therefore, as explained above, when reading the resistance state of the magnetoresistive element 11 of the memory cell 202, the sense amplifier 300 cannot distinguish a memory cell 202 that is a defective bit, having a resistance value smaller than the low resistance value or larger than the high resistance value, from a normal bit. Furthermore, for example, if the value of the reference resistance deviates significantly from the target value due to the manufacturing process or the like, the sense amplifier 300 cannot correctly detect the resistance state of the magnetoresistive element 11 of the memory cell 202 that is a normal bit.

[0098] Therefore, the present inventor has come up with a second embodiment of the individual reference type storage device 10. The first embodiment of the present disclosure created by the present inventor will be described in detail below.

[0099] 4.2 Example (1SL1BL, Low Resistance 1, Series Number Change Pattern) First, referring to FIG. 9A , the configuration of a 1SL1BL memory device 10 using an individual reference method according to a second embodiment of the present disclosure and its operation when expanded to the low resistance side will be described. FIG. 9A is a circuit diagram (series number change pattern) of the reference cell array unit 100 (1SL1BL type) of the memory device 10 (individual reference method) according to this embodiment when expanded to low resistance. Note that the bold lines in FIG. 9A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0100] As shown in FIG. 9A , even in a 1SL1BL memory device 10 using an individual reference method, the reference cell array section 100 is composed of multiple reference columns 122. The reference column 122, which is composed of multiple reference cells 102 arranged in a single column, is connected to a sense amplifier 300. Specifically, in the example of FIG. 9A , each of the multiple reference columns 122 includes multiple reference cells 102 that form a single column, one source line 120 connected to one terminal of the reference cells in the single column, and one bit line 124 connected to the other terminal of the reference cells in the single column. Furthermore, in the example of FIG. 9A , each of the multiple reference columns 122 includes a column header switch (first column switch) 126 that connects the source line 120 to the sense amplifier 300, a column footer switch (second column switch) 128 a connected to the source line 120 on the opposite side of the column header switch 126, and a column footer switch (third column switch) 128 b connected to the bit line 124. The column header switch 126 and the column footer switches 128a and 128b are, for example, FETs, and the reference cells 102 have the same configuration as the memory cells 202 shown in Figure 1B as described above. Furthermore, in the reference cell array section 100, multiple reference cells 102 located in the same row are connected to the same word line 112.

[0101] Furthermore, in this embodiment, since an individual reference method is used, as shown in FIG. 9A, the sense amplifier 300 reads data from each memory cell 202 by referring to individual reference potentials generated by multiple reference cells 102 connected to the sense amplifier 300.

[0102] 9A , the reference cell array unit 100 further includes a switch (sixth switch) 140 that connects the bit line 124 of one of the adjacent reference columns 122 to the source line 120 of the other reference column 122. The switch 140 is, for example, an FET.

[0103] In the example of FIG. 9A , to extend the reference resistance value toward the low resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example of FIG. 9A , the word line control circuit 30 is controlled to activate multiple word lines 112. As a result, as shown in FIG. 9A , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance, resulting in a lower effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, in the example shown in FIG. 9A , the number of series-connected reference cells 102 is set smaller than the number of parallel-connected reference cells 102.

[0104] (1SL2BL, low resistance 1, series number change pattern) Next, with reference to Figures 9B and 9C, the configuration of the 1SL2BL type memory device 10 of the individual reference system according to this embodiment and its operation when expanded to the low resistance side will be described. Figures 9B and 9C are circuit diagrams (series number change pattern) of the reference cell array 100 part (1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to low resistance. Note that the thick lines in Figures 9B and 9C indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0105] 9B and 9C, the reference cell array section 100 of the 1SL2BL type memory device 10 with the individual reference method is composed of a plurality of reference columns 122. In this embodiment, as shown in FIGS. 9B and 9C, the reference column 122 composed of a plurality of reference cells 102 arranged in two columns is connected to the sense amplifier 300. In detail, in the example of FIGS. 9B and 9C, each of the plurality of reference columns 122 has a plurality of reference cells 102 forming two columns, one source line 120 connected to one terminal of the two columns of reference cells, and two bit lines 124 connected to the other terminals of the two columns of reference cells, respectively. 9B and 9C , each of the multiple reference columns 122 has a column header switch (first column switch) 126 that connects the source line 120 to the sense amplifier 300, a column footer switch (second column switch) 128 a connected to the source line 120 on the opposite side of the column header switch 126, and two column footer switches (third column switches) 128 b connected to the two bit lines 124. The column header switch 126 and the column footer switches 128 a, 128 b are, for example, FETs, and the reference cells 102 have a configuration similar to that of the memory cells 202 shown in FIG. 1B as described above. Furthermore, in the reference cell array section 100, multiple reference cells 102 located in the same row are connected to the same word line 112.

[0106] Furthermore, in this embodiment, since an individual reference method is used, as shown in Figures 9B and 9C, the sense amplifier 300 reads data from each memory cell 202 by referring to individual reference potentials generated by multiple reference cells 102 connected to the sense amplifier 300.

[0107] Furthermore, in the examples shown on the right and left sides of FIG. 9B and the right side of FIG. 9C , the reference cell array unit 100 includes a switch (eighth switch) 140 that connects the bit line 124 of one of the adjacent reference columns 122 to the bit line 124 of the other reference column 122. The switch 140 is, for example, a FET. Furthermore, in the examples shown on the left side of FIG. 9B and the left side of FIG. 9C , each reference column 122 includes a switch (seventh switch) 142 that connects the bit line 124 of one of the two columns of the reference cells 102 to the sense amplifier 300. The switch 142 is, for example, a FET.

[0108] In the example on the left side of FIG. 9B , to extend the reference resistance value toward the low resistance side, the column footer switch 128 a and switches 140 and 142 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example on the left side of FIG. 9B , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the left side of FIG. 9B , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which lowers the effective resistance value of the reference resistance. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, in the example shown on the left side of FIG. 9B , the number of series-connected reference cells 102 is set smaller than the number of parallel-connected reference cells 102.

[0109] In the example on the right side of FIG. 9B , to extend the reference resistance value toward the low resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example on the right side of FIG. 9B , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the right side of FIG. 9B , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance, resulting in a lower effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, even in the example shown on the right side of FIG. 9B , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102.

[0110] In the example on the left side of FIG. 9C , to extend the reference resistance value toward the low resistance side, the column footer switch 128b and the switch 142 are controlled to change the number of columns of active reference cells 102 corresponding to the sense amplifier 300 from one to multiple, and the columns of reference cells 102 are connected in series. Furthermore, in the example on the left side of FIG. 9C , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the left side of FIG. 9C , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which lowers the effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, even in the example shown on the left side of FIG. 9C , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102.

[0111] In the example on the right side of FIG. 9C , to extend the reference resistance value toward the low resistance side, the column header switch 126, the column footer switch 128a, and the switch 140 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example on the right side of FIG. 9C , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the right side of FIG. 9C , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are referenced by the reference resistance, resulting in a lower effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, even in the example shown on the right side of FIG. 9C , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102. That is, in Figures 9B and 9C, the sense amplifier 300 may use two columns of reference cells 102 in one reference column 122, may use one column of reference cells 102 in two different reference columns 122, or may use two different reference columns 122.

[0112] As described above, in the examples shown in FIGS. 9A to 9C , the control circuit 22 changes the number of reference columns 122 to be referenced from one to multiple, and the number of columns consisting of multiple reference cells 102 to be referenced from one to multiple. Furthermore, in the examples shown in FIGS. 9A to 9C , the control circuit 22 controls the column header switch 126, the column footer switches 128 a, 128 b, and the switches 140, 142 to connect the reference columns 122 and the columns of reference cells 102 in series. In this manner, in this embodiment, the value of the reference resistance can be expanded to a range smaller than the low resistance value. However, in the examples shown in FIGS. 9A to 9C , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102. That is, although these examples require the addition of switches 140, 142, etc., the value of the reference resistance can be expanded to a range smaller than the low resistance value without changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art.

[0113] (1SL1BL / 1SL2BL, low resistance 2, parallel number change pattern) Next, with reference to Figure 10, the operation of the 1SL1BL type / 1SL2BL type memory device 10 of the individual reference system according to this embodiment when expanded to the low resistance side will be described. Figure 10 is a circuit diagram (parallel number change pattern) of the reference cell array section 100 (1SL1BL type / 1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to low resistance. Note that the thick lines in Figure 10 indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0114] The example on the left side of Fig. 10 has the same circuit configuration as the 1SL1BL memory device 10 with an individual reference system according to this embodiment shown on the right side of Fig. 9A, and therefore a description of that circuit configuration will be omitted. Also, the example on the right side of Fig. 10 has the same circuit configuration as the 1SL2BL memory device 10 with an individual reference system according to this embodiment shown on the left side of Fig. 9B, and therefore a description of that circuit configuration will be omitted.

[0115] In the 1SL1BL-type example shown on the left side of FIG. 10 , to extend the reference resistance value toward the low resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to change the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example shown on the left side of FIG. 10 , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the left side of FIG. 10 , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance, resulting in a lower effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, in the example shown on the left side of FIG. 10 , the number of series-connected reference cells 102 is set to be smaller than the number of parallel-connected reference cells 102.

[0116] In the 1SL2BL-type example on the right side of FIG. 10 , to extend the reference resistance value toward the low resistance side, the column footer switch 128b and switches 140 and 142 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example on the right side of FIG. 10 , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown on the right side of FIG. 10 , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance, resulting in a lower effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the low resistance value. However, even in the example shown on the right side of FIG. 10 , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102.

[0117] As described above, in the example shown in FIG. 10 , the control circuit 22 increases the number of reference columns 122 from one to multiple and connects them in series by controlling the column header switch 126, the column footer switch 128b, and the switches 140 and 142, thereby expanding the reference resistance value to a range smaller than the low resistance value. Note that in the example shown in FIG. 10 , the number of series-connected reference cells 102 is smaller than the number of parallel-connected reference cells 102. That is, although these examples require control of multiple word lines 112 and the addition of switches 140 and 142, the reference resistance value can be expanded to a range smaller than the low resistance value without changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art. Furthermore, in the example shown in FIG. 10 , the reference resistance is a composite of the resistances of multiple magnetoresistive elements 11, and is therefore less susceptible to variations in the resistance of each magnetoresistive element 11.

[0118] (1SL1BL, high resistance 1, parallel number change pattern) Next, referring to Figure 11A, the operation of the 1SL1BL type memory device 10 of the individual reference system according to this embodiment when expanded to the high resistance side will be described. Figure 11A is a circuit diagram (parallel number change pattern) of the reference cell array unit 100 (1SL1BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to high resistance. Note that the thick lines in Figure 11A indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0119] The example of FIG. 11A has the same circuit configuration as the 1SL1BL type memory device 10 of the individual reference system according to this embodiment shown in FIG. 9A, and therefore description of the circuit configuration will be omitted.

[0120] In the example of FIG. 11A , to extend the reference resistance value toward the high resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example of FIG. 11A , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown in FIG. 11A , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance. This increases the effective resistance value. Therefore, the reference resistance value can be extended to a range greater than the high resistance value. However, in the example shown in FIG. 11A , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102.

[0121] 11B and 11C, the operation of the 1SL2BL type memory device 10 of the individual reference system according to this embodiment when expanded to the high resistance side will be described. Figures 11B and 11C are circuit diagrams (parallel number change pattern) of the reference cell array unit 100 (1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to high resistance. Note that the thick lines in Figures 11B and 11C indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0122] The example of Fig. 11B has the same circuit configuration as the 1SL2BL memory device 10 with an individual reference system according to this embodiment shown on the left side of Fig. 9B and the left side of Fig. 9C, and therefore a description of the circuit configuration will be omitted. Also, the example of Fig. 11C has the same circuit configuration as the 1SL2BL memory device 10 with an individual reference system according to this embodiment shown on the right side of Fig. 9B and the right side of Fig. 9C, and therefore a description of the circuit configuration will be omitted.

[0123] In the example of FIG. 11B , to extend the reference resistance value toward the high resistance side, the column footer switches 128 a, 128 b and switches 140, 142 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and these columns are connected in series. Furthermore, in the example of FIG. 11B , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown in FIG. 11B , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which serve as the reference for the reference resistance. This increases the effective resistance value. Therefore, the reference resistance value can be extended to a range greater than the high resistance value. However, even in the example shown in FIG. 11B , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102.

[0124] In the example of FIG. 11C , to extend the reference resistance value toward the high resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, or increase the number of columns of reference cells 102 from one to multiple, and connect them in series. Furthermore, in the example of FIG. 11C , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown in FIG. 11C , the sense amplifier 300 increases the effective resistance value because multiple reference cells 102, which are referenced by the reference resistance, are connected in series and in parallel. Therefore, the reference resistance value can be extended to a range greater than the high resistance value. However, even in the example shown in FIG. 11C , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102.

[0125] 11A to 11C , the control circuit 22 increases the number of reference columns 122 from one to multiple and connects them in series by controlling the column header switch 126, the column footer switches 128 a and 128 b, and the switches 140 and 142, thereby expanding the range of reference resistance beyond the high resistance value. Note that in the examples shown in FIGS. 11A to 11C , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102. That is, although these examples require the addition of switches 140 and 142, the value of the reference resistance can be expanded beyond the high resistance value without changing the configuration of the reference cell array 100 of the memory device 10 of the prior art.

[0126] (1SL1BL / 1SL2BL, High Resistance 2, Series Number Change Pattern) Next, with reference to FIGS. 12A and 12B, the operation of the 1SL1BL / 1SL2BL memory device 10 with an individual reference system according to this embodiment when expanded to the low resistance side will be described. FIG. 12A is a circuit diagram (series number change pattern) of the reference cell array 100 section (1SL1BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to a high resistance. FIG. 12B is a circuit diagram (series number change pattern) of the reference cell array 100 section (1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment when expanded to a high resistance. Note that the thick lines in FIGS. 12A and 12B indicate elements in an active state through which current flows, and the dashed lines indicate current paths.

[0127] The example in Fig. 12A has the same circuit configuration as the 1SL1BL memory device 10 with an individual reference system according to this embodiment shown on the right side of Fig. 9A, and therefore a description of the circuit configuration will be omitted. Also, Fig. 12B has the same circuit configuration as the 1SL2BL memory device 10 with an individual reference system according to this embodiment shown on the left side of Fig. 9B, and therefore a description of the circuit configuration will be omitted.

[0128] In the 1SL1BL-type example of FIG. 12A , to extend the reference resistance value toward the high resistance side, the column header switch 126, the column footer switch 128b, and the switch 140 are controlled to change the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example of FIG. 12A , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown in FIG. 12A , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance. This increases the effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the high resistance value. However, in the example shown in FIG. 12A , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102.

[0129] In the 1SL2BL example of FIG. 12B , to extend the reference resistance value toward the high resistance side, the column footer switch 128 b and switches 140 and 142 are controlled to increase the number of active reference columns 122 corresponding to the sense amplifier 300 from one to multiple, and the multiple reference columns 122 are connected in series. Furthermore, in the example of FIG. 12B , the word line control circuit 30 is controlled to activate multiple word lines 112. In this manner, as shown in FIG. 12B , the sense amplifier 300 has multiple reference cells 102 connected in series and in parallel, which are reference targets of the reference resistance. This increases the effective resistance value. Therefore, the reference resistance value can be extended to a range smaller than the high resistance value. However, in the example shown in FIG. 12B , the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102.

[0130] 12A and 12B, the control circuit 22 increases the number of reference columns 122 from one to multiple and connects them in series by controlling the column header switch 126, the column footer switch 128b, and the switches 140 and 142, thereby expanding the range of reference resistance beyond the high resistance value. In the example shown in FIG. 12, the number of series-connected reference cells 102 is greater than the number of parallel-connected reference cells 102. In other words, although these examples require the addition of switches 140 and 142, the value of the reference resistance can be expanded beyond the high resistance value without changing the configuration of the reference cell array 100 of the memory device 10 of the prior art.

[0131] <<5. Third Embodiment>> In order to expand the value of the reference resistance, it is possible to devise the reference cell 102 that generates the reference resistance or to devise the circuit connection of the memory device 10. For example, in conventional technology, in order to expand the value of the reference resistance, the magnetoresistive element 11 in the reference cell 102 has been connected in series / parallel, the size of the magnetoresistive element 11 has been changed, the magnetoresistive element 11 has been replaced with another resistive element, the circuit configuration has been changed, and so on. However, these methods have been impractical because they increase the size of the memory device 10 and the manufacturing costs. Furthermore, these methods have had limitations in expanding the range of the reference resistance value.

[0132] In view of this situation, the present inventor has come up with a third embodiment of the present disclosure. According to this embodiment, the range of reference resistance values ​​can be easily expanded to a wider range without increasing the size of the memory device 10 or increasing manufacturing costs. The details of the third embodiment of the present disclosure created by the present inventor will be described below.

[0133] The configuration of the memory device 10 according to this embodiment will be described with reference to Figures 13A, 13B, and 14. Figure 13A is a circuit diagram of a reference cell array unit 100 (1SL1BL type) of the memory device 10 (common reference system) according to this embodiment, and Figure 13B is a circuit diagram of a reference cell array unit 100 (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment. Also, Figure 14 is a circuit diagram of a reference cell array unit 100 (1SL1BL type / 1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment.

[0134] 13A and 13B, a word line 112 is added to the reference cell array section 100 of the shared reference type memory device 10, and a plurality of short cells 154 are connected to the added word line 112. The short cell 154 is formed by removing the magnetoresistive element 11 from the memory cell 202 shown in FIG. 1B and shorting the portion that became open after the removal with wiring (short wiring).

[0135] In the example shown in FIG. 14, a word line 112 is added to the reference cell array section 100 of the memory device 10 using the individual reference method, and a plurality of short cells 154 are connected to the added word line 112 .

[0136] As described above, in the examples shown in Figures 13A, 13B, and 14, by making part of the reference cell array section 100 a short cell 154, the value of the reference resistance can be expanded more widely to a range smaller than the low resistance value without substantially changing the configuration of the reference cell array section 100 of the memory device 10 of the prior art.

[0137] Another configuration of the memory device 10 according to this embodiment will be described with reference to Figures 15A, 15B, and 16. Figure 15A is a circuit diagram of a reference cell array unit 100 (1SL1BL type) of the memory device 10 (common reference system) according to this embodiment, and Figure 15B is a circuit diagram of a reference cell array unit 100 (1SL2BL type) of the memory device 10 (common reference system) according to this embodiment. Also, Figure 16 is a circuit diagram of a reference cell array unit 100 (1SL1BL type / 1SL2BL type) of the memory device 10 (individual reference system) according to this embodiment.

[0138] 15A and 15B, a word line 112 is added to the reference cell array section 100 of the shared reference type memory device 10, and a plurality of open cells 156 are connected to the added word line 112. The open cell 156 has an open disconnection portion obtained by removing the magnetoresistive element 11 from the memory cell 202 shown in FIG.

[0139] In the example shown in FIG. 16, a word line 112 is added to the reference cell array section 100 of the memory device 10 using the individual reference method, and a plurality of open cells 156 are connected to the added word line 112 .

[0140] As described above, in the examples shown in Figures 15A, 15B, and 16, by making part of the reference cell array section 100 an open cell 156, the value of the reference resistance can be expanded more widely to a range larger than the high resistance value, without substantially changing the configuration of the reference cell array section 100 of the memory device 10 of the prior art.

[0141] 6. Fourth Embodiment The short cell 154 and the open cell 156 of the third embodiment may be applied to the first and second embodiments of the present disclosure described above. Therefore, with reference to FIGS. 17A, 17B, and 18, a fourth embodiment of the present disclosure in which the short cell 154 of the third embodiment and the like are applied to the first and second embodiments will be described. FIG. 17A is a circuit diagram of a reference cell array unit 100 (1SL1BL type) of a memory device 10 (common reference system) according to this embodiment, and FIG. 17B is a circuit diagram of a reference cell array unit 100 (1SL2BL type) of a memory device 10 (common reference system) according to this embodiment. Furthermore, FIG. 18 is a circuit diagram of a reference cell array unit 100 (1SL1BL type / 1SL2BL type) of a memory device 10 (individual reference system) according to this embodiment.

[0142] 17A, 17B, and 18, by using the short cell 154, it is possible to broaden the range of the reference resistance value to a value smaller than the low resistance value without substantially changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art. Similarly, by using the open cell 156, it is possible to broaden the range of the reference resistance value to a value larger than the high resistance value without substantially changing the configuration of the reference cell array unit 100 of the memory device 10 of the prior art. In other words, according to this embodiment, it is possible to broaden the range of the reference resistance value.

[0143] <<7. Fifth Embodiment>> In a fifth embodiment of the present disclosure, an example will be described in which a reference resistance (potential) used when determining data in a memory element is formed by the average resistance of a plurality of reference elements (magnetoresistive elements), and an element in a destroyed state is used as part of the reference element.

[0144] FIG. 19 is a circuit diagram showing a configuration example of a memory device 10 according to a fifth embodiment of the present disclosure. FIG. 19 illustrates the sense amplifier 300, the reference cell array 100, and the memory cell array 200 of the memory device 10. A cell to be destroyed 103 is disposed in the reference cell array 100 of FIG. 19. This cell to be destroyed 103 includes a selection element 134 and a magnetoresistive element 133. The magnetoresistive element 133 is a magnetoresistive element that is destroyed in either a high-resistance state or a low-resistance state by a destruction operation. The magnetoresistive element 133 of the cell to be destroyed 103 becomes a low-resistance state by destruction in short-circuit mode, and becomes a high-resistance state by destruction in open-circuit mode. Details of the configuration of the cell to be destroyed 103 will be described later.

[0145] The reference cell array section 100 in FIG. 19 shows an example in which only a cell to be destroyed 103 is arranged. The cell to be destroyed 103 is connected to a common wiring 110. Note that a reference cell 102 and a cell to be destroyed 103 may also be arranged in the reference cell array section 100. Even in this case, at least one cell to be destroyed 103 is arranged in the reference cell array section 100. Note that the upper side of FIG. 19 shows an example in which the selection element 134 of the cell to be destroyed 103 is connected to the common wiring 110, and the magnetoresistive element 133 is connected to a bit line. As shown in a simplified form in the lower side of FIG. 19, the magnetoresistive element 133 of the cell to be destroyed 103 may be connected to the common wiring 110, and the selection element 134 may be connected to a bit line.

[0146] 19 is arranged for each row of the reference cell array section 100 and the memory cell array section 200. A source line 120 to which one end of a memory cell 202 is connected is connected to a data input of the sense amplifier 300. A common wiring 110 is connected to a reference input of the sense amplifier 300. In FIG. 19, the data input and the reference input are denoted as "Data" and "Ref", respectively.

[0147] 20A-20C are diagrams showing an example of the configuration of a cell to be destroyed 103 according to a fifth embodiment of the present disclosure. FIG. 20A is a schematic diagram showing an example of the configuration of the cell to be destroyed 103. The cell to be destroyed 103 includes a magnetoresistive element 133 and a selection element 134 connected in series. The magnetoresistive element 133 is configured by sequentially stacking an electrode 139, a fixed layer 135, an insulating layer 136, a recording layer 137, and an electrode 138. A lower wiring 161 is connected to the electrode 139. This lower wiring 161 is connected to the selection element 134. An upper wiring 162 is connected to the electrode 138. This upper wiring 162 is connected to a bit line. FIG. 20A shows a write current during writing. The solid arrow in FIG. 20A represents the write current.

[0148] 20B shows an example of destroying the cell 103 to be destroyed in a short-circuit mode. As shown in FIG. 20B, the insulating layer 136 of the magnetoresistive element 133 is destroyed to create a short-circuit state, thereby placing the magnetoresistive element 133 in a low resistance state. This destruction can be caused by passing a current larger than the write current. This destruction operation is called destructive writing. The open arrow in FIG. 20B represents the destructive write current.

[0149] 20C shows an example of destroying the cell 103 to be destroyed in the open mode. As shown in FIG. 20C, after the insulating layer 136 of the magnetoresistive element 133 is destroyed to create a short circuit, the magnetoresistive element 133 can be put into a high resistance state by opening at least one of the lower wiring 161 and the upper wiring 162. This destruction can be caused by passing a destructive write current larger than the destructive write current of FIG. 20B. The open arrow in FIG. 20C represents this destructive write current.

[0150] The selection element 134 of the cell 103 to be destroyed can be configured with an element that can pass these destructive write currents. Note that destructive writing can be performed by passing a current that is larger than the normal write current through the magnetoresistive element 133, but it can also be performed by passing the write current for a long period of time. In this way, destructive writing can be performed by performing writing with increased write power.

[0151] The magnetoresistive element 133 in the low resistance state can have a resistance value lower than that of the magnetoresistive element 11 in the low resistance state in the reference cell 102 described in FIG. 1B. The magnetoresistive element 133 in the high resistance state can have a resistance value higher than that of the magnetoresistive element 11 in the high resistance state in the reference cell 102.

[0152] 21 is a circuit diagram showing another configuration example of the memory device 10 according to the fifth embodiment of the present disclosure. Fig. 21 shows an example in which the same word line 112 is connected to the memory cell 202 of the memory cell array section 200 and the cell 103 to be destroyed of the reference cell array section 100.

[0153] 22 is a circuit diagram showing another example configuration of the memory device 10 according to the fifth embodiment of the present disclosure. Fig. 22 shows an example in which different word lines are connected to the memory cells 202 of the memory cell array unit 200 and the cells to be destroyed 103 of the reference cell array unit 100. A word line 112 (such as WL1) is connected to the memory cells 202 of the memory cell array unit 200 in Fig. 22. On the other hand, a word line 113 (SWL) is connected to the cells to be destroyed 103 of the reference cell array unit 100.

[0154] By using the destroyed cells 103, it is possible to generate a reference resistance and reference potential in a range that cannot be generated by the reference cells 102 having non-destructive magnetoresistive elements. This makes it possible to distinguish between normal resistance bits and abnormal resistance bits in non-volatile memories such as STT-MRAM. Furthermore, when applied to OTP-MRAM (One Time Programmable-MRAM), it becomes possible to appropriately determine whether the OTP cell is in a destroyed state or a non-destructive state. Furthermore, when the destroyed cells 103 have the same configuration as the reference cells 102, it is possible to arbitrarily select which reference cells 102 will be destructively written to and become the destroyed cells 103 from among the group of reference cells 102 that form the average resistance. This makes it possible to adjust the number of destroyed cells 103 and perform optimal reference settings for each memory circuit.

[0155] <<8. Sixth Embodiment>> In a sixth embodiment of the present disclosure, a memory device 10 to which a circuit for writing data to the memory cells 202 and the cells to be destroyed 103 is added will be described.

[0156] Fig. 23 is a circuit diagram showing a configuration example of a memory device 10 according to a sixth embodiment of the present disclosure. Like Fig. 21, Fig. 23 is a circuit showing a configuration example of the memory device 10. The memory device 10 of Fig. 23 differs from the memory device 10 of Fig. 21 in that it further includes a write drive unit 33, a bit line control circuit 27B, a source line control circuit 28B, a source line control circuit 28A, and a destructive write control unit 35. Furthermore, the memory device 10 of Fig. 23 shows one row of cells 103 to be destroyed.

[0157] The write driver 33 performs writing to the memory cell 202. The write driver 33 performs writing to the memory cell 202 by supplying a write current to the bit line 124 connected to the memory cell 202. The write driver 33 also performs destructive writing to the cell to be destroyed 103. The write driver 33 performs destructive writing to the cell to be destroyed 103 by supplying a destructive write current to the bit line 125 connected to the cell to be destroyed 103. The write current is supplied via wiring 118. The destructive write current is supplied via wiring 119.

[0158] The source line control circuit 28B includes a plurality of switches 172. One end of the plurality of switches 172 is commonly connected to a wiring 117. This wiring 117 is connected to the data input of a sense amplifier 300. The other end of the switch 172 is connected to a source line 120. That is, the source line 120 is connected to the data input of the sense amplifier 300 via the switch 172. The other end of the source line 120 is connected to a circuit common via a switch 173. The bit line control circuit 27B includes a plurality of switches 171. The bit line 124 is connected to a wiring 118 via the switch 171. The other end of the bit line 124 is connected to a circuit common via a switch 174.

[0159] The source line control circuit 28 A includes a switch 175 .

[0160] The destructive write control unit 35 selects the cell 103 to be destroyed that is to be subjected to destructive writing. The destructive write control unit 35 in Fig. 23 includes a switch 176. The source line 121 connected to the cell 103 to be destroyed is connected to the common wiring 110 via a switch 175. The other end of the source line 121 is connected to the circuit common via a switch 177. The bit line 125 connected to the cell 103 to be destroyed is connected to the wiring 119 via a switch 176. The other end of the bit line 125 is connected to the circuit common via a switch 178.

[0161] When writing to the memory cell 202, the switch 171 of the bit line control circuit 27B of the row to be written is turned on, the switch 173 of the row to be written is turned on, and the switch 174 of the row to be written is turned off. Furthermore, the write drive unit 33 supplies a write current to the wiring 118. This causes writing to be performed on the memory cell 202 of the row to be written. Note that when reading from the memory cell 202, the switch 172 of the source line control circuit 28B of the row to be written is turned on, the switch 173 of the row to be written is turned off, and the switch 174 of the row to be written is turned on.

[0162] When destructive writing is performed on the to-be-destroyed cell 103, the switch 176 of the destructive writing control unit 35 is turned on, the switch 177 is turned on, and the switch 178 is turned off. Furthermore, the write drive unit 33 supplies a destructive writing current to the wiring 119. This causes destructive writing to the to-be-destroyed cell 103. When the to-be-destroyed cell 103 is used as a reference cell, the switch 175 of the source line control circuit 28A is turned on, the switch 177 is turned off, and the switch 178 is turned on.

[0163] Fig. 24 is a circuit diagram showing another configuration example of the memory device 10 according to the sixth embodiment of the present disclosure. Like Fig. 23, Fig. 24 is a diagram showing a configuration example of the memory device 10. The memory device 10 in Fig. 24 differs from the memory device 10 in Fig. 23 in that a write drive unit 33, a bit line control circuit 27B, a source line control circuit 28B, a source line control circuit 28A, and a destructive write control unit 35 are arranged in the circuit of Fig. 22.

[0164] The source line control circuit 28A in the figure includes a plurality of switches 175. The destructive write control unit 35 in the figure also includes a plurality of switches 176.

[0165] The wiring 118 is connected to the write drive unit 33 via an FET 143. The wiring 119 is connected to the write drive unit 33 via an FET 144. The signal line Array is connected to the gate of the FET 143. The signal line Array is connected to the gate of the FET 144 via an inverting gate 145.

[0166] When writing to the memory cell 202, an H-level signal is input to the signal line Array, causing the write drive unit 33 to supply a write current. This allows writing to be performed. When passing a destructive write current through the to-be-destroyed cell 103, an L-level signal is input to the signal line Array, causing the write drive unit 33 to supply a destructive write current. This allows destructive writing to be performed.

[0167] The processing of the storage device 10 will be explained with reference to FIGS.

[0168] FIG. 25 is a diagram illustrating an example of processing by the storage device 10 according to the sixth embodiment of the present disclosure. FIG. 25 is a flowchart illustrating the processing procedure for initial reference setting. First, the control circuit 22 controls the write drive unit 33 and the like to perform a destruction operation on a predetermined number of destruction target cells 103 (step S101). Next, the control circuit 22 reads the destruction target cells 103 that have been subjected to the destruction operation (step S102). Next, the control circuit 22 acquires the number of failure bits based on the read result (step S103). Next, the control circuit 22 determines whether the acquired number of failure bits is less than a judgment value (step S104). As a result, if the acquired number of failure bits is less than the judgment value (step S104, Yes), the control circuit 22 terminates the processing.

[0169] On the other hand, if the acquired number of fault bits is not less than the judgment value (step S104, No), the control circuit 22 determines whether the number of destroyed cells 103 in the reference cell array unit 100 is equal to or greater than the set number (step S105). As a result, if the number of destroyed cells 103 in the reference cell array unit 100 is equal to or greater than the set number (step S105, Yes), the control circuit 22 ends the process.

[0170] On the other hand, if the number of destroyed cells 103 in the reference cell array section 100 is not equal to or greater than the set number (step S105, No), the control circuit 22 performs a destruction operation on the cells 103 (step S106) and proceeds to the processing of step S102.

[0171] 26 is a diagram illustrating an example of processing of the storage device 10 according to the sixth embodiment of the present disclosure. The processing of FIG. 26 is processing subsequent to the processing of FIG. 25. First, the control circuit 22 selects the target cell 103 (step S111). Next, the control circuit 22 reads the selected target cell 103 (step S112). Next, the control circuit 22 determines whether the selected target cell 103 is expected to be destroyed (step S113). As a result, if the selected target cell 103 is expected to be destroyed (step S113, Yes), the control circuit 22 performs a destruction determination (step S114). As a result, if it is determined that destruction has occurred (step S114, Yes), the control circuit 22 ends the processing.

[0172] On the other hand, if it is not determined that the cell is destroyed (step S114, No), the control circuit 22 writes (step S115) and reads (step S116) the cell to be destroyed 103. Next, the control circuit 22 determines whether the cell is destroyed (step S117). If it is determined that the cell is destroyed (step S117, Yes), the control circuit 22 ends the process.

[0173] On the other hand, if it is not determined that the memory device 10 is destroyed (step S117, No), the control circuit 22 performs a rewrite process (step S118) and ends the process. Note that the control circuit 22 can also make the destroyed cell 103 a redundant bit in step S118. Also, the control circuit 22 can discard the memory device 10 in step S118.

[0174] In step S113, if the selected cell 103 to be destroyed is not expected to be destroyed (step S113, No), the control circuit 22 performs a non-destructive determination (step S119). If it is determined to be non-destructive (step S119, Yes), the control circuit 22 ends the process.

[0175] On the other hand, if it is not determined to be non-destructive (step S119, No), the control circuit 22 discards the memory device 10 (step S120). Note that the control circuit 22 can also make the cell 103 to be destroyed a redundant bit in step S120.

[0176] In this way, the storage device 10 according to the sixth embodiment of the present disclosure can perform destructive writing to the target cell 103 .

[0177] <<9. Seventh Embodiment>> The storage device 10 of the sixth embodiment of the present disclosure described above includes the write driver 33. In contrast, the storage device 10 of the seventh embodiment of the present disclosure differs from the storage device 10 of the sixth embodiment of the present disclosure in that it further includes a destructive write driver that supplies only a destructive write current.

[0178] Fig. 27 is a circuit diagram showing a configuration example of a storage device 10 according to a seventh embodiment of the present disclosure. Like Fig. 23, Fig. 27 is a circuit showing a configuration example of the storage device 10. The storage device 10 in Fig. 27 differs from the storage device 10 in Fig. 23 in that it further includes a destructive write drive unit 34.

[0179] 27 supplies only the write current of the memory cell 202. The destructive write driver 34 can supply a destructive write current of a different power from the write current of the write driver 33.

[0180] <<10. Eighth Embodiment>> An application example to a system will be described with reference to Fig. 28A and Fig. 28B. Fig. 28A is a diagram showing an overview of a system in which a storage device 10 according to an embodiment of the present disclosure is installed, and Fig. 28B is a diagram showing an operation example of the system of Fig. 28A.

[0181] As shown in FIG. 28A , the system according to this embodiment includes an MRAM 500 corresponding to the storage device 10 according to the embodiment of the present disclosure, and a CPU 502 that controls the MRAM 500 .

[0182] As shown in FIG. 28B, when the MRAM 500 works in cooperation with the CPU 502, during normal operation, the CPU 502 outputs to the MRAM 500 a Read / Write command to read / write data from / to the memory cell 202, and a Write command to write data to the reference cell 102 (to set the reference resistance value) at a predetermined timing.

[0183] Furthermore, in this embodiment, a test operation can be performed during such normal operation to detect memory cells 202 that are defective bits. Specifically, during the test operation after normal operation, the CPU 502 outputs a connection setting command to the MRAM 500 to set the reference cell 102 to a predetermined connection, and then outputs a write command to write to the reference cell 102 (to set the reference resistance value). At this time, the CPU 502 outputs a command to set the reference resistance value to a value greater than the high resistance value or less than the low resistance value (second operation). Furthermore, in this embodiment, the CPU 502 outputs a read command to the MRAM 500 to read the memory cells 202 in order to detect memory cells 202 that are defective bits, and then outputs a command to transmit the detection result to the CPU 502.

[0184] Furthermore, in this embodiment, after the above-described test operation is completed, normal operation can be resumed. Specifically, when normal operation is resumed, the CPU 502 outputs a connection setting command to the MRAM 500 to set the reference cell 102 to a predetermined connection, and outputs a write command to write to the reference cell 102. At this time, the CPU 502 outputs a command to set the reference resistance value between a high resistance value and a low resistance value (first operation). Furthermore, in this embodiment, the above-described first operation and second operation can be performed alternately.

[0185] In this embodiment, the series of operations shown in FIG. 28B can be performed without cutting off the power supply to the MRAM 500. Furthermore, in this embodiment, the system can freely change the value of the reference resistor. Furthermore, this embodiment makes it possible to easily detect faulty bits and perform calibration or the like to eliminate them.

[0186] Furthermore, if the system includes a plurality of the MRAMs 500, the CPU 502 may individually control whether each MRAM 500 performs a normal operation or a test operation, or may control each MRAM 500 to perform the same operation simultaneously. In such a case, the CPU 502 may also control the reference resistance values ​​of each MRAM 500 to be different values ​​or the same value. In this embodiment, information for control by the CPU 502 may be stored in the MRAM 500, or may be stored in an external storage layer and transferred to the MRAM 500 when used.

[0187] <<11. Summary>> As described above, the embodiments of the present disclosure can provide a storage device, an electronic device, and a method for controlling a storage device that can further improve operational reliability.

[0188] In an embodiment of the present disclosure, while utilizing the configuration of the memory device 10 of the prior art, the setting range of the reference resistance can be expanded to a range greater than the high resistance value and less than the low resistance value. Therefore, according to this embodiment, the sense amplifier 300 can distinguish memory cells 202 that are faulty bits, having resistance values ​​smaller than the low resistance value or greater than the high resistance value, from normal bits. According to this embodiment, such faulty bits can be identified during test operations of the memory device 10, and furthermore, the faulty bits can be excluded, redundant settings, etc. can be implemented, thereby improving the manufacturing yield of the memory device 10 and further improving the reliability of the operation of the memory device 10. Furthermore, in this embodiment, the sense amplifier 300 can detect memory cells 202 that are outliers, having resistance values ​​smaller than the low resistance value or greater than the high resistance value. Therefore, according to this embodiment, such outliers can be identified during operation of the memory device 10, and the outliers can be excluded, redundant settings, etc. can be implemented, thereby improving the reliability of the operation of the memory device 10.

[0189] Furthermore, in the embodiment of the present disclosure, even if the value of the reference resistor deviates significantly from the target value due to circuit design, manufacturing process, or the like, the value of the reference resistor can be brought closer to the target value while utilizing the configuration of the memory device 10 of the conventional technology. Therefore, according to this embodiment, the sense amplifier 300 can correctly detect the resistance state of the magnetoresistive element 11 of the memory cell 202 that is a normal bit, and all of the memory cells 202 detected by the sense amplifier 300 will not be recognized as defective bits. Therefore, according to this embodiment, it is possible to suppress an increase in the cost per memory capacity of the memory device 10 and further improve the operational reliability of the memory device 10.

[0190] It should be noted that the embodiments of the present disclosure are not limited to the forms shown in the drawings, and various modifications are possible.

[0191] Finally, whether the value of the reference resistor can be expanded according to an embodiment of the present disclosure was confirmed using a memory device 10 with an individual reference system. FIG. 29 shows the results when the value of the reference resistor is changed in a memory device 10 with an individual reference system. Specifically, the 1SL1BL memory device 10 with an individual reference system that was investigated has the circuit diagram shown on the left side of FIG. 9A , and the number of series and parallel connections of the reference cells 102 in the reference cell array section 100 is up to four. In FIG. 29 , "RL" indicates that the magnetoresistive element 11 of the reference cell 102 is in a low resistance state, and "RH" indicates that the magnetoresistive element 11 of the reference cell 102 is in a high resistance state.

[0192] As shown in Figure 29, according to this embodiment, the reference resistance value can be expanded not only between the high resistance value and the low resistance value, but also from values ​​greater than the high resistance value to values ​​smaller than the low resistance value.

[0193] <<12. Application Examples>> The storage device 10 according to an embodiment of the present disclosure can be implemented in various electronic devices that can include a memory (storage unit). For example, the storage device 10 may be implemented in various electronic devices, such as an imaging device 400, a distance measuring device, a game device, a notebook PC (Personal Computer), a mobile device (e.g., a smartphone or tablet PC), a PDA (Personal Digital Assistant), a wearable device, a video playback device, a music device, an in-vehicle device, an industrial machine, a home appliance, or an artificial satellite. For example, the storage device 10 may be used as various types of memory, such as storage.

[0194] An imaging device 400 to which the storage device 10 according to an embodiment of the present disclosure is applied will be described with reference to Fig. 30. Fig. 30 is a diagram showing an example of a schematic configuration of the imaging device 400. The imaging device 400 is an example of an electronic device to which the storage device 10 according to the present embodiment is applied. Examples of the imaging device 400 include electronic devices such as digital still cameras, video cameras, smartphones and mobile phones with imaging functions.

[0195] 30 , the imaging device 400 includes an optical system 401, a shutter device 402, an imaging element (solid-state imaging device) 403, a control circuit (drive circuit) 404, a signal processing circuit 405, a monitor 406, and a memory 407. The imaging device 400 can capture still images and moving images.

[0196] The optical system 401 includes one or more lenses. The optical system 401 guides light (incident light) from a subject to the image sensor 403, and forms an image on the light receiving surface of the image sensor 403.

[0197] The shutter device 402 is disposed between the optical system 401 and the image sensor 403. The shutter device 402 controls the light irradiation period and the light blocking period for the image sensor 403 under the control of the control circuit 404.

[0198] The image sensor 403 accumulates signal charges for a certain period of time in response to light that is focused on the light receiving surface via the optical system 401 and the shutter device 402. The signal charges accumulated in the image sensor 403 are transferred in accordance with a drive signal (timing signal) supplied from a control circuit 404.

[0199] The control circuit 404 outputs a drive signal that controls the transfer operation of the image sensor 403 and the shutter operation of the shutter device 402 , thereby driving the image sensor 403 and the shutter device 402 .

[0200] The signal processing circuit 405 can perform various types of signal processing on the signal charges output from the image sensor 403. The image (image data) obtained by the signal processing performed by the signal processing circuit 405 is supplied to a monitor 406 and further to a memory 407.

[0201] The monitor 406 displays a moving image or a still image captured by the image sensor 403 based on the image data supplied from the signal processing circuit 405. As the monitor 406, for example, a panel-type display device such as a liquid crystal panel or an organic EL (Electro Luminescence) panel can be used.

[0202] The memory 407 stores image data supplied from the signal processing circuit 405, i.e., image data of moving images or still images captured by the image sensor 403. The memory 407 corresponds to the storage device 10 according to an embodiment of the present disclosure.

[0203] <<13. Supplementary Information>> Although preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, the technical scope of the present disclosure is not limited to such examples. It is clear that a person skilled in the art of the present disclosure can conceive of various modified or altered examples within the scope of the technical idea described in the claims, and it is understood that these also naturally fall within the technical scope of the present disclosure.

[0204] Furthermore, the effects described herein are merely descriptive or exemplary and are not limiting. In other words, the technology according to the present disclosure may achieve other effects that will be apparent to those skilled in the art from the description of this specification, in addition to or in place of the above-described effects.

[0205] Furthermore, the components of each device shown in the figure are conceptual functional components and do not necessarily have to be physically configured as shown in the figure. In other words, the specific form of distribution and integration of each device is not limited to that shown in the figure, and all or part of them can be functionally or physically distributed and integrated in any unit depending on various loads, usage conditions, etc.

[0206] The present technology can also be configured as follows: (1) A storage device comprising: a memory cell array unit consisting of a plurality of memory cells, each including a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array unit consisting of a plurality of reference cells having a configuration similar to that of the memory cell array unit; a sense amplifier connected to the plurality of memory cells, and detecting a resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control unit capable of selecting a reference cell from the plurality of reference cells to be referenced for reading the reference resistance value, and changing the value of the reference resistance value within a predetermined range, wherein an upper limit of the predetermined range is greater than the high resistance value and a lower limit of the predetermined range is less than the low resistance value. (2) The memory device according to (1), wherein the reference cell array section has a plurality of reference columns, each of the plurality of reference columns having: a plurality of reference cells constituting one or more columns; a source line connected to one terminal of the plurality of reference cells; a bit line connected to the other terminal of the plurality of reference cells; a first column switch connecting the source line to the sense amplifier; a second column switch connected to the source line on the opposite side of the first column switch; and a third column switch connected to the bit line; and wherein the plurality of reference cells located in the same row are connected to the same word line. (3) The memory device according to (2) above, comprising a plurality of sense amplifiers connected to each other by a common line, wherein the plurality of sense amplifiers detect the resistance value of the magnetoresistive element of the selected memory cell based on an averaged resistance value obtained by averaging the resistance values ​​of the reference columns corresponding to each of the sense amplifiers, and wherein the control unit: selects one or more reference columns to be referenced from the plurality of reference columns; selects one or more columns to be referenced from the plurality of columns included in the reference column; or selects one or more word lines corresponding to rows to be driven from a plurality of word lines.(4) The memory device according to (3), wherein each reference column has one column of the reference cells. (5) The memory device according to (4), wherein the reference cell array unit has a third switch connecting the bit line of one of the reference columns to the source line of the other of the adjacent reference columns. (6) The memory device according to (3), wherein each reference column has: two columns of the reference cells; the source line connected to the two columns of the reference cells; and two bit lines connected to each of the two columns of the reference cells. (7) The memory device according to (6), wherein each reference column has a fourth switch connecting the bit line of one of the two columns of the reference cells to the sense amplifier. (8) The memory device according to (6) or (7), wherein the reference cell array unit has a fifth switch connecting the bit lines of adjacent reference columns to each other. (9) The memory device according to (2), comprising a plurality of the sense amplifiers, each of the plurality of sense amplifiers detecting a resistance value of the magnetoresistive element of the selected memory cell based on a resistance value of the reference column corresponding to the each sense amplifier, and the control unit selecting one or more of the reference columns to be referenced from the plurality of reference columns, selecting one or more of the columns to be referenced from the plurality of columns included in the reference column, or selecting one or more of the word lines corresponding to a row to be driven from a plurality of word lines. (10) The memory device according to (9), wherein each of the reference columns has one column of the plurality of reference cells. (11) The memory device according to (10), wherein the reference cell array unit has a sixth switch connecting the bit line of one of the adjacent reference columns to the source line of the other of the adjacent reference columns. (12) The memory device according to (9), wherein each of the reference columns includes: two columns of the reference cells; the source line connected to the two columns of the reference cells; and two bit lines connected to each of the two columns of the reference cells.(13) The memory device according to (12), wherein each of the reference columns has a seventh switch connecting the bit line of one of the two columns of the plurality of reference cells to the sense amplifier. (14) The memory device according to (12) or (13), wherein the reference cell array unit has an eighth switch connecting the bit lines of adjacent reference columns to each other. (15) The memory device according to any one of (1) to (14), wherein at least one of the plurality of reference cells is a short cell including a short wiring instead of the magnetoresistive element. (16) The memory device according to any one of (1) to (15), wherein at least one of the plurality of reference cells is an open cell including a disconnection point instead of the magnetoresistive element. (17) The memory device according to any one of (1) to (16), wherein at least one of the plurality of reference cells is a destroyed cell including the magnetoresistive element that is brought into a destroyed state of either a high resistance state or a low resistance state by a destruction operation. (18) The storage device according to (17), further comprising a destructive write driver that performs destructive writing equivalent to the destructive operation to set the magnetoresistive element of the cell to be destroyed to either a high resistance state or a low resistance state. (19) The storage device according to (18), further comprising a destructive write control unit that selects the cell to be destroyed as a target of the destructive writing. (20) The storage device according to (17), further comprising a write driver that writes to the memory cell and performs destructive writing equivalent to the destructive operation on the cell to be destroyed. (21) The storage device according to (20), wherein the write driver performs the destructive writing with a power different from that used for writing the memory cell. (22) The storage device according to any of (1) to (21), wherein the memory cell and the reference cell located in the same row in the memory cell array unit and the reference cell array unit are connected to the same word line.(23) An electronic device comprising a storage device for storing data, the storage device having: a memory cell array section consisting of a plurality of memory cells, each including a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells, and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section capable of selecting, from the plurality of reference cells, the reference cell to be referenced for reading the reference resistance value, and changing the value of the reference resistance value within a predetermined range, wherein an upper limit of the predetermined range is greater than the high resistance value and a lower limit of the predetermined range is less than the low resistance value. (24) A control method for a memory device comprising: a memory cell array section consisting of a plurality of memory cells, each including a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting a resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control unit capable of selecting a reference cell from the plurality of reference cells to be referenced to read the reference resistance value, and changing a value of the reference resistance value within a predetermined range, wherein the control unit changes the value of the reference resistance value within the predetermined range, and an upper limit of the predetermined range is greater than the high resistance value, and a lower limit of the predetermined range is less than the low resistance value. (25) The control method for a memory device described in (24) above, wherein, during a read operation of the memory cell array unit, the control unit performs a first operation of setting the value of the reference resistance value between the high resistance value and the low resistance value, and during a test operation of the memory cell array unit, the control unit performs a second operation of setting the value of the reference resistance value to be greater than the high resistance value or smaller than the low resistance value.(26) The control method for a storage device according to (25), wherein the control unit alternately executes the first operation and the second operation.

[0207] 10 Memory device 11, 132, 133 Magnetoresistance element 12, 130, 134 Selection element 21 I / O 22 Control circuit 26 Address decoder 27A, 27B Bit line control circuit 28A, 28B Source line control circuit 29 Word line address decoder 30, 30A, 30B Word line control circuit 31 Sense amplifier circuit 32 Column switch selection circuit 33 Write drive unit 34 Destructive write drive unit 100, 100a Reference cell array unit 102 Reference cell 103 Destroyed cell 104, 106, 108, 140, 142, 171 to 178 Switch 110 Common wiring 112, 113 Word line 120, 121 Source line 122 Reference column 124, 125 Bit line 126 Column header switch 128a, 128b Column footer switch 154 Short cell 156 Open cell 200 Memory cell array section 202 Memory cell 300 Sense amplifier 400 Imaging device 401 Optical system 402 Shutter device 403 Imaging element (solid-state imaging device) 404 Control circuit (drive circuit) 405 Signal processing circuit 406 Monitor 407 Memory 500 MRAM 502 CPU

Claims

1. A memory device comprising: a memory cell array section consisting of a plurality of memory cells, each of which includes a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section that can select a reference cell from the plurality of reference cells to be referenced to read the reference resistance value, and change the value of the reference resistance value within a predetermined range, wherein the upper limit of the predetermined range is greater than the high resistance value and the lower limit of the predetermined range is less than the low resistance value.

2. The memory device according to claim 1, wherein the reference cell array section has a plurality of reference columns, each of the plurality of reference columns having: a plurality of reference cells forming one or more columns; a source line connected to one terminal of the plurality of reference cells; a bit line connected to the other terminal of the plurality of reference cells; a first column switch connecting the source line to the sense amplifier; a second column switch connected to the source line on the opposite side of the first column switch; and a third column switch connected to the bit line; and wherein the plurality of reference cells located in the same row are connected to the same word line.

3. A memory device as described in claim 2, comprising a plurality of sense amplifiers connected to each other by a common line, wherein the plurality of sense amplifiers detect the resistance value of the magnetoresistive element of the selected memory cell based on an averaged resistance value obtained by averaging the resistance values ​​of the reference columns corresponding to each of the sense amplifiers, and wherein the control unit: selects one or more reference columns to be referenced from the plurality of reference columns; selects one or more columns to be referenced from the plurality of columns included in the reference column; or selects one or more word lines corresponding to a row to be driven from a plurality of word lines.

4. The memory device of claim 3, wherein each of said reference columns comprises one row of said plurality of reference cells.

5. The memory device according to claim 4, wherein the reference cell array section has a third switch that connects the bit line of one of the plurality of adjacent reference columns to the source line of the other of the plurality of adjacent reference columns.

6. The memory device of claim 3, wherein each of the reference columns comprises: two columns of the reference cells; a source line connected to the two columns of the reference cells; and two bit lines connected to each of the two columns of the reference cells.

7. The memory device according to claim 6, wherein each of said reference columns has a fourth switch connecting said bit line of one of said two columns of a plurality of reference cells to said sense amplifier.

8. The memory device according to claim 6, wherein said reference cell array section has a fifth switch for connecting said bit lines of a plurality of adjacent reference columns together.

9. A memory device as described in claim 2, comprising a plurality of sense amplifiers, each of which detects the resistance value of the magnetoresistive element of the selected memory cell based on the resistance value of the reference column corresponding to each sense amplifier, and wherein the control unit: selects one or more of the reference columns to be referenced from the plurality of reference columns; selects one or more of the columns to be referenced from the plurality of columns included in the reference column; or selects one or more of the word lines corresponding to the row to be driven from a plurality of word lines.

10. The memory device of claim 9, wherein each of said reference columns comprises one row of said plurality of reference cells.

11. The memory device according to claim 10, wherein said reference cell array section has a sixth switch connecting said bit line of one of said adjacent reference columns to said source line of the other of said adjacent reference columns.

12. The memory device of claim 9, wherein each of the reference columns comprises: two columns of the reference cells; a source line connected to the two columns of the reference cells; and two bit lines connected to each of the two columns of the reference cells.

13. The memory device according to claim 12, wherein each of the reference columns has a seventh switch connecting the bit line of one of the two columns of the plurality of reference cells to the sense amplifier.

14. The memory device according to claim 12, wherein said reference cell array section has an eighth switch that connects said bit lines of a plurality of adjacent reference columns together.

15. The memory device according to claim 1, wherein at least one of said plurality of reference cells is a short cell including a short wiring in place of said magnetoresistive element.

16. The memory device according to claim 1, wherein at least one of said plurality of reference cells is an open cell that includes an open circuit in place of said magnetoresistive element.

17. The memory device according to claim 1, wherein at least one of said plurality of reference cells is a cell to be destroyed, which includes said magnetoresistive element that is brought into a destroyed state of either a high resistance state or a low resistance state by a destruction operation.

18. The storage device according to claim 17, further comprising a destructive write driver that performs destructive writing corresponding to the destructive operation to set the magnetoresistive element of the cell to be destroyed to either a high resistance state or a low resistance state.

19. The storage device according to claim 18, further comprising a destructive write control unit that selects the cells to be destructed as targets for the destructive write.

20. The storage device according to claim 17, further comprising a write driver that writes to said memory cells and performs destructive writing on said target cells, which corresponds to said destructive operation.

21. The storage device according to claim 20, wherein the write driver performs the destructive write with a power different from that used for writing to the memory cells.

22. The memory device according to claim 1, wherein the memory cells and the reference cells located on the same row in the memory cell array section and the reference cell array section are connected to the same word line.

23. An electronic device comprising a storage device for storing data, the storage device having: a memory cell array section consisting of a plurality of memory cells, each of which includes a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section capable of selecting, from the plurality of reference cells, the reference cell to be referenced for reading the reference resistance value, and changing the value of the reference resistance value within a predetermined range, wherein the upper limit of the predetermined range is greater than the high resistance value and the lower limit of the predetermined range is less than the low resistance value.

24. A control method for a storage device comprising: a memory cell array section consisting of a plurality of memory cells, each including a magnetoresistive element whose resistance value is variable between a high resistance value and a low resistance value, and a transistor connected to the magnetoresistive element; a reference cell array section consisting of a plurality of reference cells having a configuration similar to that of the memory cell array section; a sense amplifier connected to the plurality of memory cells and detecting the resistance value of the magnetoresistive element of a memory cell selected from the plurality of memory cells based on a reference resistance value; and a control section which can select a reference cell from the plurality of reference cells to be referenced to read the reference resistance value, and change the value of the reference resistance value within a predetermined range, wherein the control section changes the value of the reference resistance value within the predetermined range, and an upper limit of the predetermined range is greater than the high resistance value and a lower limit of the predetermined range is less than the low resistance value.

25. A control method for a memory device as described in claim 24, wherein, during a read operation of the memory cell array unit, the control unit performs a first operation of setting the reference resistance value between the high resistance value and the low resistance value, and during a test operation of the memory cell array unit, the control unit performs a second operation of setting the reference resistance value to a value greater than the high resistance value or less than the low resistance value.

26. The method for controlling a storage device according to claim 25, wherein the control unit alternately executes the first operation and the second operation.

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