Solid-state imaging device and imaging device

Abstract

[Problem] To provide a solid-state imaging device and an imaging device that enable the inhibition of a residual image which occurs in a pixel. [Solution] A solid-state imaging device according to a first aspect of the present disclosure comprises a pixel array unit in which a plurality of pixels are arranged in a 2D array format, wherein each of the pixels includes: a photoelectric conversion unit which accumulates electrical charge resulting from photoelectric conversion; a transfer transistor which transfers electrical charge stored in the photoelectric conversion unit resulting from the photoelectric conversion; a floating diffusion which stores the electrical charge transferred by the transfer transistor; a first capacitor which is connected to a first switching transistor and stores the electrical charge received from the floating diffusion; and a second capacitor which is connected to a second switching transistor and stores the electrical charge received from the floating diffusion.

Description

Solid-state imaging device and imaging device

[0001] FIELD Embodiments of the present invention relate to a solid-state imaging device and an imaging apparatus.

[0002] In recent years, high-density capacitors have been used in pixel circuits such as lateral overflow integration capacitor (LOFIC) pixels and voltage domain global shutter (VDGS) pixels.

[0003] When such a capacitor is used in a pixel circuit, dielectric absorption may cause an afterimage of the previous frame to appear in the reference frame.

[0004] When charging and resetting is performed using a capacitor, the charge will be zero in an ideal capacitor. However, in reality, dielectric absorption causes charge to rebound from GND to the capacitor, and charge is stored in the capacitor, which can cause an afterimage to remain in the reference frame, i.e., the frame after the reset.

[0005] U.S. Pat. No. 1,169,6048

[0006] In the above-described method, in order to prevent the occurrence of image lag due to dielectric absorption, the amount of image lag in the reference frame is calculated and corrected using data from a frame preceding the reference frame.

[0007] However, calculating the amount of residual image requires a large-capacity frame buffer, making it difficult to implement in a solid-state imaging device. Furthermore, if the pixel values ​​in the frame before the reference frame are saturated, the amount of residual image cannot be calculated correctly. Furthermore, this residual image is more likely to occur when using analog gain.

[0008] In view of these problems, the present disclosure provides a solid-state imaging device and an imaging device that can suppress image retention that occurs in pixels.

[0009] According to a first aspect of the present disclosure, there is provided a solid-state imaging device including a pixel array unit having a plurality of pixels arranged in a two-dimensional array, each of the pixels including a photoelectric conversion unit configured to accumulate charge by photoelectric conversion, a transfer transistor configured to transfer the charge accumulated in the photoelectric conversion unit by the photoelectric conversion, a floating diffusion configured to accumulate the charge transferred by the transfer transistor, a first capacitance connected to a first switching transistor to accumulate the charge received from the floating diffusion, and a second capacitance connected to a second switching transistor to accumulate the charge received from the floating diffusion. This allows the solid-state imaging device to have sufficient time to discharge charge generated by dielectric absorption, thereby suppressing the occurrence of image lag even when capturing images continuously.

[0010] In this first aspect, the first switching transistor and the second switching transistor are turned on at a first timing that is a reference timing and a second timing that is different from the first timing, respectively. This allows, for example, the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, and can suppress the occurrence of afterimages even when capturing images continuously.

[0011] In this first aspect, the first timing is included in a period of a first frame, and the second timing is included in a period of a second frame following the first frame. This allows, for example, the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, and can suppress the occurrence of afterimages even when capturing images continuously.

[0012] In addition, in this first aspect, the solid-state imaging device may further include a reset transistor that drains charges from the first capacitance and the second capacitance, and while the reset transistor is in an on state, the first switching transistor and the second switching transistor are in an on state. This allows, for example, the solid-state imaging device to reset the charges in the first capacitance and the second capacitance.

[0013] In the first aspect, the second switching transistor is turned off at the first timing, which allows the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, thereby suppressing the occurrence of afterimages even when capturing images continuously.

[0014] In the first aspect, the first switching transistor is turned off at the second timing, which allows the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, thereby suppressing the occurrence of afterimages even when capturing images continuously.

[0015] In this first aspect, the first switching transistor is arranged on a higher potential side than the first capacitor, and the second switching transistor is arranged on a higher potential side than the second capacitor, thereby enabling the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, and to suppress the occurrence of afterimages even when capturing images continuously.

[0016] In this first aspect, the first switching transistor is arranged on a lower potential side than the first capacitance, and the second switching transistor is arranged on a lower potential side than the second capacitance. As a result, even if a leakage current occurs when the first switching transistor or the second switching transistor is turned on, the leakage current does not flow into the first capacitance or the second capacitance, and charge is not stored, thereby preventing fixed pattern noise from occurring in an image.

[0017] In addition, according to the first aspect, the solid-state imaging device further includes a fifth capacitor connected to the fifth switching transistor, wherein the first capacitor or the second capacitor stores charge at a pixel signal level, and the fifth capacitor stores charge at a pixel reset level. As a result, for example, when the solid-state imaging device reads out the pixel signal level, charge is stored in the first capacitor or the second capacitor due to dielectric absorption, but by alternately using these capacitors for each frame, charge can be sufficiently discharged and image retention can be suppressed.

[0018] According to a second aspect of the present disclosure, there is provided a solid-state imaging device including a pixel array unit having a plurality of pixels arranged in a two-dimensional array, each of the pixels including a photoelectric conversion unit configured to accumulate charge by photoelectric conversion, a transfer transistor configured to transfer the charge accumulated in the photoelectric conversion unit by the photoelectric conversion, a floating diffusion configured to accumulate the charge transferred by the transfer transistor, a first capacitance configured to accumulate the charge received from the floating diffusion, and a second capacitance configured to accumulate charge having a polarity different from that of the charge accumulated in the first capacitance. As a result, for example, the solid-state imaging device can reverse the polarity by changing the connection destination of the second capacitance for each frame, thereby canceling the charge accumulated in the first capacitance by dielectric absorption.

[0019] In the second aspect, the solid-state imaging device further includes a first switching transistor that connects one end of the second capacitance to a node on a high potential side, and a second switching transistor that connects the other end of the second capacitance to a node on a low potential side. This allows, for example, the solid-state imaging device to change the connection destination of the second capacitance for each frame, thereby reversing polarity and canceling charge stored in the first capacitance due to dielectric absorption.

[0020] In the second aspect, the solid-state imaging device further includes a fourth switching transistor that connects one end of the second capacitor to a node on a low potential side, and a third switching transistor that connects the other end of the second capacitor to a node on a high potential side. As a result, for example, by changing the connection destination of the second capacitor for each frame, the solid-state imaging device can invert the polarity and cancel out the charge stored in the first capacitor due to dielectric absorption.

[0021] In the second aspect, the first switching transistor and the second switching transistor are turned on at a first reference timing, so that, for example, the solid-state imaging device can reverse the polarity by changing the connection destination of the second capacitance for each frame, thereby canceling the charge stored in the first capacitance due to dielectric absorption.

[0022] In this second aspect, the third switching transistor and the fourth switching transistor are turned on at a second timing different from the first timing, so that, for example, the solid-state imaging device can reverse the polarity by changing the connection destination of the second capacitance for each frame, thereby canceling the charge stored in the first capacitance by dielectric absorption.

[0023] In the second aspect, the first switching transistor and the second switching transistor are turned off at the second timing, thereby canceling the charge stored in the first capacitor due to dielectric absorption, for example.

[0024] In the second aspect, the third switching transistor and the fourth switching transistor are turned off at the first timing, thereby canceling the charge stored in the first capacitor due to dielectric absorption, for example.

[0025] In this second aspect, the pixel circuit further includes a fifth capacitor connected to the fifth switching transistor, the first capacitor storing charge at the pixel signal level, and the fifth capacitor storing charge at the pixel reset level, so that, for example, when the fifth switching transistor is turned on by a control signal, the fifth capacitor can store charge according to the pixel reset level.

[0026] According to a third aspect of the present disclosure, there is provided an imaging device including a solid-state imaging device, the solid-state imaging device including a pixel array unit in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion unit that accumulates charge by photoelectric conversion; a transfer transistor that transfers the charge accumulated in the photoelectric conversion unit by the photoelectric conversion; a floating diffusion that accumulates the charge transferred by the transfer transistor; a first capacitance connected to a first switching transistor that accumulates the charge received from the floating diffusion; and a second capacitance connected to a second switching transistor that accumulates the charge received from the floating diffusion. This allows, for example, the imaging device to have sufficient time to discharge charge generated by dielectric absorption, thereby suppressing the occurrence of afterimages even when capturing images continuously.

[0027] In the third aspect, the first switching transistor and the second switching transistor are turned on at a first timing that is a reference timing and a second timing that is different from the first timing, respectively. This allows, for example, the solid-state imaging device to have sufficient time to discharge charges generated by dielectric absorption, and can suppress the occurrence of afterimages even when capturing images continuously.

[0028] In this third aspect, the first timing is included in a period of a first frame, and the second timing is included in a period of a second frame following the first frame. This allows, for example, the imaging device to have sufficient time to discharge charges generated by dielectric absorption, and can suppress the occurrence of afterimages even when capturing images continuously.

[0029] 1 is a block diagram showing an example of the configuration of an imaging device in a first embodiment. FIG. 2 is a block diagram showing a schematic configuration of a solid-state imaging device in the first embodiment. FIG. 3 is an example of a circuit diagram of a pixel in the first embodiment. FIG. 4 is an example of a timing chart of each element in odd-numbered frames and even-numbered frames in the first embodiment. FIG. 5 is a diagram explaining dielectric absorption. FIG. 6 is an example of a circuit diagram of a pixel in a comparative example of the first embodiment. FIG. 7 is a diagram explaining how an object is imaged using an imaging device. FIG. 8 is a diagram comparing an ideal image with an image in which an afterimage occurs due to dielectric absorption. FIG. 9 is an example of a circuit diagram of a pixel in a modified example of the first embodiment. FIG. 10 is an example of a circuit diagram of a pixel in another comparative example of the first embodiment. FIG. 11 is an example of a circuit diagram of a pixel in a modified example of the second embodiment. FIG. 12 is a diagram explaining the configuration and operation of a portion of a pixel circuit in a third embodiment. FIG. 13 is a circuit diagram of a pixel in the third embodiment. FIG. 14 is a diagram explaining connection of capacitances in the third embodiment. FIG. 15 is a diagram showing the relationship between pixel potential and time in the third embodiment. FIG. 16 is a circuit diagram of a pixel in a modified example of the third embodiment. FIG. 17 is a block diagram showing an example of the configuration of a vehicle control system. FIG. 18 is a diagram showing an example of a sensing area.

[0030] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In this specification and the drawings, components having substantially the same functional configurations are designated by the same reference numerals, and their description will be omitted as appropriate. The drawings are simplified, and components necessary for implementation other than those shown in the drawings are also included as appropriate. Furthermore, when terms such as "first" and "second" are used in this specification or claims, unless otherwise specified, they do not represent any order or importance, but are used to distinguish one configuration from another.

[0031] Additionally, in this disclosure, the terms "equal to or greater than" and "equal to or less than" can be read as "greater than" and "less than," respectively.

[0032] First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device 2 according to a first embodiment.

[0033] The imaging device 2 is a device that captures an image of an object, and includes an imaging lens 210, a solid-state imaging device 10, a recording unit 211, and an imaging control unit 230. Examples of the imaging device 2 are a digital camera such as an IoT camera, or an electronic device with an imaging function (such as a smartphone or a personal computer).

[0034] The solid-state imaging device 10 captures an image under the control of the imaging control unit 230. The solid-state imaging device 10 supplies the image to a recording unit 211 via a signal line 209.

[0035] The imaging lens 210 collects light and guides it to the solid-state imaging device 10. The imaging control unit 230 controls the solid-state imaging device 10 to capture an image. The imaging control unit 230 supplies an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging device 10 via, for example, a signal line 139. The recording unit 211 records the image.

[0036] Here, the vertical synchronization signal VSYNC is a signal that indicates the timing of imaging, and a periodic signal with a fixed frequency (such as 60 Hz) is used as the vertical synchronization signal VSYNC.

[0037] In this embodiment, the imaging device 2 records the captured images in the recording unit 211, but the images may also be transmitted to the outside of the imaging device 2. In this case, an external interface for transmitting the images to the imaging device 2 is further provided. The imaging device 2 may also display the captured images. In this case, the imaging device 2 is further provided with a display unit.

[0038] FIG. 2 is a block diagram showing a schematic configuration of the solid-state imaging device 10 according to the first embodiment.

[0039] 2 includes a pixel array section 20 in which a plurality of pixels are arranged in a matrix, and a peripheral circuit section therearound, which includes a vertical drive section 12, an AD conversion section 13, a horizontal drive section 14, a control section 15, a signal processing section 16, a data storage section 17, an input / output section 18, and the like.

[0040] Each pixel arranged in a two-dimensional array in the pixel array unit 20 is composed of a photoelectric conversion unit and a plurality of pixel transistors, etc. The plurality of pixel transistors are, for example, MOS transistors such as transfer transistors, amplification transistors, selection transistors, and reset transistors. Each pixel in the pixel array unit 20 has, for example, red (R), green (G), or blue (B) color filters arranged in a Bayer array, and each pixel outputs a pixel signal of either R, G, or B (hereinafter simply referred to as a signal).

[0041] The vertical drive unit 12 is configured by, for example, a shift register, and drives the pixels row by row by supplying drive pulses to each pixel of the pixel array unit 20 via pixel drive wiring (not shown). That is, the vertical drive unit 12 selects and scans each pixel of the pixel array unit 20 row by row in the vertical direction, and outputs pixel signals based on signal charges generated in the photoelectric conversion unit of each pixel according to the amount of incident light to the signal processing unit 16 via vertical signal lines provided in common for each column.

[0042] The AD conversion unit (ADC) 13 performs AD conversion on the signal output from the pixel array unit 20 .

[0043] The horizontal drive unit 14 is composed of, for example, a shift register, and sequentially outputs horizontal scanning pulses to sequentially output the (digital) pixel signals after AD conversion of each pixel in a specified row held in the AD conversion unit 13 to the signal processing unit 16.

[0044] The control unit 15 receives a clock signal input from the outside and data instructing the operation mode, etc., and controls the operation of the entire solid-state imaging device 10. For example, the control unit 15 generates a vertical synchronization signal, a horizontal synchronization signal, etc. based on the input clock signal, and supplies them to the vertical drive unit 12, the AD conversion unit 13, the horizontal drive unit 14, etc. Each control signal supplied to each element, which will be described later, is supplied under the control of the control unit 15.

[0045] The signal processing unit 16 performs various digital signal processing such as black level adjustment, column variation correction, and demosaic processing on the pixel signals supplied from the AD conversion unit 13 as needed, and supplies the resulting signals to the input / output unit 18. Depending on the operation mode, the signal processing unit 16 may only buffer the pixel signals and output them. The data storage unit 17 stores data such as parameters required for the signal processing performed by the signal processing unit 16. The data storage unit 17 also includes a frame memory for storing image signals in processes such as demosaic processing. The signal processing unit 16 can store parameters and the like input from an external image processing device via the input / output unit 18 in the data storage unit 17, and can appropriately select and execute signal processing based on instructions from the external image processing device.

[0046] The input / output unit 18 outputs the image signals sequentially input from the signal processing unit 16 to an external image processing device, for example, an ISP (Image Signal Processor) at a subsequent stage, etc. The input / output unit 18 also supplies signals and parameters input from the external image processing device to the signal processing unit 16 and the control unit 15.

[0047] The solid-state imaging device 10 is configured as described above and is, for example, a CMOS image sensor of a column AD type.

[0048] FIG. 3 is an example of a circuit diagram of the pixel 200 according to the first embodiment.

[0049] In this embodiment, each pixel 200 in the pixel array unit 20 includes a photoelectric conversion unit PD, a transfer transistor TRG, a floating diffusion FD, a connection transistor FDG, a reset transistor RST, a switching transistor S1, a capacitance C1, a switching transistor S2, a capacitance C2, an amplification transistor AMP, and a selection transistor SEL. In this diagram, a node to which the switching transistor S1, the capacitance C1, the switching transistor S2, and the capacitance C2 are connected is called an In node, and the input side of this node is called an In side.

[0050] The power supplies VDD shown below may have different voltage values. Each power supply VDD may be supplied from the same power supply or from a different power supply. The potential of the power supply VDD is an example of a first reference potential, and the potential of GND is an example of a second reference potential. These potentials are merely examples. The second reference potential may be a potential other than GND to ensure the withstand voltage of the capacitors C1 and C2. Furthermore, the relationship between the potential levels of the first reference potential and the second reference potential may be reversed. In other words, the first reference potential may be on the low potential side, and the second reference potential may be on the high potential side.

[0051] In this example, each pixel 200 is a LOFIC pixel, and electric charge overflowing from the floating diffusion FD is stored in a capacitor C1 or a capacitor C2. The capacitors C1 and C2 are high-density capacitors and can be made of, for example, MIM (Metal Insulator Metal).

[0052] The photoelectric conversion unit PD receives incident light, performs photoelectric conversion, and accumulates the resulting electric charge. When a drive signal TRG supplied to the source of the transfer transistor TRG goes high and the transfer transistor TRG is turned on, the electric charge accumulated in the photoelectric conversion unit PD is transferred to the floating diffusion FD via the transfer transistor TRG. The cathode of the photoelectric conversion unit PD is connected to either the source or drain of the transfer transistor TRG.

[0053] The floating diffusion FD temporarily holds the charge transferred from the photoelectric conversion unit SP by the transfer transistor TRG. The floating diffusion FD is formed at the connection point between the other of the source or drain of the transfer transistor TRG and the gate of the amplification transistor AMP.

[0054] The amplification transistor AMP outputs a pixel signal corresponding to the potential of the floating diffusion FD. That is, the amplification transistor AMP forms a source follower circuit together with a load MOS (not shown) serving as a constant current source, and a pixel signal indicating a level corresponding to the charges held in the floating diffusion FD, capacitors C1 and C2 is output from the amplification transistor AMP to the AD conversion unit 13 via the selection transistor SEL. One of the source or drain of the amplification transistor AMP is connected to one of the source or drain of the selection transistor SEL, and the other of the source or drain is connected to the power supply VDD.

[0055] The selection transistor SEL is turned on when the pixel 200 is selected by the selection signal SEL, and outputs a pixel signal of the pixel 200 to the AD conversion unit 13 via a vertical signal line. One of the source or drain of the selection transistor SEL is connected to one of the source or drain of the amplification transistor AMP, the other of the source or drain is connected to the AD conversion unit 13 via a vertical signal line, and the gate is connected to the vertical drive unit 12 via a pixel drive line.

[0056] The connection transistor FDG connects the floating diffusion FD to the switching transistor S1 or the switching transistor S2. One of the drain or source of the connection transistor FDG is connected to the floating diffusion FD, the other of the drain or source is connected to the switching transistor S1, the switching transistor S2, and the reset transistor RST, and the gate is connected to the vertical drive unit 12 via a pixel drive line.

[0057] The capacitor C1 stores the charge received from the floating diffusion FD when the connection transistor FDG is turned on by the control signal FDG and the switching transistor S1 is turned on by the control signal S1. In this embodiment, the switching transistor S1 is arranged on a higher potential side than the capacitor C1. The switching transistor S1 is an example of a first switching transistor, and the capacitor C1 is an example of a first capacitor.

[0058] The capacitor C2 stores the charge received from the floating diffusion FD when the connection transistor FDG is turned on by the control signal FDG and the switching transistor S2 is turned on by the control signal S2. In this embodiment, the switching transistor S2 is arranged on a higher potential side than the capacitor C2. The switching transistor S2 is an example of a second switching transistor, and the capacitor C2 is an example of a second capacitor.

[0059] When the reset transistor RST is turned on by a reset signal RST, the charges held in the floating diffusion FD, the capacitors C1 and C2 are discharged to the power supply VDD, thereby resetting the charges in the floating diffusion FD, the capacitors C1 and C2. One of the source or drain of the reset transistor RST is connected to the power supply VDD, the other of the source or drain is connected to the connection transistor FDG, the source or drain of the switching transistor S1 and the source or drain of the switching transistor S2, and the gate is connected to the vertical drive unit 12 via a pixel drive line.

[0060] In this embodiment, by connecting either one of the capacitors C1 and C2 to the circuit in addition to the floating diffusion FD, when a large signal charge flows in from the photoelectric conversion unit PD, it can be stored in these capacitors, and the dynamic range is not limited.

[0061] Furthermore, even after charging and discharging the capacitor C1 or C2, a certain amount of charge accumulates in the capacitor C1 or C2 due to a rebound charge from GND due to dielectric absorption. If either the capacitor C1 or the capacitor C2 is connected to the circuit for consecutive vertical periods, the influence of these charges may appear as an afterimage in the image. Therefore, in this embodiment, the capacitors C1 and C2 are alternately connected to the circuit during each vertical period to provide a discharge period for the rebound charge.

[0062] In the following examples, the vertical period is also referred to as a frame. For example, in the case of a solid-state imaging device 10 that captures 60 frames per second, the duration of one frame is 1 / 60 seconds. Because the capacitors C1 and C2 are provided with a sufficient period during one frame to be disconnected from the circuit and discharge their charge, the amount of charge accumulated due to dielectric absorption can be reduced when they are next connected to the circuit. In the following examples, an example is described in which the capacitors C1 and C2 are alternately connected to the circuit for each frame. However, the period during which each capacitor is alternately connected to the circuit is not limited to a frame-by-frame basis, and may be any period long enough to sufficiently discharge the capacitor C1 or the capacitor C2. For example, discharge periods for the capacitors C1 and C2 may be provided within one frame. The discharge period for the capacitor C1 is also referred to as the first timing, which serves as a reference, and the discharge period for the capacitor C2, which is different from the first timing, is also referred to as the second timing. For example, if the first timing is included in the first frame, the second timing is included in the second frame, which is the frame following the first frame.

[0063] FIG. 4 is an example of a timing chart of each element in odd-numbered frames and even-numbered frames in the first embodiment.

[0064] This timing chart shows the charge / discharge states of capacitors C1 and C2 in addition to the potential on the In side and the operating states of switching transistors S1 and S2. In an even-numbered frame, which is an example of a first frame, capacitor C2 is connected to the circuit to store and use the charge overflowing from the floating diffusion FD. During this period, capacitor C1 discharges the charge generated by dielectric absorption. In an odd-numbered frame, which is an example of a second frame, capacitor C1 is connected to the circuit to store and use the charge overflowing from the floating diffusion FD. During this period, capacitor C2 discharges the charge generated by dielectric absorption. In the following example, the operation during the period from time T1 to T3 is similar to that during the period from time T5 to T7, so the period from time T1 to T3 will be described. Furthermore, the operation during the period from time T3 to T5 is similar to that during the period from time T7 to T9, so the period from time T3 to T5 will be described. The first frame may be an odd-numbered frame. In this case, the second frame is an even-numbered frame.

[0065] First, the operation of the even-numbered frames will be described. The period from T1 to T2 indicates the reset period. By turning on the reset transistor RST, a reset potential is input to the In side, and the potential on the In side becomes the reset level. During this period, the switching transistors S1 and S2 are turned on. This causes charge to be discharged from the capacitors C1 and C2, temporarily setting the potential to the reset level. The period from T2 to T3 indicates the discharge period of the capacitor C1 and the use period of the capacitor C2. During this period, a pixel signal is input to the In node. By turning off the switching transistor S1, the capacitor C1 is disconnected from the circuit, allowing the capacitor C1 to fully discharge the charge generated by dielectric absorption. During this period, by continuing to turn on the switching transistor S2, the capacitor C2 is connected to the circuit and stores the charge overflowing from the floating diffusion FD.

[0066] Next, the operation of odd-numbered frames will be described. Times T3 to T4 represent the reset period, during which the reset transistor RST is turned on, causing the potential on the In side to reach the reset level. Also, during this period, the switching transistors S1 and S2 are turned on. This causes charge to be discharged from the capacitors C1 and C2, temporarily bringing the potential to the reset level. Times T4 to T5 represent the use period of capacitor C1 and the discharge period of capacitor C2. During this period, the switching transistor S1 remains on, connecting capacitor C1 to the circuit and storing charge overflowing from the floating diffusion FD. Also during this period, the switching transistor S2 is turned off, disconnecting capacitor C2 from the circuit and allowing capacitor C2 to fully discharge the charge generated by dielectric absorption.

[0067] The connections of the switching transistors in the even and odd frames are merely an example, and for example, the connections may be reversed between the odd and even frames.

[0068] FIG. 5 is a diagram illustrating dielectric absorption.

[0069] The charging period of the capacitor C7, the discharging period of the capacitor C7, and the period during which dielectric absorption occurs will be described using the circuit shown in Fig. 5A and the relationship between potential and time shown in Fig. 5B. Note that the description will be given assuming that the potential of the power supply Vref is higher than the potential Vcut.

[0070] 5A, dielectric absorption will be described using a circuit 1000 including a switch 1010, a switch 1020, and a capacitor C7. In this circuit 1000, when switch 1010 is turned on, charge is stored in capacitor C7 from a power supply Vref. In addition, in this circuit 1000, when switch 1020 is turned on, the charge stored in capacitor C7 is discharged to GND.

[0071] In FIG. 5B, times T21 to T22 indicate a charging period. During this period, switch 1010 of circuit 1000 is turned on, connecting power supply Vref to circuit 1000, and storing charge in capacitor C7. Times T22 to T23 indicate a discharging period. During this period, switch 1010 of circuit 1000 is turned off, and switch 1020 is turned on. By turning switch 1020 on, GND is connected to circuit 1000, and the charge stored in capacitor C7 is discharged. After a sufficient period has passed, the charge stored in capacitor C7 becomes zero.

[0072] The period from time T23 to time T24 indicates the period during which dielectric absorption occurs. During this period, the charge discharged to GND rebounds to the circuit 1000, and charge is again stored in the capacitor C7. The charging period and the period during which dielectric absorption occurs have a roughly linear relationship, and the longer the charging period, the longer the period during which dielectric absorption occurs. If dielectric absorption occurs in this way and this charge is not discharged in the pixel 200, it may appear in the image as an afterimage.

[0073] FIG. 6 is an example of a circuit diagram of a pixel 200 in a comparative example of the first embodiment.

[0074] In the comparative example, each pixel of the pixel array unit 20 includes a photoelectric conversion unit PD, a transfer transistor TRG, a floating diffusion FD, a connection transistor FDG, a reset transistor RST, a capacitor C7, an amplification transistor AMP, and a selection transistor SEL.

[0075] In the comparative example, each pixel 200 is a LOFIC pixel, and the charge overflowing from the floating diffusion FD is stored in a capacitor C7. The capacitor C7 is a high-density capacitor, and can be, for example, an MIM.

[0076] In the comparative example, after charge is stored and discharged in the capacitor C7, the charge rebounds from GND and is stored again in the capacitor C7. In the comparative example, since the capacitors C1 and C2 cannot be used separately as in the present embodiment, the charge stored in the capacitor C7 appears as an afterimage when pixel signals are read out.

[0077] FIG. 7 is a diagram illustrating how an image of a subject 3 is captured using the imaging device 2. As shown in FIG.

[0078] 7 shows an example in which the imaging device 2 continuously captures images of a subject 3 moving at high speed. The subject 3 in one frame is shown as subject 3, and the subject 3 after movement in the next frame is shown as subject 3'.

[0079] FIG. 8 is a diagram comparing an ideal image with an image in which image retention occurs due to dielectric absorption.

[0080] FIG. 8A shows an example of an image captured by an imaging device 2 having a pixel 200 including an ideal capacitance, i.e., a capacitance C7 where no dielectric absorption occurs, and FIG. 8B shows an example of an image captured by an imaging device 2 having a pixel 200 including a real capacitance, i.e., a capacitance C7 where dielectric absorption occurs.

[0081] In Fig. 8A, when dielectric absorption does not occur in the capacitor C7, no residual image of the previous frame occurs in a certain frame even when continuous imaging is performed. On the other hand, in Fig. 8B, when dielectric absorption occurs in the capacitor C7, residual image of the previous frame occurs in the image when continuous imaging is performed.

[0082] In this embodiment, the image capture device 2 selectively connects the capacitors C1 and C2 to the circuit for each frame, so that even if charge is generated in the capacitors C1 or C2 due to dielectric absorption, there is sufficient time for the capacitors to discharge. As a result, the captured image reduces the residual image of the previous frame and becomes closer to the ideal image, as shown in FIG. 8A .

[0083] FIG. 9 is an example of a circuit diagram of a pixel 200 according to a modification of the first embodiment.

[0084] In this modified example, the pixel 200 includes a photoelectric conversion unit PD, a transfer transistor TRG, a floating diffusion FD, a reset transistor RST, a discharge transistor OFG, a current source ID1, a switching transistor S5, a capacitance C5, a switching transistor S1, a switching transistor S2, a capacitance C1, a capacitance C2, an amplification transistor AMP, and a selection transistor SEL.

[0085] In this modification, each pixel 200 is a VDGS pixel, and the charge generated when reading out the pixel signal level (also referred to as the D phase) is stored in a capacitor C1 or a capacitor C2. The capacitors C1 and C2 are high-density capacitors, and may be MIM capacitors, for example. The following mainly describes the differences from the above-described embodiment.

[0086] The capacitor C5 is connected to the switching transistor S5. When the switching transistor S5 is turned on by the control signal S5, the capacitor C5 stores a charge corresponding to the pixel reset level (also referred to as the P phase). The capacitor C5 is an example of a fifth capacitor, and the switching transistor S5 is an example of a fifth switching transistor.

[0087] In the VDGS pixel, CDS (Correlated Double Sampling) is performed under the control of the control unit 15, and the P phase and D phase are read out in this order. In the readout, a signal obtained when the floating diffusion FD is initialized is read out as the P phase, and a signal obtained when charge is transferred from the photoelectric conversion unit PD to the floating diffusion FD is read out as the D phase.

[0088] The D phase depends on the charge amount of the photoelectric conversion unit PD, so its value varies from frame to frame and is affected by dielectric absorption, whereas the P phase is a reset level, so it does not depend on the imaging scene, has the same value for every frame, and is not affected by dielectric absorption.

[0089] Furthermore, the P-phase charge is stored in the capacitor C5, and the D-phase charge is stored in the capacitor C1 or C2. As in the above-described embodiment, the D-phase charge is stored alternately in the capacitors C1 and C2 for each frame.

[0090] The drain transistor OFG has a gate electrode connected to the drain of the transfer transistor TRG and the source of the reset transistor RST, one of its source or drain connected to the power supply VDD, and the other connected to one of the sources or drains of the switching transistors S1, S2, and S5. The other of its source or drain is connected to a current source ID1. The drain transistor OFG drains the charges of the capacitors C1, C2, and C5 in response to a control signal ODG.

[0091] When reading out the D phase, electric charge is stored in the capacitor C1 or C2 due to dielectric absorption, but by connecting these capacitors to the circuit alternately for each frame, pixel 200 can sufficiently discharge the stored electric charge and suppress afterimages.

[0092] FIG. 10 is an example of a circuit diagram of a pixel 200 in another comparative example of the first embodiment.

[0093] In this comparative example, each pixel of the pixel array section 20 includes a photoelectric conversion section PD, a transfer transistor TRG, a floating diffusion FD, a reset transistor RST, a discharge transistor OFG, a current source ID1, a switching transistor S5, a capacitance C5, a switching transistor S6, a capacitance C6, an amplification transistor AMP, and a selection transistor SEL.

[0094] Each pixel 200 in this comparative example is a VDGS pixel, and stores charge during D-phase readout in a capacitor C6. The capacitor C6 is a high-density capacitor, and can be, for example, an MIM. The following mainly describes the differences from the above-described embodiment.

[0095] As described above, in this comparative example, the pixel 200 stores charge in the capacitor C6 during readout of the D phase and resets this charge at a predetermined timing. If the solid-state imaging device 10 uses the capacitor C6 continuously during imaging, an afterimage may appear due to charge generated by dielectric absorption.

[0096] According to this embodiment, the solid-state imaging device 10 includes capacitors C1 and C2 in the circuit of the pixel 200 to store charge overflowing from the floating diffusion FD. The capacitors C1 and C2 are alternately connected to the circuit in each frame, allowing sufficient time for the charge generated by dielectric absorption to be discharged. This allows the solid-state imaging device 10 to suppress the occurrence of afterimages even when capturing images continuously.

[0097] Furthermore, according to this embodiment, the solid-state imaging device 10 alternately uses the capacitors C1 and C2 for each frame to discharge the charge generated by dielectric absorption, eliminating the need to calculate and correct the amount of residual image, and therefore eliminating the need for a large-capacity frame buffer, making it suitable for miniaturizing circuits.

[0098] Furthermore, when calculating and correcting the amount of residual image, if the pixel value of the pixel 200 in the frame before the reference frame is saturated (also called full code), the amount of residual image cannot be calculated correctly. In particular, if the solid-state imaging device 10 has a high analog gain, the pixel output value is likely to become full code. On the other hand, the solid-state imaging device 10 according to this embodiment does not require calculation of the amount of residual image, so such a problem does not occur.

[0099] Second Embodiment FIG. 11 is an example of a circuit diagram of a pixel 200 according to a second embodiment.

[0100] In this embodiment, each pixel 200 of the pixel array unit 20 includes a photoelectric conversion unit PD, a transfer transistor TRG, a floating diffusion FD, a connection transistor FDG, a reset transistor RST, a switching transistor S1, a capacitance C1, a switching transistor S2, a capacitance C2, an amplification transistor AMP, and a selection transistor SEL. The following mainly describes the parts that are different from the first embodiment.

[0101] Compared with the first embodiment, each pixel 200 in this embodiment differs in the connections of the switching transistor S1, the capacitor C1, the switching transistor S2, and the capacitor C2.

[0102] In this embodiment, unlike the example of FIG. 3, the switching transistors S1 and S2 are provided on the lower potential side, that is, on the GND side, of the capacitors C1 and C2, respectively.

[0103] When a transistor disposed in pixel 200 is turned on, a leakage current may flow and appear as fixed pattern noise (FPN) in an image. In this example, even if a leakage current occurs when switching transistor S1 or S2 is turned on, in order to prevent charge from being stored in capacitor C1 or C2 due to this current, switching transistor S1 is disposed on the lower potential side of capacitor C1, and switching transistor S2 is disposed on the lower potential side of capacitor C2.

[0104] FIG. 12 is an example of a circuit diagram of a pixel 200 according to a modification of the second embodiment.

[0105] In this modified example, the pixel 200 includes a photoelectric conversion unit PD, a transfer transistor TRG, a floating diffusion FD, a reset transistor RST, a discharge transistor OFG, a current source ID1, a switching transistor S5, a capacitance C5, a switching transistor S1, a switching transistor S2, a capacitance C1, a capacitance C2, an amplification transistor AMP, and a selection transistor SEL.

[0106] Compared with the modification of the first embodiment, each pixel 200 in this modification differs in the connections of the switching transistor S1, the capacitor C1, the switching transistor S2, and the capacitor C2.

[0107] In this embodiment, unlike the example of FIG. 3, the switching transistors S1 and S2 are provided on the lower potential side, that is, on the GND side, of the capacitors C1 and C2, respectively, at the In node.

[0108] As described above, even if a leakage current occurs when the switching transistor S1 or S2 is turned on, by placing these transistors on the low potential side, it is possible to prevent charge from being stored in the capacitor C1 or C2 due to the leakage current.

[0109] According to this embodiment, the switching transistors S1 and S2 are provided on the lower potential side, i.e., on the GND side, of the capacitors C1 and C2, respectively, at the In node, and even if a leakage current occurs when the switching transistor S1 or S2 is turned on, the leakage current does not flow into the capacitor C1 or C2, and no charge is stored therein. This allows the solid-state imaging device 10 to prevent fixed pattern noise from occurring in images.

[0110] Third Embodiment FIG. 13 is a diagram illustrating the configuration and operation of a part of the circuit of a pixel 200 according to a third embodiment.

[0111] FIG. 13A is a diagram showing the configuration of a part of the circuit of a pixel 200 in the third embodiment, and FIG. 13B is a diagram for explaining the operating state of each switch transistor in the third embodiment.

[0112] In the above-described embodiment, the pixel 200 is configured to include the capacitor C1, the capacitor C2, the switching transistor S1, and the switching transistor S2, but in this embodiment, the pixel 200 is configured to include switching transistors S1, S2, S3, and S4 and the capacitors C1 and C2 instead of these elements, and the connections are different, as shown in Fig. 13A. Furthermore, the capacitors C1 and C2 have the same capacitance value so that the charges due to dielectric absorption cancel each other out.

[0113] 13A, the capacitor C1 is always connected to the circuit. In the pixel 200, the In node is connected between the connection transistor FDG and the reset transistor RST. In addition, in a certain frame, one side of the capacitor C2 is connected to the In side, i.e., the high potential side, via the switching transistor S1, and the other side is connected to GND, which serves as the reference potential, i.e., the low potential side, via the switching transistor S2. In the next frame, one side of the capacitor C2 is connected to GND, which serves as the reference potential, i.e., the low potential side, via the switching transistor S4, and the other side is connected to the In side, i.e., the high potential side, via the switching transistor S3. In other words, the connection destination of the capacitor C2 changes between one frame and the next frame, and the polarity is reversed.

[0114] 13B shows the operating states of the switching transistors S1 to S4. In this example, the pixel 200 turns on the switching transistors S1 and S2 in even frames, and turns on the switching transistors S3 and S4 in odd frames.

[0115] In even frames, one end of capacitor C2 is connected to the In side via switching transistor S1, and the other end is connected to GND via switching transistor S2. In odd frames, one end of capacitor C2 is connected to GND via switching transistor S4, and the other end is connected to the In side via switching transistor S3. The connections between even and odd frames are merely examples, and the connections of capacitor C2 in odd and even frames may be reversed, for example.

[0116] FIG. 14 is a circuit diagram of a pixel 200 according to the third embodiment.

[0117] In this embodiment, each pixel 200 of the pixel array section 20 includes a photoelectric conversion section PD, a transfer transistor TRG, a floating diffusion FD, a connection transistor FDG, a reset transistor RST, a switching transistor S1, a switching transistor S2, a switching transistor S3, a capacitance C1, and a capacitance C2.

[0118] In this circuit diagram, the reset transistor RST plays the role of the above-mentioned switching transistor S4.

[0119] In odd-numbered and even-numbered frames, the polarity of the capacitance C2 can be reversed for each frame by connecting the switching transistors S1 to S4 as shown in Fig. 13B. This makes the polarity of the capacitance C2 opposite to the polarity caused by the charge generated in the capacitance C1 by dielectric absorption, allowing the charges to cancel each other out.

[0120] FIG. 15 is a diagram illustrating the connection of the capacitor C2 in the third embodiment.

[0121] In this figure, elements connected to the circuit are shown with solid lines, and elements not connected to the circuit are shown with dashed lines.

[0122] In even-numbered frames, the switching transistors S1 and S2 are turned on, and one end of the capacitor C2 is connected to the high-potential side In and the other end is connected to the low-potential side GND. At this time, the In side is the positive side of the capacitor C2, and the GND side is the negative side of the capacitor C2. Also, at this time, the switching transistor S3 and the reset transistor RST are turned off. In odd-numbered frames, the switching transistor S3 and the reset transistor RST are turned on, and one end of the capacitor C2 is connected to the high-potential side In and the other end is connected to the low-potential side power supply VDD. At this time, the switching transistors S1 and S2 are turned off.

[0123] FIG. 16 is a diagram showing the relationship between pixel potential and time in the third embodiment.

[0124] This diagram shows the relationship between the potential on the In side, the potential of the capacitance C1, and the potential of the capacitance C2 in the pixel 200. The thick solid line indicates the potential on the In side, the thin solid line indicates the potential of the capacitance C1, and the dashed line indicates the potential of the capacitance C2.

[0125] The time period from time T31 to time T32 indicates the potential of the In side in the frame preceding the reference frame, etc. In this example, the signal potential in the frame preceding the reference frame is high, indicating that the signal is large.

[0126] The time period from time T32 to time T33 indicates the potential of the In side in the reference frame. In this example, the signal potential on the In side in the reference frame is small, indicating that the signal is small. At this time, charge accumulates in capacitor C1 after reset due to dielectric absorption. At this time, charge also accumulates in capacitor C2 after reset due to dielectric absorption, but if the polarity is reversed, charge accumulates in capacitor C2 so as to cancel out the charge.

[0127] FIG. 17 is a circuit diagram of a pixel 200 according to a modification of the third embodiment.

[0128] In this modified example, each pixel 200 of the pixel array section 20 includes a photoelectric conversion section PD, a transfer transistor TRG, a floating diffusion FD, a reset transistor RST, a discharge transistor OFG, a current source ID1, a switching transistor S5, a capacitance C5, a switching transistor S1, a switching transistor S2, a switching transistor S3, a switching transistor S4, a capacitance C1, a capacitance C2, an amplification transistor AMP, and a selection transistor SEL.

[0129] In this modification, each pixel 200 is a VDGS pixel, and the charge generated during D-phase readout is stored in capacitors C1 and C2. Capacitors C1 and C2 are high-density capacitors, and may be MIM, for example. The following mainly describes the differences from the above-described embodiment.

[0130] The capacitor C5 stores a charge corresponding to the P phase when the switching transistor S5 is turned on by the control signal S5.

[0131] In the VDGS pixel, CDS is performed under the control of the control unit 15, and P-phase and D-phase readout are performed in this order. In the P-phase readout, a signal obtained when the floating diffusion FD is initialized is read out as the P-phase, and a signal obtained when charge is transferred from the photoelectric conversion unit PD to the floating diffusion FD is read out as the D-phase.

[0132] The charge of the P phase is stored in the capacitor C5, and the charge of the D phase is stored in the capacitors C1 and C2.

[0133] According to this embodiment, the solid-state imaging device 10 changes the connection destination of the capacitor C2 for each frame, thereby inverting the polarity. This allows the solid-state imaging device 10 to cancel the charge stored in the capacitor C1 through dielectric absorption. Furthermore, the solid-state imaging device 10 can simultaneously connect the capacitors C1 and C2 to the circuit, allowing both capacitors to be used effectively.

[0134] <<1. Configuration Example of Vehicle Control System>> FIG. 18 is a block diagram showing a configuration example of a vehicle control system 11, which is an example of a mobility device control system to which the present technology is applied.

[0135] The vehicle control system 11 is provided in the vehicle 1 and performs processing related to automated driving of the vehicle 1. This automated driving includes automated driving of levels 1 to 5, and remote driving and remote assistance of the vehicle 1 by a remote driver.

[0136] The vehicle control system 11 includes a vehicle control ECU (Electronic Control Unit) 21, a communication unit 22, a map information storage unit 23, a location information acquisition unit 24, an external recognition sensor 25, an in-vehicle sensor 26, a vehicle sensor 27, a memory unit 28, a driving automation control unit 29, a DMS (Driver Monitoring System) 30, an HMI (Human Machine Interface) 31, and a vehicle control unit 32.

[0137] The vehicle control ECU 21, communication unit 22, map information storage unit 23, position information acquisition unit 24, external recognition sensor 25, in-vehicle sensor 26, vehicle sensor 27, memory unit 28, driving automation control unit 29, DMS 30, HMI 31, and vehicle control unit 32 are connected to each other so as to be able to communicate with each other via a communication network 41. The communication network 41 is configured, for example, by an in-vehicle communication network or bus conforming to a digital two-way communication standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), FlexRay (registered trademark), or Ethernet (registered trademark). Different communication networks 41 may be used depending on the type of data being transmitted. For example, CAN may be used for data related to vehicle control, and Ethernet may be used for large-volume data. In addition, each part of the vehicle control system 11 may be directly connected without going through the communication network 41, using wireless communication intended for communication over relatively short distances, such as near field communication (NFC) or Bluetooth (registered trademark).

[0138] In the following description, when each unit of the vehicle control system 11 communicates via the communication network 41, the description of the communication network 41 will be omitted. For example, when the vehicle control ECU 21 and the communication unit 22 communicate via the communication network 41, it will simply be described that the vehicle control ECU 21 and the communication unit 22 communicate with each other.

[0139] The vehicle control ECU 21 is configured with various processors such as a CPU (Central Processing Unit), an MPU (Micro Processing Unit), etc. The vehicle control ECU 21 controls the entire or part of the functions of the vehicle control system 11.

[0140] The communication unit 22 communicates with various devices inside and outside the vehicle, other vehicles, servers, base stations, etc., and transmits and receives various data. At this time, the communication unit 22 can perform communication using a plurality of communication methods.

[0141] The following provides an overview of communication with the outside of the vehicle that can be performed by the communication unit 22. The communication unit 22 communicates with a server (hereinafter referred to as an external server) or the like on an external network via a base station or an access point using a wireless communication method such as 5G (fifth generation mobile communication system), LTE (Long Term Evolution), or DSRC (Dedicated Short Range Communications). The external network with which the communication unit 22 communicates is, for example, the Internet, a cloud network, or a network specific to a carrier. The communication method used by the communication unit 22 with the external network is not particularly limited as long as it is a wireless communication method that enables digital two-way communication at a communication speed equal to or higher than a predetermined distance.

[0142] Furthermore, for example, the communication unit 22 can communicate with a terminal located near the vehicle using P2P (Peer to Peer) technology. The terminal located near the vehicle can be, for example, a terminal worn by a mobile object moving at a relatively slow speed, such as a pedestrian or a bicycle, a terminal installed at a fixed location in a store, or an MTC (Machine Type Communication) terminal. Furthermore, the communication unit 22 can also perform V2X communication. V2X communication refers to communication between the vehicle and others, such as vehicle-to-vehicle communication with another vehicle, vehicle-to-infrastructure communication with a roadside unit, vehicle-to-home communication, and vehicle-to-pedestrian communication with a terminal carried by a pedestrian.

[0143] The communication unit 22 can receive, for example, a program for updating software that controls the operation of the vehicle control system 11 from the outside (over the air). The communication unit 22 can also receive map information, traffic information, information about the surroundings of the vehicle 1, and the like from the outside. For example, the communication unit 22 can also transmit information about the vehicle 1 and information about the surroundings of the vehicle 1 to the outside. Information about the vehicle 1 that the communication unit 22 transmits to the outside includes, for example, data indicating the state of the vehicle 1 and the recognition result by the recognition unit 73. Furthermore, for example, the communication unit 22 performs communication corresponding to a vehicle emergency notification system such as e-call.

[0144] For example, the communication unit 22 receives electromagnetic waves transmitted by a road traffic information and communication system (VICS (Vehicle Information and Communication System) (registered trademark)) such as a radio beacon, an optical beacon, or FM multiplex broadcasting.

[0145] The following provides an overview of communication with the vehicle interior that can be performed by the communication unit 22. The communication unit 22 can communicate with each device in the vehicle using, for example, wireless communication. The communication unit 22 can communicate with each device in the vehicle using a communication method that enables bidirectional digital communication at a predetermined communication speed or higher via wireless communication, such as wireless LAN, Bluetooth, NFC, or Wireless USB (WUSB). The communication unit 22 can also communicate with each device in the vehicle using wired communication. For example, the communication unit 22 can communicate with each device in the vehicle using wired communication via a cable connected to a connection terminal (not shown). The communication unit 22 can communicate with each device in the vehicle using a communication method that enables bidirectional digital communication at a predetermined communication speed or higher via wired communication, such as Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI) (registered trademark), or Mobile High-Definition Link (MHL).

[0146] Here, the in-vehicle device refers to, for example, a device in the vehicle that is not connected to the communication network 41. Possible in-vehicle devices include, for example, a mobile device or wearable device carried by a user in the vehicle, such as a driver, and an information device brought into the vehicle and temporarily installed therein.

[0147] The map information storage unit 23 stores one or both of a map acquired from an external source and a map created by the vehicle 1. For example, the map information storage unit 23 stores a three-dimensional high-precision map, a global map that is less accurate than a high-precision map and covers a wide area, and the like.

[0148] Examples of high-precision maps include dynamic maps, point cloud maps, and vector maps. A dynamic map is a map consisting of four layers of dynamic information, quasi-dynamic information, quasi-static information, and static information, and is provided to the vehicle 1 from an external server or the like. A point cloud map is a map made up of a point cloud (point cloud data). A vector map is a map adapted to automated driving by associating traffic information such as the positions of lanes and traffic lights with the point cloud map.

[0149] The point cloud map and the vector map may be provided, for example, from an external server or the like, or may be created in the vehicle 1 based on sensing results from the camera 51, radar 52, LiDAR 53, etc. as a map for matching with a local map described later, and stored in the map information storage unit 23. Furthermore, when a high-precision map is provided from an external server or the like, map data of, for example, an area of ​​several hundred square meters relating to the planned route along which the vehicle 1 will travel is acquired from the external server or the like in order to reduce communication capacity.

[0150] The location information acquisition unit 24 receives GNSS (Global Navigation Satellite System) signals from GNSS satellites and acquires location information of the vehicle 1. The acquired location information is supplied to the driving automation control unit 29. Note that the method used by the location information acquisition unit 24 is not limited to using GNSS signals, and it may also acquire location information using a beacon, for example.

[0151] The external recognition sensor 25 includes various sensors used to recognize the situation outside the vehicle 1, and supplies sensor data from each sensor to each part of the vehicle control system 11. The type and number of sensors included in the external recognition sensor 25 are arbitrary.

[0152] For example, the external recognition sensor 25 includes a camera 51, a radar 52, a LiDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) 53, and an ultrasonic sensor 54. Without being limited to this, the external recognition sensor 25 may be configured to include one or more types of sensors selected from the camera 51, the radar 52, the LiDAR 53, and the ultrasonic sensor 54. The number of cameras 51, radars 52, LiDARs 53, and ultrasonic sensors 54 is not particularly limited as long as the number is a number that can be realistically installed on the vehicle 1. Furthermore, the types of sensors included in the external recognition sensor 25 are not limited to this example, and the external recognition sensor 25 may include other types of sensors. Examples of sensing areas of each sensor included in the external recognition sensor 25 will be described later.

[0153] The imaging method of the camera 51 is not particularly limited. For example, cameras of various imaging methods capable of distance measurement, such as a time-of-flight camera, a stereo camera, a monocular camera, or an infrared camera, can be applied to the camera 51 as needed. However, the camera 51 may simply acquire an image without distance measurement.

[0154] Furthermore, for example, the external recognition sensor 25 may include an environmental sensor for detecting the environment for the vehicle 1. The environmental sensor is a sensor for detecting the environment such as weather, climate, brightness, etc., and may include various sensors such as a raindrop sensor, a fog sensor, a sunlight sensor, a snow sensor, and an illuminance sensor.

[0155] Furthermore, for example, the external recognition sensor 25 includes a microphone used to detect sounds around the vehicle 1 and the location of sound sources.

[0156] The interior sensor 26 includes various sensors for detecting information inside the vehicle, and supplies sensor data from each sensor to each unit of the vehicle control system 11. The types and number of the various sensors included in the interior sensor 26 are not particularly limited as long as they are of types and numbers that can be realistically installed in the vehicle 1.

[0157] For example, the interior sensor 26 may include one or more types of sensors selected from the group consisting of a camera, radar, a seating sensor, a steering wheel sensor, a microphone, and a biometric sensor. The camera included in the interior sensor 26 may be a camera using any of various imaging methods capable of measuring distances, such as a Time of Flight (ToF) camera, a stereo camera, a monocular camera, or an infrared camera. The camera included in the interior sensor 26 may also be a camera simply for acquiring captured images, regardless of distance measurement. The biometric sensor included in the interior sensor 26 may be provided, for example, on a seat, a steering wheel, or the like, and detect various types of biometric information of the user.

[0158] The vehicle sensor 27 includes various sensors for detecting the state of the vehicle 1, and supplies sensor data from each sensor to each unit of the vehicle control system 11. The types and number of the various sensors included in the vehicle sensor 27 are not particularly limited as long as they are of types and numbers that can be realistically installed on the vehicle 1.

[0159] For example, the vehicle sensor 27 includes a speed sensor, an acceleration sensor, an angular velocity sensor (gyro sensor), and an inertial measurement unit (IMU) that integrates these sensors. For example, the vehicle sensor 27 includes a steering angle sensor that detects the steering angle of the steering wheel, a yaw rate sensor, an accelerator sensor that detects the amount of accelerator pedal operation, and a brake sensor that detects the amount of brake pedal operation. For example, the vehicle sensor 27 includes a rotation sensor that detects the number of rotations of the engine or motor, an air pressure sensor that detects tire air pressure, a slip ratio sensor that detects tire slip ratio, and a wheel speed sensor that detects the rotation speed of the wheels. For example, the vehicle sensor 27 includes a battery sensor that detects the remaining battery charge and temperature, and an impact sensor that detects external impacts.

[0160] The storage unit 28 includes at least one of a non-volatile storage medium and a volatile storage medium, and stores data and programs. The storage unit 28 is used, for example, as an electrically erasable programmable read-only memory (EEPROM) and a random access memory (RAM). Examples of storage media that can be used include a magnetic storage device such as a hard disk drive (HDD), a semiconductor storage device, an optical storage device, and a magneto-optical storage device. The storage unit 28 stores various programs and data used by each component of the vehicle control system 11. For example, the storage unit 28 includes an event data recorder (EDR) and a data storage system for automated driving (DSSAD), and stores information about the vehicle 1 before and after an event such as an accident, and information acquired by the in-vehicle sensors 26.

[0161] The driving automation control unit 29 controls the driving automation function of the vehicle 1. For example, the driving automation control unit 29 includes an analysis unit 61, an action planning unit 62, and an operation control unit 63.

[0162] The analysis unit 61 performs an analysis process of the vehicle 1 and the surrounding situation. The analysis unit 61 includes a self-position estimation unit 71, a sensor fusion unit 72, and a recognition unit 73.

[0163] The self-position estimation unit 71 estimates the self-position of the vehicle 1 based on the sensor data from the external recognition sensor 25 and the high-precision map stored in the map information storage unit 23. For example, the self-position estimation unit 71 generates a local map based on the sensor data from the external recognition sensor 25 and matches the local map with the high-precision map to estimate the self-position of the vehicle 1. The position of the vehicle 1 is based on, for example, the center of the rear wheel pair axle.

[0164] The local map is, for example, a three-dimensional high-precision map or an occupancy grid map created using a technique such as SLAM (Simultaneous Localization and Mapping). The three-dimensional high-precision map is, for example, the point cloud map described above. The occupancy grid map is a map in which the three-dimensional or two-dimensional space around the vehicle 1 is divided into grids of a predetermined size and the occupancy status of objects is indicated on a grid-by-grid basis. The occupancy status of objects is indicated, for example, by the presence or absence of an object and its probability of existence. The local map is also used, for example, in the detection process and recognition process of the situation outside the vehicle 1 by the recognition unit 73.

[0165] The self-position estimation unit 71 may estimate the self-position of the vehicle 1 based on the position information acquired by the position information acquisition unit 24 and the sensor data from the vehicle sensor 27 .

[0166] The sensor fusion unit 72 performs sensor fusion processing to obtain information by combining multiple different types of sensor data (for example, image data supplied from the camera 51 and sensor data supplied from the radar 52). Methods for combining different types of sensor data include compounding, integration, fusion, and association.

[0167] The recognition unit 73 executes a detection process for detecting the situation outside the vehicle 1 and a recognition process for recognizing the situation outside the vehicle 1 .

[0168] For example, the recognition unit 73 performs detection processing and recognition processing of the situation outside the vehicle 1 based on information from the external recognition sensor 25, information from the self-position estimation unit 71, information from the sensor fusion unit 72, etc.

[0169] Specifically, for example, the recognition unit 73 performs detection processing and recognition processing of objects around the vehicle 1. The object detection processing is, for example, processing to detect the presence or absence, size, shape, position, movement, etc. of an object. The object recognition processing is, for example, processing to recognize attributes such as the type of object, or to identify a specific object. However, the detection processing and the recognition processing are not necessarily clearly separated, and may overlap.

[0170] For example, the recognition unit 73 detects objects around the vehicle 1 by performing clustering to classify a point cloud based on sensor data from the radar 52, the LiDAR 53, or the like into clusters of points. This allows the presence, size, shape, and position of objects around the vehicle 1 to be detected.

[0171] For example, the recognition unit 73 performs tracking to follow the movement of clusters of point clouds classified by clustering, thereby detecting the movement of objects around the vehicle 1. As a result, the speed and traveling direction (movement vector) of the objects around the vehicle 1 are detected.

[0172] For example, the recognition unit 73 detects or recognizes vehicles, people, bicycles, obstacles, structures, roads, traffic lights, traffic signs, road markings, etc. based on image data supplied from the camera 51. The recognition unit 73 may also recognize the types of objects around the vehicle 1 by performing recognition processing such as semantic segmentation.

[0173] For example, the recognition unit 73 can perform a recognition process of traffic rules around the vehicle 1 based on the map stored in the map information storage unit 23, the result of estimation of the self-position by the self-position estimation unit 71, and the result of recognition of objects around the vehicle 1 by the recognition unit 73. Through this process, the recognition unit 73 can recognize the positions and states of traffic lights, the contents of traffic signs and road markings, the contents of traffic regulations, and lanes that can be traveled, etc.

[0174] For example, the recognition unit 73 can perform a recognition process of the environment around the vehicle 1. The surrounding environment to be recognized by the recognition unit 73 may include weather, temperature, humidity, brightness, and road surface conditions.

[0175] The behavior planning unit 62 creates a behavior plan for the vehicle 1. For example, the behavior planning unit 62 creates the behavior plan by performing route planning and route tracking processing.

[0176] The route planning includes global path planning and local path planning. Global path planning includes a process of planning a rough route from a start to a goal. Local path planning, also called trajectory planning, includes a process of generating a trajectory that allows the vehicle 1 to proceed safely and smoothly in the vicinity of the vehicle 1 on the planned route, taking into account the motion characteristics of the vehicle 1.

[0177] Path following is a process of planning an operation for safely and accurately traveling along a route planned by a route plan within a planned time. The behavior planning unit 62 can, for example, calculate a target speed and a target angular velocity of the vehicle 1 based on the results of this path following process.

[0178] The operation control unit 63 controls the operation of the vehicle 1 in order to realize the action plan created by the action planning unit 62 .

[0179] For example, the operation control unit 63 controls a steering control unit 81, a brake control unit 82, and a drive control unit 83 included in a vehicle control unit 32 described later, to perform lateral vehicle motion control and longitudinal vehicle motion control so that the vehicle 1 travels along the trajectory calculated by the trajectory plan. For example, the operation control unit 63 performs control aimed at driver assistance functions such as collision avoidance or impact mitigation, following driving, vehicle speed maintenance driving, host vehicle collision warning, host vehicle lane departure warning, and driving automation such as driving without operation by the driver or a remote driver.

[0180] The DMS 30 performs processes such as authenticating the driver and recognizing the driver's state based on sensor data from the in-vehicle sensors 26 and input data input to the HMI 31 (described later). Examples of the driver's state to be recognized include physical condition, level of alertness, level of concentration, level of fatigue, line of sight, level of intoxication, driving operation, and posture.

[0181] The DMS 30 may be configured to perform authentication processing for users other than the driver and recognition processing for the status of the users. Furthermore, for example, the DMS 30 may be configured to perform recognition processing for the status inside the vehicle based on sensor data from the in-vehicle sensor 26. Examples of the status inside the vehicle that may be recognized include temperature, humidity, brightness, and odor.

[0182] The HMI 31 inputs various data and instructions and presents various data to the user.

[0183] The following provides an overview of data input via the HMI 31. The HMI 31 includes input devices for a person to input data. The HMI 31 generates input signals based on data, instructions, and the like input via the input devices and supplies the signals to each component of the vehicle control system 11. The HMI 31 includes, as input devices, controls such as a touch panel, buttons, switches, and levers. The HMI 31 may also include input devices that allow information to be input by voice, gestures, or other means other than manual operation. Furthermore, the HMI 31 may use, as input devices, externally connected devices such as a remote control device using infrared or radio waves, or a mobile or wearable device compatible with the operation of the vehicle control system 11.

[0184] The presentation of data by the HMI 31 will be briefly described. The HMI 31 generates visual information, auditory information, and tactile information for the user or the outside of the vehicle. The HMI 31 also performs output control, controlling the output, output content, output timing, output method, etc. of each piece of generated information. The HMI 31 generates and outputs, as visual information, information indicated by images or lights, such as an operation screen, a status display of the vehicle 1, a warning display, and a monitor image showing the situation around the vehicle 1. The HMI 31 also generates and outputs, as auditory information, information indicated by sounds, such as voice guidance, warning sounds, and warning messages. The HMI 31 also generates and outputs, as tactile information, information imparted to the user's sense of touch by, for example, force, vibration, movement, etc.

[0185] Examples of output devices that the HMI 31 uses to output visual information include a display device that displays an image on its own to present visual information and a projector device that projects an image to present visual information. The display device may be a device that displays visual information within the user's field of vision, such as a head-up display, a transmissive display, or a wearable device with an augmented reality (AR) function, in addition to a display device with a normal display. The HMI 31 may also use display devices included in a navigation system, an instrument panel, a camera monitoring system (CMS), an electronic mirror, a lamp, or the like provided in the vehicle 1 as output devices that output visual information.

[0186] As an output device for the HMI 31 to output auditory information, for example, an audio speaker, a headphone, or an earphone can be applied.

[0187] For example, a haptic element using haptic technology can be applied as an output device for outputting tactile information from the HMI 31. The haptic element is provided on a part that the user touches, such as a steering wheel or a seat.

[0188] The vehicle control unit 32 controls each part of the vehicle 1. The vehicle control unit 32 includes a steering control unit 81, a brake control unit 82, a drive control unit 83, a body system control unit 84, a light control unit 85, and a horn control unit 86.

[0189] The steering control unit 81 detects and controls the state of the steering system of the vehicle 1. The steering system includes, for example, a steering mechanism including a steering wheel, an electric power steering, etc. The steering control unit 81 includes, for example, a steering ECU that controls the steering system, an actuator that drives the steering system, etc.

[0190] The brake control unit 82 detects and controls the state of the brake system of the vehicle 1. The brake system includes, for example, a brake mechanism including a brake pedal, an antilock brake system (ABS), a regenerative brake mechanism, etc. The brake control unit 82 includes, for example, a brake ECU that controls the brake system, an actuator that drives the brake system, etc.

[0191] The drive control unit 83 detects and controls the state of the drive system of the vehicle 1. The drive system includes, for example, an accelerator pedal, a drive force generating device for generating drive force such as an internal combustion engine or a drive motor, and a drive force transmission mechanism for transmitting the drive force to the wheels. The drive control unit 83 includes, for example, a drive ECU for controlling the drive system, and an actuator for driving the drive system.

[0192] The body system control unit 84 detects and controls the states of the body system systems of the vehicle 1. The body system systems include, for example, a keyless entry system, a smart key system, a power window device, a power seat, an air conditioning system, an airbag, a seat belt, a shift lever, etc. The body system control unit 84 includes, for example, a body system ECU that controls the body system systems, an actuator that drives the body system systems, etc.

[0193] The light control unit 85 detects and controls the states of various lights of the vehicle 1. Examples of lights to be controlled include headlights, backlights, fog lights, turn signals, brake lights, projections, and bumper displays. The light control unit 85 includes a light ECU that controls the lights, an actuator that drives the lights, and the like.

[0194] The horn control unit 86 detects and controls the state of the car horn of the vehicle 1. The horn control unit 86 includes, for example, a horn ECU that controls the car horn, an actuator that drives the car horn, and the like.

[0195] Fig. 19 is a diagram showing an example of a sensing area by the camera 51, radar 52, LiDAR 53, ultrasonic sensor 54, etc. of the external recognition sensor 25 in Fig. 18. Note that Fig. 19 schematically shows the vehicle 1 as viewed from above, with the left end side being the front end (front) side of the vehicle 1 and the right end side being the rear end (rear) side of the vehicle 1.

[0196] Sensing area 101F and sensing area 101B show examples of sensing areas of the ultrasonic sensors 54. Sensing area 101F covers the periphery of the front end of the vehicle 1 with multiple ultrasonic sensors 54. Sensing area 101B covers the periphery of the rear end of the vehicle 1 with multiple ultrasonic sensors 54.

[0197] The sensing results in the sensing area 101F and the sensing area 101B are used, for example, for parking assistance for the vehicle 1.

[0198] Sensing area 102F to sensing area 102B show examples of sensing areas of a short-range or medium-range radar 52. Sensing area 102F covers a position farther in front of the vehicle 1 than sensing area 101F. Sensing area 102B covers a position farther behind the vehicle 1 than sensing area 101B. Sensing area 102L covers the periphery behind the left side of the vehicle 1. Sensing area 102R covers the periphery behind the right side of the vehicle 1.

[0199] The sensing results in sensing area 102F are used, for example, to detect vehicles, pedestrians, and the like that are present in front of the vehicle 1. The sensing results in sensing area 102B are used, for example, for a collision prevention function behind the vehicle 1. The sensing results in sensing area 102L and sensing area 102R are used, for example, to detect objects in blind spots on the sides of the vehicle 1.

[0200] Sensing areas 103F to 103B show examples of sensing areas sensed by camera 51. Sensing area 103F covers a position farther in front of vehicle 1 than sensing area 102F. Sensing area 103B covers a position farther in the rear of vehicle 1 than sensing area 102B. Sensing area 103L covers the periphery of the left side of vehicle 1. Sensing area 103R covers the periphery of the right side of vehicle 1.

[0201] The sensing results in the sensing area 103F can be used for, for example, recognition of traffic lights and traffic signs, lane departure prevention assistance systems, and automatic headlight control systems. The sensing results in the sensing area 103B can be used for, for example, parking assistance and surround view systems. The sensing results in the sensing areas 103L and 103R can be used for, for example, surround view systems.

[0202] Sensing area 104 shows an example of the sensing area of ​​LiDAR 53. Sensing area 104 covers a position farther ahead of vehicle 1 than sensing area 103F. On the other hand, sensing area 104 has a narrower range in the left-right direction than sensing area 103F.

[0203] The sensing results in the sensing area 104 are used to detect objects such as surrounding vehicles, for example.

[0204] A sensing area 105 shows an example of the sensing area of ​​the long-range radar 52. The sensing area 105 covers a position further ahead of the vehicle 1 than the sensing area 104. On the other hand, the sensing area 105 has a narrower range in the left-right direction than the sensing area 104.

[0205] The sensing results in the sensing area 105 are used for, for example, adaptive cruise control (ACC), emergency braking, collision avoidance, and the like.

[0206] The sensing areas of the cameras 51, radars 52, LiDARs 53, and ultrasonic sensors 54 included in the external recognition sensor 25 may have various configurations other than those shown in FIG. 19 . Specifically, the ultrasonic sensors 54 may also sense the sides of the vehicle 1, and the LiDAR 53 may sense the rear of the vehicle 1. The installation positions of the sensors are not limited to the above-described examples. The number of each sensor may be one or more.

[0207] The present disclosure has been described above by giving embodiments and their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0208] Furthermore, for example, the present disclosure can be configured as follows.

[0209] (1) A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates electric charges by photoelectric conversion; a transfer transistor that transfers the electric charges accumulated in the photoelectric conversion section by the photoelectric conversion; a floating diffusion that accumulates the electric charges transferred by the transfer transistor; a first capacitance connected to a first switching transistor that accumulates the electric charges received from the floating diffusion; and a second capacitance connected to a second switching transistor that accumulates the electric charges received from the floating diffusion.

[0210] (2) The solid-state imaging device according to (1), wherein the first switching transistor and the second switching transistor are turned on at a first timing that is a reference and a second timing that is different from the first timing, respectively.

[0211] (3) The solid-state imaging device according to (2), wherein the first timing is included in a period of a first frame, and the second timing is included in a period of a second frame that follows the first frame.

[0212] (4) The solid-state imaging device according to (2), further including a reset transistor that drains charges from the first capacitance and the second capacitance, wherein while the reset transistor is in an on state, the first switching transistor and the second switching transistor are in an on state.

[0213] (5) The solid-state imaging device according to (2), wherein the second switching transistor is turned off at the first timing.

[0214] (6) The solid-state imaging device according to (2), wherein the first switching transistor is turned off at the second timing.

[0215] (7) The solid-state imaging device according to (1), wherein the first switching transistor is arranged on a higher potential side than the first capacitance, and the second switching transistor is arranged on a higher potential side than the second capacitance.

[0216] (8) The solid-state imaging device according to (1), wherein the first switching transistor is arranged on a lower potential side than the first capacitance, and the second switching transistor is arranged on a lower potential side than the second capacitance.

[0217] (9) The solid-state imaging device according to (2), further comprising a fifth capacitor connected to a fifth switching transistor, wherein the first capacitor or the second capacitor stores charge at a pixel signal level, and the fifth capacitor stores charge at a pixel reset level.

[0218] (10) A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates electric charges through photoelectric conversion; a transfer transistor that transfers the electric charges accumulated in the photoelectric conversion section through the photoelectric conversion; a floating diffusion that accumulates the electric charges transferred by the transfer transistor; a first capacitance that accumulates the electric charges received from the floating diffusion; and a second capacitance that accumulates electric charges having a polarity different from that of the electric charges accumulated in the first capacitance.

[0219] (11) The solid-state imaging device according to (10), further including: a first switching transistor that connects one end of the second capacitance to a node on a high potential side; and a second switching transistor that connects the other end of the second capacitance to a node on a low potential side.

[0220] (12) The solid-state imaging device according to (11), further including: a fourth switching transistor that connects one end of the second capacitance to a node on a low potential side; and a third switching transistor that connects the other end of the second capacitance to a node on a high potential side.

[0221] (13) The solid-state imaging device according to (12), wherein the first switching transistor and the second switching transistor are turned on at a first timing that serves as a reference.

[0222] (14) The solid-state imaging device according to (13), wherein the third switching transistor and the fourth switching transistor are turned on at a second timing different from the first timing.

[0223] (15) The solid-state imaging device according to (14), wherein the first switching transistor and the second switching transistor are turned off at the second timing.

[0224] (16) The solid-state imaging device according to (14), wherein the third switching transistor and the fourth switching transistor are turned off at the first timing.

[0225] (17) The solid-state imaging device according to (10), further comprising a fifth capacitor connected to a fifth switching transistor, wherein the first capacitor stores charge at a pixel signal level, and the fifth capacitor stores charge at a pixel reset level.

[0226] (18) An imaging device including a solid-state imaging device, wherein the solid-state imaging device includes a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, and each of the pixels includes: a photoelectric conversion section that accumulates electric charges by photoelectric conversion; a transfer transistor that transfers the electric charges accumulated in the photoelectric conversion section by the photoelectric conversion; a floating diffusion that accumulates the electric charges transferred by the transfer transistor; a first capacitance connected to a first switching transistor that accumulates the electric charges received from the floating diffusion; and a second capacitance connected to a second switching transistor that accumulates the electric charges received from the floating diffusion.

[0227] (19) The imaging device according to (18), wherein the first switching transistor and the second switching transistor are turned on at a first timing that is a reference and a second timing that is different from the first timing, respectively.

[0228] (20) The imaging device according to (19), wherein the first timing is included in a period of a first frame, and the second timing is included in a period of a second frame following the first frame.

[0229] 1: Vehicle, 2: Imaging device, 3: Subject, 3': Subject, 11: Vehicle control system, 10: Solid-state imaging device, 12: Vertical drive unit, 13: AD conversion unit, 14: Horizontal drive unit, 15: Control unit, 16: Signal processing unit, 17: Data storage unit, 18: Input / output unit, 20: Pixel array unit, 21: Vehicle control ECU, 22: Communication unit, 23: Map information storage unit, 24: Position information acquisition unit, 25: External recognition sensor, 26: In-vehicle sensor, 27: Vehicle sensor, 28: Storage unit, 29: Cruise assistance / autonomous driving control unit, 30: DMS, 31: HMI, 32: Vehicle control unit, 61: Analysis unit, 62: Action planning unit, 63: Operation control unit, 71: Self-position estimation unit, 72: Sensor fusion unit, 73: Recognition unit, 81: Steering control unit, 82: Brake control unit, 83: Drive control unit, 84: Body system control unit, 85: Light control unit, 86: Horn control unit, 130: Semiconductor substrate, 139: Signal line, 200: Pixel, 209: Signal line, 210: Imaging lens, 211: Recording unit, 220: Information processing device, 230: Imaging control unit, 1000: Circuit, 1010: Switch, 1020: Switch,

Claims

1. A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates electric charge through photoelectric conversion; a transfer transistor that transfers the electric charge accumulated in the photoelectric conversion section through the photoelectric conversion; a floating diffusion that accumulates the electric charge transferred by the transfer transistor; a first capacitance connected to a first switching transistor that accumulates the electric charge received from the floating diffusion; and a second capacitance connected to a second switching transistor that accumulates the electric charge received from the floating diffusion.

2. The solid-state imaging device according to claim 1, wherein the first switching transistor and the second switching transistor are turned on at a first timing that serves as a reference and a second timing that is different from the first timing, respectively.

3. A solid-state imaging device according to claim 2, wherein the first timing is included in a period of a first frame, and the second timing is included in a period of a second frame following the first frame.

4. The solid-state imaging device according to claim 2, further comprising a reset transistor that drains the charges of the first capacitance and the second capacitance, and while the reset transistor is in an on state, the first switching transistor and the second switching transistor are in an on state.

5. The solid-state imaging device according to claim 2, wherein the second switching transistor is turned off at the first timing.

6. The solid-state imaging device according to claim 2, wherein the first switching transistor is turned off at the second timing.

7. The solid-state imaging device according to claim 1, wherein the first switching transistor is arranged on a higher potential side than the first capacitance, and the second switching transistor is arranged on a higher potential side than the second capacitance.

8. The solid-state imaging device according to claim 1, wherein the first switching transistor is arranged on a lower potential side than the first capacitance, and the second switching transistor is arranged on a lower potential side than the second capacitance.

9. The solid-state imaging device according to claim 2, further comprising a fifth capacitor connected to a fifth switching transistor, wherein the first capacitor or the second capacitor stores charge at a pixel signal level, and the fifth capacitor stores charge at a pixel reset level.

10. A solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates electric charges through photoelectric conversion; a transfer transistor that transfers the electric charges accumulated in the photoelectric conversion section through the photoelectric conversion; a floating diffusion that accumulates the electric charges transferred by the transfer transistor; a first capacitance that accumulates the electric charges received from the floating diffusion; and a second capacitance that accumulates electric charges having a polarity different from that of the electric charges accumulated in the first capacitance.

11. The solid-state imaging device according to claim 10, further comprising: a first switching transistor that connects one end of the second capacitance to a node on the high potential side; and a second switching transistor that connects the other end of the second capacitance to a node on the low potential side.

12. The solid-state imaging device according to claim 11, further comprising: a fourth switching transistor that connects one end of the second capacitor to a node on the low potential side; and a third switching transistor that connects the other end of the second capacitor to a node on the high potential side.

13. The solid-state imaging device according to claim 12, wherein the first switching transistor and the second switching transistor are turned on at a first timing that serves as a reference.

14. The solid-state imaging device according to claim 13, wherein the third switching transistor and the fourth switching transistor are turned on at a second timing different from the first timing.

15. The solid-state imaging device according to claim 14, wherein the first switching transistor and the second switching transistor are turned off at the second timing.

16. The solid-state imaging device according to claim 14, wherein the third switching transistor and the fourth switching transistor are turned off at the first timing.

17. The solid-state imaging device according to claim 10, further comprising a fifth capacitor connected to a fifth switching transistor, wherein the first capacitor stores charge at a pixel signal level, and the fifth capacitor stores charge at a pixel reset level.

18. An imaging device comprising a solid-state imaging device, the solid-state imaging device comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional array, each of the pixels including: a photoelectric conversion section that accumulates electric charges through photoelectric conversion; a transfer transistor that transfers the electric charges accumulated in the photoelectric conversion section through the photoelectric conversion; a floating diffusion that stores the electric charges transferred by the transfer transistor; a first capacitance connected to a first switching transistor that stores the electric charges received from the floating diffusion; and a second capacitance connected to a second switching transistor that stores the electric charges received from the floating diffusion.

19. The imaging device according to claim 18, wherein the first switching transistor and the second switching transistor are turned on at a first timing that serves as a reference and a second timing that is different from the first timing, respectively.

20. The imaging device according to claim 19, wherein the first timing is included in the period of a first frame, and the second timing is included in the period of a second frame following the first frame.

Images