Photodetection element and electronic device

Abstract

The present invention achieves the size reduction of a photodetection element. This photodetection element comprises: a photoelectric conversion part that is disposed on a first semiconductor substrate; a charge holding part that is disposed on the first semiconductor substrate and holds charge generated by the photoelectric conversion part; a transfer transistor that transfers the charge generated by the photoelectric conversion part to the charge holding part; an amplification transistor that is disposed on a second semiconductor substrate laminated on the first semiconductor substrate, generates a pixel signal on the basis of the charge held by the charge holding part, and outputs the pixel signal from a source; through wiring that is formed in a columnar shape penetrating the second semiconductor substrate and transmits voltage corresponding to the charge held by the charge holding part to the amplification transistor; a first well region that is formed in the second semiconductor substrate in a region close to the through wiring and is applied with the potential of the source of the amplification transistor; a second well region that is formed in the second semiconductor substrate; and a separation part that separates the first well region and the second well region.

Description

Photodetector element and electronic device

[0001] The present disclosure relates to a photodetector and an electronic device.

[0002] In photodetection elements such as image sensors, image sensors configured by stacking multiple substrates are used. Such image sensors are configured by stacking, for example, a semiconductor substrate including a photoelectric conversion unit that performs photoelectric conversion of incident light and a charge storage unit that stores charges generated by the photoelectric conversion, and a semiconductor substrate including a pixel circuit that generates a signal corresponding to the charges stored in the charge storage unit. In this way, by distributing pixel functions across multiple semiconductor substrates and stacking them, the chip area can be reduced.

[0003] In such stacked image sensors, the charge retention unit and the pixel circuit are arranged on different semiconductor substrates, which increases the wiring length connecting the charge retention unit and the pixel circuit. This increases the parasitic capacitance of the wiring. This parasitic capacitance is connected in parallel to the capacitance of the charge retention unit, which increases the capacitance of the charge retention unit and reduces sensitivity. Note that the charge retention unit is composed of a floating diffusion region (FD) formed on the semiconductor substrate, so the wiring connecting the charge retention unit and the pixel circuit is sometimes referred to as FD wiring.

[0004] To reduce the parasitic capacitance of the FD wiring, an image sensor has been proposed that includes a shield wiring that runs parallel to the FD wiring (see, for example, Patent Document 1). The shield wiring receives the source voltage of an amplifier transistor that amplifies the voltage of a charge storage unit included in a pixel circuit. This reduces the parasitic capacitance of the FD wiring.

[0005] International Publication No. 2020 / 262629

[0006] However, the shield wiring is arranged in a trench formed on the semiconductor substrate on which the charge retention unit is arranged, extending from the semiconductor substrate on which the pixel circuit is arranged to the FD wiring in parallel, which makes miniaturization difficult with the conventional technology.

[0007] Therefore, the present disclosure proposes a photodetector element that is miniaturized while reducing the parasitic capacitance of the wiring that connects the charge storage section and the pixel circuit.

[0008] a charge holding portion disposed on the first semiconductor substrate and holding charges generated by the photoelectric conversion portion; a transfer transistor configured to transfer charges generated by the photoelectric conversion portion to the charge holding portion; an amplifying transistor disposed on a second semiconductor substrate stacked on the first semiconductor substrate and generating a pixel signal based on charges held in the charge holding portion and outputting the pixel signal from a source; a through-wire configured in a pillar shape that penetrates the second semiconductor substrate and transmitting a voltage corresponding to the charges held in the charge holding portion to the amplifying transistor; a first well region formed in the second semiconductor substrate in a region adjacent to the through-wire and to which a potential of the source of the amplifying transistor is applied; a second well region formed in the second semiconductor substrate; and an isolation portion that isolates the first well region from the second well region.

[0009] FIG. 1 is a diagram illustrating an example of a configuration of a photodetector element according to an embodiment of the present disclosure. FIG. 2 is a diagram illustrating an example of a configuration of a pixel according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of a configuration of a pixel according to an embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of a configuration of a pixel according to an embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 8 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 9 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 10 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 11 is a diagram illustrating an example of a manufacturing method of a photodetector element according to an embodiment of the present disclosure. FIG. 1 is a diagram illustrating another example of the configuration of a photodetector element according to a second embodiment of the present disclosure. FIG. 2 is a diagram illustrating another example of the configuration of a photodetector element according to a second embodiment of the present disclosure. FIG. 3 is a diagram illustrating another example of the configuration of a photodetector element according to a third embodiment of the present disclosure. FIG. 4 is a diagram illustrating an example of the configuration of a photodetector element according to a third embodiment of the present disclosure. FIG. 5 is a diagram illustrating an example of the configuration of a photodetector element according to a third embodiment of the present disclosure. FIG. 6 is a diagram illustrating an example of the configuration of a photodetector element according to a fourth embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of the configuration of a photodetector element according to a fourth embodiment of the present disclosure. FIG. 8 is a diagram illustrating another example of the configuration of a photodetector element according to a fourth embodiment of the present disclosure. FIG. 9 is a diagram illustrating another example of the configuration of a photodetector element according to a fourth embodiment of the present disclosure.FIG. 1 is a diagram illustrating a configuration example of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 2 is a diagram illustrating a configuration example of a photodetector element according to a fifth embodiment of the present disclosure. FIG. 3 is a diagram illustrating a configuration example of a photodetector element according to a sixth embodiment of the present disclosure. FIG. 4 is a diagram illustrating another configuration example of a photodetector element according to the sixth embodiment of the present disclosure. FIG. 5 is a diagram illustrating another configuration example of a photodetector element according to the sixth embodiment of the present disclosure. FIG. 6 is a diagram illustrating another configuration example of a photodetector element according to the sixth embodiment of the present disclosure. FIG. 7 is a diagram illustrating another configuration example of a photodetector element according to the sixth embodiment of the present disclosure.

[0010] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The description will be given in the following order. Note that in the following embodiments, the same components will be assigned the same reference numerals to avoid redundant description. 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Fourth embodiment 5. Fifth embodiment 6. Sixth embodiment

[0011] (1. First Embodiment) [Configuration of Photodetection Element] FIG. 1 is a diagram illustrating an example configuration of a photodetection element according to an embodiment of the present disclosure. The figure is a block diagram illustrating an example configuration of a photodetection element 1. The photodetection element 1 is a semiconductor element that generates and outputs pixel signals that constitute image data of a subject. The photodetection element 1 includes a pixel array unit 10, a vertical drive unit 20, a column signal processing unit 30, and a control unit 40.

[0012] The pixel array unit 10 is configured by arranging a plurality of pixels 100. The pixel array unit 10 in the figure illustrates an example in which the plurality of pixels 100 are arranged in a two-dimensional matrix. Here, the pixel 100 includes a photoelectric conversion unit that performs photoelectric conversion of incident light and generates a pixel signal of an object based on the incident light. The photoelectric conversion unit may be, for example, a photodiode. The pixel 100 also includes a pixel circuit that generates a pixel signal based on electric charges generated by the photoelectric conversion unit. Signal lines 11 and 12 are wired to each pixel 100. The pixel 100 generates a pixel signal under control of a control signal transmitted through the signal line 11 and outputs the generated pixel signal via the signal line 12. The signal line 11 is arranged in rows in the two-dimensional matrix and is wired in common to the plurality of pixels 100 arranged in one row. The signal line 12 is arranged in columns in the two-dimensional matrix and is wired in common to the plurality of pixels 100 arranged in one column.

[0013] The vertical drive unit 20 generates control signals for the above-mentioned pixels 100. The vertical drive unit 20 in the figure generates control signals for each row of the two-dimensional matrix of the pixel array unit 10 and outputs them sequentially via signal lines 11.

[0014] The column signal processing unit 30 processes pixel signals generated by the pixels 100. The column signal processing unit 30 in the same figure simultaneously processes pixel signals from multiple pixels 100 arranged in one row of the pixel array unit 10, which are transmitted via signal lines 12. This processing can include, for example, analog-to-digital conversion, which converts analog pixel signals generated by the pixels 100 into digital pixel signals, and correlated double sampling (CDS), which removes offset errors in the pixel signals. The processed pixel signals are output to a circuit or the like external to the photodetector element 1.

[0015] The control unit 40 controls the vertical drive unit 20 and the column signal processing unit 30. The control unit 40 in the figure outputs control signals via signal lines 41 and 42 to control the vertical drive unit 20 and the column signal processing unit 30. The column signal processing unit 30 is an example of the "processing circuit" in the present disclosure.

[0016] FIG. 2 is a diagram illustrating an example configuration of a photodetector according to an embodiment of the present disclosure. This diagram is a schematic diagram illustrating an example configuration of a photodetector 1. The photodetector 1 is configured by stacking multiple semiconductor substrates. Specifically, the photodetector 1 is configured by stacking a first semiconductor substrate 110, a second semiconductor substrate 210, and a third semiconductor substrate 310. A wiring region 120 is arranged on the front surface side of the first semiconductor substrate 110. A wiring region 220 is arranged on the front surface side of the second semiconductor substrate 210, and a second wiring region 230 is arranged on the back surface side. A wiring region 320 is arranged on the front surface side of the third semiconductor substrate 310. The first semiconductor substrate 110 and the second semiconductor substrate 210 are stacked such that the wiring region 120 and the second wiring region 230 are in contact with each other. That is, the back surface side of the second semiconductor substrate 210 is stacked on the front surface side of the first semiconductor substrate 110. The second semiconductor substrate 210 and the third semiconductor substrate 310 are stacked in a shape in which the wiring region 220 and the wiring region 320 are in contact with each other. That is, the front surface side of the third semiconductor substrate 310 is stacked on the front surface side of the second semiconductor substrate 210.

[0017] [Pixel Configuration] Fig. 3 is a diagram showing an example configuration of a pixel according to an embodiment of the present disclosure. The figure is a circuit diagram showing an example configuration of a pixel 100. Note that the pixel 100 in the figure shows an example in which the pixel 100 includes two photoelectric conversion units (photoelectric conversion units 101a and 101b). The pixel 100 includes the photoelectric conversion units 101a and 101b, transfer transistors 102a and 102b, a charge holding unit 103, a reset transistor 104, an amplifier transistor 105, and a selection transistor 106. The transfer transistors 102a and 102b, the reset transistor 104, the amplifier transistor 105, and the selection transistor 106 can be configured using n-channel MOS transistors.

[0018] As described above, signal lines 11 and 12 are wired to the pixel 100. The signal lines 11 in FIG. 3 include signal lines TG1, TG2, RST, and SEL. The signal lines 12 include signal line VSL. In addition, a power supply line Vdd is wired to the pixel 100. This power supply line Vdd is a line that supplies power to the pixel 100. Note that FIG. 3 also illustrates a column signal processing unit 30.

[0019] The anode of the photoelectric conversion unit 101a is connected to a reference potential line, and the cathode is connected to the source of the transfer transistor 102a. The drain of the transfer transistor 102a is connected to the drain of the transfer transistor 102b, the source of the reset transistor 104, the gate of the amplification transistor 105, and one end of the charge holding unit 103. The other end of the charge holding unit 103 is connected to the reference potential line. The anode of the photoelectric conversion unit 101b is connected to the reference potential line, and the cathode is connected to the source of the transfer transistor 102b. The drain of the reset transistor 104 is connected to the power supply line Vdd. The drain of the amplification transistor 105 is connected to the power supply line Vdd, and the source is connected to the drain of the selection transistor 106. The source of the selection transistor 106 is connected to the signal line VSL.

[0020] A signal line TG1, a signal line TG2, a signal line RST, and a signal line SEL are connected to the gate of the transfer transistor 102a, the gate of the transfer transistor 102b, the gate of the reset transistor 104, and the gate of the selection transistor 106, respectively.

[0021] The photoelectric conversion units 101a and 101b perform photoelectric conversion of incident light and can be configured by photodiodes formed on a first semiconductor substrate 110, which will be described later.

[0022] The charge holding portion 103 holds electric charges. The charge holding portion 103 holds electric charges generated by photoelectric conversion of the photoelectric conversion portions 101 a and 101 b. The charge holding portion 103 can be configured by a floating diffusion region (FD), which is a semiconductor region formed in the first semiconductor substrate 110.

[0023] The transfer transistors 102a and 102b transfer the charges generated by photoelectric conversion in the photoelectric conversion units 101a and 101b, respectively, to the charge holding unit 103. Control signals for the transfer transistors 102a and 102b are transmitted via signal lines TG1 and TG2.

[0024] The reset transistor 104 resets the charge holding portion 103. This reset can be performed by establishing electrical continuity between the charge holding portion 103 and the power supply line Vdd to drain the charge from the charge holding portion 103. A control signal for the reset transistor 104 is transmitted via a signal line RST.

[0025] As described above, the gate of the amplifying transistor 105 is connected to the charge holding unit 103. Therefore, a pixel signal having a voltage corresponding to the charge held in the charge holding unit 103 is generated at the source of the amplifying transistor 105. Furthermore, by making the selection transistor 106 conductive, this pixel signal can be output to a signal line VSL. A control signal for the selection transistor 106 is transmitted via a signal line SEL. A constant current circuit 31 disposed in the column signal processing unit 30 is connected to the signal line VSL. This constant current circuit 31 constitutes a source follower load for the amplifying transistor 105.

[0026] 4 is a diagram showing an example of the configuration of a pixel according to an embodiment of the present disclosure. This figure is a plan view showing an example of the configuration of a pixel 100. The pixel 100 in this figure shows an example in which the vertical size is twice as large as the horizontal size. The upper side of this figure shows the configuration of a first semiconductor substrate 110. The lower side of this figure shows the configuration of a second semiconductor substrate 210. In this figure, the dotted hatched area represents the gate of a MOS transistor. The diagonal hatched area from top right represents a semiconductor region. The diagonal hatched area from bottom right represents an insulating layer.

[0027] Photoelectric conversion units 101a and 101b, transfer transistors 102a and 102b, and a charge holding unit 103 are arranged on a first semiconductor substrate 110. The photoelectric conversion unit 101a is composed of a semiconductor region 111 formed inside the first semiconductor substrate 110. The photoelectric conversion unit 101b is similarly configured. The charge holding unit 103 is arranged in the center of the pixel 100. The charge holding unit 103 is composed of a semiconductor region 112 that forms a floating diffusion region. The transfer transistor 102a is arranged between the photoelectric conversion unit 101a and the charge holding unit 103, and the transfer transistor 102b is arranged between the photoelectric conversion unit 101b and the charge holding unit 103. FIG. 4 shows the gates 130 of the transfer transistors 102a and 102b. Note that "PD," "TRG," and "FD" represent the photoelectric conversion unit, transfer transistor, and charge holding unit, respectively.

[0028] A contact plug 124 is arranged in the gate 130. The open rectangle in FIG. 4 represents the contact plug 124. This contact plug 124 is a pillar-shaped wiring that transmits signals and the like to the semiconductor region of the first semiconductor substrate 110 and the gate 130. A semiconductor region 113 is further arranged in the first semiconductor substrate 110. This semiconductor region 113 is a region to which a reference potential is transmitted. A contact plug 124 is also arranged in the semiconductor region 113. This contact plug 124 corresponds to a well contact. Furthermore, a through wiring 229 is arranged in the charge retention portion 103. This through wiring 229 transmits the voltage of the charge retention portion 103 to the element of the second semiconductor substrate 210. The through wiring 229 can be made of a pillar-shaped metal.

[0029] The reset transistor 104, the amplifier transistor 105, and the select transistor 106 are arranged on the second semiconductor substrate 210. FIG. 4 shows the semiconductor regions and gates that form the drain and source. The reset transistor 104, the amplifier transistor 105, and the select transistor 106 are arranged in a second well region 213. A semiconductor region 216, which will be described later, is further arranged in the second well region 213. A contact plug 224 is arranged in the reset transistor 104, etc. The thick lines in FIG. 4 indicate the connection of signal lines. "RST," "AMP," and "SEL" represent the reset transistor, the amplifier transistor, and the select transistor, respectively.

[0030] The through-hole wiring 229 described above is disposed in the center of the pixel 100 region of the second semiconductor substrate 210. An insulating layer 241 having a shape surrounding the through-hole wiring 229 is further disposed on the second semiconductor substrate 210. This insulating layer 241 can be made of the same material as the insulating layer 221 in the wiring region 220 of the second semiconductor substrate 210. A first well region 211 is disposed outside the insulating layer 241. This first well region 211 is disposed in a region of the second semiconductor substrate 210 close to the through-hole wiring 229. The first well region 211 in FIG. 4 represents an example in which the first well region 211 is configured in a shape surrounding the through-hole wiring 229. In addition, the source potential of the amplification transistor 105 is applied to the first well region 211 via a contact plug 224. An isolation portion 240 is disposed between the first well region 211 and the second well region 213. The isolation portion 240 is made of an insulating material such as oxide, etc. Note that "well 1" and "well 2" represent the first well region and the second well region, respectively.

[0031] 5 is a diagram showing an example of the configuration of a pixel according to an embodiment of the present disclosure. The diagram is a cross-sectional view showing an example of the configuration of the pixel 100. As described above, the pixel 100 is configured by stacking a first semiconductor substrate 110, a second semiconductor substrate 210, and a third semiconductor substrate 310.

[0032] The first semiconductor substrate 110 is a semiconductor substrate on which the photoelectric conversion units 101a and 101b, the charge holding unit 103, and the transfer transistors 102a and 102b are disposed. The first semiconductor substrate 110 can be made of silicon (Si). The first semiconductor substrate 110 in FIG. 5 is assumed to be configured in a well region having a p-type conductivity. The photoelectric conversion unit 101a and the like can be formed by disposing an n-type semiconductor region in this p-type well region. As described above, the photoelectric conversion unit 101a is configured by a semiconductor region 111 having an n-type conductivity. Specifically, the photodiode formed by a pn junction at the interface between the semiconductor region 111 and the well region corresponds to the photoelectric conversion unit 101a. The charge holding unit 103 is configured by a semiconductor region 112 having an n-type conductivity. The transfer transistor 102a is a MOS transistor with the semiconductor region 111 as the source and the semiconductor region 112 as the drain. The transfer transistor 102a includes a gate 130. In addition, a semiconductor region 113 of p-type conductivity to which a well contact is connected is disposed on the first semiconductor substrate 110 .

[0033] The wiring region 120 is a region where wiring for transmitting signals from elements and the like of the first semiconductor substrate 110 is formed. The wiring region 120 includes an insulating layer 121, wiring 122, via plugs 123, contact plugs 124, and pads 125. The wiring 122 transmits signals from elements and the like. The wiring 122 can be made of a metal such as copper (Cu). The wiring 122 can also be configured in multiple layers. The via plugs 123 are made of columnar metal and connect the wiring 122 arranged in different layers. The contact plugs 124 connect the semiconductor region 113 and the gate 130 to the wiring 122. The pads 125 are electrodes arranged on the surface of the wiring region 120 and transmit signals between stacked wiring regions. The pads 125 can be made of Cu. The pads 125 in FIG. 5 transmit the voltage of the charge retention unit 103.

[0034] The second semiconductor substrate 210 is a semiconductor substrate on which the reset transistor 104, the amplifier transistor 105, and the select transistor 106 (not shown) are disposed. The second semiconductor substrate 210 can be made of Si. A first well region 211 and a second well region 213 are disposed in the second semiconductor substrate 210. The second well region 213 can be configured as a p-type well. The reset transistor 104, the amplifier transistor 105, and the select transistor 106 (not shown) are disposed in the second well region 213. The amplifier transistor 105 is configured by n-type semiconductor regions 214 and 215 and a gate 251. The reset transistor 104 and the select transistor 106 (not shown) have a similar configuration. A n-type semiconductor region 216 is disposed in the second well region 213. A contact plug 224 constituting a well contact is connected to this semiconductor region 216.

[0035] The through-wire 229 is configured to penetrate the second semiconductor substrate 210. Specifically, the through-wire 229 is disposed in an opening 249 formed in the second semiconductor substrate 210. The aforementioned insulating layer 241 is disposed in this opening 249. This insulating layer 241 insulates the through-wire 229 from the second semiconductor substrate 210. A first well region 211 is disposed outside the insulating layer 241. This first well region 211 can be configured to be p-type or n-type. The first well region 211 in FIG. 5 shows an example in which it is configured to be p-type. A semiconductor region 217 is disposed in the first well region 211. This semiconductor region 217 is a semiconductor region for obtaining an ohmic connection and can be configured to be the same conductivity type as the first well region 211. The source potential of the amplification transistor 105 is transmitted to the semiconductor region 217. The isolation portion 240 is disposed between the first well region 211 and the second well region 213. As described above, the isolation portion 240 can be made of an insulating material. Specifically, the isolation portion 240 can be made of silicon oxide (SiO ２ ), silicon nitride (SiN), and polycrystalline silicon containing no impurities.

[0036] The wiring region 220 is a region where wiring is formed to transmit signals of elements, etc., of the second semiconductor substrate 210. The wiring region 220 includes an insulating layer 221, wiring 222, via plugs 223, contact plugs 224, and pads 225.

[0037] Furthermore, a second wiring region 230 is arranged on the back surface side of the second semiconductor substrate 210. In this second wiring region 230, an insulating layer 231, wiring 232, via plugs 233, and pads 235 are arranged. The pads 235 are made of Cu and are bonded to the pads 125 of the wiring region 120. Such a connection using the pads 125 etc. is called a CuCu connection. An end of a through wiring 229 is connected to the wiring 232.

[0038] The third semiconductor substrate 310 is a semiconductor substrate on which the vertical drive unit 20 and the column signal processing unit 30 shown in FIG. 1 are arranged. The third semiconductor substrate 310 can be made of Si. A semiconductor region 311 is arranged on the third semiconductor substrate 310. This semiconductor region 311 is a semiconductor region for transmitting a reference potential.

[0039] The wiring region 320 is a region where wiring is formed to transmit signals from elements, etc., of the third semiconductor substrate 310. The wiring region 320 includes an insulating layer 321, wiring 322, via plugs 323, contact plugs 324, and pads 325. The pads 325 are made of Cu and are bonded to the pads 225 of the wiring region 220.

[0040] A color filter 191 is disposed on the back surface side of the first semiconductor substrate 110. This color filter 191 transmits incident light of a predetermined wavelength. The color filter 191 can be a color filter that transmits red light, green light, and blue light.

[0041] An on-chip lens 192 is disposed on the surface of the color filter 191. This on-chip lens 192 is a lens that condenses incident light.

[0042] 5, the through-wire 229 is configured to penetrate the second semiconductor substrate 210, which increases the wire length and parasitic capacitance. As a result, the capacitance of the charge holding unit 103 increases and the sensitivity decreases. Therefore, a first well region 211 is disposed close to the through-wire 229, and the potential of the source of the amplification transistor 105 is applied to this first well region 211. As a result, the potential of the first well region 211 follows the potential of the through-wire 229, and the capacitance between the through-wire 229 and the first well region 211 can be reduced.

[0043] [Method for Manufacturing Photodetector Element] Figures 6A-6H are diagrams illustrating an example of a method for manufacturing a photodetector element according to an embodiment of the present disclosure. Figures 6A-6H are diagrams illustrating an example of a manufacturing process for a photodetector element 1. First, a semiconductor region (not shown) is formed in a second semiconductor substrate 210 (Figure 6A). An isolation portion 240 is also formed on the surface side of the second semiconductor substrate 210. This can be achieved by forming a groove-shaped opening on the surface side of the second semiconductor substrate 210 and filling it with an insulating material. Next, a wiring region 220 is formed in the second semiconductor substrate 210. In the same figure, wiring 222 and pads 225 are depicted in the wiring region 220. Similarly, a semiconductor region (not shown) is formed in a third semiconductor substrate 310, and a wiring region 320 is arranged therein. In the same figure, wiring 322 and pads 325 are depicted in the wiring region 320 (Figure 6A).

[0044] Next, the second semiconductor substrate 210 is laminated on the third semiconductor substrate 310 ( FIG. 6B ). Specifically, the wiring regions 320 and 220 are brought into contact with each other while aligning the pads 225 and 325, and the third semiconductor substrate 310 and the second semiconductor substrate 210 are heated and compressed together. At this time, the pads 225 and 325 are bonded together.

[0045] Next, the rear surface of the second semiconductor substrate 210 is ground to thin it (FIG. 6C), at which point the end of the isolation portion 240 is exposed.

[0046] Next, an opening 249 is formed in the second semiconductor substrate 210 (FIG. 6D). Next, an insulating layer 231 is disposed on the surface of the second semiconductor substrate 210 including the opening 249. At this time, an insulating layer 241 is formed (FIG. 6E).

[0047] Next, the through wiring 229 is formed (FIG. 6F). This can be done by placing the material of the through wiring 229 in an opening formed in the region where the through wiring 229 is to be placed.

[0048] Next, a second wiring region 230 is formed on the second semiconductor substrate 210 (FIG. 6G). In the second wiring region 230 in the same figure, wiring 232 and pads 235 are shown.

[0049] Next, the first semiconductor substrate 110 is further laminated ( FIG. 6H ). Specifically, the second wiring region 230 and the wiring region 120 are brought into contact with each other while aligning the pads 235 and 125, and the second semiconductor substrate 210 and the first semiconductor substrate 110 are heated and compressed together. At this time, the pads 235 and 125 are bonded together. Thereafter, the color filter 191 and the on-chip lens 192 are arranged. The photodetector element 1 can be manufactured through the above steps.

[0050] As described above, the photodetector element 1 according to the first embodiment of the present disclosure has the first well region 211 disposed adjacent to the through-wire 229, and the potential of the source of the amplification transistor 105 applied to this first well region 211. This reduces the capacitance between the through-wire 229 and the first well region 211. Since only the insulating layer 241 is disposed in the opening 249 of the second semiconductor substrate 210 where the through-wire 229 is disposed, miniaturization can be easily achieved.

[0051] 2. Second Embodiment A variation of the photodetector element 1 of the first embodiment will be described.

[0052] 7A to 7D are diagrams illustrating an example of the configuration of a photodetector according to a second embodiment of the present disclosure, and are plan views illustrating an example of the configuration of the second semiconductor substrate 210 of the pixel 100.

[0053] Fig. 7A shows an example in which the first well region 211 is configured in a shape that faces three sides of the through wiring 229. Fig. 7B shows an example in which the first well region 211 is configured in a shape that faces two sides of the through wiring 229. Fig. 7C shows an example in which the first well region 211 is configured in a shape that faces one side of the through wiring 229. Fig. 7D shows an example in which two first well regions 211 are arranged with the through wiring 229 sandwiched between them.

[0054] 8 is a diagram showing another configuration example of a photodetector element according to the second embodiment of the present disclosure. The figure is a plan view showing a configuration example of the second semiconductor substrate 210 of the pixel 100. The figure shows an example in which two pixels 100 (pixels 100a and 100b) are arranged adjacent to each other.

[0055] 9A and 9B are diagrams illustrating another exemplary configuration of a photodetector element according to the second embodiment of the present disclosure. Similar to FIG. 8 , FIGS. 9A and 9B are plan views illustrating an exemplary configuration of a second semiconductor substrate 210 of a pixel 100, illustrating an example in which two pixels 100 (pixels 100a and 100b) are arranged adjacent to each other. The pixel 100 in FIGS. 9A and 9B illustrates an example in which a pixel isolation region is arranged between adjacent first well regions 211. FIG. 9A illustrates an example in which a semiconductor region 242 is arranged as the pixel isolation region. This semiconductor region 242 can be configured as a well region with a fixed potential. This well region corresponds to a third well region (Well 3). FIG. 9B illustrates an example in which a metal plate 243 is arranged as the pixel isolation region. A reference potential (Vss) or a power supply voltage (Vdd) can be applied to this metal plate 243. The metal plate 243 can be formed simultaneously with the through-hole wiring 229.

[0056] 10A and 10B are diagrams illustrating another exemplary configuration of a photodetector element according to a second embodiment of the present disclosure. FIGS. 10A and 10B are plan views illustrating an exemplary configuration of a second semiconductor substrate 210 of a pixel 100, illustrating an example in which two pixels 100 (pixels 100a and 100b) are arranged adjacent to each other. A signal line 12 (signal line VSL) is illustrated in the pixel 100 in FIGS. 10A and 10B. The signal line 12 can be arranged in a position that does not overlap with the first well region 211 when viewed from the normal direction of the surface of the second semiconductor substrate 210. FIG. 10A illustrates the case of a second semiconductor substrate 210 similar to that of FIG. 4. FIG. 10B illustrates the case of a second semiconductor substrate 210 including a pixel isolation region (semiconductor region 242).

[0057] If the signal line 12 is capacitively coupled to the first well region 211, fluctuations in the potential of the signal line 12 are transmitted to the first well region 211, causing further fluctuations in the potential of the signal line 12. This causes a problem of an increased settling time for the potential of the signal line 12. To prevent this, it is necessary to reduce the capacitance of the signal line 12 and the first well region 211. Therefore, it is desirable to arrange the signal line 12 and the first well region 211 so that they do not overlap. Note that it is also possible to further arrange wiring for another node, for example, wiring to which a reference potential is applied, between the signal line 12 and the first well region 211. In this case, the capacitance of the signal line 12 and the first well region 211 can be further reduced.

[0058] 11A and 11B are diagrams illustrating another exemplary configuration of a photodetector element according to a second embodiment of the present disclosure. FIGS. 11A and 11B are cross-sectional views illustrating an exemplary configuration of a second semiconductor substrate 210 of a pixel 100. The second semiconductor substrate 210 in FIG. 11A illustrates an example in which an isolation portion 244 is disposed within the isolation portion 240. The isolation portion 244 can be formed of an insulator different from that of the isolation portion 240. The second semiconductor substrate 210 in FIG. 11B illustrates an example in which the bottom of the isolation portion 240 is disposed near the bottom surface of the second semiconductor substrate 210. Therefore, the first well region 211 and the second well region 213 are in contact near the bottom of the second semiconductor substrate 210. However, since this region is separated from the surface of the second semiconductor substrate 210, it has a low electric field. Therefore, even if the first well region 211 and the second well region 213 are in contact with each other, this does not have a significant effect.

[0059] The configuration of the photodetector element 1 other than that described above is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0060] (3. Third Embodiment) In the photodetector element 1 of the first embodiment described above, the amplification transistor 105 is disposed in the second well region 213. In contrast, the photodetector element 1 of the third embodiment of the present disclosure differs from the first embodiment described above in that the amplification transistor 105 is disposed in the first well region 211.

[0061] 12 is a diagram showing a configuration example of a photodetector element according to a third embodiment of the present disclosure. Similar to FIG. 3, this figure is a circuit diagram showing a configuration example of a pixel 100. The pixel 100 in this figure differs from the pixel 100 in FIG. 2 in that the source of the amplifier transistor 105 is connected to the substrate of the amplifier transistor 105.

[0062] 13 is a diagram showing a configuration example of a photodetector element according to a third embodiment of the present disclosure. Similar to FIG. 4, this figure is a plan view showing a configuration example of a pixel 100. The pixel 100 in this figure differs from the pixel 100 in FIG. 4 in that the amplification transistor 105 is disposed in a first well region 211. The source potential of the amplification transistor 105 is applied to the first well region 211. A separation portion 240 is disposed between the first well region 211 and the second well region 213.

[0063] 14 is a diagram showing a configuration example of a photodetector element according to a third embodiment of the present disclosure. Similar to FIG. 5, this figure is a cross-sectional view showing a configuration example of a pixel 100. The pixel 100 in this figure differs from the pixel 100 in FIG. 5 in that the amplification transistor 105 is disposed in the first well region 211.

[0064] The configuration of the photodetector element 1 other than that described above is the same as the configuration of the photodetector element 1 in the first embodiment of the present disclosure, and therefore description thereof will be omitted.

[0065] As described above, in the photodetector element 1 according to the third embodiment of the present disclosure, the amplification transistor 105 is disposed in the first well region 211, and the source potential of the amplification transistor 105 is applied to the first well region 211. This makes it possible to reduce the parasitic capacitance of the through-wire 229.

[0066] 4. Fourth Embodiment A variation of the photodetector element 1 of the third embodiment will be described.

[0067] [Pixel Configuration] FIGS. 15A and 15B are diagrams illustrating an example configuration of a photodetector element according to a fourth embodiment of the present disclosure. Similar to FIG. 13 , FIGS. 15A and 15B are plan views illustrating an example configuration of a pixel 100. The pixel 100 in FIG. 15A illustrates an example in which a first well region 211 and a first well region 212 are arranged. FIG. 15B illustrates an example in which the first well region 211 is configured to face one side of the through-hole wiring 229. Note that the first well region 211 can be configured to be closer to the through-hole wiring 229 than the second well region 213. In FIG. 15B , "d1" represents the distance between the first well region 211 and the through-hole wiring 229. Furthermore, "d2" represents the distance between the second well region 213 and the through-hole wiring 229. As illustrated in FIG. 15B , d2 can be set to be greater than d1. This reduces the influence of the second well region 213.

[0068] 16A and 16B are diagrams illustrating another configuration example of a photodetector element according to the fourth embodiment of the present disclosure. Fig. 16A illustrates an example in which two pixels 100 (pixels 100a and 100b) are arranged adjacent to each other. Fig. 16B illustrates an example in which a semiconductor region 242 is arranged between first well regions 211.

[0069] 17 is a diagram showing another configuration example of a photodetector according to the fourth embodiment of the present disclosure. Similar to FIG. 14 , this figure is a cross-sectional view showing the configuration example of a pixel 100. The amplification transistor 105 in this figure differs from the pixel 100 in FIG. 14 in that a through-hole wiring 229 is connected to the gate 151.

[0070] The configuration of the photodetector element 1 other than that described above is the same as the configuration of the photodetector element 1 in the third embodiment of the present disclosure, and therefore description thereof will be omitted.

[0071] (5. Fifth Embodiment) In the photodetector element 1 of the third embodiment described above, the separation portion 240 made of an insulator is disposed between the first well region 211 and the second well region 213. In contrast, the photodetector element 1 of the fifth embodiment of the present disclosure differs from the third embodiment described above in that a separation portion made of a semiconductor region is disposed.

[0072] 18 is a diagram showing a configuration example of a photodetector element according to a fifth embodiment of the present disclosure. Similar to FIG. 12, this figure is a circuit diagram showing a configuration example of a pixel 100. The pixel 100 in this figure differs from the pixel 100 in FIG. 12 in that one photoelectric conversion unit 101 and one transfer transistor 102 are arranged.

[0073] 19 is a diagram showing a configuration example of a photodetector according to a fifth embodiment of the present disclosure. Similar to FIG. 13 , this figure is a plan view showing a configuration example of a pixel 100. The second semiconductor substrate 210 in this figure differs from the second semiconductor substrate 210 in FIG. 13 in that an isolation portion 245 is disposed instead of the isolation portion 240. The isolation portion 245 is formed by a semiconductor region of a different conductivity type from the first well region 211 and the second well region 213.

[0074] 20 is a diagram showing a configuration example of a photodetector element according to a fifth embodiment of the present disclosure. Similar to FIG. 14 , this figure is a cross-sectional view showing a configuration example of a pixel 100. In the pixel 100 of this figure, similar to the pixel 100 of FIG. 14 , an amplification transistor 105 is disposed in a first well region 211. A semiconductor region 217 is further disposed in the first well region 211. This semiconductor region 217 is connected to the source of the amplification transistor 105. The first well region 211 and the second well region 213 are configured as p-type. In contrast, the isolation portion 245 is configured as n-type.

[0075] The amplifier transistor 105 is disposed in the first well region 211, and the first well region 211 and the source of the amplifier transistor 105 are connected by a wire. This allows the gain of the amplifier transistor 105 to be approximately 1, and the stray capacitance of the through-wire 229 to be approximately 0.

[0076] The configuration of the photodetector element 1 other than that described above is the same as the configuration of the photodetector element 1 in the third embodiment of the present disclosure, and therefore description thereof will be omitted.

[0077] As described above, the photodetector element 1 according to the fifth embodiment of the present disclosure uses the separation section 245 formed of a semiconductor region, which simplifies the manufacturing process of the separation section 245.

[0078] 6. Sixth Embodiment A variation of the photodetector element 1 of the fifth embodiment will be described.

[0079] [Pixel Configuration] Fig. 21 is a diagram showing a configuration example of a photodetector element according to a sixth embodiment of the present disclosure. The figure is a cross-sectional view showing a configuration example of a pixel 100. The pixel 100 in the figure shows an example in which the selection transistor 106 and the reset transistor 104 (not shown) are arranged on the third semiconductor substrate 310, and only the amplification transistor 105 is arranged on the second semiconductor substrate 210. This can improve the layout efficiency of the elements of the pixel 100. Note that the reset transistor 104 can also be arranged on the first semiconductor substrate 110.

[0080] Fig. 22 is a diagram showing another configuration example of a photodetector element according to the sixth embodiment of the present disclosure. Similar to Fig. 18, Fig. 22 is a circuit diagram showing a configuration example of a pixel 100. The pixel 100 in Fig. 22 differs from the pixel 100 in Fig. 18 in that the transfer transistor 102, the reset transistor 104, the amplification transistor 105, and the selection transistor 106 are configured as p-channel MOS transistors.

[0081] Fig. 23 is a diagram showing another configuration example of a photodetector according to the sixth embodiment of the present disclosure. Similar to Fig. 20, Fig. 23 is a cross-sectional view showing a configuration example of a pixel 100. The pixel 100 in Fig. 23 differs from the pixel 100 in Fig. 20 in that the first well region 211 and the second well region 213 are configured as n-type, and the isolation portion 245 is configured as p-type. Furthermore, the amplification transistor 105 in Fig. 23 is configured as a p-channel MOS transistor.

[0082] 24 is a diagram showing another configuration example of a photodetector according to the sixth embodiment of the present disclosure. Similar to FIG. 18 , this figure is a circuit diagram showing a configuration example of a pixel 100. In this figure, two pixels 100 (pixels 100a and 100b) are arranged adjacent to each other. In the pixel 100a, the source of the amplifier transistor 105 is connected to the substrate of the amplifier transistor 105. In contrast, in the pixel 100b, the source of the amplifier transistor 105 is not connected to the substrate.

[0083] 25 is a diagram showing another example configuration of a photodetector element according to the sixth embodiment of the present disclosure. This diagram is a cross-sectional view showing an example configuration of a pixel 100a and a pixel 100b. The amplifier transistor 105 of the pixel 100a and the amplifier transistor 105 of the pixel 100b are disposed in the same first well region 211. That is, the amplifier transistor 105 of the pixel 100a and the amplifier transistor 105 of the pixel 100b share the first well region 211. The source of the amplifier transistor 105 of the pixel 100a is connected to the first well region 211. In contrast, the source of the amplifier transistor 105 of the pixel 100b is not connected to the first well region 211. In this way, the isolation portion 245 between the pixel 100a and the pixel 100b in this diagram can be eliminated.

[0084] On the other hand, if the pixel signals in the pixels 100a and 100b differ significantly, the capacitance reduction effect of the through-hole wiring 229 in the pixel 100b will be reduced. Therefore, it is necessary to devise a way to align the pixel signals in the pixels 100a and 100b. For example, the pixel signals can be aligned by making the pixels 100a and 100b correspond to incident light of the same wavelength. This will be described with reference to Figures 26A and 26B.

[0085] 26A and 26B are diagrams illustrating another configuration example of a photodetector element according to the sixth embodiment of the present disclosure. Figures 26A and 26B illustrate an example in which the pixel 100a and the pixel 100b illustrated in Figure 24 are used. In addition, in Figures 26A and 26B, the configuration of the pixel 100a, etc. is depicted in a simplified form.

[0086] 26A, the letters attached to the pixels 100a and 100b indicate the type of color filter 191. Specifically, "G" indicates that a color filter 191 corresponding to green light is disposed, and "R" indicates that a color filter 191 corresponding to red light is disposed.

[0087] 26B shows an example in which pixels 100a, 100b, 100c, and 100d are used. Note that the amplification transistors 105 of the pixels 100a, 100b, 100c, and 100d share the first well region 211. Among the pixels 100a, 100b, 100c, and 100d, the source of the amplification transistor 105 of the pixel 100a is connected to the substrate.

[0088] In this way, the pixels 100 corresponding to incident light of the same wavelength share the first well region 211 in which the amplification transistor 105 is disposed, thereby making it possible to make pixel signals uniform.

[0089] The configuration of the photodetector element 1 other than that described above is the same as the configuration of the photodetector element 1 in the third embodiment of the present disclosure, and therefore description thereof will be omitted.

[0090] The effects described in this specification are merely examples and are not limiting, and other effects may also be present.

[0091] The present technology may also be configured as follows: (1) A photodetector including: a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light; a charge holding unit disposed on the first semiconductor substrate and holding charge generated by the photoelectric conversion unit; a transfer transistor configured to transfer charge generated by the photoelectric conversion unit to the charge holding unit; an amplifying transistor disposed on a second semiconductor substrate stacked on the first semiconductor substrate and generating a pixel signal based on charge held in the charge holding unit and outputting the pixel signal from a source; a through-wire configured in a pillar shape that penetrates the second semiconductor substrate and transmitting a voltage corresponding to the charge held in the charge holding unit to the amplifying transistor; a first well region formed in the second semiconductor substrate in a region adjacent to the through-wire and to which a potential of the source of the amplifying transistor is applied; a second well region formed in the second semiconductor substrate; and an isolation unit that isolates the first well region and the second well region. (2) The photodetector according to (1), wherein the amplifying transistor is disposed in the second well region. (3) The photodetector element according to (1), wherein the amplifying transistor is disposed in the first well region. (4) The photodetector element according to any one of (1) to (3), further comprising a reset transistor that resets the charge retention unit. (5) The photodetector element according to (4), wherein the reset transistor is disposed in the second well region. (6) The photodetector element according to (4), wherein the reset transistor is disposed on the first semiconductor substrate. (7) The photodetector element according to any one of (1) to (6), further comprising a selection transistor that outputs the pixel signal based on a selection signal that is a control signal. (8) The photodetector element according to (7), wherein the selection transistor is disposed in the second well region. (9) The photodetector element according to any one of (1) to (8), wherein the separation unit is made of an insulator. (10) The photodetector element according to any one of (1) to (8), wherein the separation unit is made of a semiconductor region. (11) The photodetector element according to any one of (1) to (10), wherein the first well region is configured in a shape surrounding the through-wiring.(12) The photodetector according to any one of (1) to (10), wherein the second well region is disposed close to the through-hole wiring. (13) The photodetector according to (12), wherein the first well region is disposed closer to the through-hole wiring than the second well region. (14) The photodetector according to any one of (1) to (13), further including a third semiconductor substrate stacked on a surface of the second semiconductor substrate different from the surface stacked on the first semiconductor substrate. (15) The photodetector according to (14), wherein a circuit for generating a control signal is disposed on the third semiconductor substrate. (16) The photodetector according to (14), wherein a selection transistor for outputting the pixel signal based on a selection signal that is a control signal is disposed on the third semiconductor substrate. (17) The photodetector according to (14), wherein a reset transistor for resetting the charge holding unit is disposed on the third semiconductor substrate. (18) The photodetector according to any one of (1) to (17), including a plurality of pixels each including the photoelectric conversion unit, the charge holding unit, the transfer transistor, the amplification transistor, the through-hole wiring, the first well region, the second well region, and the isolation unit. (19) The photodetector according to (18), further including a pixel isolation region arranged between the first well regions of each of the plurality of pixels. (20) The photodetector according to (19), wherein the pixel isolation region is formed of a semiconductor region. (21) The photodetector according to (19), wherein the pixel isolation region is formed of a metal. (22) The photodetector according to (18), including the first well region in which the amplification transistors of adjacent pixels are commonly arranged. (23) The photodetector according to any one of (1) to (22), further including a pixel signal line arranged in a wiring region of the second semiconductor substrate and transmitting the pixel signal. (24) The photodetector element according to (23), wherein the pixel signal lines are arranged at positions that do not overlap the first well region when viewed from the normal direction of the surface of the second semiconductor substrate.(25) An electronic device comprising: a photoelectric conversion unit disposed on a first semiconductor substrate and performing photoelectric conversion of incident light; a charge holding unit disposed on the first semiconductor substrate and holding charges generated by the photoelectric conversion unit; a transfer transistor that transfers charges generated by the photoelectric conversion unit to the charge holding unit; an amplifying transistor disposed on a second semiconductor substrate stacked on the first semiconductor substrate and generating a pixel signal based on charges held in the charge holding unit and outputting the pixel signal from a source; a through wiring configured in a pillar shape that passes through the second semiconductor substrate and transmits a voltage corresponding to the charges held in the charge holding unit to the amplifying transistor; a first well region formed in the second semiconductor substrate in a region adjacent to the through wiring and to which a potential of the source of the amplifying transistor is applied; a second well region formed in the second semiconductor substrate; an isolation unit that isolates the first well region and the second well region; and a processing circuit that processes the pixel signal.

[0092] REFERENCE SIGNS LIST 1 Photodetector element 11, 12 Signal line 20 Vertical drive section 30 Column signal processing section 100, 100a, 100b, 100c, 100d Pixel 101, 101a, 101b Photoelectric conversion section 102, 102a, 102b Transfer transistor 103 Charge holding section 104 Reset transistor 105 Amplification transistor 106 Selection transistor 110 First semiconductor substrate 191 Color filter 210 Second semiconductor substrate 211, 212 First well region 213 Second well region 229 Through wiring 251 Gate 240, 244, 245 Isolation section 242 Semiconductor region 241 Insulating layer 243 Metal plate 310 Third semiconductor substrate

Claims

1. A photodetector comprising: a photoelectric conversion unit disposed on a first semiconductor substrate for photoelectric conversion of incident light; a charge holding unit disposed on the first semiconductor substrate for holding charges generated by the photoelectric conversion unit; a transfer transistor for transferring charges generated by the photoelectric conversion unit to the charge holding unit; an amplifying transistor disposed on a second semiconductor substrate stacked on the first semiconductor substrate for generating a pixel signal based on the charges held in the charge holding unit and outputting the signal from its source; a through-wire configured in a pillar shape that passes through the second semiconductor substrate for transmitting a voltage corresponding to the charges held in the charge holding unit to the amplifying transistor; a first well region formed in the second semiconductor substrate in a region adjacent to the through-wire and to which a potential of the source of the amplifying transistor is applied; a second well region formed in the second semiconductor substrate; and an isolation unit that isolates the first well region from the second well region.

2. The photodetector element according to claim 1, wherein the amplifying transistor is disposed in the second well region.

3. The photodetector element according to claim 1, wherein the amplifying transistor is disposed in the first well region.

4. The photodetector element according to claim 1, further comprising a reset transistor for resetting the charge storage portion.

5. The photodetector element according to claim 4, wherein the reset transistor is disposed in the second well region.

6. The photodetector element according to claim 4, wherein the reset transistor is disposed on the first semiconductor substrate.

7. The photodetector element according to claim 1, further comprising a selection transistor that outputs the pixel signal based on a selection signal that is a control signal.

8. The photodetector element according to claim 7, wherein the selection transistor is disposed in the second well region.

9. The photodetector according to claim 1, wherein the separating portion is made of an insulating material.

10. The photodetector according to claim 1, wherein the isolation section is formed of a semiconductor region.

11. The photodetector according to claim 1, wherein the first well region is configured in a shape that surrounds the through-wiring.

12. The photodetector according to claim 1, wherein the second well region is disposed adjacent to the through-wiring.

13. The photodetector according to claim 12, wherein the first well region is disposed closer to the through-wiring than the second well region.

14. The photodetector according to claim 1, further comprising a third semiconductor substrate laminated on a surface of said second semiconductor substrate different from the surface on which said first semiconductor substrate is laminated.

15. The photodetector element according to claim 14, wherein a circuit for generating a control signal is disposed on the third semiconductor substrate.

16. The photodetector element according to claim 14, wherein a selection transistor that outputs the pixel signal based on a selection signal that is a control signal is disposed on the third semiconductor substrate.

17. The photodetector element according to claim 14, wherein a reset transistor for resetting the charge holding portion is disposed on the third semiconductor substrate.

18. The photodetector element according to claim 1, comprising a plurality of pixels each including the photoelectric conversion section, the charge storage section, the transfer transistor, the amplification transistor, the through wiring, the first well region, the second well region, and the isolation section.

19. The photodetector element according to claim 18, further comprising a pixel isolation region disposed between the first well regions of each of the plurality of pixels.

20. The photodetector according to claim 19, wherein the pixel isolation region is formed of a semiconductor region.

21. The photodetector according to claim 19, wherein the pixel isolation region is made of metal.

22. The photodetector element according to claim 18, wherein the first well region is commonly disposed for the amplification transistors of the adjacent pixels.

23. The photodetector element according to claim 1, further comprising a pixel signal line disposed in a wiring region of said second semiconductor substrate and transmitting said pixel signal.

24. The photodetector element according to claim 23, wherein the pixel signal lines are arranged at positions that do not overlap the first well region when viewed from the normal direction of the surface of the second semiconductor substrate.

25. An electronic device comprising: a photoelectric conversion unit disposed on a first semiconductor substrate for photoelectrically converting incident light; a charge holding unit disposed on the first semiconductor substrate for holding charges generated by the photoelectric conversion unit; a transfer transistor for transferring charges generated by the photoelectric conversion unit to the charge holding unit; an amplifying transistor disposed on a second semiconductor substrate stacked on the first semiconductor substrate for generating a pixel signal based on charges held in the charge holding unit and outputting the signal from its source; a through-wire configured in a pillar shape that passes through the second semiconductor substrate for transmitting a voltage corresponding to the charges held in the charge holding unit to the amplifying transistor; a first well region formed in the second semiconductor substrate in a region adjacent to the through-wire and to which a potential of the source of the amplifying transistor is applied; a second well region formed in the second semiconductor substrate; an isolation unit that isolates the first well region and the second well region; and a processing circuit for processing the pixel signal.

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