Sensor circuit and method

Abstract

A sensor circuit, method and apparatus are provided. A clock source may be configured to generate a clock signal. A plurality of samplers may be configured to receive a plurality of radio frequency signals and to produce, based on the clock signal, a plurality of low-frequency samples. A data analyzer may be configured to process low-resolution or medium-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances and process them at low or medium resolution to generate one or more data analysis metrics associated with the plurality of RF signals. The sensor circuit including samplers taking low-frequency samples, and a data analyzer processing low-resolution or medium-resolution representations of a number of samples collected over time for statistical analysis, provides power efficiency compared to known approaches that use power-hungry samplers at a high frequency.

Description

SENSOR CIRCUIT AND METHODFIELD

[0001] The present disclosure relates to electronic devices, including but not limited to a sensor circuit and associated systems, computing platforms, methods, and storage media.BACKGROUND

[0002] Analog circuits are used in a number of different applications. Radio frequency (RF) circuits are a subset of analog circuits that operate at radio frequencies. One example of an RF circuit is a power amplifier (PA). There are instances where it can be beneficial to sense one or more parameters relating to an RF circuit.

[0003] According to a known approach, a digital predistortion (DPD) filter linearizes a power amplifier. A sensor is provided at the output port, and the sensed signal is fed back through to a chip earlier in the transmit signal chain. The output signal of the PA goes back through an analog to digital converter (ADC), then undergoes digital processing, then that signal is used to drive a digital predistortion circuit meant to anticipate the non-linearities of the PA and effectively to cancel the distortion that would occur in respect of the original signal. Such a method is sampling at a high rate to effectively recapture the intended modulated signal and analyze it, which is very power hungry. The return path of the sensed signal is termed an observation loop which duplicates much of the functionality of signal reception and demodulation.

[0004] Environmental and manufacturing variations of the circuit may result in non-ideal performance characteristics for a power amplifier. Some known approaches to improving nonideal performance characteristics is to enable phase and gain control of an input signal before the input signal is provided to the power amplifier. However, such known approaches are not able to sufficiently account for both changes in environment and for manufacturing variances, resulting in undesirable performance characteristics for the power amplifier.

[0005] Improvements in approaches relating to sensor circuits are desirable.SUMMARY OF EMBODIMENTS

[0006] Embodiments of the disclosure can be described with reference to the followingclauses, with specific features laid out in the dependent clauses.

[0007] In accordance with an embodiment there is provided a radio frequency power amplifier comprising: a splitter configured to perform a distribution of an RF input signal into a plurality of sub-path input signals distributed over a plurality of paths; a plurality of sub-path control units configured to receive the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, each of the plurality of paths comprising at least one configurable sub-path, at least one of the sub-path output signals having a piecewise linear response; a plurality of sub-path combiners configured to combine the plurality of sub-path output signals into a plurality of path signals; and a path combiner configured to combine the plurality of path signals and to generate an RF output signal, the plurality of configurable sub-paths being configured, and the plurality of sub-path control units cooperating, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0008] In an example embodiment, the path combiner is configured to combine the plurality of path signals and to facilitate load modulation to achieve the power efficiency target.

[0009] In an example embodiment, at least one of the plurality of sub-path control units comprises an RF signal amplifier contributing to the one or more of phase control, gain control and bias control and to achieving the linearity target and / or another target or, alternatively multi variant targets.

[0010] In an example embodiment, each of the plurality of sub-path control units comprises an RF signal amplifier contributing to the one or more of phase control, gain control and bias control and to achieving the linearity target, the plurality of sub-paths being configured to use different biasing values for the RF signal amplifier in each configurable sub-path.

[0011] In an example embodiment, at least one of the plurality of sub-path control units comprises a piecewise-linear passive component configured to produce a piecewise-linear response for the configurable sub-path associated with the at least one of the plurality of sub-path control units.

[0012] In an example embodiment, the plurality of configurable sub-paths are configured andthe plurality of sub-path control units cooperate to produce a piecewise-linear response for one or more of the plurality of configurable sub-paths.

[0013] In an example embodiment, the plurality of configurable sub-paths are configured and the plurality of sub-path control units cooperate to produce a piecewise-linear response for one or more of the plurality of paths.

[0014] In an example embodiment, at least one of the plurality of sub-path control units is configured and the plurality of sub-path control units cooperate to produce a piecewise-linear response for one or more of the plurality of sub-paths.

[0015] In an example embodiment, the plurality of sub-path control units is configured to provide two or more of phase control, gain control and bias control to produce the plurality of sub-path output signals.

[0016] In an example embodiment, the plurality of sub-path control units is configured to provide phase control, gain control and bias control to produce the plurality of sub-path output signals.

[0017] In an example embodiment, at least one of the plurality of paths comprises at least two sub-paths.

[0018] In an example embodiment, the plurality of configurable sub-paths are configured, and the plurality of sub-path control units cooperate, to achieve an efficiency target with respect to one or more of the configurable sub-paths, the paths or the RF output signal.

[0019] In an example embodiment, the plurality of configurable sub-paths are configured, and the plurality of sub-path control units cooperate, to simultaneously achieve an efficiency target and the linearity target with respect to one or more of the configurable sub-paths, the paths or the RF output signal.

[0020] In an example embodiment, the plurality of configurable sub-paths are configured, and the plurality of sub-path control units cooperate, to simultaneously achieve the linearity target, the power efficiency target and a gain target with respect to one or more of the configurable sub-paths, the paths or the RF output signal.

[0021] In an example embodiment, at least one of the plurality of sub-path control units comprises a combined phase and gain controller configured to control phase and gain of aselected sub-path signal and to produce a corresponding sub-path output signal.

[0022] In an example embodiment, at least one of the plurality of sub-path control units comprises a bias voltage controller configured to control the bias voltage of a selected sub-path signal and to produce a corresponding sub-path output signal.

[0023] In an example embodiment, at least one of the plurality of sub-path control units comprises: a gain controller; and a phase controller; the phase controller being in coordination with the gain controller to provide a gain and phase controlled output signal.

[0024] In an example embodiment, the plurality sub-path control units is equal in number to the plurality of sub-path input signals, each of the plurality of sub-path control units being configured to receive a different one of the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control of the respective received sub-path signal, the plurality of sub-path control units producing the plurality of sub-path output signals.

[0025] In accordance with an embodiment there is provided a processor-implemented method for processing a radio frequency (RF) input signal, the method comprising: receiving the RF input signal; performing a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; performing one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a piecewise linear response; and combining the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0026] In accordance with an embodiment there is provided an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: receive the RF input signal; perform a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; perform one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, atleast one of the sub-path output signals having a piecewise linear response; and combine the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0027] In accordance with an embodiment there is provided a radio frequency power amplifier comprising: a splitter configured to perform a distribution of an RF input signal into a plurality of sub-path input signals distributed over a plurality of paths; a plurality of sub-path control units, each of the plurality of sub-path control units configured to receive a selected one of the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control of the selected one of the plurality of sub-path signals, the plurality of sub-path control units producing a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a piecewise linear response; and a combiner network configured to combine the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths being configured, and the plurality of sub-path control units cooperating, such that the RF output signal achieves a linearity target and / or a power efficiency target across a full amplitude range of the RF output signal.

[0028] In accordance with an embodiment there is provided a radio frequency power amplifier comprising: a splitter configured to perform a distribution of an RF input signal into a plurality of sub-path input signals distributed over a plurality of paths; a plurality of sub-path control units configured to receive the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, each of the plurality of paths comprising at least one configurable sub-path, at least one of the sub-path output signals having a non-linear response, a plurality of sub-path combiners configured to combine the plurality of sub-path output signals into a plurality of path signals; and a path combiner configured to combine the plurality of path signals and to generate an RF output signal, the plurality of configurable sub-paths being configured, and the plurality of sub-path control units cooperating, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0029] In accordance with an embodiment there is provided a processor-implementedmethod for processing a radio frequency (RF) input signal, the method comprising: receiving the RF input signal; performing a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; performing one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a non-linear response; and combining the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0030] In accordance with an embodiment there is provided an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: receive the RF input signal; perform a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; perform one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a non-linear response; and combine the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0031] In accordance with an embodiment there is provided a processor-implemented method for processing radio frequency signals, the method comprising: generating a clock signal; receiving a plurality of RF signals; producing, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency samples; processing low-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances; and generating a data analysis metric associated with the plurality of RF signals.

[0032] In a further embodiment, the present disclosure provides an apparatus comprising: a non-transient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: generatea clock signal; receive a plurality of RF signals; produce, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency-samples; process low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances; and generate a data analysis metric associated with the plurality of RF signals.

[0033] Embodiments of the present disclosure provides a system comprising low rate, low resolution sampling of an RF circuit, such as a power amplifier. Embodiments of the present disclosure may be used in applications such as RF & mmWave communications and sensing. Embodiments of the present disclosure provide low-power samplers, which may be sample-and- hold samplers, to measure a plethora of RF signals.

[0034] In some embodiments, a clock source is provided to drive samplers. The sampling rate is sub-Nyquist, and is asynchronous to an input RF signal. Alternatively, the sampling rate is sub-Nyquist and is synchronous to an input RF signal. Precise, adjustable delays are provided on clocks to various samplers. A signal conditioning circuit, e.g. a filter such as a harmonic filter, is provided ahead of the samplers in some embodiments.

[0035] At a data analyzer, a statistical ensemble of one-bit and / or multi-bit samples and sample correlations are collected, processed, and used to measure and / or analyze key metrics. For example, the data analyzer processes or generates low-resolution or medium-resolution representations of a plurality of low-frequency samples collected or accumulated over a plurality of sampling instances. Example metrics include: relative gain and phase, relative distortion, VSWR, voltage and current distributions, reliability protection, etc.

[0036] Embodiments of the present disclosure also enable phase and gain alignment of relative signals (e.g. Vi and Vo). Such an embodiment requires very good sampling clock stability and adjustability between the two samplers.

[0037] In accordance with an embodiment there is provided a computer program product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible, non- transitory medium, including magnetic, optical, or electrical storage medium including a compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray Disc Read Only Memory (BD-ROM), memory device (volatile or non-volatile), or similar storagemechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor or other suitable processing device, and can interface with circuitry to perform the described tasks.

[0038] The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art without departing from the scope, which is defined solely by the claims appended hereto.

[0039] Embodiments of the disclosure can be described with reference to the following clauses, with specific features laid out in the dependent clauses.

[0040] In an aspect, the present disclosure provides a sensor circuit comprising: a clock source configured to generate a clock signal; a plurality of samplers configured to receive a plurality of radio frequency signals and to produce, based on the clock signal, a plurality of low- frequency samples; and a data analyzer configured to process low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances and to generate a data analysis metric associated with the plurality of RF signals.

[0041] In an example embodiment, the circuit further comprises: a signal aligner configured to align a plurality of received clock signals for sampling, at each of the plurality of samplers, at the same relative waveform position on each of the plurality of RF signals.

[0042] In an example embodiment, the signal aligner further comprises: a plurality of delay elements each configured to apply a delay to one of the plurality of received clock signals and to provide a delayed clock signal to one of the plurality of samplers, the delays for the plurality of delay elements being configured for aligning the plurality of clock signals for sampling the plurality of RF signals at the same relative waveform position.

[0043] In an example embodiment, the plurality of samplers comprises a first sampler configured to receive a first RF signal and a second sampler configured to receive a second RF signal, and the signal aligner comprises: an alignment circuit controlled by the data analysismetric generated by the data analyzer and configured to enable phase alignment of first and second received clock signals to align sampling of the first and second RF signals.

[0044] In an example embodiment, the plurality of samplers comprises a first sampler configured to receive a first RF signal and a second sampler configured to receive a second RF signal, and the signal aligner comprises: an alignment circuit controlled by the data analysis metric generated by the data analyzer and configured to enable amplitude alignment of first and second received clock signals to align sampling of the first and second RF signals.

[0045] In an example embodiment, the plurality of samplers comprises a first sampler configured to receive an input RF signal with respect to a device-under-observation and a second sampler configured to receive a corresponding output RF signal, and the signal aligner comprises: an alignment circuit controlled by a metric generated by the data analyzer and configured to enable phase alignment or amplitude alignment of first and second received clock signals to align sampling of the input RF signal and the corresponding output RF signal.

[0046] In an example embodiment, the plurality of samplers are configured to produce the low-frequency samples at a sub-Nyquist sampling rate.

[0047] In an example embodiment, the plurality of samplers are configured to produce the low-frequency samples at a sampling rate that is asynchronous to the RF signal.

[0048] In an example embodiment, one or more of the plurality of samplers comprises a low- power sample-and-hold sampler.

[0049] In an example embodiment, the circuit further comprises: a signal conditioner configured to condition one or more of the plurality of RF signals prior to being provided to the samplers.

[0050] In an example embodiment, the data analyzer is configured to provide a generated data analysis metric as input information for provision to a controller to optimize performance of a device-under-observation producing an RF waveform.

[0051] In an example embodiment, the data analyzer is configured to perform data correlation to determine amplitude and phase relationships (BETWEEN WHAT).

[0052] In an example embodiment, the data analyzer is configured to generate the data analysis metric based on a low-resolution representation of a comparison of a plurality of low-frequency samples.

[0053] In an example embodiment, the data analyzer is configured to process mediumresolution representations of the plurality of low-frequency samples collected over the plurality of sampling instances.

[0054] In an example embodiment, the generated data analysis metric comprises at least one of relative gain; relative phase; relative distortion; voltage standing wave ratio (VSWR); voltage distribution; current distribution; and reliability protection.

[0055] In accordance with an embodiment there is provided a sensor system comprising: the sensor circuit as both generally and specifically described and illustrated herein; and an RF circuit configured to produce one or more of the plurality of RF signals.

[0056] In accordance with an embodiment there is provided a processor-implemented method for processing radio frequency signals, the method comprising: generating a clock signal; receiving a plurality of RF signals; producing, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency samples; processing low-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances; and generating a data analysis metric associated with the plurality of RF signals.

[0057] In accordance with an embodiment there is provided an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: generate a clock signal; receive a plurality of RF signals; produce, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency samples; processing low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances; and generate a data analysis metric associated with the plurality of RF signals.

[0058] In accordance with an embodiment there is provided a sensor circuit, comprising: a clock source configured to generate a clock signal; a sampler configured to receive a radio frequency signal and to produce, based on the clock signal, a low-frequency sample; and a data analyzer configured to process low-resolution representations of the low-frequency samples collected over a plurality of sampling instances and to generate a data analysis metric associatedwith the RF signal.

[0059] Among known approaches with respect to PA implementation is a Doherty amplifier. A Doherty amplifier is a simple load-modulated PA with 2 driver paths and 2 sub-paths, with only 1 sub-path per path. To achieve a linear output response, each path and sub-path in a Doherty amplifier must be linear. An embodiment of the present disclosure may comprise two paths, each with at least one sub-path, where at least one of the sub-paths has a piecewise linear response. Embodiments of the present disclosure may comprise N paths and M sub-paths per path, going far beyond the Doherty amplifier to achieve superior performance.

[0060] In an embodiment, the present disclosure provides a radio frequency power amplifier comprising: a splitter configured to perform a distribution of an RF input signal into a plurality of sub-path input signals distributed over a plurality of paths; a plurality of sub-path control units configured to receive the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, each of the plurality of paths comprising at least one configurable sub-path, at least one of the sub-path output signals having a piecewise linear response; a plurality of sub-path combiners configured to combine the plurality of sub-path output signals into a plurality of path signals; and a path combiner configured to combine the plurality of path signals and to generate an RF output signal, the plurality of configurable subpaths being configured, and the plurality of sub-path control units cooperating, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0061] In an embodiment, the present disclosure provides a processor-implemented method for processing a radio frequency (RF) input signal, the method comprising: receiving the RF input signal; performing a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; performing one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable subpaths, at least one of the sub-path output signals having a piecewise linear response; and combining the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves alinearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0062] In an embodiment, the present disclosure provides an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: receive the RF input signal; perform a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; perform one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a piecewise linear response; and combine the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0063] Embodiments of the present disclosure provide a load-modulated intelligent RF power amplifier comprising at least two and up to N driver paths, with at least one path, each path comprising up to M sub-paths. A set of up to M sub-paths may comprise a main sub-path, and zero or more secondary (or “kink”) sub-paths. A separate sub-path control unit may be provided for each configurable sub-path, providing one or more of fine phase control, gain control and bias control of the sub-paths, for optimization of one or more of gain, output power, linearity and efficiency.

[0064] In an embodiment, the present disclosure provides a radio frequency power amplifier comprising: a splitter configured to perform a distribution of an RF input signal into a plurality of sub-path input signals distributed over a plurality of paths; a plurality of sub-path control units configured to receive the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, each of the plurality of paths comprising at least one configurable sub-path, at least one of the sub-path output signals having a piecewise linear response; a plurality of sub-path combiners configured to combine the plurality of sub-path output signals into a plurality of path signals; and a path combiner configured to combine the plurality of path signals and to generate an RF output signal, the plurality of configurable sub-paths being configured, and the plurality of sub-path control units cooperating, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0065] In an embodiment, the present disclosure provides a processor-implemented method for processing a radio frequency (RF) input signal, the method comprising: receiving the RF input signal; performing a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; performing one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable subpaths, at least one of the sub-path output signals having a piecewise linear response; and combining the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0066] In an embodiment, the present disclosure provides an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: receive the RF input signal; perform a distribution of the RF input signal into a plurality of sub-path signals, the plurality of sub-path signals distributed over a plurality of paths; perform one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths, at least one of the sub-path output signals having a piecewise linear response; and combine the plurality of sub-path output signals to generate an RF output signal, the plurality of configurable sub-paths configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal.

[0067] In accordance with another embedment, a radio frequency power amplifier, apparatus and method for processing an RF input signal are provided comprising a splitter for distributing a first RF input signal into a plurality of sub-path input signals distributed over a plurality of paths. A plurality of sub-path control units each receive a subpath input signal of the plurality of subpath input signals and provides one or more of phase control, gain control and bias control toproduce a sub-path output signal within one of the plurality of subpath output signal paths. Each path comprising at least one configurable path and at least one sub-path signal having a piecewise linear response. A combiner network combines the plurality of sub-path output signals to generate an RF output signal. The plurality of configurable sub-paths are configured such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a predetermined amplitude range of the RF output signal.BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Embodiments of the present disclosure will now be described, by way of example only, with reference to the attached Figures.

[0069] FIG. l is a block diagram illustrating a sensor circuit, in accordance with one or more embodiments.

[0070] FIG. 2 is a block diagram illustrating a sensor circuit comprising a signal aligner, in accordance with one or more embodiments.

[0071] FIG. 3 is a functional block diagram illustrating an apparatus, in accordance with one or more embodiments, such as a sampler or a sensor circuit.

[0072] FIG. 4 illustrates a method for processing an RF signal, in accordance with one or more embodiments.

[0073] FIG. 5 is a block diagram illustrating a power amplifier, in accordance with one or more embodiments.

[0074] FIG. 6 illustrates a sub-path control unit for a sub-path of the power amplifier of FIG. 5, in accordance with one or more embodiments.

[0075] FIG. 7 illustrates a graph showing path output voltage versus path input voltage for a piecewise linear combination within a path in a power amplifier, in accordance with one or more embodiments.

[0076] FIG. 8 is a block diagram illustrating a power amplifier with N paths, in accordance with one or more embodiments.

[0077] FIG. 9 is a functional block diagram illustrating an apparatus, in accordance with oneor more embodiments, such as a power amplifier.

[0078] FIG. 10 illustrates a method for processing a signal in a power amplifier, in accordance with one or more embodiments.DETAILED DESCRIPTION

[0079] A sensor circuit, method and apparatus are provided. The sensor is described with reference to a radio frequency power amplifier.Definitions“absolute measurement” is a measurement in absolute terms or on a known scale;“align”: two signals are aligned when they share a timing quality one relative to another, for example two signals can be aligned based on period of a carrier wave;“clock signal” is a periodic signal for triggering an event;“clock source” is a port for receiving or a circuit for generating a clock signal;“data analysis metric” is a metric or number used for analysing or resulting from analysing data;“data analyzer” is a circuit, software process, or device for analysing data;“distributes”, “splits” is to separate a signal into parts where each part is a copy of the whole typically carrying less energy than the unsplit signal;“high frequency” as used herein with reference to sampling refers to samples taken at or above the Nyquist rate (or frequency);“Kink” is a change in linear response of a signal over a known range such that changing one or more characteristics of a combined signal can achieve a change in the combined signal;“low-frequency” is a range of frequencies below the Nyquist rate, and preferably less than half the Nyquist rate;“low frequency sample” is a sample sampled at a sampling rate below the Nyquist rate;“low-frequency sampling rate” is a sampling rate below the Nyquist sampling rate;“Low-Resolution” is a resolution at or below 6 bits;“Low-Resolution Low Frequency Samples” are samples having a resolution at or below 6 bits and sampled at below the Nyquist rate;“Low-Resolution Samples” are digital samples with a resolution of 6 bits or fewer;“Medium-resolution” relates to digital resolution supporting 7 - 9 bits;“Module” refers to any component or set of components that perform the functionality attributed to the module“Power amplifier” (PA) is an electronic component for amplifying a signal in amplitude;“Power-hungry” is a process that consumes a significant portion of the power consumed by a circuit or a segment of a circuit; the term is generally used in relation to circuits where a lower power design would significantly impact the overall circuit power consumption;“Process low-resolution representations of the low-frequency samples” involves forming data driven results based on poor quality data, for example data that is insufficient in frequency and that is insufficient in quantization;“Radio Frequency” (RF) is a portion of the electromagnetic frequency spectrum;“Radio frequency (RF) signal” is a signal within the Radio Frequency portion of the electromagnetic frequency spectrum;"Same relative waveform position” refers to a position within a waveform that is aligned with a position within another waveform, the two waveforms align-able as to beginning of a period and the period to which it pertains;“Same waveform” refers to two different signals, each a same or modified version of a same waveform;“Sampler” is a circuit or process that determines samples of a signal at intervals;“Sampling clock signals” are clock signals for triggering sampling of signal to be sampled;“Sampling instances” are individual samples within a stream of samples;“Sensor circuit” is a circuit for sensing some real world aspect of an optical or electronic signal;“Signal aligner” is a circuit or process to one of align two signals or align a relative clock for aligning sampling of two signals;“Statistically relevant information about the waveform and about a relative measure of each different signal is a term used to refer to information usable by or generated by an expert system,an Al, and / or a correlation process, for example a trained software system, for effecting a quality of an output waveform signal from a circuit to improve the output waveform relative to some criteria; and“Time within the waveform” is a reference to a particular position in a waveform representing the same information and the same phase within the signal.

[0080] A clock source is configured to generate a clock signal. A plurality of samplers are configured to receive a plurality of radio frequency signals and to produce, based on a plurality of sampling clock signals derived from the clock signal, a plurality of low-frequency samples, in the form of low-resolution representations of samples. A data analyzer is configured to process the low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances and to generate one or more data analysis metrics associated with the plurality of RF signals. A signal aligner may be configured to align relatively the plurality of RF signals for sampling and associated sampling clock signals, at each of the plurality of samplers, at the same position on a waveform of the RF signals. A sensor circuit including samplers taking low-frequency samples, and a data analyzer processing low-resolution or medium-resolution representations of a number of samples over time for statistical analysis, provides power efficiency compared to known approaches that use power-hungry samplers at a high frequency. For example, commonly used sampling circuits for sampling with n-bits use 2An power. Thus for a single bit, 2 units of power are needed, but for 4 bits 16 units of power are needed. Thus, a sampling circuit of this type used to sample 32 signals within a single circuit is relatively power hungry when n=12 compares to when n=2. The quantity of sampling circuits, their frequency of sampling, and their resolution (n) all contribute to the power consumption associated with taking samples of the RF signal.

[0081] As described above, a known approach using a digital predistortion filter relies on feedback outside of the chip, and runs at a high sampling rate, typically at or above the Nyquist rate, with high resolution samples, which is very power hungry. The Nyquist theorem defines the Nyquist rate as twice the highest frequency of a function or signal to be measured accurately. In an example implementation, the output frequency can be 1 GHz bandwidth, and a digital predistortion filter requires an ADC to sample at 3-5 GHz and high resolution, which would be extremely power hungry. The ADC in this known approach may comprise a 12-bit or 14-bitADC, which consumes a lot of power, and each sample may be useful in itself.

[0082] In an embodiment, the present disclosure provides a sensor system comprising: a sensor circuit as both generally and specifically described and illustrated herein; and an RF circuit configured to produce one or more of the plurality of RF signals.

[0083] In an embodiment, the present disclosure provides a processor-implemented method for processing radio frequency signals, the method comprising: generating a clock signal; receiving a plurality of RF signals; producing, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency low resolution samples; processing low-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances; and generating a data analysis metric associated with the plurality of RF signals.

[0084] In an embodiment, the present disclosure provides an apparatus comprising: a nontransient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: generate a clock signal; receive a plurality of RF signals; produce, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency samples; processing low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances; and generate a data analysis metric associated with the plurality of RF signals.

[0085] In an embodiment, the present disclosure provides a sensor circuit, comprising: a clock source configured to generate a clock signal; a sampler configured to receive a radio frequency signal and to produce, based on the clock signal, a low-frequency sample; and a data analyzer configured to process low-resolution representations of the low-frequency samples collected over a plurality of sampling instances and to generate a data analysis metric associated with the RF signal.

[0086] For the purpose of promoting an understanding of the principles of the disclosure, reference will now be made to the features illustrated in the drawings and specific language will be used to describe the same. It will nevertheless be understood that no limitation of the scope of the disclosure is thereby intended. Any alterations and further modifications, and any further applications of the principles of the disclosure as described herein are contemplated as would normally occur to one skilled in the art to which the disclosure relates. It will be apparent to those skilled in the relevant art that some features that are not relevant to the present disclosuremay not be shown in the drawings for the sake of clarity.

[0087] Certain terms used in this application and their meaning as used in this context are set forth in the description below. To the extent a term used herein is not defined, it should be given the broadest definition persons in the pertinent art have given that term as reflected in at least one printed publication or issued patent. Further, the present processes are not limited by the usage of the terms shown below, as all equivalents, synonyms, new developments and terms or processes that serve the same or a similar purpose are considered to be within the scope of the present disclosure.

[0088] The present disclosure relates to statistical sensors for in-situ observation of an RF circuit, such as a power amplifier. Other non-limiting examples of an RF circuit include an optical driver, an optical receiver, a low-noise amplifier, an analog to digital converter (ADC), and a digital to analog converter (DAC). A sensor circuit as described herein optionally comprises one or more samplers, and optionally includes delay adjustment or other circuitry.

[0089] A sensor circuit in accordance with one or more embodiments is optionally provided as an add-on to the RF circuit being observed. The sensor circuit in accordance with one or more embodiments and the RF circuit being observed is optionally provided as components of a sensor system in accordance with one or more embodiments.

[0090] According to one or more embodiments of the present disclosure, the sensor circuit is contained entirely in the same chip as the RF circuit being observed and employs sub-Nyquist sampling. According to one or more embodiments of the present disclosure, the sensor circuit is co-integrated into the same chip package as the RF circuit being observed. According to one or more embodiments of the present disclosure, the sensor circuit is provided on same printed circuit board as the RF circuit being observed Sensors or samplers may comprise very low power sample-and-holds, and a clock source may be provided to drive the samplers. The clock rate of the clock source may be independent of the RF signal.

[0091] An example implementation may run the clock rate at 1 GHz, even though the RF signal is at 28 GHz. This results in low power, samples, and the sensor circuit collects many of those samples. The system may accumulate or assemble the samples into data for analysis, for example by a controller that is used to make diagnostic observations, and close the loop for live operation. The controller may be provided anywhere in relation to the sensor circuit and may, inan example embodiment, be on the same chip as the sensor circuit.

[0092] FIG. 1 is a block diagram illustrating a sensor circuit 100, in accordance with one or more embodiments. The sensor circuit 100 may comprise a clock source 110 configured to generate a clock signal 120. A clock rate associated with the clock signal 120 may be used to establish a sampling rate of the sensor circuit 100. The clock signal may have a clock rate that is asynchronous to a received RF signal, or independent of the RF signal. An advantage of the clock rate being asynchronous to the RF signal is that it is not necessary to know or determine the frequency of the RF signal. Another advantage of the clock rate being asynchronous to the RF signal is that a wider range of clock rates may be used to provide sampling, since there is no requirement for the sampling rate to be synchronous with the RF signal.

[0093] For example, for an RF signal having a frequency of 28 GHz, a clock signal having a clock rate of 1.1 GHz or 1.2 GHz may be used. While this may result in sampling the RF signal at different positions or points on the waveform from one sample to another, when the sampling is performed over a plurality of sampling instances, a sufficient number of samples are collected over time to obtain relevant and accurate data. In another embodiment, the clock signal has a clock rate that is synchronous to the RF signal. The clock rate of the clock signal is synchronous to the received RF signal, for example by detecting the RF signal frequency and producing a clock that is a fraction of that frequency. In an example embodiment, the clock source generates the clock signal with a clock rate of 1 GHz and the received RF signal has a frequency of 28 GHz.

[0094] A plurality of samplers 130. . . 132 are configured to receive a plurality of radio frequency signals, for example RF signal 1 through to RF signal N, as shown in FIG. 1, and to receive the clock signal generated by the clock source 110. In the embodiment of FIG. 1, the same clock signal 120 is provided to plurality of samplers 130. . . 132. The plurality of samplers 130. . . 132 are configured to produce, based on the clock signal 120, a plurality of low-frequency samples 140. . . 142. The samplers are low power and low frequency, which is dictated by the clock source. One or more of the samplers obtains the clock, make its sample, and feed the sampler output data to a data analyzer. Other samplers in the system may be configured to do the same thing and keep gathering these samples up over and over.

[0095] In an example implementation, first sampler 130 is configured to produce a firstsample 140 based on the received RF signal 1 and the clock rate of the clock signal 120. Second sampler 132 is configured to produce a second sample 142 based on the received RF signal N and the clock rate of the clock signal 120. One or more of the plurality of low-resolution samplers 130. . . 132 comprises a low-power sample-and-hold sampler, providing both low- frequency and low-power functionality.

[0096] The plurality of samplers 130. . . 132 are configured to produce the low-frequency samples at a sub-Nyquist sampling rate. Sampling at a low-frequency such as a sub-Nyquist sampling rate contributes to embodiments of the present disclosure providing power savings and advantages compared to known approaches that are power hungry when sampling at a higher frequency, such as at or above the Nyquist rate. The plurality of samplers 130. . . 132 are configured to produce the low-frequency-samples at a sampling rate that is asynchronous to the RF signal, or that is synchronous to the RF signal.

[0097] A data analyzer 150 is configured to process low-resolution representations of the plurality of low-frequency samples 140. .. 142 collected or accumulated over a plurality of sampling instances and to generate a data analysis metric 152 associated with the plurality of RF signals. Known approaches typically use the full resolution output data of a sampler. For example, for a 12-bit sampler, the 12-bit sample would be collected and processed. According to one or more embodiments, the data analyzer 150 is configured to process low-resolution representations of the plurality of low-frequency samples, for example based on the original received resolution of the received low-frequency samples. The data analyzer 150 is configured to produce or generate the low-resolution representations of the plurality of low-frequency samples collected or accumulated over the plurality of sampling instances.

[0098] In an example embodiment, a low-resolution representation comprises a 1 -bit representation. In an example embodiment, a low-resolution representation comprises a multi-bit representation, where multi-bit may be anywhere from a 2 -bit representation to an 8-bit representation. An 8-bit representation is sometimes considered a medium-resolution representation, which may be processed or provided according to an embodiment. A known DPD system uses a high-resolution sampler with a resolution of about 12-14 bits, which is very power intensive relative to a lower resolution sampler. Embodiments presented herein provide power efficiency and power savings compared to known approaches by processing low-resolutionrepresentations of the plurality of low-frequency samples, or by processing medium-resolution representations of the plurality of low-frequency samples.

[0099] When using a sampler to produce a low-frequency sample, collecting a small number of samples such as 1-10 samples would not provide an accurate measurement. The plurality of sampling instances may comprise thousands of samples, hundreds of thousands of samples, a million samples, or more. The data analyzer 150 is configured to process low-resolution representations of such a plurality of low-frequency samples, which are collected over a plurality of sampling instances. The data analyzer 150 is configured to generate one or more data analysis metrics 152 and is configured to generate a plurality of data analysis metrics.

[0100] In an example embodiment, the data analyzer 150 is configured to process low- resolution representations of the plurality of low-frequency samples 140. .. 142 collected or accumulated over a plurality of sampling instances and to generate a data analysis metric 152 associated with the plurality of RF signals.

[0101] In an example embodiment, the data analyzer 150 is configured to generate the data analysis metric 152 based on a low-resolution representation of a comparison of the plurality of low-frequency samples. For example, when the low-resolution representation comprises a 1 -bit representation, the data analyzer 150 is configured to compare a first 1 -bit representation of a sample with a second 1 -bit representation of a sample. The data analyzer 150 is configured to collect comparisons of samples. In an example implementation, the data analyzer 150 comprises a comparator or a 1 -bit ADC is configured to generate a 1 -bit representation of a sample, and to determine whether a sample from a first sampler is greater than a sample from a second sampler. These implementations are extremely different from known DPD approaches which operate using the high-resolution samples.

[0102] Of note, because of the asynchronous low-frequency samples, the overall transform of input RF signal to output RF signal is not determined based on contiguous RF signal portions. Instead, samples are from different periods of the RF signal and are used in aggregate to statistically model aspects of the circuit - how the circuit transforms the input signal to form the output signal. In this way, a single period of the RF signal is not sampled at the input port and then again at the output port for comparison to determine a circuit transformation. Instead, a plurality of input samples having a correlation to a plurality of output samples is statisticallyrelied upon to estimate the circuit transformation.

[0103] In an example embodiment, the data analyzer 150 performs data analysis using low- resolution quantized samples, medium-resolution quantized samples, or a comparison of samples. Sampling takes an analog snapshot in time of a continuous time-series like waveform. Samples may be quantized to represent the analog snapshot with a finite number of representations in the voltage domain, such as N bits between 0 volts and 1 volt. For example, an 8-bit quantization comprises 256 possible representations, while a 1 -bit quantization results in only 2 possible representations.

[0104] In an example embodiment, the data analyzer 150 is configured to perform statistical data assembly with respect to the processed low-resolution representations of the collected plurality of low-frequency samples. In an example embodiment, the data analyzer 150 may build up a histogram based on the processed low-resolution representations of the collected plurality of low-frequency samples, for example using 1 -bit or multi-bit representations. For example, a sampler is provided that has a threshold of zero, so that a sample with a value of 1 is produced for a positive value and a sample with a value of 0 is produced for a negative value. The sampling point may move around on the waveform of the signal, for example when the sampling rate is asynchronous with respect to the RF signal frequency, such as a sampling rate of 1.2 GHz and an RF frequency of 27 GHz. When only 3 samples are collected with values of 1, 1, 1, a related histogram would include a count of 3 positives and zero negatives, which would be statistically inaccurate. However, when the data analyzer 150 collects a large number of samples, such as a million samples, the result is statistically relevant.

[0105] In an example embodiment, the data analyzer 150 is configured to generate the data analysis metric 152 associated with the plurality of RF signals, where the data analysis metric comprises a metric of gain. The metric of gain requires two signals. Other metrics may just use one signal, or one of the collected signals. Another example metric is DC offset. Statistical data assembly by the data analyzer 150 employs many, many processed low-resolution representations of the samples to build a metric. Embodiments of the present disclosure essentially sacrifice sample resolution when processing the samples, compared to known approaches such as DPD, and gather a large amount of data, and obtain good results from gathering this large amount of data. In an example implementation, the data analyzer 150 usestens of thousands, or closer to a million or more, samples to provide accurate results.

[0106] In an example embodiment, the data analyzer 150 is configured to provide the generated data analysis metric 152 as input data to a controller (not shown in FIG. 1) to optimize performance of a device-under-observation producing the RF waveform. In such an implementation, the controller controls parameters associated with the device-under-observation. In an example embodiment, the data analyzer 150 is configured to perform data correlation to determine amplitude and phase relationships. In an example embodiment, the generated data analysis metric 152 comprises: relative gain; relative phase; relative distortion; voltage standing wave ratio (VSWR); voltage distribution; current distribution; and / or reliability protection. Alternatively, the data analysis metric 152 comprises other parameters or characteristics that are relevant.

[0107] When compared to a known DPD approach, embodiments of the present disclosure often collect a similar number of samples. The DPD approach collects samples at a higher clock rate than embodiments of the present disclosure, and each DPD sample is captured with a higher resolution than the low-resolution representations of the samples of embodiments of the present disclosure. A DPD approach compensates digitally by expanding the signal, to invert the compression that is happening, and high-resolution information is collected to be able to do this. Embodiments of the present disclosure may use the data analysis metric 152 as input data to a controller, for example associated with a power amplifier being observed, to adjust gains, phases and / or bias voltages within the amplifier.

[0108] The data analyzer 150 is configured to assemble statistical data, or to assemble data in a statistical manner, for example based on a large number data set, or a data set with a large number of samples. The samples are optionally collected and assembled into a structure, for example a histogram of positive / negative bins. The data analyzer 150 assembles the processed low-resolution representations of the samples into a data set with a count of, for example, two or more “bins”, where putting the processed low-resolution representations of the samples into bins is part of the assembly process. The data analyzer 150 optionally performs post-processing, for example based on one or more mathematical operations, to make the samples into a usable data structure. The data analyzer 150 comprises one or more of hardware, firmware and software. A controller, for example built with a neural network, may be configured to take the statistical data,for example one or more data analysis metrics 152, and use the metric(s) as input value(s) to determine how to control a device-under-observation.

[0109] Consider an example where the data analyzer 150 is configured to generate a data analysis metric 152 relating to gain. The data analyzer 150 generates a statistical structure of values that relate to gain, based on processed low-resolution representations of the plurality of low-frequency samples collected or accumulated over a plurality of sampling instances. Such operations form a signature that the data set comprises 100 elements, and the data analyzer is configured to generate a histogram with 100 bins, one for each element. A controller is configured to, for example based on training and on the received data analysis metric 152, determine that the gain is too low, and to generate information or a control signal to bump up the bias voltage to get more gain. In an embodiment, statistical data such as the data analysis metric 152 is employed by a feedback controller to adjust the system to optimize performance.

[0110] In many instances, a plurality of samplers is used, as shown in FIG. 1, for example when it is desirable to concurrently obtain a plurality of samples, for example from an input signal and output signal (e.g. Vin and Vout) of a device-under-observation. In other instances, it is desirable to capture absolute signal statistics on one measurement, for example amplitude of an input signal of an RF amplifier. In an example embodiment, a sensor circuit only has one sampler, and just one bit moves a threshold with respect to the amplitude, such as the amount of amplitude. The sensor circuit assembles an output gain from one sampler. This is referred to as an absolute measurement.

[0111] According to an example embodiment, a single sampler is provided in the sensor circuit. In such an embodiment, the present disclosure provides a sensor circuit, comprising: a clock source configured to generate a clock signal; a sampler configured to receive a radio frequency signal and to produce, based on the clock signal, a low resolution low-frequency sample; and a data analyzer configured to process the low-resolution low-frequency samples collected over a plurality of sampling instances and to generate a data analysis metric associated with the RF signal. In this embodiment, low-resolution representations of the samples produced by the sampler are collected, and the data analysis metric is generated based on the plurality of sampling instances of the processed low-resolution representations of the low-frequency sample produced by the sampler. Alternatively, a lower resolution low frequency sample is used than thelow resolution low frequency sample received.

[0112] FIG. 2 is a block diagram illustrating a sensor circuit 200 comprising a signal aligner, in accordance with one or more embodiments. As many elements in FIG. 2 are similar to corresponding elements in FIG. 1, detailed discussion of those elements will be omitted; reference is made to related description with respect to FIG. 1. The sensor circuit 200 comprises a clock source 210 in the form of a circuit configured to generate a clock signal 220, optionally provided as a plurality of clock signals 220. The clock signal(s) have a clock rate that is asynchronous to a received RF signal, resulting in greater flexibility. Alternatively, the clock signal(s) are synchronous with the RF signal.

[0113] A plurality of samplers 230. . .232 are configured to receive a plurality of radio frequency signals, for example RF signal 1 through to RF signal N, as shown in FIG. 2, and to receive a plurality of clock signals 220.

[0114] The circuit 200 optionally comprises a signal aligner 260 configured to align a plurality of received clock signals for sampling, at each of the plurality of samplers 230. . .232, at the same relative waveform position on each of the plurality of RF signals. This may be described as sampling at each of the plurality of samplers at a consistent relative waveform position on each of the plurality of RF signals. For example, the signal aligner aligns the plurality of clock signals such that the RF signals are sampled at the same position on the RF signal waveform by each of the plurality of samplers 230. . .232, so as to provide a relative measurement involving two or more elements. For example, in relation to a PA that has an input port and output port, the sensor circuit is configured to measure the gain between the input port and the output port. The signal aligner aligns the sampling clocks to compensate for delays in the circuit, take the output signals from the two samplers (input 1st RF signal and output 2nd RF signal) and combine them in a different way and measure gain, or another parameter, as a relative measurement. The same circuit with three subpaths within the amplifier can sample at 5 places in the circuit - input port, output port, and 3 intermediary ports. Aligning the RF signal sampling to a same relative location within the RF signals allows for sampling of each signal at a same relative position for direct comparison.

[0115] In an example of relative measurement of Vi and Vo, when passing through a sinusoid into PA, an RF signal may come in at a 1 V peak and come out at a 5 V peak, but it isan oscillating waveform. The signal aligner 260 is configured to align the clock signals or sampling clocks to a same relative point on the waveform - a same phase and period, for example to measure at the peak of each waveform. Without the signal aligner, when the measurement is out of phase by 90 degrees, the sampler may sample zero and 5 V.

[0116] The signal aligner 260 optionally comprises hardware, firmware and / or software components. The signal aligner 260 optionally comprises an alignment circuit. In an example embodiment, the plurality of samplers comprises a first sampler 230 configured to receive a first RF signal 1 and a second sampler 232 configured to receive a second RF signal N. In such an example embodiment, the signal aligner 260 comprises an alignment circuit controlled by a data analysis metric generated by the data analyzer and configured to enable phase alignment of received clock signals to align sampling of the first and second RF signals.

[0117] In another example embodiment, the plurality of samplers comprises a first sampler 230 configured to receive a first RF signal 1 and a second sampler 232 configured to receive a Nth RF signal N. The signal aligner 260 comprises an alignment circuit controlled by a data analysis metric generated by the data analyzer and configured to enable amplitude alignment, or gain alignment, of first and second received clock signals to align sampling relative to each of the first and Nth RF signals.

[0118] In a further example embodiment, the plurality of samplers comprises a first sampler 230 configured to receive an input RF signal with respect to a device-under-observation and a second sampler 232 configured to receive a corresponding output RF signal. The signal aligner 260 comprises an alignment circuit controlled by a data analysis metric generated by the data analyzer and configured to enable phase alignment or amplitude alignment of first and second received clock signals to align sampling of the input RF signal and the corresponding output RF signal.

[0119] In an example embodiment, the signal aligner 260 forms part of a feedback loop provided to align signals, which are, for example, dynamically adjusted. For example, when the temperature changes, the gain may change. The signal aligner 260 comprises hardware, software and / or firmware configured to obtain and observe statistical data, for example from the data analyzer 250, and observe that collected samples comprise a lot of sampling of zero volts at the input port, indicating that it is not properly aligned. The signal aligner 260 is configured to movethe sampling point based on the detected samples having a particular characteristic, such as being at zero volts. There are a number of different approaches to align signals, and the signal aligner 260 employs one or more of those alignment approaches.

[0120] In an example embodiment as shown in FIG. 2, the signal analyzer 260 further comprises a plurality of delay elements. Each of the plurality of delay elements is configured to apply a delay to a respective one of the plurality of received clock signals 220 and to provide a delayed clock signal to at least one of the plurality of samplers. For example, first delay element 270 is configured to apply a first delay to the clock signal 220 to provide a first delayed clock signal 280 to a first sampler 230. Similarly, second delay element 272 is configured to apply a second delay to the clock signal 220 to provide a second delayed clock signal 282 to a second sampler 232. The delays for the plurality of delay elements, which in FIG. 2 are delay elements 270 and 272, are configured for relatively aligning the plurality of clock signals to align sampling of the plurality of RF signals relative to a phase of each RF signal, e.g. RF signal 1 and RF signal N, are sampled at approximately the same relative waveform position on each of the RF signal waveforms, by the samplers 230 and 232.

[0121] The delay elements are employed to perform relative measurement. For example, to measure the gain and phase differences between RF signal 1 and RF signal N, it is statistically relevant to align the clocks so that they sample at the same relative position - period and phase - on the RF signal waveform. The delay blocks align sampling to the same relative positions on the RF signal, for example ensuring that both samples are at a peak of a RF signal cycle, or at least that the samples are taken for different input RF signals at the same relative position on the signal. When the signals are not aligned, for example no delay is introduced, the sensor circuit may obtain uncorrelated relative measurements over and over that do not provide valuable statistical information. As an example, with a clock rate of 1.1 GHz and carrier frequency of 27GHz, the sampling clock is moving relative to the signal. The sensor circuit may slide across the carrier wave period. Relative signals are occurring at the same point in the period, based on use of the delays. The delay blocks ensure that the two samplers are sampling at the same relative point in the signal period for the two signals being sampled. This is statistically advantageous when relying on asynchronous or sub-Nyquist sampling.

[0122] Alternatively, sampling is aligned relative to the waveform but not relative to eachsample allowing for a different statistical correlation including relative measurement of different parts of the waveform over time.

[0123] The plurality of samplers 230. . .232 are configured to sample a plurality of radio frequency signals, for example RF signal 1 through to RF signal N, as shown in FIG. 2, and to receive the respective delayed clock signals 280. . .282 generated by the clock source 210 via the signal aligner 260, as described above. The plurality of samplers 230. . .232 are configured to produce, based on the respective delayed clock signals, a plurality of low-frequency samples240. . .242. For example, first sampler 230 is configured to produce a first sample 240 based on the received RF signal 1 and the clock rate of the first delayed clock signal 280. Second sampler 232 may be configured to produce a second sample 242 based on the received RF signal N and the clock rate of the second delayed clock signal 282.

[0124] The plurality of samplers 230. . .232 are configured to produce the low-frequency samples at a sub-Nyquist sampling rate. Sampling at a low-frequency sampling rate such as a sub-Nyquist sampling rate contributes to embodiments of the present disclosure providing power savings and advantages compared to known approaches that are power hungry when sampling at a higher frequency, such as at or above the Nyquist sampling rate. The plurality of samplers230. . .232 are configured to produce low-frequency-samples at a low frequency sampling rate asynchronous to the RF signal. Alternatively, the plurality of samplers 230. . .232 are configured to produce low-frequency-samples at a low frequency sampling rate synchronous to the RF signal.

[0125] One or more of the plurality of samplers 130. . . 132 comprises a 1 -bit sampler. Alternatively one or more of the plurality of samplers 130. . . 132 comprises a multi-bit sampler in the form of a low-power sample-and-hold sampler.

[0126] A data analyzer 250 is configured to process low-resolution representations of the plurality of low-frequency samples 240. . .242 collected or accumulated over a plurality of sampling instances and to generate a data analysis metric 252 associated with the plurality of RF signals. In an example embodiment, the data analyzer 250 is configured to process mediumresolution representations of the plurality of low-frequency samples. In an example embodiment, the data analyzer 250 is configured to produce or generate low-resolution or medium-resolution representations of the plurality of low-frequency samples. In an example embodiment, the dataanalyzer 250 is configured to generate a plurality of data analysis metrics 252 associated with the plurality of RF signals.

[0127] In an example embodiment, the data analyzer 250 is configured to provide the generated data analysis metric 252 as input information for provision to a controller (not shown in FIG. 1) to optimize performance of a device-under-observation, the device producing the RF waveform. In such an implementation, the controller controls parameters associated with the device-under-observation. In an example embodiment, the data analyzer 250 is configured to perform data correlation to determine amplitude and phase relationships between RF signals. In an example embodiment, the generated data analysis metric 252 comprises: relative gain; relative phase; relative distortion; voltage standing wave ratio (VSWR); voltage distribution; current distribution; or reliability protection, or any other parameters or characteristics that are relevant to performance and determinable between two or more RF signals. In some embodiments, only parameters and characteristics relating to controllable performance are analysed.

[0128] The data analyzer 250 receives samples to process in 1 -bit or multi -bit form. In an embodiment, each sampler comprises a low power sampler running at a low clock rate below the Nyquist rate. The data analyzer 250 collects information about various RF signals, builds up statistics about what was observed, uses the built-up statistics to generate first metrics, and provides a feedback signal based on the first metrics. Alternatively, the data analyzer 250 collects information about various RF signals to generate properties for first metrics.

[0129] FIG. 3 is a functional block diagram illustrating an apparatus 300, in accordance with one or more embodiments, such as a sampler or a sensor circuit. The embodiments of FIG. 1 and FIG. 2 illustrate a sensor circuit in specific implementations, which may be implemented in a product and at one location, for example with all of the elements being on-chip. The embodiment of FIG. 3 illustrates that some functionality is optionally distributed or provided as modules, either internal or external to the chip.

[0130] In some embodiments, system 300 includes one or more computing platforms 302. Computing platform(s) 302 are configured to communicate with one or more remote platforms 304, for example according to a client / server architecture, a peer-to-peer architecture, and / or other architectures. Remote platform(s) 304 is configured to communicate with other remote platforms, for example via computing platform(s) 302 and / or according to a client / serverarchitecture, a peer-to-peer architecture, and / or other architectures. Users typically access system 300 via remote platform(s) 304.

[0131] Computing platform(s) 302 is configured by machine-readable instructions 306. Machine-readable instructions 306 include one or more instruction modules. The instruction modules include computer program modules. The instruction modules include one or more of clock module 308, sensor module 310, data analyzer module 312, and other instruction modules.

[0132] Clock module 308 is configured to generate a clock signal. Alternatively, clock module 308 is configured to generate a plurality of clock signals each having a same clock period but a different clock phase. Further alternatively, clock module 308 is configured to generate a plurality of clock signals.

[0133] Sensor module 310 is configured to receive a plurality of RF signals. Sensor module 310 is configured to produce, based on the clock signal(s) and the plurality of RF signals, a plurality of low-frequency-samples.

[0134] Data analyzer module 312 is configured to process the plurality of low-frequency samples over a plurality of sampling instances. Data analyzer module 312 is configured to generate at least a data analysis metric, associated with the plurality of RF signals. In some embodiments, the low-frequency samples comprise low-resolution low-frequency-samples.

[0135] In one or more embodiments, one or more of the features and characteristics described above in relation to the clock source 110 of FIG. 1 or the clock source 210 of FIG. 2 are applied to the clock module 308. In one or more embodiments, one or more of the features and characteristics described above in relation to the samplers 130. . . 132 of FIG. 1 or the samplers 230. . .232 of FIG. 2 are applied to the sensor module 310. In one or more embodiments, one or more of the features and characteristics described above in relation to the data analyzer 150 of FIG. 1 or the data analyzer 250 of FIG. 2 are applied to the data analyzer module 312.

[0136] In some embodiments, computing platform(s) 302, remote platform(s) 304, and / or external resources 314 are operatively linked via one or more electronic communication links. For example, electronic communication links are established, at least in part, via a network such as the Internet and / or another network. Alternatively, the electronic communication link is apeer-to-peer wireless communication link. It will be appreciated that this is not intended to be limiting, and that the scope of this disclosure includes implementations in which computing platform(s) 302, remote platform(s) 304, and / or external resources 314 are operatively linked via some other communication medium.

[0137] A given remote platform 304 includes one or more processors configured to execute computer program modules. The computer program modules are configured to enable an expert or user associated with the given remote platform 304 to interface with system 300 and / or external resources 314, and / or provide other functionality attributed herein to remote platform(s) 304. By way of non-limiting example, a given remote platform 304 and / or a given computing platform 402 includes one or more of a server, a desktop computer, a laptop computer, a handheld computer, a tablet computing platform, a NetBook, a Smartphone, a gaming console, and / or other computing platforms.

[0138] External resources 314 include sources of information outside of system 300, external entities participating with system 300, and / or other resources. In some embodiments, some or all of the functionality attributed herein to external resources 314 is provided by resources included in system 300.

[0139] Computing platform(s) 302 includes electronic storage 316, one or more processors 318, and other components. Computing platform(s) 302 includes communication ports to enable the exchange of information with other components, for example via a network. Illustration of computing platform(s) 302 in FIG. 3 is not intended to be limiting. Computing platform(s) 302 include a plurality of hardware, software, and / or firmware components operating together to provide the functionality attributed herein to computing platform(s) 302. For example, computing platform(s) 302 is implemented by one or more cloud of computing platforms operating as computing platform(s) 302.

[0140] Electronic storage 316 comprises non-transitory storage media that electronically stores information. The electronic storage media of electronic storage 316 at least one of system storage that is provided integrally (i.e., substantially non-removable) with computing platform(s) 302 and removable storage that is removably connectable to computing platform(s) 302 via, for example, a port (e.g., a USB port, a firewire port, etc.). Electronic storage 316 includes one or more of optically readable storage media (e.g., optical disks, etc.), magnetically readable storagemedia (e.g., magnetic tape, magnetic hard drive, floppy drive, etc.), electrical charge-based storage media (e.g., EEPROM, RAM, etc.), solid-state storage media (e.g., flash drive, etc.), and / or other electronically or optically readable storage media. Electronic storage 316 optionally includes one or more virtual storage resources (e.g., cloud storage, a virtual private network, and / or other virtual storage resources). Electronic storage 316 optionally stores software algorithms, data determined by processor(s) 318, data received from computing platform(s) 302, data received from remote platform(s) 404, and / or other data that enables computing platform(s) 302 to function as described herein.

[0141] Processor(s) 318 are configured to provide information processing capabilities in computing platform(s) 302. As such, processor(s) 318 includes one or more of a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and other mechanisms for electronically processing information. Although processor(s) 318 is shown in FIG. 3 as a single entity, this is for illustrative purposes only. In some embodiments, processor(s) 318 includes a plurality of processing units. These processing units are physically located within the same device. Alternatively, processor(s) 318 represent processing functionality of a plurality of devices operating in coordination. Processor(s) 318 are configured to execute modules 308, 310, and / or 312. Processor(s) 318 is configured to execute modules 308, 310, and 312 by software; hardware; firmware; some combination of software, hardware, and / or firmware; and / or other mechanisms for configuring processing capabilities on processor(s) 318. As used herein, the term “module” refers to any component or set of components that perform the functionality attributed to a module. This includes one or more physical processors for execution of processor readable instructions, the processor readable instructions, circuitry, hardware, storage media, or any other components.

[0142] It should be appreciated that although modules 308, 310, and / or 312 are illustrated in FIG. 3 as being implemented within a single processing unit, in embodiments in which processor(s) 318 includes multiple processing units, one or more of modules 308, 310, and 312 are implemented in other modules, for example remotely from the other modules. The description of the functionality provided by the different modules 308, 310, and 312 described below is for illustrative purposes, and is not intended to be limiting, as any of modules 308, 310, and / or 312 optionally provide more or less functionality than is described. For example, one ormore of modules 308, 310, and 312 are optionally eliminated, and some or all of its functionality provided by other ones of modules 308, 310, and 312. As another example, processor(s) 318 is optionally configured to execute one or more additional modules that perform some or all of the functionality attributed below to one of modules 308, 310 and 312.

[0143] FIG. 4 illustrates a method 400 for processing an RF signal, in accordance with one or more embodiments. The operations of method 400 are intended to be illustrative. In some embodiments, method 400 is accomplished with one or more additional operations not described. In other embodiments, the method 400 is accomplished without one or more of the operations described. Additionally, the order in which the operations of method 400 are illustrated in FIG. 4 and described below is not intended to be limiting.

[0144] In some embodiments, method 400 is implemented in one or more processing devices (e.g., a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information). The one or more processing devices include one or more devices executing some or all of the operations of method 400 in response to instructions stored electronically or stored within a storage medium. The one or more processing devices include one or more devices configured through hardware, firmware, and / or software to be designed for execution of one or more of the operations of method 400.

[0145] An operation 402 includes generating a clock signal. In an embodiment, operation 402 includes generating a plurality of clock signals. Operation 402 is optionally performed by a clock source, such as clock source 110 in FIG. 1 or clock source 210 in FIG. 2, or by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to clock module 308 in FIG. 3. Operation 402 comprises applying a delay to the clock signal(s) to provide at least a plurality of relatively delayed clock signals to a plurality of samplers. For example, operation 402 comprises applying a first delay to the clock signal to provide a first delayed clock signal to a first sampler, and applying a second delay to the clock signal to provide a second delayed clock signal to a second sampler.

[0146] An operation 404 includes receiving a plurality of RF signals. The plurality of RF signals include RF signal 1 . . .RF signal N. Operation 404 is performed by one or more samplers, such as samplers 130. . . 132 of FIG. 1 or samplers 230. . .232 of FIG. 2, or by one or morehardware processors configured by machine-readable instructions including a module that is the same as or similar to sensor module 308 in FIG. 3. The plurality of RF signals is optionally received by one or more signal conditioners, such as signal conditioners 290. . .292 of FIG. 2. One or more of the signal conditioners comprise an attenuator. Alternatively, one or more of the signal conditioners comprise a filter, such as a harmonic filter. For example, when the sensor circuit is used to sense an output signal of a PA, the PA output signal may have distortion in the form of a harmonic. In that case, the signal conditioner comprises a filter that filters out all or some of the harmonic.

[0147] An operation 406 includes producing, based on the clock signal and based on the plurality of RF signals, a plurality of low-frequency-samples. Operation 406 is performed by one or more samplers, such as samplers 130. . . 132 of FIG. 1 or samplers 230. . .232 of FIG. 2, or by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to sensor module 308 in FIG. 3.

[0148] An operation 408 includes processing low-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances. Operation 408 includes processing medium-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances. Operation 508 is performed by the data analyzer 150 of FIG. 1 or the data analyzer 250 of FIG. 2. Operation 408 is optionally performed by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to data analyzer module 312 in FIG. 3.

[0149] An operation 410 includes generating a data analysis metric associated with the plurality of RF signals. Operation 410 includes generating a plurality of data analysis metrics associated with the plurality of RF signals. Operation 410 comprises providing the generated data analysis metric as input data to a controller to optimize performance of a device-under- observation producing the RF waveform. Operation 410 comprises performing data correlation to determine amplitude and phase relationships. The generated data analysis metric comprises at least one of relative gain; relative phase; relative distortion; voltage standing wave ratio; voltage distribution; current distribution; and reliability protection Alternatively, the generated data analysis metric comprises another parameter or characteristic that is relevant.

[0150] Operation 410 is performed by the data analyzer 150 of FIG. 1 or the data analyzer250 of FIG. 2. Operation 410 is alternatively performed by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to data analyzer module 312 in FIG. 3.

[0151] Embodiments of the present disclosure comprise a PA that employs a plurality of paths and a plurality of configurable sub-paths to generate an RF output signal that concurrently achieves a linearity target and a power efficiency target across a predetermined amplitude range of the RF output signal. An RF power amplifier of embodiments of the present disclosure combines behaviours of the different configurable sub-paths to achieve a desired behaviour for the RF output signal, where at least one of the sub-path output signals has a piecewise linear response. In an embodiment, the sub-paths and paths may combine to achieve the desired behaviour for the RF power amplifier as a whole. Within a path, one sub-path may include nonideal behaviour, and another sub-path may be used to achieve a linearity target across the full amplitude range of the RF output signal. In another embodiment, a configurable sub-path may be used to produce a particular behaviour and / or correct for non-idealities in the configurable subpath itself, or in other sub-paths or paths.

[0152] Embodiments of the present disclosure are designed to operate in scenarios in which at least one sub-path in the PA has a non-linear response, such as a piecewise linear response. A piecewise linear response is a combination of straight lines that is not linear as a whole; each section or piece may be linear, but the overall curve is not linear. When at least one-sub path in the PA has a non-linear response, then at least one path has a non-linear response. The sub-path control units of embodiments of the present disclosure are configured to compensate for nonlinearity in one or more of the sub-paths to achieve the linearity target for the RF output signal.

[0153] FIG. 5 is a block diagram illustrating a load balanced radio frequency power amplifier 500, in accordance with one or more embodiments. The RF PA 500 receives and control an RF input signal 502, and distributes or split the input signal 502 over a plurality of paths.

[0154] The RF power amplifier 500 of FIG. 5 comprises a splitter 510 configured to perform a distribution, for example a linear separation, of the input signal 502 into a plurality of sub-path signals 512, 514 and 516 distributed over a plurality of paths. In an example embodiment described in relation to FIG. 5, the plurality of sub-path signals includes first and second subpath signals 512 and 514 associated with a first path and a third sub-path signal 516 associatedwith a second path. First sub-path signal 512 may be described as relating to sub-path 1.1, and second sub-path signal 514 may be described as relating to sub-path 1.2, where sub-paths 1.1 and 1.2 are sub-paths of path 1. Similarly, third sub-path signal 516 may be described as relating to sub-path 2.1, which is a sub-path of path 2.

[0155] The PA 500 comprises a plurality of sub-path control units 522, 524. . .526 configured to receive the plurality of sub-path signals and to provide one or more of phase control, gain control and bias control of the to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths. For example, a configurable sub-path is a sub-path on which a sub-path control unit is provided. In an example embodiment, each of the plurality of paths comprises at least one configurable sub-path. At least one of the sub-path output signals has a piecewise linear response. In a particular embodiment, at least one of the plurality of paths comprises at least two configurable sub-paths. This is in contrast to some known approaches according to which each path can only have one sub-path.

[0156] The PA 500 comprises a plurality of paths, and each path has a plurality of sub-paths. In an example embodiment, each sub-path comprises a sub-path control unit. In another example embodiment, a set of sub-path control units is provided on a subset of the sub-paths, and the set of sub-path control units are configured to compensate for the piecewise linear response of one of more sub-path output signals. At least some piecewise linear response is on a sub-path that has a sub-path control unit. Alternatively, the sub-path control unit(s) compensate for a piecewise linear response on at least one sub-path having a piecewise linear response, even when the piecewise linear response is on a different sub-path than the sub-path control unit(s).

[0157] In an example embodiment, the PA 500 comprises a plurality of paths, such as the two paths 1 and 2 shown in FIG. 5. Each path acts on one or more of the sub-path input signals and each path produces a path output signal.

[0158] For example, as part of path 1, sub-path 1.1 control unit 522 is associated with subpath 1.1 and configured to receive sub-path input signal 512 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 532. Also as part of path 1, sub-path 1.2 control unit 524 is associated with sub-path 1.2 and configured to receive subpath input signal 514 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 534. As part of path 2, sub-path 2.1 control unit 526 isassociated with sub-path 2.1 and configured to receive sub-path input signal 516 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 536.

[0159] The PA 500 comprises a combiner network configured to combine the plurality of sub-path output signals to generate an RF output signal. In the example embodiment of FIG. 5, a path combiner 560 combines signals provided from first and second sub-path combiners 542 and 544. A first sub-path combiner 542 is configured to combine sub-path output signals 532 and 534 to generate a path 1 output signal 552. A second path combiner 544 is configured to combine sub-path output signals for path 2, which in this case include only 536, to generate a path 2 output signal 554. The path combiner 560 is configured to combine the path output signals 552 and 554 to generate an RF output signal 504.

[0160] The plurality of configurable sub-paths are configured, and the associated plurality of sub-path control units 522, 524. . .526 cooperate, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal. The linearity target comprises a target with respect to an amount of linearity for the RF output signal 504. The linearity target for the RF output signal substantially linear, within a given tolerance according to a specification for the PA. The power efficiency target comprises a target with respect to a power efficiency value or rating for the RF output signal 504.Embodiments of the present disclosure enable the PA 500 to concurrently achieve a linearity target and a power efficiency target across the full amplitude range of the RF output signal. This is in contrast to known approaches, according to which achieving a linearity target often adversely affects power efficiency, and achieving a power efficiency target often adversely affect linearity.

[0161] The PA 500 concurrently achieves a linearity target and a power efficiency target based on the configurable sub-paths and the associated plurality of sub-path control units. Alternatively, the PA 500 achieves a tradeoff between linearity and efficiency. A configurable sub-path compensates for non-linearity in the sub-path itself, or in another sub-path. For example, based on a determined non-linearity in one or more other sub-paths, a configurable subpath provides one or more of phase control, gain control and bias control on its sub-path input signal to produce a related sub-path output signal that, when combined with the other sub-pathoutput signals, enable the PA 500 to concurrently achieve a linearity target and a power efficiency target across the full amplitude range of the RF output signal. The example of compensating for a sub-path’s own non-linearity will be described in further detail in relation to FIG. 6.

[0162] According to embodiments of the present disclosure, the RF output signal 504 concurrently achieves a linearity target and a power efficiency target across the full amplitude range of the RF output signal, even when at least one of the sub-path output signals has a piecewise linear response. The path output signals 552 and 554 combine so that the RF output signal 504 achieves the linearity target. In an example embodiment, one or more of the path output signals 552 and 554 has a piecewise linear response, and for example each one is piecewise linear. Similarly, the sub-path output signals 532, 534 and 536 combine so that the RF output signal 504 achieves the linearity target. In an example embodiment, one or more of the sub-path output signals 532, 534 and 536 has a piecewise linear response, and for example each one is piecewise linear. In such embodiments, one or more of the plurality of sub-path control units are configured to compensate for the piecewise linear response of the path(s) / sub-path(s), so that the RF output signal achieves the linearity target.

[0163] In an example embodiment, the plurality of sub-path control units 522, 524 and 526 is configured to cooperate so that a piecewise linear combination of the plurality of sub-path output signals 532, 534 and 536 by the combiner cooperate to concurrently achieve linearity and power efficiency across a full amplitude range of the RF output signal 504. For example, the combiner includes first and second path combiners 542 and 544 and PA combiner 560. In an example embodiment, the piecewise linear combination of the plurality of sub-path output signals is configured to concurrently achieve linearity and power efficiency, for example using joint optimization or multi-variable optimization.

[0164] In an example implementation, the first sub-path signal is associated with a driver sub-path of the first path, and the second sub-path signal is associated with a secondary sub-path of the first path. In one embodiment, the secondary sub-path is configured to achieve linearity optimization with respect to the driver sub-path. In another embodiment, the secondary sub-path is configured to achieve gain optimization with respect to the driver sub-path. In a further embodiment, the secondary sub-path is configured to achieve output power optimization withrespect to the driver sub-path. In another embodiment, the secondary sub-path is configured to achieve efficiency optimization with respect to the driver sub-path.

[0165] In a further embodiment, the secondary sub-path is configured to simultaneously achieve linearity optimization and efficiency optimization with respect to the driver sub-path. In another embodiment, the secondary sub-path is configured to simultaneously achieve linearity optimization, gain optimization, output power optimization and efficiency optimization with respect to the driver sub-path. In a yet further embodiment, the secondary sub-path is configured to achieve linearity and power efficiency optimization with respect to the third sub-path.

[0166] Embodiments of the present disclosure provide improved performance over known approaches, such as a Doherty amplifier, for example by providing fine gain and phase control for each of a plurality of sub-paths. This permits embodiments of the disclosure to operate with at least one sub-path being piecewise linear, and still achieve a linearity target at the RF output port that would not be achievable with known approaches. Embodiments of the present disclosure are beneficial when sub-paths have non-linear or piecewise linear response due to non-ideal characteristics compared to expected performance, which may be due to imperfections, degradation or other factors. Embodiments of the present disclosure are applied to RF & mmWave communications and sensing.

[0167] Embodiments of the present disclosure provide sub-path control units that compensate for piecewise-linear (kink) sub-paths to achieve RF output linearization. A given driver path has a multiplicity of sub-paths feeding it, enabling linearization across the full signal amplitude range. The kinks may be active and / or passive.

[0168] Embodiments of the present disclosure provide advanced control features, including fine phase & gain control of paths for optimization of gain, output power, linearity, and efficiency. Embodiments of the present disclosure also provide advanced diagnostics, such as voltage, current, and power measurement capabilities at various key points.

[0169] FIG. 6 illustrates a sub-path control unit for a sub-path of the power amplifier of FIG. 5, in accordance with one or more embodiments. The example embodiment in FIG. 6 shows the sub-path control unit 522, which is associated with sub-path 1.1 and with path 1. The sub-path control unit 522 is configured to receive sub-path input signal 512 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 532. The sub-pathcontrol unit comprises a combined phase and gain controller 600 configured to control phase and gain of the sub-path signal 512 to produce the sub-path output signal 532. In an example embodiment, the sub-path control unit comprises a gain controller 602 and a phase controller 604. In an example implementation, the sub-path signal 512 comes in with 100 mV at 30 degrees, then the sub-path control unit with a combined phase and gain controller is configured to amplify the signal to 200 mV but shift phase to 45 degrees. The sub-path control unit in this example is configured to control the bias voltage, for example using an amplifier 206.

[0170] In an embodiment, the sub-path control unit provides the ability for a sub-path to achieve a linearity target or have a piecewise linear shape by itself, without requiring combination with another sub-path. The sub-path control unit comprises a piecewise linear passive component 608 configured to produce a piecewise-linear response for the configurable sub-path with which the sub-path control unit is associated. In such an embodiment, creating a piecewise linear response at the sub-path output port results in a piecewise linear response at the path output port.

[0171] In an embodiment, at least one of the plurality of sub-path control units comprises a combined phase and gain controller configured to control phase and gain of a selected sub-path signal and to produce a corresponding sub-path output signal.

[0172] In an embodiment, at least one of the plurality of sub-path control units comprises a bias voltage controller configured to control the bias voltage a selected sub-path signal and to produce a corresponding sub-path output signal.

[0173] In an embodiment, at least one of the plurality of sub-path control units comprises: a gain controller; and a phase controller, the phase controller being in communication with the gain controller to provide a gain and phase controlled output signal. In an embodiment, the at least one of the plurality of sub-path control units comprises an amplifier to increase the gain of the gain and phase-controlled output signal.

[0174] In one or more embodiments, the elements in FIG. 6 are passive. In other embodiments, the elements of FIG. 6 are active. In an example embodiment, the phase shifter is passive. In an example embodiment, the gain adjustment is passive.

[0175] FIG. 7 illustrates a graph 700 showing path output voltage versus path input voltagefor a piecewise linear combination within a path in a power amplifier. As evidenced by the graph in FIG. 7, the main sub-path control unit and the one or more secondary sub-path control units cooperate such that the performance characteristics of the plurality of sub-paths provide a piecewise linear combination within a path. This results in a desired performance of path input / output voltage over an entire spectrum of an input signal and output signal. For example the piecewise linear combination comprises a combination of the path output voltage versus path input voltage behaviour of the main sub-path 702, which comprises a first sub-path. Alternatively, it comprises a driver path. Following that, the main sub-path 702 behaviour is combined at 704 with the behaviour of the first kink path or secondary path, then at 706 with the behaviour of the second kink path or secondary path.

[0176] FIG. 8 is a block diagram illustrating a power amplifier 800 with N paths. The RF PA 800 receives and control an RF input signal 802, and distributes the input signal 802 over different sub-paths.

[0177] The RF power amplifier 800 comprises a splitter 810 configured to perform a distribution, for example a linear separation, of the input signal 802 into a plurality of sub-path signals 812, 814, 816 and 818 distributed over a plurality of paths. This number of the plurality of sub-path signals is exemplary, and there may be any number of sub-path signals. The example of FIG. 8 shows an implementation in which up to N paths are provided, with each of the N paths comprising up to M sub-paths.

[0178] In an example embodiment described in relation to FIG. 8, the plurality of sub-path signals includes first and second sub-path signals 812 and 814 associated with a first path, and third and fourth sub-path signals 816 and 818 associated with an Nth path. There may be any number of additional paths between the first path and the Nth path. First sub-path signal 812 is described as relating to sub-path 1.1, and second sub-path signal 814 is described as relating to sub-path l.M, where sub-paths 1.1 through l.M comprise up to M sub-paths of path 1. Similarly, third and fourth sub-path signals 816 and 818 are described as relating to sub-path N.1 through N.M, which comprise up to M sub-paths of path N. There may be any number of additional subpaths and associated sub-path signals between the first sub-path and the Mth sub-path for one or more of path 1 through path N.

[0179] The PA 800 comprises a plurality of sub-path control units 822, 824, 826. . .828configured to receive the plurality of sub-path signals and to provide one or more of phase control, gain control and bias control of the plurality of sub-path signals distributed over a plurality of configurable sub-paths. For example, a configurable sub-path is a sub-path on which a sub-path control unit is provided. In an example embodiment, each of the plurality of paths comprises at least one configurable sub-path, and at least one of the plurality of paths comprises at least two configurable sub-paths. This is in contrast to some known approaches according to which each path only has one sub-path. The plurality of sub-path control units are configured to produce a plurality of sub-path output signals.

[0180] For example, as part of path 1, sub-path 1.1 control unit 822 is associated with subpath 1.1 and configured to receive sub-path input signal 812 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 832. Also as part of path 1, sub-path l.M control unit 824 is associated with sub-path l.M and configured to receive subpath input signal 814 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 834. As part of path N, sub-path 2.1 control unit 826 is associated with sub-path 2.1 and configured to receive sub-path input signal 816 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 836. Also as part of path N, sub-path N.M control unit 828 is associated with sub-path N.M and configured to receive sub-path input signal 818 and to provide one or more of phase control, gain control and bias control to produce sub-path output signal 838.

[0181] There may be any number of additional paths between the first path and the Nth path. There may be any number of additional sub-paths and associated sub-path signals between the first sub-path and the Mth sub-path for one or more of path 1 through path N. In an example embodiment, the plurality sub-path control units is equal in number to the plurality of sub-path input signals, each of the plurality of sub-path control units being configured to receive a different one of the plurality of sub-path input signals and to provide one or more of phase control, gain control and bias control of the respective received sub-path signal, the plurality of sub-path control units producing the plurality of sub-path output signals.

[0182] The PA 800 comprises a plurality of paths, and each path has a plurality of sub-paths. In an example embodiment, each sub-path comprises a sub-path control unit. In another example embodiment, a set of sub-path control units is provided on a subset of the sub-paths, and the setof sub-path control units are configured to compensate for the piecewise linear response of one of more sub-path output signals. The piecewise linear response is on a sub-path that has a subpath control unit. Alternatively, the sub-path control unit(s) compensate for a piecewise linear response on at least one sub-path having a piecewise linear response, even when the piecewise linear response is on a different sub-path than the sub-path control unit(s).

[0183] The PA 800 comprises a combiner network configured to combine the plurality of sub-path output signals to generate an RF output signal. In the example embodiment of FIG. 8, a path combiner 860 combines signals provided from a plurality of sub-path combiners, for example sub-path combiner 842 through to sub-path combiner 844. First sub-path combiner 842 is configured to combine sub-path output signals 832 and 834 to generate a path 1 output signal 852. Nth path combiner 544 is configured to combine sub-path output signals for path N, which in this case includes 836 and 838, to generate a path N output signal 854. The path combiner 860 is configured to combine the sub-path output signals 852 and 854 to generate an RF output signal 804. There may be any number of additional paths between the first path and the Nth path, which result in an equal number of associated path combiners. There may be any number of additional sub-paths and associated sub-path signals between the first sub-path and the Mth sub-path for one or more of path 1 through path N.

[0184] The plurality of configurable sub-paths are configured, and the associated plurality of sub-path control units 822, 824. . .826 cooperate, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal. The linearity target comprises a target with respect to an amount of linearity for the RF output signal 804. The power efficiency target comprises a target with respect to a power efficiency value or rating for the RF output signal 804. Embodiments of the present disclosure enable the PA 500 to concurrently achieve a linearity target and a power efficiency target across an amplitude range of the RF output signal. This is in contrast to known approaches, according to which achieving a linearity target adversely affects power efficiency, and / or achieving a power efficiency target adversely affects linearity.

[0185] The PA 800 concurrently achieves a linearity target and a power efficiency target based on the configurable sub-paths and the associated plurality of sub-path control units. A configurable sub-path compensates for non-linearity in the sub-path itself, or in another sub-path.For example, based on a determined non-linearity in one or more other sub-paths, a configurable sub-path provides one or more of phase control, gain control and bias control on its sub-path input signal to produce a related sub-path output signal that, when combined with the other subpath output signals, enable the PA 800 to concurrently achieve a linearity target and a power efficiency target across the full amplitude range of the RF output signal.

[0186] In an example embodiment, the plurality of sub-path control units 822, 824, 826. . .828 are configured to cooperate so that a piecewise linear combination of the plurality of sub-path output signals 832, 834, 836. . .838 by the combiner acts to concurrently achieve linearity and power efficiency across a full amplitude range of the RF output signal 804. For example, the combiner includes a plurality of path combiners 842. . .844 and PA combiner 860. In an example embodiment, the piecewise linear combination of the plurality of sub-path output signals is configured to concurrently achieve linearity and power efficiency using joint optimization or multi-variable optimization.

[0187] According to embodiments of the present disclosure, the RF output signal 804 concurrently achieves a linearity target and a power efficiency target across the full amplitude range of the RF output signal, even when at least one of the sub-path output signals has a piecewise linear response. The path output signals 852. . .854 combine so that the RF output signal 804 achieves the linearity target. In an example embodiment, one or more of the path output signals 852 and 854 have a piecewise linear response, and for example each one is piecewise linear. Similarly, the sub-path output signals 832, 834, 836 and 838 combine so that the RF output signal 804 achieves the linearity target.

[0188] In an example embodiment, one or more of the sub-path output signals 832, 834, 836 and 838 have a piecewise linear response; for example, each one is piecewise linear. In such embodiments, one or more of the plurality of sub-path control units are configured to compensate for the piecewise linear response of the path(s) / sub-path(s), so that the RF output signal achieves the linearity target. There are any number of additional paths and associated path output signals between the first and Nth paths, any one or more of which are piecewise linear. There are any number of additional sub-paths and associated sub-path output signals between the first sub-path and the Mth sub-path for one or more of path 1 through path N, any one or more ofwhich are piecewise linear.

[0189] FIG. 9 is a functional block diagram illustrating an apparatus 900, such as a load balanced power amplifier. The embodiments of FIG. 5 and FIG. 8 illustrate a system or PA in specific implementations, for example with all of the elements being on-chip. The embodiment of FIG. 9 illustrates an embodiment where some functionality is distributed or provided as modules.

[0190] In some embodiments, system 900 includes one or more computing platforms 902. Computing platform(s) 902 are configured to communicate with one or more remote platforms 904 according to a client / server architecture, a peer-to-peer architecture, and / or other architectures. Remote platform(s) 904 is configured to communicate with other remote platforms via computing platform(s) 902 and / or according to a client / server architecture, a peer-to-peer architecture, and / or other architectures. Users access system 900 via remote platform(s) 904.

[0191] Computing platform(s) 902 are configured by machine-readable instructions 906. Machine-readable instructions 906 include one or more instruction modules. The instruction modules include computer program modules. The instruction modules include one or more of splitter module 908, sub-path controller module 910, combiner module 912, and / or other instruction modules.

[0192] Splitter module 908 is configured to receive the RF input signal and to perform a distribution, such as a linear separation, of the RF input signal into a plurality of sub-path signals distributed over a plurality of paths.

[0193] Sub-path controller module 910 is configured to perform one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of sub-path output signals distributed over a plurality of configurable sub-paths. Each of the plurality of paths comprises at least one configurable sub-path. At least one of the sub-path output signals has a piecewise linear response. In an embodiment, at least one of the plurality of paths comprises at least two configurable sub-paths. In a particular example, the sub-path controller module 910 comprises first, second and third sub-path control modules configured to receive the first, second and third sub-path signals, respectively, and to provide phase and gain control of the respective sub-path signal and produce first, second and third sub-path outputsignals.

[0194] Combiner module 912 is configured to combine the plurality of sub-path output signals to generate an RF output signal. The plurality of configurable sub-paths are configured, and the plurality of sub-path control units cooperate, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal. In an embodiment, a piecewise linear combination of the plurality of sub-path output signals cooperates to achieve linearity across a full amplitude range of the RF output signal. In an embodiment, the combiner module 912 is configured to combine the first, second and third sub-path output signals to generate an RF output signal such that a piecewise linear combination of the first, second and third sub-path output signals by the combiner cooperates to concurrently achieve linearity and power efficiency across a full amplitude range of the RF output signal.

[0195] In one or more embodiments, one or more of the features and characteristics described above in relation to the PA splitter 510 of FIG. 5 or PA splitter 810 of FIG.8 are also be applied to the splitter module 908. In one or more embodiments, one or more of the features and characteristics described above in relation to the sub-path control units 522, 524, 526 of FIG. 5 or the sub-path control units 822, 824, 826. . .828 of FIG. 8 are applied to the sub-path controller module 510. In one or more embodiments, one or more of the features and characteristics described above in relation to the path combiner 560 of FIG. 5 or the path combiner 860 of FIG. 8 are applied to the combiner module 912.

[0196] In some embodiments, computing platform(s) 902, remote platform(s) 904, and / or external resources 914 are operatively linked via one or more electronic communication links. For example, such electronic communication links are established, at least in part, via a network such as the Internet and / or other networks. It will be appreciated that this is not intended to be limiting, and that the scope of this disclosure includes implementations in which computing platform(s) 902, remote platform(s) 904, and / or external resources 914 are operatively linked via some other communication media.

[0197] A given remote platform 904 includes one or more processors configured to execute computer program modules. The computer program modules are configured to enable an expert or user associated with the given remote platform 904 to interface with system 900 and / orexternal resources 914, and / or provide other functionality attributed herein to remote platform(s) 904. By way of non-limiting example, a given remote platform 904 and / or a given computing platform 902 include one or more of a server, a desktop computer, a laptop computer, a handheld computer, a tablet computing platform, a NetBook, a Smartphone, a gaming console, and / or other computing platforms.

[0198] External resources 914 include sources of information outside of system 900, external entities participating with system 900, and / or other resources. In some embodiments, some or all of the functionality attributed herein to external resources 914 are provided by resources included in system 900.

[0199] Computing platform(s) 902 include electronic storage 916, one or more processors 918, and / or other components. Computing platform(s) 902 includes communication lines, or ports to enable the exchange of information with a network and / or other computing platforms. Illustration of computing platform(s) 902 in FIG. 9 is not intended to be limiting. Computing platform(s) 902 includes a plurality of hardware, software, and / or firmware components operating together to provide the functionality attributed herein to computing platform(s) 902. For example, computing platform(s) 902 is implemented by a cloud of computing platforms operating together as computing platform(s) 902.

[0200] Electronic storage 916 may comprise non-transitory storage media that electronically stores information. The electronic storage media of electronic storage 916 include one or both of system storage that is provided integrally (i.e., substantially non-removable) with computing platform(s) 902 and / or removable storage that is removably connectable to computing platform(s) 902 via, for example, a port (e.g., a USB port, a firewire port, etc.) or a drive (e.g., a disk drive, etc.). Electronic storage 916 includes one or more of optically readable storage media (e.g., optical disks, etc.), magnetically readable storage media (e.g., magnetic tape, magnetic hard drive, floppy drive, etc.), electrical charge-based storage media (e.g., EEPROM, RAM, etc.), solid-state storage media (e.g., flash drive, etc.), and / or other electronically readable storage media. Electronic storage 916 includes one or more virtual storage resources (e.g., cloud storage, a virtual private network, and / or other virtual storage resources). Electronic storage 916 stores software algorithms, information determined by processor(s) 918, information received from computing platform(s) 902, information received from remote platform(s) 904, and / or otherinformation that enables computing platform(s) 902 to function as described herein.

[0201] Processor(s) 918 is configured to provide information processing capabilities in computing platform(s) 902. As such, processor(s) 918 includes one or more of a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information. Although processor(s) 918 is shown in FIG. 9 as a single entity, this is for illustrative purposes only. In some embodiments, processor(s) 918 includes a plurality of processing units. These processing units are physically located within the same device, or processor(s) 918 represents processing functionality of a plurality of devices operating in coordination. Processor(s) 918 is configured to execute modules 908, 910, and / or 912, and / or other modules. Processor(s) 918 is configured to execute modules 908, 910, and / or 912, and / or other modules by software; hardware; firmware; some combination of software, hardware, and / or firmware; and / or other mechanisms for configuring processing capabilities on processor(s) 918. As used herein, the term “module” refers to any component or set of components that perform the functionality attributed to the module. This includes one or more physical processors during execution of processor readable instructions, the processor readable instructions, circuitry, hardware, storage media, or any other components.

[0202] It should be appreciated that although modules 908, 910, and / or 912 are illustrated in FIG. 9 as being implemented within a single processing unit, in embodiments in which processor(s) 918 includes multiple processing units, one or more of modules 908, 910, and / or 912 are implemented remotely from the other modules. The description of the functionality provided by the different modules 908, 910, and / or 912 described below is for illustrative purposes, and is not intended to be limiting, as any of modules 908, 910, and / or 912 are provide more or less functionality than is described. For example, one or more of modules 908, 910, and / or 912 are eliminated, and some or all of its functionality is provided by other ones of modules 908, 910, and / or 912. As another example, processor(s) 918 is configured to execute one or more additional modules that perform some or all of the functionality attributed below to one of modules 908, 910 and / or 912.

[0203] FIG. 10 illustrates a method 1000 for processing a signal in a power amplifier, in accordance with one or more embodiments. The operations of method 1000 presented below areintended to be illustrative. In some embodiments, method 1000 is accomplished with one or more additional operations not described, and / or without one or more of the operations discussed. Additionally, the order in which the operations of method 1000 are illustrated in FIG. 10 and described below is not intended to be limiting.

[0204] In some embodiments, method 1000 is implemented in one or more processing devices (e.g., a digital processor, an analog processor, a digital circuit designed to process information, an analog circuit designed to process information, a state machine, and / or other mechanisms for electronically processing information). The one or more processing devices includes one or more devices executing some or all of the operations of method 1000 in response to instructions stored electronically on an electronic storage medium. The one or more processing devices includes one or more devices configured through hardware, firmware, and / or software to be specifically designed for execution of one or more of the operations of method 1000.

[0205] An operation 1002 includes receiving a radio frequency (RF) input signal. Operation 1002 is performed by a PA splitter, such as PA splitter 510 in FIG. 5 or PA splitter 810 in FIG. 8, or by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to splitter module 908 in FIG. 9.

[0206] An operation 1004 includes performing a distribution, such as a linear separation, of the RF input signal into a plurality of sub-path signals distributed over a plurality of paths. Each of the plurality of paths comprises at least one configurable sub-path. At least one of the sub-path output signals has a piecewise linear response. The plurality of sub-path signals includes first and second sub-path signals associated with a first path and a third sub-path signal associated with a second path. Operation 1004 is performed by a PA splitter, such as PA splitter 510 in FIG. 5 or PA splitter 810 in FIG. 8, or by one or more hardware processors configured by machine- readable instructions including a module that is the same as or similar to splitter module 908 in FIG. 9.

[0207] An operation 1006 includes performing one or more of phase control, gain control and bias control with respect to the plurality of sub-path signals to produce a plurality of subpath output signals. For example, operation 1006 comprises receiving first, second and third subpath signals and providing phase and gain control to produce first, second and third sub-pathoutput signals. In another example, operation 1006 comprises providing one or more of phase control, gain control or bias control. Operation 1006 is performed by one or more of sub-path control units 522, 524, 526 of FIG. 5 or one or more of sub-path control units 822, 824, 826. . .828 of FIG. 8, or by one or more hardware processors configured by machine-readable instructions including a module that is the same as or similar to sub-path controller module 910.

[0208] An operation 1008 includes combining the plurality of sub-path output signals to generate an RF output signal. The plurality of configurable sub-paths are configured, and the plurality of sub-path control units cooperate, such that the RF output signal concurrently achieves a linearity target and a power efficiency target across a full amplitude range of the RF output signal. In an example implementation, a piecewise linear combination of the plurality of sub-path output signals cooperates to achieve linearity across a full amplitude range of the RF output signal. Operation 1008 includes combining the first, second and third sub-path output signals to generate an RF output signal such that a piecewise linear combination of the first, second and third sub-path output signals by the combiner cooperates to concurrently achieve linearity and power efficiency across a full amplitude range of the RF output signal. Operation 1008 is performed by the path combiner 560 of FIG. 5 or the path combiner 860 of FIG. 8. Operation 1008 is performed by one or more hardware processors configured by machine- readable instructions including a module that is the same as or similar to combiner module 912.

[0209] Embodiments of the present disclosure provide a load-modulated intelligent RF power amplifier comprising at least two and up to N driver paths, with at least one path, each path comprising up to M sub-paths. Each set of M sub-paths comprises a main sub-path, and zero or more secondary sub-paths. A separate phase and gain control unit is optionally provided for each sub-path, providing fine phase and gain control of the sub-paths, for optimization of gain, output power, linearity and efficiency. Embodiments of the present disclosure are able to compensate for changes in environment and for manufacturing variances, resulting in desirable performance characteristics for the power amplifier, which are less affected by or unaffected by environmental and manufacturing variations.

[0210] Embodiments of the present disclosure are designed to operate in scenarios in which at least one sub-path in the PA has a non-linear response, such as a piecewise linear response. A piecewise linear response is a combination of straight lines that is not linear as a whole; eachsection or piece may be linear, but the overall curve is not linear. When at least one-sub path in the PA has a non-linear response, then at least one path has a non-linear response. The sub-path control units of embodiments of the present disclosure are configured to compensate for nonlinearity in one or more of the sub-paths to achieve the linearity target for the RF output signal.

[0211] In the preceding description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the embodiments. However, it will be apparent to one skilled in the art that these specific details are not required. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the understanding. For example, specific details are not provided as to whether the embodiments described herein are implemented as a software routine, hardware circuit, firmware, or a combination thereof.

[0212] Embodiments of the disclosure can be represented as a computer program product stored in a machine-readable medium (also referred to as a computer-readable medium, a processor-readable medium, or a computer usable medium having a computer-readable program code embodied therein). The machine-readable medium can be any suitable tangible, non- transitory medium, including magnetic, optical, or electrical storage medium including a compact disk read only memory (CD-ROM), digital versatile disk (DVD), Blu-ray Disc Read Only Memory (BD-ROM), memory device (volatile or non-volatile), or similar storage mechanism. The machine-readable medium can contain various sets of instructions, code sequences, configuration information, or other data, which, when executed, cause a processor to perform steps in a method according to an embodiment of the disclosure. Those of ordinary skill in the art will appreciate that other instructions and operations necessary to implement the described implementations can also be stored on the machine-readable medium. The instructions stored on the machine-readable medium can be executed by a processor or other suitable processing device, and can interface with circuitry to perform the described tasks.

[0213] The above-described embodiments are intended to be examples only. Alterations, modifications and variations can be effected to the particular embodiments by those of skill in the art without departing from the scope, which is defined solely by the claims appended hereto.

Claims

CLAIMS:What is claimed is:

1. A sensor circuit comprising: a clock source configured to generate a first clock signal; a plurality of samplers configured to receive a plurality of radio frequency (RF) signals and to produce, based on the clock signal, a plurality of one of low resolution and medium resolution samples at or below 9 bits, the plurality of one of low resolution and medium resolution samples sampled at a low-frequency below the Nyquist rate; and a data analyzer configured to process the one of low-resolution and medium resolution samples of the plurality of one of low-resolution and medium resolution samples collected over a plurality of sampling instances and to generate a data analysis metric associated with the plurality of RF signals.

2. The sensor circuit of claim 1 further comprising: a circuit splitting the first clock signal into a plurality of received clock signals; a signal aligner configured to align relatively at least some of the plurality of received clock signals for sampling, at each of the plurality of samplers, at the same relative waveform position on each of the plurality of RF signals.

3. The sensor circuit of claim 2 wherein the signal aligner further comprises: a plurality of delay elements each configured to apply a delay to one of the plurality of received clock signals and to provide a delayed clock signal to one of the plurality of samplers, the delays for the plurality of delay elements being configured for aligning the plurality of clock signals for sampling the plurality of RF signals at the same relative waveform position.

4. The sensor circuit of claim 2 wherein the plurality of samplers comprises a first sampler configured to receive a first RF signal and a second sampler configured to receive a second RF signal, and wherein the signal aligner comprises:an alignment circuit controlled by the data analysis metric generated by the data analyzer and configured to enable phase alignment of first and second received clock signals to align sampling of the first and second RF signals.

5. The sensor circuit of claim 2 wherein the plurality of samplers comprises a first sampler configured to receive a first RF signal and a second sampler configured to receive a second RF signal, and wherein the signal aligner comprises: an alignment circuit controlled by the data analysis metric generated by the data analyzer and configured to enable amplitude alignment of first and second received clock signals to align sampling of the first and second RF signals.

6. The sensor circuit of claim 2 wherein the plurality of samplers comprises a first sampler configured to receive an input RF signal with respect to a device-under-observation and a second sampler configured to receive a corresponding output RF signal, and wherein the signal aligner comprises: an alignment circuit controlled by a metric generated by the data analyzer and configured to enable at least one of phase alignment and amplitude alignment of first and second received clock signals to align sampling of the input RF signal and the corresponding output RF signal.

7. The sensor circuit of claim 2 wherein the plurality of samplers is configured to produce low-resolution samples having fewer than 7 bits.

8. The sensor circuit of any one of claims 1 - 7, wherein the clock signal has a clock rate that is asynchronous to the RF signal.

9. The sensor circuit of any one of claims 1 - 7, wherein the plurality of samplers is configured to produce the low-frequency samples at a sampling rate that is asynchronous to the RF signal.

10. The sensor circuit of any one of claims 1 - 9, wherein one or more of the plurality of samplers comprises a low-power sample-and-hold sampler.

11. The sensor circuit of any one of claims 1 - 10, further comprising: a signal conditioner configured to condition one or more of the plurality of RF signals prior to being provided to the samplers.

12. The sensor circuit of any one of claims 1 - 11, wherein the data analyzer is configured to provide the generated data analysis metric as input information to a controller to optimize performance of a device-under-observation producing the RF waveform.

13. The sensor circuit of any one of claims 1 - 12, wherein the data analyzer is configured to perform data correlation to determine amplitude and phase relationships.

14. The sensor circuit of any one of claims 1 - 13, wherein the data analyzer is configured to generate the data analysis metric based on a low-resolution representation of a comparison of the plurality of low-frequency samples.

15. The sensor circuit of any one of claims 1 - 6 and 8 - 14, wherein the sampler generates medium resolution samples and where the data analyzer is configured to process medium-resolution samples collected over the plurality of sampling instances.

16. The sensor circuit of any one of claims 1 - 15, wherein the generated data analysis metric comprises at least one of relative gain; relative phase; relative distortion; voltage standing wave ratio (VSWR); voltage distribution; current distribution; and reliability protection.

17. A sensor circuit according to any one of claims 1 to 16 comprising: an output port; a tuning circuit for modifying at least an aspect of at least an RF signal to adjust an output RF signal presented at the output port.

18. A sensor circuit according to claim 17 wherein the output RF signal meets a predeterminedcondition for transmission in accordance with at least a standard, the tuning circuit for maintaining the output RF signal in accordance with the predetermined condition.

19. A sensor circuit according to claim 17 comprising: an input port; and wherein the output RF signal at the output port is predictable within known limits based on a first RF input signal at the input port, the RF output signal an amplified version of the first RF input signal and with known characteristics in accordance with at least a standard, the tuning circuit for maintaining the output RF signal in accordance with the at least a standard.

20. A sensor system comprising: the sensor circuit of claim 1; and an RF circuit configured to produce one or more of the plurality of RF signals.

21. A processor-implemented method for processing radio frequency (RF) signals, the method comprising: generating a clock signal; receiving a plurality of RF signals; producing, based on the clock signal and on the plurality of RF signals, a plurality of low- frequency samples; processing low-resolution representations of the plurality of low-frequency-samples collected over a plurality of sampling instances; and generating a data analysis metric associated with the plurality of RF signals.

22. A method according to claim 21 wherein the plurality of low-frequency samples are low- resolution low frequency samples.

23. A method according to claim 22 wherein the plurality of low-resolution low-frequency samples are one-bit samples.

24. An apparatus comprising: a non-transient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: generate a clock signal; receive a plurality of RF signals; produce, based on the clock signal and on the plurality of RF signals, a plurality of low-frequency samples; processing low-resolution representations of the plurality of low-frequency samples collected over a plurality of sampling instances; and generate a data analysis metric associated with the plurality of RF signals.

25. An apparatus comprising: a non-transient computer-readable storage medium having executable instructions embodied thereon; and one or more hardware processors configured to execute the instructions to: generate a clock signal; receive a plurality of RF signals; produce, based on the clock signal and on the plurality of RF signals, one of a plurality of low-frequency low-resolution first samples and a plurality of low-frequency medium-resolution first samples; processing the first samples collected over a plurality of sampling instances; and generate a data analysis metric associated with the plurality of RF signals.

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