Method for preparing semiconductor structure and semiconductor structure

Abstract

A method for manufacturing a semiconductor structure, and a semiconductor structure. The method comprises: providing a substrate, and forming isolation structures in the substrate, wherein the isolation structures are spaced apart; forming a stack structure on the substrate, wherein the stack structure is formed by alternately stacking first layers and second layers in a third direction; forming stack openings, wherein the stack openings run through the stack structure in the third direction; forming first substrate openings, wherein the first substrate openings are below the stack openings and extend into the substrate, the stack openings and the first substrate openings form first openings, and the orthographic projection of a first opening on the substrate is located within the orthographic projection of an isolation structure on the substrate and / or the orthographic projection of the first opening on the substrate is located between adjacent isolation structures; removing part of the second layers to form second openings, and etching the first substrate openings to form substrate openings, wherein the stack openings, the substrate openings and the second openings together form combined openings; and forming capacitor structures in the combined openings, wherein the capacitor structures extend in a first direction and are spaced apart in both a second direction and the third direction.

Description

A semiconductor structure and a preparation method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The present disclosure claims priority to the Chinese patent application No. 202410853869.4, filed on June 27, 2024, and entitled “A semiconductor structure and a preparation method thereof”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] Embodiments of the present disclosure relate to the field of semiconductor, and in particular, to a semiconductor structure and a preparation method thereof. BACKGROUND

[0004] The development of dynamic random access memory (DRAM) pursues high speed, high integration density, low power consumption and other performance indicators. With the miniaturization of semiconductor device structure size, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers.

[0005] The emergence of three-dimensional dynamic random access memory (3D DRAM) meets the above-mentioned needs. However, the existing 3D DRAM needs multiple etching and cleaning processes, which may damage the substrate during etching, affecting the performance and yield of the semiconductor structure.

[0006] SUMMARY

[0007] Embodiments of the present disclosure provide a semiconductor structure and a preparation method thereof, which at least facilitate the protection of the substrate and improve the performance and yield of the semiconductor memory device.

[0008] According to some embodiments of the present disclosure, in one aspect, a preparation method of a semiconductor structure is provided, comprising: providing a substrate, forming an isolation structure in the substrate, and spacing the isolation structure;

[0009] forming a stack structure on the substrate, the stack structure being formed by alternately stacking a first layer and a second layer in a third direction, the third direction being perpendicular to a surface of the substrate;

[0010] forming a stack opening, the stack opening penetrating the stack structure along the third direction;

[0011] forming a first substrate opening, the first substrate opening being located below the stack opening and extending into the substrate, the stack opening and the first substrate opening forming a first opening, a projection of the first opening on the substrate being located within a projection of the isolation structure on the substrate and / or a projection of the first opening on the substrate being located between adjacent isolation structures;

[0012] The second layer is removed to form a second opening, and the first substrate opening is etched to form a substrate opening, the stack opening, the substrate opening and the second opening jointly form a joint opening;

[0013] A capacitor structure is formed in the joint opening, the capacitor structure extends along the first direction and is spaced apart in both the second direction and the third direction.

[0014] In another aspect, the present disclosure provides a semiconductor structure, comprising: a substrate, the substrate having an isolation structure therein, the isolation structure being spaced apart;

[0015] A stack structure is disposed on the substrate, the stack structure is formed by alternately stacking a first layer and a second layer in a third direction, the third direction being perpendicular to a surface of the substrate;

[0016] A stack opening extends through the stack structure along the third direction;

[0017] A substrate opening is below the stack opening and extends into the substrate, a dimension of the substrate opening along the first direction is greater than a dimension of the stack opening along the first direction;

[0018] The isolation structure is at least located at a side and / or a bottom of the substrate opening;

[0019] A second opening is formed by removing part of the second layer, the stack opening, the substrate opening and the second opening jointly form a joint opening;

[0020] A capacitor structure is located in the joint opening, the capacitor structure extends along the first direction and is spaced apart in both the second direction and the third direction.

[0021] The technical solutions provided by the embodiments of the present disclosure have at least the following advantages: by disposing the isolation structure in the substrate, and the isolation structure at least surrounding the bottom surface and / or the side surface of the substrate opening, the leakage or short circuit of the silicon substrate caused by excessive etching in the process of lateral etching or other etching is effectively improved, and the performance and yield of the semiconductor device are improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] One or more embodiments are illustrated by way of example in the drawings that are for illustrative purposes only, and not for the purposes of limiting the embodiments, unless otherwise explicitly stated in the embodiments, the drawings in the drawings do not constitute a proportional limit; in order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings needed to be used in the embodiments will be briefly introduced below, and obviously, the drawings in the following description can also be obtained by other drawings without creative labor for those skilled in the art.

[0023] FIG. 1 is a flow block diagram of a semiconductor structure preparation method provided by an embodiment of the present disclosure;

[0024] FIGS. 2A-2P are process flow diagrams of a method for fabricating a semiconductor structure according to an embodiment of the present disclosure.

[0025] FIGS. 3A-3P are process flow diagrams of a method for fabricating a semiconductor structure according to another embodiment of the present disclosure.

[0026] FIGS. 4A-4O are process flow diagrams of a method for fabricating a semiconductor structure according to yet another embodiment of the present disclosure.

[0027] FIG. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0028] FIG. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0029] FIG. 7 is a schematic diagram of a semiconductor structure according to yet another embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] As known from the background, the development of dynamic random access memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. With the miniaturization of semiconductor device structures, the technical barriers encountered by existing structures are becoming more and more obvious. Therefore, developing more novel structures on the basis of existing structures is a favorable means to break through the existing technical barriers. The emergence of three-dimensional dynamic random access memory (3D DRAM), such as multilayer horizontal cell (MHC) capacitor memory, meets the above-mentioned needs. However, the existing 3D DRAM requires multiple etching and cleaning processes, which may damage the substrate during etching, affecting the performance and yield of the semiconductor structure.

[0031] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure thereof. By providing an isolation structure in the substrate, and the isolation structure at least surrounds the bottom surface and / or the side surface of the opening of the substrate, the leakage or short circuit of the silicon substrate caused by excessive etching during the lateral etching or other etching process is effectively improved, so that the performance and yield of the semiconductor device are improved.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. However, those skilled in the art can understand that in the embodiments of the present disclosure, many technical details are proposed in order to enable the reader to better understand the present disclosure. However, the technical solutions claimed by the present disclosure can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0033] The present disclosure will be described with respect to the following examples in conjunction with the accompanying drawings. The advantages and features of the present disclosure will become clear to those skilled in the art from the following description and claims. It should be noted that the drawings are in simplified form and are not drawn to precise scale. They are intended only to aid in understanding the present disclosure.

[0034] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means the meaning of "on" something with no intervening features or layers therebetween (i.e., directly on something), but also includes the meaning of "on" something with intervening features or layers therebetween.

[0035] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects, and do not necessarily have to describe a specific order or sequence.

[0036] In the embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. The layer can extend over the entirety of the underlying or overlying structure, or can have a scope that is less than the scope of the underlying or overlying structure. Further, the layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness that is less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be between any horizontal pair of planes at the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface. The layer can include a plurality of sub-layers.

[0037] It should be noted that the technical solutions described in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0038] FIG. 1 is a flow chart of a semiconductor structure preparation method according to an embodiment of the present disclosure;

[0039] FIGS. 2A to 2P are process flow diagrams of a semiconductor structure preparation method according to an embodiment of the present disclosure.

[0040] FIGS. 3A to 3P are process flow diagrams of a semiconductor structure preparation method according to another embodiment of the present disclosure.

[0041] FIGS. 4A to 4O are process flow diagrams of a semiconductor structure preparation method according to another embodiment of the present disclosure.

[0042] FIG. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0043] FIG. 6 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0044] FIG. 7 is a schematic diagram of a semiconductor structure according to another embodiment of the present disclosure.

[0045] As shown in FIG. 1, the preparation method comprises at least the following steps: S10, providing a substrate, forming an isolation structure in the substrate, and spacing the isolation structure; S20, forming a laminated structure on the substrate, the laminated structure being formed by alternately stacking a first layer and a second layer in a third direction, the third direction being perpendicular to the surface of the substrate; S30, forming a laminated opening, the laminated opening penetrating the laminated structure along the third direction; S40, forming a first substrate opening, the first substrate opening being located below the laminated opening and extending into the substrate, the laminated opening and the first substrate opening forming a first opening, the orthographic projection of the first opening on the substrate being located within the orthographic projection of the isolation structure on the substrate and / or the orthographic projection of the first opening on the substrate being located between adjacent isolation structures; S50, removing part of the second layer to form a second opening, etching the first substrate opening to form a substrate opening, the laminated opening, the substrate opening and the second opening jointly forming a combined opening; S60, forming a capacitor structure in the combined opening, the capacitor structure extending along a first direction and being spaced apart in both a second direction and a third direction.

[0046] The embodiments of the present disclosure will be described in more detail below with reference to the drawings.

[0047] Referring to FIG. 1 and FIG. 2A-2B, a substrate 10 is provided, a photoresist layer S102 is formed on the substrate 10, the photoresist layer S102 has a first opening S101, the substrate 10 is subjected to a first treatment through the first opening S101 to form a first initial isolation structure 21' in the substrate 10, and the first initial isolation structure 21' is subjected to a second treatment to form an isolation structure 20, the top of the isolation structure 20 has a first spacing H1 from the substrate surface, the length of the isolation structure 20 along a first direction X is a first length D1, and a plurality of isolation structures 20 are arranged at intervals, the first direction X refers to the direction in which the isolation structure 20 extends, and the first direction X is parallel to the surface of the substrate 10; the first treatment can be plasma implantation (the arrow in the figure represents plasma implantation), different depths of the first initial isolation structure 21' can be obtained by controlling the energy of the plasma implantation, different concentrations of the first initial isolation structure 21' can be obtained by controlling the dose of the plasma implantation, and different positions of the first initial isolation structure 21' can be obtained by controlling the angle of the plasma implantation, and the required first initial isolation structure 21' can be obtained by controlling the energy, dose and angle of the plasma implantation according to the process requirements, and in an embodiment, the ion implantation element can be oxygen atoms. The second treatment can be a high-temperature annealing treatment, and in a specific embodiment, the oxygen element implanted by ion implantation reacts with the silicon substrate through high-temperature annealing to form the isolation structure 20, and the material of the isolation structure 20 can be silicon oxide. Here, only silicon oxide is taken as an example for description, and in other embodiments, the material of the isolation structure 20 can be silicon nitride, silicon oxynitride, etc. The material of the substrate can be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); can also be silicon on insulator (SOI), germanium on insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds. In the embodiment, the substrate material is silicon.

[0048] Next, referring to FIG. 1 and FIG. 2C, a stack structure 101 is formed on the substrate 10, the stack structure 101 is formed by alternately stacking a first layer 102 and a second layer 103 in a third direction Z, and the third direction Z is perpendicular to the substrate surface; and the etching stop layer 201 and the hard mask layer 202 are further included above the stack structure 101, the etching stop layer 201 is located above the stack structure 101, and the hard mask layer 202 is located above the etching stop layer 201, the etching stop layer 201 and the hard mask layer 202 provide protection for subsequent etching to form a stack opening and a substrate opening, and prevent damage to the stack structure 101.

[0049] Next, please refer to FIG. 1 and FIG. 2D-2E, a stack opening 301 is formed, the stack opening 301 passes through the stack structure 101 along the third direction Z and stays on the upper surface of the substrate 10; before forming the stack opening 301, it also includes forming a photoresist layer S102 on the stack structure 101, the photoresist layer S102 has an opening between them, and the stack structure 101 is etched through the opening to form the stack opening 301.

[0050] Next, please refer to FIG. 1 and FIG. 2F, a first substrate opening 401 is formed, the first substrate opening 401 is located below the stack opening 301 and extends into the substrate 10, the first substrate opening 401 and the stack opening 301 have the same length along the first direction X, both are the second length D2, the second length D2 is less than the first length D1, the first substrate opening 401 extends into the substrate 10 to a depth of the second spacing H2; the stack opening 301 and the first substrate opening 401 constitute a first opening K1, the orthographic projection of the first opening K1 on the substrate 10 is located within the orthographic projection of the isolation structure 20 on the substrate 10, that is, the second length D2 of the first opening K1 is less than the first length D1 of the isolation structure 20, the orthographic projection of the first opening K1 on the substrate 10 can be in the middle of the orthographic projection of the isolation structure 20, or it can deviate from the middle of the orthographic projection of the isolation structure 20, the middle means that the central axis of the first opening K1 coincides with the central axis of the isolation structure 20, but the orthographic projection of the first opening K1 on the isolation structure 20 cannot deviate from the isolation structure 20; in the process of forming the first substrate opening 401, the hard mask layer 202 and the photoresist layer S102 on the top of the stack structure 101 are also removed.

[0051] Please refer to FIG. 1 and FIG. 2G, the second layer 103 is removed to form the second opening 302, and the first base opening 401 is etched to form the second base opening 402 in the process of removing the second layer 103 to form the second opening 302, the second base opening 402 has a third length D3 along the first direction X, the first base opening 401 has a second length D2 along the first direction X, the third length D3 is greater than the second length D2; the second base opening 402 extends to the substrate 10 along the third direction Z to a third interval H3, the first base opening 401 extends to the substrate 10 along the third direction Z to a second interval H2, the third interval H3 is greater than the second interval H2, the first direction X is parallel to the surface of the substrate 10, and the third direction Z is perpendicular to the surface of the substrate 10. The stack opening 301, the second opening 302, and the second base opening 402 jointly form a third opening 303, and the substrate 10 is over-etched in the process of etching to form the second opening 302, and in FIG. 2G, only the depth of the second base opening 402 along the third direction does not expose the isolation structure 20, that is, the third interval H3 is less than the first interval H1, but in other embodiments, the depth of the second base opening 402 along the third direction can expose the isolation structure 20, that is, the third interval H3 is equal to the first interval H1, and the presence of the isolation structure 20 can make the substrate 10 over-etch stop on the surface of the isolation structure 20, preventing further damage to the substrate 10.

[0052] Please refer to FIG. 1 and FIG. 2H, after forming the second opening 302, the first layer 102 is removed along the third direction Z to form a first expanded hole 302', the size of the first expanded hole 302' along the third direction Z is greater than the size of the second opening 302 along the third direction Z, and the first expanded hole 302' is provided to provide a larger window for subsequent formation of a capacitor structure, and the stack opening 301, the first expanded hole 302', and the second base opening 402 jointly form a third opening expanded hole K2'. In the subsequent process of the embodiment, only the third opening 303 is taken as an example, a first conductive material layer is formed in the third opening 303, and in other embodiments, the first conductive material layer can also be formed in the third opening expanded hole K2'; that is, the third opening expanded hole K2' is an optimization of the third opening 303, and subsequent processes in the third opening 303 are also applicable to the third opening expanded hole K2'; in the embodiment, only the third opening 303 is taken as an example for subsequent processes, and the subsequent processes are also applicable to the third opening expanded hole K2'.

[0053] Referring to FIGS. 1 and 2I-2N, as shown in FIG. 2I, the stack opening 301, the second opening 302 and the second substrate opening 402 jointly form a third opening 303, a first conductive material layer 501' is formed in the third opening 303, and the first conductive material layer 501' covers the surface exposed by the third opening 303; as shown in FIG. 2J, a first sacrificial layer 502 is formed, and the first sacrificial layer 502 fills the remaining third opening 303; as shown in FIG. 2K, part of the first sacrificial layer 502 is removed to form a fourth opening 304, and the remaining first sacrificial layer 502 is only located in the second opening 302, and the fourth opening 304 exposes part of the first conductive material layer 501', as shown in FIG. 2K, the fourth opening 304 exposes at least part of the first conductive material layer 501' of the sidewall of the first layer 102; as shown in FIG. 2L, the first conductive material layer 501' exposed by the fourth opening 304 is removed; as shown in FIG. 2M, the first conductive material layer 501' and the first sacrificial layer 502 in the second substrate opening 402 are also removed in the process of removing the first conductive material layer 501' exposed by the fourth opening 304, so as to prevent the first conductive material layer 501' and the first sacrificial layer 502 from existing in the second substrate opening 402 to cause the generation of leakage current. As shown in FIG. 2N, the first sacrificial layer 502 in the second opening 302 is removed, and the remaining first conductive material layer 501' serves as a first conductive layer 501, and the first conductive layer 501 only covers the surface exposed by the second opening 302; the stack opening 301, the substrate opening 404 and the second opening 302 jointly form a joint opening K2.

[0054] As shown in FIG. 2M, in order to completely remove the first conductive material layer 501' and the first sacrificial layer 502 in the second substrate opening 402, over-etching may be caused to the substrate 10, so that the second substrate opening 402 is further enlarged to form a third substrate opening 403; the third substrate opening 403 has a fourth length D4 along the first direction X, the fourth length D4 is greater than the third length D3, and the fourth length D4 is less than the first length D1; the third substrate opening 403 has a fourth interval H4 along the third direction Z, and the fourth interval H4 is greater than the third interval H3, and FIG. 2M only schematically shows that the fourth interval H4 is less than the first interval H1; it should be noted that even if the fourth interval H4 is equal to the first interval H1, the performance of the substrate 10 will not be affected, because the existence of the isolation structure 20 causes the substrate 10 to stop at the top of the isolation structure 20 in the process of over-etching, and the isolation structure 20 has a large etching selectivity ratio with the substrate 10, so that the third substrate opening 403 will not extend beyond the top of the isolation structure 20 even if it extends along the third direction, and if the isolation structure 20 does not exist, the third substrate opening 403 may continue to extend along the third direction Z and the first direction X, so that the adjacent third substrate openings are interconnected to cause the semiconductor structure to fail, and even cause the top stack structure to peel off and collapse, thereby affecting the performance and yield of the semiconductor structure.

[0055] As shown in FIG. 2N, in the process of removing the first sacrificial layer 502 in the second opening 302, the third base opening 403 is etched to form a base opening 404, the base opening 404 exposes the upper surface of the isolation structure 20, the length of the base opening 404 along the first direction X is a fifth length D5, the fifth length D5 is greater than the fourth length D4, the fifth length D5 is less than the first length D1; the depth of the base opening 404 along the third direction Z is a fifth interval H5, the fifth interval H5 is greater than the fourth interval H4, the fifth interval H5 is equal to the first interval H1. The base opening 404 stops on the isolation structure 20, that is, the base opening 404 exposes the upper surface of the isolation structure 20, which prevents the base opening 404 from continuing to extend along the third direction Z, prevents interconnection between adjacent base openings and collapse of the layered structure, and improves the performance and yield of the semiconductor structure.

[0056] As shown in FIGS. 2N-2P, the layered opening 301, the base opening 404 and the second opening 302 jointly constitute a joint opening K2, and the capacitor structure 50 is formed in the joint opening K2, specifically including: forming the first conductive layer 501 in the second opening 302, the first conductive layer 501 covers only the exposed surface of the second opening 302; forming the dielectric layer 502 on the first conductive layer 302, and forming the second conductive layer 505 on the dielectric layer 502, the second conductive layer 505 includes the third conductive layer 503 and the fourth conductive layer 504, the second conductive layer 505 fills the remaining joint opening K2, and the first conductive layer 501, the dielectric layer 502 and the second conductive layer 505 jointly constitute the capacitor structure 50, the capacitor structure 50 extends along the first direction X and is spaced apart in the second direction Y and the third direction Z; the first conductive layer 501 and the third conductive layer 503 can be one or more of a metal (such as tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal nitride, a metal silicide, a metal carbide, such as at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), etc. The fourth conductive layer 504 can be one or more of polysilicon or conductive doped semiconductor material, such as conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc. The dielectric layer 502 can be silicon oxide, silicon nitride or silicon oxynitride, etc.

[0057] FIGS. 3A-3P are process flow diagrams of a method for manufacturing a semiconductor structure according to another embodiment of the present disclosure.

[0058] Referring to FIG. 1 and FIG. 3A-3B, a substrate 10 is provided, a photoresist layer S102 is formed on the substrate 10, the photoresist layer S102 has a first opening S101, the substrate 10 is subjected to a first treatment through the first opening S101 to form a second initial isolation structure 22' in the substrate 10, and the second initial isolation structure 22' is subjected to a second treatment to form an isolation structure 20, a top of the isolation structure 20 has a first spacing H1 from a surface of the substrate, a plurality of the isolation structures 20 are arranged at intervals, adjacent isolation structures 20 have a first width M1 along a first direction X, the first direction X refers to a direction in which the isolation structure 20 extends, and the first direction X is parallel to the surface of the substrate 10; the first treatment can be plasma implantation, different depths of the second initial isolation structure 22' can be obtained by controlling the energy of the plasma implantation, different concentrations of the second initial isolation structure 22' can be obtained by controlling the dose of the plasma implantation, and different positions of the second initial isolation structure 22' can be obtained by controlling the angle of the plasma implantation, and the second initial isolation structure 22' required can be obtained by controlling the energy, dose and angle of the plasma implantation according to process requirements, and in an embodiment, the element of the ion implantation can be oxygen atoms. The second treatment can be a high-temperature annealing treatment, and in a specific embodiment, the oxygen element of the ion implantation reacts with the silicon substrate through high-temperature annealing to form the isolation structure 20, and the material of the isolation structure 20 can be silicon oxide. Here, only silicon oxide is taken as an example for description, and in other embodiments, the material of the isolation structure 20 can be silicon nitride, silicon oxynitride, etc. The material of the substrate can be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); can also be silicon on insulator (SOI), germanium on insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds, and the material of the substrate in the present embodiment is silicon.

[0059] Different from the previous embodiment, in the present embodiment, the length of the isolation structure 20 along the first direction X is an original length D1', the original length D1' is less than the first length D1, the first width M1 between adjacent isolation structures 20 along the first direction X is much greater than the original length D1', the surface of the substrate has a first spacing H1 from the top of the isolation structure 20, and the surface of the substrate has a bottom spacing H1' from the bottom of the isolation structure 20.

[0060] Fig. 3C-3D are another embodiment of forming the isolation structure 20. As shown in Fig. 3C, forming the isolation structure 20 in the substrate 10 specifically includes: etching the substrate 10 to form a first trench 200', the first trench 200' is spaced apart, filling the first trench 200' with oxide to form the isolation structure 20, the top of the isolation structure 20 is flush with the substrate 10, the length of the isolation structure 20 along the first direction X is the self-length D1', the self-length D1' is less than the first length D1, the first width M1 between adjacent isolation structures 20 along the first direction X is much greater than the self-length D1', and the bottom spacing H1' between the substrate surface and the bottom of the isolation structure 20. The top of the isolation structure 20 can be flush with the upper surface of the substrate 10, or can have a first spacing H1 with the upper surface of the substrate 10, which is not limited here and can be selected according to process needs; the top of the isolation structure 20 and the upper surface of the substrate 10 have a first spacing H1 in the subsequent steps.

[0061] Referring to Fig. 1 and Fig. 3E, a stack structure 101 is formed on the substrate 10, the stack structure 101 is formed by alternately stacking a first layer 102 and a second layer 103 in a third direction Z, the third direction Z is perpendicular to the substrate surface; and the stack structure 101 further includes an etching stop layer 201 and a hard mask layer 202 above the stack structure 101, the etching stop layer 201 is located above the stack structure 101, and the hard mask layer 202 is located above the etching stop layer 201, the etching stop layer 201 and the hard mask layer 202 provide protection for subsequent etching to form a stack opening and a substrate opening, and prevent damage to the stack structure 101.

[0062] Referring to Fig. 1 and Fig. 3F-3G, a stack opening 301 is formed, the stack opening 301 passes through the stack structure 101 along the third direction Z and stops at the upper surface of the substrate 10; and before forming the stack opening 301, a photoresist layer S102 is formed on the stack structure 101, the photoresist layer S102 has an opening, and the stack structure 101 is etched through the opening to form the stack opening 301.

[0063] Referring to FIG. 1 and FIG. 3H, a first substrate opening 401 is formed below the stack opening 301 and extends into the substrate 10, the first substrate opening 401 and the stack opening 301 have the same length along the first direction X, both are the second length D2, the second length D2 is less than the first width M1, the first substrate opening 401 extends into the substrate 10 by the second interval H2; the stack opening 301 and the first substrate opening 401 jointly form a first opening K1, the orthographic projection of the first opening K1 on the substrate 10 is between the adjacent isolation structures 20, that is, the second length D2 of the first opening K1 is less than the first width M1 between the adjacent isolation structures 20, the orthographic projection of the first opening K1 on the substrate 10 can be in the middle of the adjacent isolation structures 20 or deviate from the middle of the adjacent isolation structures 20, the middle means that the central axis of the first opening K1 coincides with the middle line between the adjacent isolation structures 20, but the orthographic projection of the first opening K1 on the isolation structure 20 cannot deviate from the first width M1 of the adjacent isolation structure 20; in the process of forming the first substrate opening 401, the hard mask layer 202 and the photoresist layer S102 on the top of the stack structure 101 are also removed; the first opening K1 arranged between the adjacent isolation structures 20 can prevent the leakage and short circuit phenomenon caused by over-etching of the substrate 10 in the later stage.

[0064] Referring to FIG. 1 and FIG. 3I, the second layer 103 is removed to form the second opening 302, and the first base opening 401 is etched to form the second base opening 402 in the process of laterally etching the second layer 103 to form the second opening 302. The second base opening 402 has a third length D3 along the first direction X, and the first base opening 401 has a second length D2 along the first direction X. The third length D3 can be greater than or equal to the second length D2. In the embodiment, the third length D3 is equal to the second length D2. The second base opening 402 extends to the substrate 10 along the third direction Z to a third interval H3, and the first base opening 401 extends to the substrate 10 along the third direction Z to a second interval H2. The third interval H3 is greater than the second interval H2. The first direction X is parallel to the surface of the substrate 10, and the third direction Z is perpendicular to the surface of the substrate 10. The stack opening 301, the second opening 302, and the second base opening 402 together form a third opening 303. Over-etching of the substrate 10 can occur in the process of laterally etching the second layer 103 to form the second opening 302. The over-etching of the substrate 10 can occur in the lateral direction or in the vertical direction. That is, the substrate 10 can be over-etched along the first direction X or along the third direction Z in the process of laterally etching the second layer 103 to form the second opening 302. In FIG. 3I, the second base opening 402 along the first direction has a width D3 that does not expose the isolation structure 20. That is, the third length D3 is less than the first width M1. In other embodiments, the second base opening 402 along the first direction can expose the isolation structure 20. That is, the third length D3 is equal to the first width M1. The presence of the isolation structure 20 can limit the over-etching of the substrate 10. That is, the over-etching of the substrate 10 is limited between adjacent isolation structures 20, and further damage to the substrate 10 in the lateral direction is prevented.

[0065] Referring to FIG. 1 and FIG. 3J-3N, as shown in FIG. 3I-3J, the stack opening 301, the second opening 302 and the second substrate opening 402 jointly form a third opening 303, a first conductive material layer 501' is formed in the third opening 303, and the first conductive material layer 501' covers the surface exposed by the third opening 303; as shown in FIG. 3K, a first sacrificial layer 502 is formed, and the first sacrificial layer 502 fills the remaining third opening 303; as shown in FIG. 3L, part of the first sacrificial layer 502 is removed to form a fourth opening 304, and the remaining first sacrificial layer 502 is only located in the second opening 302, and the fourth opening 304 exposes part of the first conductive material layer 501', as shown in FIG. 3L, the fourth opening 304 exposes the first conductive material layer 501' on the sidewall of the first layer 102 and the surface of the second substrate opening 402; as shown in FIG. 3M, the first conductive material layer 501' exposed by the fourth opening 304 is removed, and the remaining first conductive material layer 501' serves as a first conductive layer 501; as shown in FIG. 3N, after the first conductive material layer 501' exposed by the fourth opening 304 is removed, the first sacrificial layer 502 in the second opening 302 is also removed; in the process of removing the first sacrificial layer 502 in the second opening 302, the substrate 10 is also over-etched, so that a substrate opening 404 is formed by etching the second substrate opening 402, and the stack opening 301, the substrate opening 404 and the second opening 302 jointly form a joint opening K2; the length of the substrate opening 404 along the first direction X is a fourth length D4, and the fourth length D4 is less than the first width M1; the depth of the substrate opening 404 along the third direction Z is a fourth interval H4, and the fourth interval H4 is less than the bottom interval H1'; FIG. 3N only schematically shows that the fourth length D4 is less than the first width M1; it should be pointed out that even if the fourth length is equal to the first width M1, it will not affect the performance of the substrate 10, because the existence of the isolation structure 20 makes the substrate 10 stay between adjacent isolation structures 20 in the process of over-etching, and the isolation structure 20 has a large etching selectivity ratio with the substrate 10, so that the substrate opening 404 will not exceed the isolation structure 20 even if it extends along the first direction, and without the existence of the isolation structure 20, the substrate opening 404 may continue to extend along the first direction X, so that the adjacent substrate openings are interconnected to cause the semiconductor structure to fail, and even the top stack structure may be peeled off and collapsed, affecting the performance and yield of the semiconductor structure.

[0066] Referring to FIGS. 1 and 3O-3P, the stack opening 301, the substrate opening 404 and the second opening 302 jointly form a joint opening K2 in which the capacitor structure 50 is formed, specifically including: forming the first conductive layer 501 in the second opening 302, the first conductive layer 501 covering only the exposed surface of the second opening 302; forming the dielectric layer 502 on the first conductive layer 302, and forming the second conductive layer 505 on the dielectric layer 502, the second conductive layer 505 including the third conductive layer 503 and the fourth conductive layer 504, the second conductive layer 505 filling the remaining joint opening K2, the first conductive layer 501, the dielectric layer 502 and the second conductive layer 505 jointly forming the capacitor structure 50, the capacitor structure 50 extending along the first direction X and being spaced apart in the second direction Y and the third direction Z; the first conductive layer 501 and the third conductive layer 503 can be one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal nitride, a metal silicide, a metal carbide, such as at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), etc. The fourth conductive layer 504 can be one or more of polysilicon or a conductive doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc. The dielectric layer 502 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0067] FIGS. 4A-4O are process flow diagrams of a method of fabricating a semiconductor structure according to another embodiment of the present disclosure.

[0068] Referring to FIG. 1 and FIG. 4A-4C, a substrate 10 is provided, a photoresist layer S102 is formed on the substrate 10, the photoresist layer S102 has a first opening S101 therebetween, the substrate 10 is subjected to a first treatment through the first opening S101 to form a first initial isolation structure 21' in the substrate 10; then a new photoresist layer S102 is formed, the photoresist layer S102 has a second opening S202 therebetween, the substrate 10 is subjected to a first treatment through the second opening S202 to form a second initial isolation structure 22' in the substrate 10; the first initial isolation structure 21' and the second initial isolation structure 22' are subjected to a second treatment to form a first isolation structure 21 and a second isolation structure 22 respectively, the first isolation structure 21 and the second isolation structure 22 together form an isolation structure 20; the first isolation structure 21 has a first width M1 along a first direction X, the first isolation structure 21 has a bottom spacing H1' between an upper surface thereof and a surface of the substrate 10; the second isolation structure 22 has a first spacing H1 between a top thereof and the surface of the substrate 10, the second isolation structure 22 has a bottom spacing H1' between a bottom thereof and the surface of the substrate 10, the second isolation structure 22 has a length D1' along the first direction X; the first isolation structures 21 are arranged at intervals along the first direction X, and the second isolation structures 22 are also arranged at intervals along the first direction X. The first treatment can be plasma implantation, by controlling the energy of the plasma implantation, different depths of the first initial isolation structure 21' and the second initial isolation structure 22' can be obtained, by controlling the dose of the plasma implantation, different concentrations of the first initial isolation structure 21' and the second initial isolation structure 22' can be obtained, by controlling the angle of the plasma implantation, different positions of the first initial isolation structure 21' and the second initial isolation structure 22' can be obtained, according to process requirements, the required first initial isolation structure 21' and the second initial isolation structure 22' can be obtained by controlling the energy, dose and angle of the plasma implantation, in an embodiment, the implanted element can be oxygen atoms. The second treatment can be a high-temperature annealing treatment, specifically, in an embodiment, the implanted oxygen element reacts with the silicon substrate through high-temperature annealing to form the first isolation structure 21 and the second isolation structure 22, the isolation structure 20 is composed of the first isolation structure 21 and the second isolation structure 22, and the material of the isolation structure 20 can be silicon oxide. Here, only silicon oxide is taken as an example for description, in other embodiments, the material of the isolation structure 20 can be silicon nitride, silicon oxynitride, etc. The material of the substrate can be silicon (Si), germanium (Ge), silicon germanium (GeSi), or silicon carbide (SiC); can also be silicon on insulator (SOI), germanium on insulator (GOI); or can also be other materials, such as gallium arsenide and other group III-V compounds, in the embodiment, the material of the substrate is silicon.

[0069] Different from other embodiments, in the present embodiment, the isolation structure 20 is composed of a first isolation structure 21 and a second isolation structure 22, the first isolation structure 21 has a first width M1 along the first direction X, and a bottom spacing H1' between the upper surface of the first isolation structure 21 and the surface of the substrate 10; the second isolation structure 22 has a first spacing H1 between the top and the surface of the substrate 10, and a bottom spacing H1' between the bottom and the surface of the substrate 10, and the length of the second isolation structure 22 along the first direction X is the original length D1'; the first isolation structures 21 are arranged at intervals along the first direction X, and the second isolation structures 22 are also arranged at intervals along the first direction X, and the adjacent second isolation structures 22 and the closest first isolation structures 21 form an enclosing shape, so that the isolation structure 20 can enclose the substrate opening from the bottom and the side during the process of forming the substrate opening later, preventing the over-etching of the substrate opening from affecting the performance of the semiconductor structure.

[0070] Please refer to FIG. 1 and FIG. 4D, a stack structure 101 is formed on the substrate 10, the stack structure 101 is composed of first layers 102 and second layers 103 stacked alternately in the third direction Z, the third direction Z is perpendicular to the surface of the substrate; and the stack structure 101 further includes an etching stop layer 201 and a hard mask layer 202, the etching stop layer 201 is located above the stack structure 101, and the hard mask layer 202 is located above the etching stop layer 201, the etching stop layer 201 and the hard mask layer 202 provide protection for subsequent etching to form stack openings and substrate openings, preventing damage to the stack structure 101.

[0071] Please refer to FIG. 1 and FIG. 4E-4F, a stack opening 301 is formed, the stack opening 301 passes through the stack structure 101 along the third direction Z and stops at the upper surface of the substrate 10; before forming the stack opening 301, a photoresist layer S102 is formed on the stack structure 101, the photoresist layer S102 has openings between them, and the stack structure 101 is etched through the openings to form the stack opening 301.

[0072] Referring to FIG. 1 and FIG. 4G, a first substrate opening 401 is formed below the stack opening 301 and extends into the substrate 10, the first substrate opening 401 and the stack opening 301 have the same length along the first direction X, both are the second length D2, the second length D2 is less than the first width M1, the first substrate opening 401 extends into the substrate 10 by the second interval H2; the stack opening 301 and the first substrate opening 401 jointly form a first opening K1, the orthographic projection of the first opening K1 on the substrate 10 is between the adjacent isolation structures 20, that is, the second length D2 of the first opening K1 is less than the first width M1 between the adjacent isolation structures 20, the orthographic projection of the first opening K1 on the substrate 10 can be in the middle of the adjacent isolation structures 20 or deviate from the middle of the adjacent isolation structures 20, the middle means that the central axis of the first opening K1 coincides with the middle line between the adjacent isolation structures 20, but the orthographic projection of the first opening K1 on the isolation structure 20 cannot deviate from the first width M1 of the adjacent isolation structure 20; in the process of forming the first substrate opening 401, the hard mask layer 202 and the photoresist layer S102 on the top of the stack structure 101 are also removed; the first opening K1 arranged between the adjacent isolation structures 20 can prevent the leakage and short circuit phenomenon caused by over-etching of the substrate 10 in the later stage.

[0073] Referring to FIG. 1 and FIG. 4H, the second layer 103 is removed to form the second opening 302, and the first base opening 401 is etched to form the second base opening 402 in the process of laterally etching the second layer 103 to form the second opening 302. The second base opening 402 has a third length D3 along the first direction X, and the first base opening 401 has a second length D2 along the first direction X. The third length D3 can be greater than or equal to the second length D2. In this embodiment, the third length D3 is equal to the second length D2. The second base opening 402 extends to the substrate 10 along the third direction Z to a third distance H3, and the first base opening 401 extends to the substrate 10 along the third direction Z to a second distance H2. The third distance H3 is greater than the second distance H2. The first direction X is parallel to the surface of the substrate 10, and the third direction Z is perpendicular to the surface of the substrate 10. The stack opening 301, the second opening 302, and the second base opening 402 together form a third opening 303. Over-etching of the substrate 10 occurs in the process of laterally etching the second layer 103 to form the second opening 302. The over-etching of the substrate 10 can occur in the lateral direction or in the vertical direction. That is, the substrate 10 is over-etched along the first direction X and along the third direction Z in the process of laterally etching the second layer 103 to form the second opening 302. In FIG. 3I, the second base opening 402 does not expose the isolation structure 20 along the first direction, that is, the third length D3 is less than the first width M1. However, in other embodiments, the second base opening 402 can expose the isolation structure 20 along the first direction, that is, the third length D3 is equal to the first width M1. The presence of the isolation structure 20 can limit the over-etching of the substrate 10 in the lateral direction or in the vertical direction. The over-etching of the substrate 10 is limited within the isolation structure 20, preventing further damage to the substrate 10.

[0074] Referring to FIG. 1 and FIG. 4I-4M, the combined opening K2 is formed, as shown in FIG. 4H-4I, the stack opening 301, the second opening 302 and the second substrate opening 402 jointly form the third opening 303, the first conductive material layer 501' is formed in the third opening 303, the first conductive material layer 501' covers the surface exposed by the third opening 303; as shown in FIG. 4J, the first sacrificial layer 502 is formed, the first sacrificial layer 502 fills the remaining third opening 303; as shown in FIG. 4K, part of the first sacrificial layer 502 is removed to form the fourth opening 304, the remaining first sacrificial layer 502 is only located in the second opening 302, the fourth opening 304 exposes part of the first conductive material layer 501', as shown in FIG. 4K, the fourth opening 304 exposes the first conductive material layer 501' on the sidewall of the first layer 102 and the surface of the second substrate opening 402; as shown in FIG. 4L, the first conductive material layer 501' exposed by the fourth opening 304 is removed, the remaining first conductive material layer 501' serves as the first conductive layer 501; as shown in FIG. 4M, after the first conductive material layer 501' exposed by the fourth opening 304 is removed, the first sacrificial layer 502 in the second opening 302 is also removed; in the process of removing the first sacrificial layer 502 in the second opening 302, the substrate 10 is also etched to form the substrate opening 404 in the second substrate opening 402, the stack opening 301, the substrate opening 404 and the second opening 302 jointly form the combined opening K2; the length of the substrate opening 404 along the first direction X is a fourth length D4, the fourth length D4 is less than the first width M1; the depth of the substrate opening 404 along the third direction Z is a fourth interval H4, the fourth interval H4 is less than the bottom interval H1', FIG. 4M only schematically shows that the fourth length D4 is less than the first width M1 and the fourth interval H4 is less than the bottom interval H1'; it should be pointed out that even if the fourth length is equal to the first width M1 and the fourth interval H4 is equal to the bottom interval H1', it will not affect the performance of the substrate 10, because the first isolation structure 21 limits the over-etching of the substrate 10 from the bottom, and the second isolation structure 22 limits the over-etching of the substrate 10 from the side, that is, the isolation structure 20 surrounds the substrate opening 404, the existence of the isolation structure 20 makes the substrate 10 stay within the isolation structure 20 in the process of over-etching, the large etching selectivity between the isolation structure 20 and the substrate 10 makes the substrate opening 404 not exceed the isolation structure 20 even if it extends along the first direction and the third direction, if there is no isolation structure 20, the substrate opening 404 may continue to extend along the first direction X, which may cause the adjacent substrate openings to be interconnected, resulting in failure of the semiconductor structure, and even the top stack structure may be peeled off and collapsed, affecting the performance and yield of the semiconductor structure; the existence of the isolation structure 20 prevents the stack structure from being peeled off and collapsed, and improves the performance and yield of the semiconductor structure.

[0075] Referring to FIG. 1 and FIG. 4N-4O, the stack opening 301, the substrate opening 404 and the second opening 302 jointly form a joint opening K2 in which the capacitor structure 50 is formed, specifically including: forming the first conductive layer 501 in the second opening 302, the first conductive layer 501 covering only the exposed surface of the second opening 302; forming the dielectric layer 502 on the first conductive layer 302, and forming the second conductive layer 505 on the dielectric layer 502, the second conductive layer 505 including the third conductive layer 503 and the fourth conductive layer 504, the second conductive layer 505 filling the remaining joint opening K2, the first conductive layer 501, the dielectric layer 502 and the second conductive layer 505 jointly forming the capacitor structure 50, the capacitor structure 50 extending along the first direction X and being spaced apart in the second direction Y and the third direction Z; the first conductive layer 501 and the third conductive layer 503 can be one or more of a metal (e.g., tungsten, titanium, nickel, platinum, rhodium, ruthenium, aluminum, copper, molybdenum, iridium, silver, gold), a metal alloy, a metal nitride, a metal silicide, a metal carbide, such as at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrOx), ruthenium oxide (RuOx), etc. The fourth conductive layer 504 can be one or more of polysilicon or a conductive doped semiconductor material, such as conductively doped silicon, conductively doped germanium, conductively doped silicon germanium, etc. The dielectric layer 502 can be silicon oxide, silicon nitride, or silicon oxynitride, etc.

[0076] FIG. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure.

[0077] Referring to FIG. 5, the semiconductor structure provided by an embodiment of the present disclosure includes a substrate 10, the substrate 10 has an isolation structure 20 therein, the isolation structure 20 is arranged in an interval manner; a stack structure 101 is arranged on the substrate 10, the stack structure 101 is formed by alternately stacking a first layer 102 and a second layer 103 in a third direction Z, the third direction Z is perpendicular to the surface of the substrate 10; a stack opening 301 is shown by a dashed line in the figure, the stack opening 301 penetrates the stack structure 101 along the third direction Z; a substrate opening 404 is shown by a dashed line in the figure, the substrate opening 404 is below the stack opening 301 and extends into the substrate 10, the size of the substrate opening 404 along a first direction X is greater than the size of the stack opening 301 along the first direction X, the length of the substrate opening 404 along the first direction X is a fifth length D5, the length of the isolation structure along the first direction X is a first length D1, the fifth length D5 is less than the first length D1; the orthographic projection of the substrate opening 404 on the substrate 10 is located in the orthographic projection of the isolation structure 20 on the substrate 10. The isolation structure 20 is located at the bottom of the substrate opening 404, and the substrate opening 404 exposes the upper surface of the isolation structure 20. The top of the isolation structure 20 and the top of the substrate 10 have a first interval H1; a second opening 302 is shown by a dashed line in the figure, the second opening 302 is formed by removing part of the second layer 103, the stack opening 301, the substrate opening 404 and the second opening 302 jointly constitute a joint opening K2; a capacitor structure 50 is located in the joint opening K2, the capacitor structure is located above the isolation structure, the capacitor structure 50 extends along the first direction X and is arranged in an interval manner in the second direction Y and the third direction Z. The presence of the isolation structure 20 prevents the stack structure 101 from being peeled off and collapsed, and prevents the problems such as electric leakage or short circuit caused by over-etching of the substrate 10, and improves the performance and yield of the semiconductor structure.

[0078] FIG. 6 is a schematic view of a semiconductor structure provided by another embodiment of the present disclosure.

[0079] Referring to FIG. 6, another embodiment of the present disclosure provides a semiconductor structure including a substrate 10, the substrate 10 having isolation structures 20 spaced apart, the isolation structures 20 having a self-width D1’ along a first direction X, adjacent isolation structures 20 having a first width M1 along the first direction X; a stack structure 101 disposed on the substrate 10, the stack structure 101 formed by first layers 102 and second layers 103 stacked alternately along a third direction Z perpendicular to a surface of the substrate 10; a stack opening 301 shown by dashed lines in the figure, the stack opening 301 extending through the stack structure 101 along the third direction Z; a substrate opening 404 shown by dashed lines in the figure, the substrate opening 404 extending into the substrate 10 below the stack opening 301, the substrate opening 404 having a size along the first direction X greater than that of the stack opening 301 along the first direction X; the substrate opening 404 having a fourth length D4 along the first direction X, adjacent isolation structures 20 having the first width M1 along the first direction X, the fourth length D4 being less than the first width M1; a projection of the substrate opening 404 on the substrate 10 being located between adjacent isolation structures 20, i.e., the isolation structures 20 being located on both sides of the substrate opening 404. The isolation structures 20 have a first spacing H1 from a top of the substrate 10, the substrate 10 has a bottom spacing H1’ from a bottom of the isolation structures 20, the substrate opening 404 has a fourth spacing H4 along the third direction Z, the fourth spacing H4 being less than the bottom spacing H1’. A second opening 302 shown by dashed lines in the figure, the second opening 302 being formed by removing part of the second layers 103, the stack opening 301, the substrate opening 404 and the second opening 302 jointly forming a joint opening K2; a capacitor structure 50 located in the joint opening K2, the capacitor structure 50 being located above the isolation structures 20, the capacitor structure 50 extending along the first direction X and being spaced apart along a second direction Y and the third direction Z. The presence of the isolation structures 20 prevents the stack structure from being peeled off and collapsed due to over-etching of the substrate, and prevents problems such as leakage or short circuit, thereby improving the performance and yield of the semiconductor structure.

[0080] FIG. 7 is a schematic view of a semiconductor structure according to another embodiment of the present disclosure.

[0081] Referring to FIG. 7, the semiconductor structure provided by another embodiment of the present disclosure includes a substrate 10, and the substrate 10 has an isolation structure 20. In this embodiment, the isolation structure 20 is composed of a first isolation structure 21 and a second isolation structure 22. The first isolation structure 21 has a first width M1 along a first direction X. The first isolation structure 21 has a bottom spacing H1' between its upper surface and the surface of the substrate 10. The second isolation structure 22 has a first spacing H1 between its top and the surface of the substrate 10. The second isolation structure 22 has a bottom spacing H1' between its bottom and the surface of the substrate 10. The second isolation structure 22 has a length D1' along the first direction X. The first isolation structure 21 is arranged at intervals along the first direction X. The second isolation structure 22 is also arranged at intervals along the first direction X. A laminated structure 101 is arranged on the substrate 10. The laminated structure 101 is composed of a first layer 102 and a second layer 103 stacked alternately along a third direction Z perpendicular to the surface of the substrate 10. A laminated opening 301 is shown by the dashed line in the figure. The laminated opening 301 penetrates the laminated structure 101 along the third direction Z. A substrate opening 404 is shown by the dashed line in the figure. The substrate opening 404 extends into the substrate 10 below the laminated opening 301. The size of the substrate opening 404 along the first direction X is greater than that of the laminated opening 301 along the first direction X. The length of the substrate opening 404 along the first direction X is a fourth length D4. The first width M1 of the adjacent isolation structure 20 along the first direction X is greater than the fourth length D4. The orthographic projection of the substrate opening 404 on the substrate 10 is located between the adjacent isolation structures 20, i.e., the isolation structure 20 is located on both sides of the substrate opening 404. The top of the isolation structure 20 and the top of the substrate 10 have a first spacing H1. The bottom of the substrate 10 and the bottom of the isolation structure 20 have a bottom spacing H1'. The depth of the substrate opening 404 along the third direction Z is a fourth spacing H4, which is less than the bottom spacing H1'. A second opening 302 is shown by the dashed line in the figure. The second opening 302 is formed by removing part of the second layer 103. The laminated opening 301, the substrate opening 404, and the second opening 302 jointly constitute a combined opening K2. A capacitor structure 50 is located in the combined opening K2. The capacitor structure 50 is located above the isolation structure 20. The capacitor structure 50 extends along the first direction X and is arranged at intervals along the second direction Y and the third direction Z. The adjacent second isolation structure 22 and the closest first isolation structure 21 form an enclosure. The isolation structure 20 can enclose the substrate opening 404 from the bottom and the side, preventing the over-etching of the substrate opening 404 from affecting the performance of the semiconductor structure. That is, the presence of the isolation structure 20 prevents the peeling and collapse of the laminated structure caused by the over-etching of the substrate, and prevents the problems such as leakage or short circuit, thereby improving the performance and yield of the semiconductor structure.

[0082] Those skilled in the art can understand that the above-mentioned embodiments are specific embodiments for realizing the present disclosure, and in actual applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make respective changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be limited by the scope defined by the claims.

Claims

1. A method for manufacturing a semiconductor structure, comprising: providing a substrate (10) and forming isolation structures (20) in the substrate (10), the isolation structures (20) being spaced apart; forming a stack structure (101) on the substrate (10), the stack structure (101) being formed by first layers (102) and second layers (103) being alternately stacked in a third direction (Z), the third direction (Z) being perpendicular to a surface of the substrate (10); forming a stack opening (301) through the stack structure (101) in the third direction (Z); forming a first substrate opening (401) below the stack opening (301) and extending into the substrate (10), the stack opening (301) and the first substrate opening (401) forming a first opening (K1), a projection of the first opening (K1) on the substrate (10) being located within a projection of the isolation structures (20) on the substrate (10) and / or the projection of the first opening (K1) on the substrate (10) being located between adjacent isolation structures (20); removing part of the second layers (103) to form second openings (302) and etching the first substrate opening (401) to form a substrate opening (404), the stack opening (301), the substrate opening (404) and the second openings (302) jointly forming a combined opening (K2); forming a capacitor structure (50) in the combined opening (K2), the capacitor structure (50) extending in a first direction (X) and being spaced apart in a second direction (Y) and the third direction (Z).

2. The method of producing a semiconductor structure according to claim 1, wherein the removing part of the second layers (103) to form the second openings (302) further comprises etching the first substrate opening (401) to form a second substrate opening (402), a dimension of the second substrate opening (402) in the first direction (X) being greater than a dimension of the first substrate opening (401) in the first direction (X); a depth of the second substrate opening (402) in the third direction (Z) is greater than a depth of the first substrate opening (401) in the third direction (Z), the first direction (X) being parallel to the surface of the substrate (10), the first direction (X) being perpendicular to the third direction (Z).

3. The method of producing a semiconductor structure according to claim 2, wherein, Also included are: the stack opening (301), the second opening (302) and the second substrate opening (402) jointly constitute a third opening (303), a first conductive material layer (501') is formed in the third opening (303), the first conductive material layer (501') covers the surface exposed by the third opening (303); a first sacrificial layer (502) is formed, the first sacrificial layer (502) fills the remaining third opening (303); part of the first sacrificial layer (502) is removed to form a fourth opening (304), the remaining first sacrificial layer (502) is only located in the second opening (302); part of the first conductive material layer (501') exposed by the fourth opening (304) is removed, the first sacrificial layer (502) in the second opening (302) is removed, and the remaining first conductive material layer (501') serves as a first conductive layer (501).

4. The method of producing a semiconductor structure according to claim 3, wherein In the process of removing part of the first conductive material layer (501') exposed by the fourth opening (304), the second substrate opening (402) is etched to form a third substrate opening (403), the third substrate opening (403) has a size along the first direction (X) greater than that of the second substrate opening (402) along the first direction (X); the third substrate opening (403) has a depth along the third direction (Z) greater than that of the second substrate opening (402) along the third direction (Z).

5. The method of producing a semiconductor structure according to claim 4, wherein, In the process of removing the first sacrificial layer (502) in the second opening (302), the third substrate opening (403) is etched to form the substrate opening (404), the substrate opening (404) exposes the upper surface of the isolation structure (20) and / or the isolation structure (20) located on both sides of the substrate opening (404).

6. The method of producing a semiconductor structure according to claim 5, wherein The stack opening (301), the substrate opening (404) and the second opening (302) jointly constitute a joint opening (K2), and a capacitor structure (50) is formed in the joint opening (K2), specifically including: forming a first conductive layer (501) in the second opening (302), the first conductive layer (501) only covers the surface exposed by the second opening (302); a dielectric layer (502) is formed on the first conductive layer (501), and a second conductive layer (505) is formed on the dielectric layer (502), the second conductive layer (505) fills the remaining joint opening (K2), and the first conductive layer (501), the dielectric layer (502) and the second conductive layer (505) jointly constitute the capacitor structure (50).

7. The method of producing a semiconductor structure according to claim 6, wherein The isolation structure (20) is located on both sides of the substrate opening (404), and a bottom distance (H1') is provided between the bottom of the isolation structure (20) along the third direction (Z) and the surface of the substrate (10), and the substrate opening (404) has a fourth distance along the third direction (Z), and the fourth distance is not greater than the bottom distance (H1').

8. The method of fabricating a semiconductor structure of claim 1, wherein, The formation of the isolation structure (20) in the substrate (10) specifically comprises: forming a photoresist layer (S102) and defining a first opening (S101), performing a first treatment through the first opening (S101) to form a first initial isolation structure (21'), and performing a second treatment on the first initial isolation structure (21') to form the isolation structure (20), wherein the top of the isolation structure (20) has a first distance (H1) from the surface of the substrate (10).

9. The method of fabricating a semiconductor structure of claim 1, wherein, The formation of the isolation structure (20) in the substrate (10) specifically comprises: etching the substrate (10) to form a first groove (200'), and the first groove (200') is arranged in an interval, and the isolation structure (20) is formed in the first groove (200'), and the top of the isolation structure (20) is flush with the substrate (10).

10. The method of fabricating a semiconductor structure of claim 1, wherein, The formation of the isolation structure (20) in the substrate (10) specifically comprises: forming a photoresist layer (S102) and defining a first opening (S101), performing a first treatment through the first opening (S101) to form a first initial isolation structure (21'), forming a photoresist layer (S102) and defining a second opening (S202), performing a first treatment through the second opening (S202) to form a second initial isolation structure (22'), and performing a second treatment on the first initial isolation structure (21') and the second initial isolation structure (22') to form a first isolation structure (21) and a second isolation structure (22) respectively, wherein the first isolation structure (21) and the second isolation structure (22) constitute the isolation structure (20), the first isolation structure (21) is located at the bottom of the first substrate opening (401), and the second isolation structure (22) is located at the side of the first substrate opening (401).

11. The method of fabricating a semiconductor structure of claim 1, wherein, After forming the second opening (302), the method further comprises removing part of the first layer (102) to form a first expanded hole (302'), and the size of the first expanded hole (302') along the third direction (Z) is greater than the size of the second opening (302) along the third direction (Z).

12. A semiconductor structure, comprising: a substrate (10) having an isolation structure (20) arranged in an interval in the substrate (10); a laminated structure (101) arranged on the substrate (10), the laminated structure (101) being formed by alternately stacking a first layer (102) and a second layer (103) in a third direction (Z), and the third direction (Z) being perpendicular to the surface of the substrate (10); a laminated opening (301) penetrating through the laminated structure (101) along the third direction (Z). a substrate opening (404) below the stack opening (301) and extending into the substrate (10), the substrate opening (404) having a dimension along the first direction (X) that is greater than a dimension of the stack opening (301) along the first direction (X); the isolation structure (20) is located at least at a side and / or a bottom of the substrate opening (404); a second opening (302) formed by removing part of the second layer (103), the stack opening (301), the substrate opening (404) and the second opening (302) together forming a joint opening (K2); a capacitor structure (50) located in the joint opening (K2), the capacitor structure (50) extending along the first direction (X) and being spaced apart in both the second direction (Y) and the third direction (Z).

13. The semiconductor structure of claim 12, wherein, the isolation structure (20) is located at both sides of the substrate opening (404), a footprint of the substrate opening (404) on the substrate (10) being located between the adjacent isolation structures (20).

14. The semiconductor structure of claim 12, wherein, the isolation structure (20) is located at a bottom of the substrate opening (404), a footprint of the substrate opening (404) on the substrate (10) being located within a footprint of the isolation structure (20) on the substrate (10).

15. The semiconductor structure of claim 12, wherein, the isolation structure (20) comprises a first isolation structure (21) located at a bottom of the substrate opening (404) and a second isolation structure (22) located at a side of the substrate opening (404).

16. The semiconductor structure of claim 13, wherein, a top of the isolation structure (20) has a first spacing (H1) from a top of the substrate (10) or the top of the isolation structure (20) is flush with the top of the substrate (10).

17. The semiconductor structure of claim 16, wherein, a bottom of the isolation structure (20) has a bottom spacing (H1’) from a surface of the substrate (10) along the third direction (Z), the substrate opening (404) has a fourth spacing along the third direction (Z), the fourth spacing being not greater than the bottom spacing (H1’).

18. The semiconductor structure of claim 14, wherein, the substrate opening (404) exposes the isolation structure (20), the capacitor structure (50) being located above the isolation structure (20).

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