Data processing method, data processing apparatus, memory controller, electronic device, storage medium, and computer program product

Abstract

A data processing method, a data processing apparatus, a memory controller, an electronic device, a storage medium, and a computer program product. The data processing method comprises: acquiring data to be transmitted that comprises first data and second data; generating a data block to be transmitted that comprises a first data block generated from the first data and a second data block generated from the second data, and an error correction data block corresponding to the data block to be transmitted, wherein the sum of the number of symbols in the second data block and the number of symbols in the error correction data block is adapted to the data transmission capacity of a data channel for transmitting redundant data, and the ratio of the number of symbols in the second data block to the number of symbols in the error correction data block is less than or equal to 1:3; interleaving error correction data groups to obtain a target data block comprising a payload data area and a redundant data area, the redundant data area being transmitted on the basis of the data channel for the redundant data, and comprising multiple rows of data, wherein at least one row of data comprises both the second data and error correction data, and at least one row of data comprises only error correction data; and transmitting the target data block to a preset device.

Description

Data processing method, data processing apparatus, memory controller, electronic device, storage medium, and computer program product

[0001] This application claims priority to Chinese Patent Application No. 202410840320.1, filed on June 26, 2024, the disclosure of which is incorporated herein in its entirety as part of the present application. TECHNICAL FIELD

[0002] Embodiments of the present disclosure relate to a data processing method, a data processing apparatus, a memory controller, an electronic device, a storage medium, and a computer program product. BACKGROUND

[0003] In a computer system, the ECC (Error Correction Code) technology is a commonly used error correction technology, which is used to detect and correct errors by adding redundant error correction data to the data. However, the addition of redundancy inevitably increases the overall size of the data, thereby to a certain extent, resulting in a decrease in the amount of actual storable and transmittable data, and being unable to store and transmit more data.

[0004] In this context, how to provide a data processing method to achieve storing and transmitting more data while ensuring data transmission quality has become a technical problem that technicians in the field need to solve urgently. SUMMARY

[0005] Therefore, embodiments of the present disclosure provide a data processing method, a data processing apparatus, a memory controller, an electronic device, a storage medium, and a computer program product to achieve storing and transmitting more data while ensuring data transmission quality.

[0006] To achieve the above-mentioned purpose, the embodiments of the present disclosure provide the following technical solutions.

[0007] In a first aspect, the embodiments of the present disclosure provide a data processing method, comprising:

[0008] obtaining to-be-transmitted data; wherein the to-be-transmitted data comprises first data and second data;

[0009] generating a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data, the to-be-transmitted data block comprising a first data block generated by the first data and a second data block generated by the second data, a to-be-transmitted data block and an error correction data block corresponding thereto forming an error correction data group; wherein the sum of the number of symbols of the second data block and the number of symbols in the error correction data block is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols of the second data block to the number of symbols of the error correction data block is less than or equal to 1:3.

[0010] interleaving the error correction data group to obtain a target data block, the target data block comprising an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is based on data channel transmission of the redundant data, the redundant data area comprises multiple rows of data, the second data and the error correction data are included in at least one row of data, and the error correction data is included in at least one row of data;

[0011] transmitting the target data block to a preset device based on a transmission rule of the target data block.

[0012] In a second aspect, the embodiments of the present disclosure provide a data processing method, comprising:

[0013] obtaining a target data block, the target data block being obtained by interleaving an error correction data group, the error correction data group comprising a to-be-transmitted data block and a corresponding error correction data block, the to-be-transmitted data block comprising a first data block generated by first data and a second data block generated by second data; the target data block comprising an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is based on data channel transmission of the redundant data, the redundant data area comprises multiple rows of data, the second data and the error correction data are included in at least one row of data, and the error correction data is included in at least one row of data;

[0014] de-interleaving the target data block to obtain the error correction data group;

[0015] correcting data errors of the to-be-transmitted data block in the error correction data group based on the error correction data block in the error correction data group;

[0016] generating to-be-transmitted data based on the to-be-transmitted data block after error correction.

[0017] In a third aspect, the embodiments of the present disclosure provide a data processing apparatus, comprising:

[0018] a first data acquisition module configured to acquire to-be-transmitted data; wherein the to-be-transmitted data comprises first data and second data;

[0019] The processing module is configured to generate a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data, the to-be-transmitted data block includes a first data block generated by first data and a second data block generated by second data, a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block form an error correction data group; wherein a sum of a number of symbols of the second data block and a number of symbols in the error correction data block is adapted to a data transmission amount of a data channel for transmitting redundant data, and a ratio of the number of symbols of the second data block to the number of symbols of the error correction data block is less than or equal to 1:3.

[0020] The interleaving module is configured to interleave the error correction data group to obtain a target data block, the target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel for redundant data, the redundant data area includes multiple rows of data, the second data and the error correction data are included in at least one row of data, and only the error correction data is included in at least one row of data.

[0021] The data transmission module is configured to transmit the target data block to a preset device based on a transmission rule of the target data block.

[0022] In a fourth aspect, an embodiment of the present disclosure provides a data processing apparatus, including:

[0023] The second data acquisition module is configured to acquire a target data block, the target data block is obtained by interleaving an error correction data group, the error correction data group includes a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block, the to-be-transmitted data block includes a first data block generated by first data and a second data block generated by second data; the target data block includes an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel for redundant data, the redundant data area includes multiple rows of data, the second data and the error correction data are included in at least one row of data, and only the error correction data is included in at least one row of data.

[0024] The deinterleaving module is configured to deinterleave the target data block to obtain an error correction data group.

[0025] The error correction module is configured to correct data errors of the to-be-transmitted data block in the error correction data group based on the error correction data block in the error correction data group.

[0026] The to-be-transmitted data generation module is configured to generate to-be-transmitted data based on the to-be-transmitted data block after error correction.

[0027] In a fifth aspect, an embodiment of the present disclosure provides a memory controller,

[0028] The memory controller is configured with the data processing apparatus according to the third aspect.

[0029] and / or

[0030] The memory controller is configured with the data processing apparatus according to the fourth aspect.

[0031] In a sixth aspect, an electronic device is provided, including the memory controller according to the fifth aspect.

[0032] In a seventh aspect, a storage medium is provided, which stores one or more computer-executable instructions, which, when executed, implement the data processing method according to the first aspect, and / or implement the data processing method according to the second aspect.

[0033] In an eighth aspect, a computer program product is provided, which includes one or more computer-executable instructions, which, when executed, implement the data processing method according to the first aspect, and / or implement the data processing method according to the second aspect.

[0034] The data processing method, the data processing apparatus, the memory controller, the electronic device, the storage medium, and the computer program product are provided, and the method includes: obtaining to-be-transmitted data; wherein the to-be-transmitted data includes first data and second data; based on the to-be-transmitted data, generating a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block, the to-be-transmitted data block including a first data block generated by the first data and a second data block generated by the second data, a to-be-transmitted data block and an error correction data block corresponding thereto forming an error correction data group; wherein the sum of the number of symbols of the second data block and the number of symbols in the error correction data block is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols of the second data block to the number of symbols of the error correction data block is less than or equal to 1:3; interleaving the error correction data group to obtain a target data block, the target data block including an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel for redundant data, the redundant data area includes multiple rows of data, the second data and the error correction data are included in at least one row of data, and only the error correction data is included in at least one row of data; and transmitting the target data block to a preset device based on a transmission rule of the target data block.

[0035] It can be seen that the data processing method provided by the embodiment of the present disclosure, by making the sum of the number of symbols of the second data block and the number of symbols in the error correction data block adapt to the data transmission amount of the data channel for transmitting redundant data, and in the data interleaving step, making the error correction data and the second data interleaved to obtain a redundant data area, the redundant data area is transmitted based on the data channel for transmitting redundant data, so that the error correction data and the second data are transmitted simultaneously in the data channel for transmitting redundant data; and by making the ratio of the number of symbols of the second data block and the number of symbols of the error correction data block less than or equal to 1:3, and in the data interleaving step, making the redundant data area of the target data block obtained by interleaving include the second data and the error correction data in at least one row of data, and only include the error correction data in at least one row of data, so as to ensure the data amount of the error correction data, thereby transmitting more data under the premise of ensuring the error correction capability. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art without any creative effort based on the provided drawings.

[0037] FIG. 1 is a schematic diagram of a data structure;

[0038] FIG. 2 is a schematic diagram of another data structure;

[0039] FIG. 3 is a schematic diagram of an optional flow of a data processing method provided by an embodiment of the present disclosure;

[0040] FIG. 4 is an optional schematic diagram of step S110 in FIG. 3 provided by an embodiment of the present disclosure;

[0041] FIG. 5 is an optional schematic diagram of a data processing flow provided by an embodiment of the present disclosure;

[0042] FIG. 6 is an optional schematic diagram of data interleaving provided by an embodiment of the present disclosure;

[0043] FIG. 7 is a schematic diagram of a data structure of a burst length provided by an embodiment of the present disclosure;

[0044] FIG. 8 is an optional schematic diagram of a hardware module provided by an embodiment of the present disclosure;

[0045] FIG. 9 is an optional flow schematic diagram of another data processing method provided by an embodiment of the present disclosure;

[0046] FIG. 10 is an optional schematic diagram of another hardware module provided by an embodiment of the present disclosure;

[0047] FIG. 11 is a reference diagram of a data structure for transmitting a burst length to an X4 granular chip according to an embodiment of the present disclosure;

[0048] FIG. 12 is a reference diagram of a data structure for transmitting a next burst length according to a four-way RS8(20, 17) encoding interleaving of error correction data according to an embodiment of the present disclosure;

[0049] FIG. 13 is an optional block diagram of a data processing apparatus according to an embodiment of the present disclosure; and

[0050] FIG. 14 is an optional block diagram of another data processing apparatus according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the scope of protection of the present disclosure.

[0052] As described in the background, in a computer system, the ECC (Error Correction Code) technology is a commonly used error correction technology for detecting and correcting errors by adding redundant error correction data to data. However, the addition of redundancy inevitably increases the overall size of the data, thereby to a certain extent, resulting in a decrease in the amount of actual storable and transmittable data, and being unable to store and transmit more data.

[0053] Referring to a data structure diagram shown in FIG. 1, the structure corresponds to a data storage structure of an X4 granular chip (i.e., each storage granule corresponds to 4 transmission channels). The structure has a total of 10 storage granules, which are 8 data granules Data 0, Data 1, Data 2, Data 3, Data 4, Data 5, Data 6, and Data 7, and 2 ECC granules ECC 0 and ECC 1. Among them, the data granule is a memory granule for storing valid data, and the ECC granule is a memory granule for storing error correction data. The 10 storage granules correspond to a total of 40 transmission channels (i.e., 40-bit channel), supporting the transmission or reception of 512-bit valid data and 128-bit error correction data in a burst length 16 transmission.

[0054] Wherein, the Burst Length refers to the number of data units (also called "shots") continuously transmitted without changing the address. The Burst Length 16 is to continuously transmit 16 data units without changing the address. For example, the Burst 0, Burst 1...Burst 15 in FIG. 1, wherein the Burst 0 is the first data unit of burst transmission, the Burst 1 is the second data unit of burst transmission, and so on until the Burst 15, which is the last data unit of burst transmission.

[0055] In the transmission / storage process of data, the data is encoded and interleaved based on a symbol as the smallest transmission unit / storage unit of data. In the data storage process, one symbol data should be stored in one storage grain. FIG. 1 takes 8-bit symbol as an example, in the encoding and interleaving process, one symbol data is evenly divided into 2 rows, each row has 4 bits (in the figure, only the configuration mode of symbol 1 marked by the diagonal line in ECC 1 is illustrated as an example, in fact, each 2 rows of the corresponding area of each Data / ECC pair is configured with one symbol data), thereby forming a data structure as shown in FIG. 1, and the data in the data structure is transmitted / stored to the X4 grain chip based on the corresponding transmission channel.

[0056] From the storage and error correction capability, in the data structure shown in FIG. 1, taking RS (Reed-Solomon code) encoding as an example (a kind of encoding using 2t error correction symbols to correct t symbol errors, t is a positive integer).

[0057] In an alternative implementation, the corresponding data transmission channel can be regarded as 40-bit width, wherein 8-bit is ECC bit width, in the RS encoding of 8-bit as one symbol, RS8 (10, 8) or RS16 (10, 8) encoding is applicable.

[0058] Wherein, RS8 in RS8 (10, 8) represents that the RS encoding uses 8-bit symbol; the numbers in (10, 8) represent the number of symbols, wherein 10 represents the total number of symbols (effective data symbol+ECC symbol), and 8 represents the number of effective data symbols. Similarly, RS16 in RS16 (10, 8) represents that the RS encoding uses 16-bit symbol (not shown in the figure); the numbers in (10, 8) represent the number of symbols, wherein 10 represents the total number of symbols (effective data symbol+ECC symbol), and 8 represents the number of effective data symbols.

[0059] That is, 8-bit ECC per beat can correct 4-bit data. That is, even if one X4 storage grain in the structure shown in FIG. 1 fails completely, the data of the X4 storage grain can be calculated completely by relying on ECC only, and chipkill can be achieved.

[0060] However, in order to correct 4-bit errors per beat, 8-bit ECC is required, and there is no spare bit to store additional data. That is, if 8 bits of a 40-bit wide data transmission channel are used as ECC bit width, the error correction data will occupy the entire ECC space (i.e., ECC 0 + ECC 1), and there is no space to store additional information such as data attributes, tags, etc.

[0061] In another alternative implementation, referring to FIG. 2, 4 bits of the 8-bit ECC bit width can be used to store additional information (as shown by the diagonal shaded portion in FIG. 2), and only the remaining 4 bits can be used for error correction (as shown by the dotted shaded portion in FIG. 2). However, 4-bit ECC cannot correct 4-bit errors, and cannot achieve complete correction of a single X4 grain chip. Although this data structure can store additional information, its error correction capability is reduced, which will have a great impact on the stability of the system.

[0062] In RS encoding with 8 bits as a code element, RS8(20, 18) encoding is used. The specific meaning of RS8(20, 18) can be referred to the explanation of RS8(10, 8) or RS16(10, 8) in RS encoding above, which will not be repeated here.

[0063] As can be seen, using 4 bits of the 8-bit ECC bit width to store additional information and only using the remaining 4 bits for error correction can store 64-bit other information (e.g., encryption information, identification information, etc.), but this way is at the expense of error correction capability.

[0064] It can be understood that the above two ways either use data on two ECC grains to correct errors of one X4 storage grain and cannot store additional information, or use data on one ECC grain to correct errors of half an X4 storage grain and sacrifice error correction capability to store additional information. That is, in order to use ECC bits to achieve error correction and store additional information at the same time, a trade-off must be made between the two. If the ECC bits are all used for error correction, there is no space to store additional information. Conversely, if some ECC bits are left for storing additional information, its error correction capability will decrease accordingly.

[0065] In view of this, the data processing method, device and related equipment are provided, and the method comprises the following steps.

[0066] It can be seen that the data processing method provided by the embodiments of the present disclosure can realize the transmission of the second data and the error correction data on the data channel for transmitting the redundant data by making the sum of the symbol quantity of the second data block and the symbol quantity in the error correction data block adapt to the data transmission amount of the data channel for transmitting the redundant data and making the error correction data and the second data interleave to obtain the redundant data area in the data interleaving step, and the redundant data area is transmitted based on the data channel for transmitting the redundant data. In addition, the data amount of the error correction data is ensured by making the symbol quantity ratio of the second data block and the error correction data block less than or equal to 1:3 and making the second data and the error correction data included in at least one row of data in the redundant data area of the target data block obtained by interleaving in the data interleaving step, and only the error correction data is included in at least one row of data. Therefore, more data can be transmitted under the premise of ensuring the error correction capability.

[0067] In order to better understand the scheme provided by the embodiments of the present disclosure, the specific content of the data processing scheme will be further explained and described below.

[0068] In the embodiments of the present disclosure, a data processing method is provided, and an optional flowchart of a data processing method is shown in FIG. 3. The method comprises the following steps.

[0069] Step S100: acquiring to-be-transmitted data.

[0070] The to-be-transmitted data can refer to data ready to be transmitted or data ready to be stored. The to-be-transmitted data includes first data and second data. The first data can be binary data, and the corresponding data amount can be determined based on a data transmission mechanism or a data storage mechanism of the hardware device. In an optional example, the data amount of the first data corresponds to the data amount of data that can be transmitted by a hardware burst length, such as 128 bits, 256 bits, 512 bits, or the like. The second data can be binary data, and the corresponding data amount can be determined based on a preset encoding method, the data amount of the first data, and a ratio of the number of symbols of the second data block to the number of symbols of the error correction data block. For example, in the case of an encoding method of RS8(20, 17), the data amount of the first data is 256 bits, and the ratio of the number of symbols of the second data block to the number of symbols of the error correction data block is equal to 1:3. In the case of the encoding method of RS8(20, 17), the number of symbols of the error correction data block is 3, and the number of symbols of the corresponding second data block is 1 (the data amount of the second data block is 8 bits). The number of symbols of the first data block is 16 (the data amount of the first data block is 128 bits).

[0071] The data amount of the second data needs to satisfy that the number of second data blocks after subsequent segmentation is the same as the number of first data blocks after segmentation of the data amount of the first data. In the above example, the first data of 256 bits can be segmented into four first data blocks of 128 bits, and the number of corresponding second data blocks is also four. At this time, the data amount of the second data is 32 bits (i.e., four second data blocks of 8 bits).

[0072] The first data is valid data, and the second data is valid data, or one or more of identification data, attribute data, check data, and encryption information corresponding to the valid data. The second data can be understood as additional data that can be transmitted or stored.

[0073] Step S110: generating a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data.

[0074] The to-be-transmitted data block includes a first data block generated by the first data and a second data block generated by the second data. A to-be-transmitted data block and an error correction data block corresponding thereto form an error correction data group. The first data block and the second data block are data blocks that meet the required number of data bits of a preset encoding method, and are used as a to-be-transmitted data part in the error correction data group, so that the to-be-transmitted data is corrected based on the error correction data in the error correction data group in a subsequent process.

[0075] In an optional implementation, referring to FIG. 4, the step of generating the to-be-transmitted data block and the error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data can include:

[0076] Step S111: dividing the first data into a plurality of first data blocks and dividing the second data into a plurality of second data blocks.

[0077] A first data block and a second data block are a to-be-transmitted data block.

[0078] The step of dividing the first data into a plurality of first data blocks and dividing the second data into a plurality of second data blocks specifically includes: dividing the first data into a plurality of first data blocks with a first preset bit number and dividing the second data into a plurality of second data blocks with a second preset bit number. In this step, the number of the first data blocks and the number of the second data blocks can be determined based on the data amount of the first data and the second data and a preset encoding mode. It should be noted that the number of the first data blocks and the number of the second data blocks are the same.

[0079] The error correction data block is a redundant data block obtained based on a specific encoding algorithm and based on the to-be-transmitted data block, and is an error correction data set for correcting error data in the to-be-transmitted data.

[0080] In some optional examples, a specific encoding algorithm can be determined based on a hardware configuration and a system configuration, and the specific encoding algorithm can be fixedly configured in hardware, for example, a specific hardware can be configured as an encoding module to execute the specific encoding algorithm.

[0081] The error correction data block can be understood as an error correction data set corresponding to the to-be-transmitted data block. In this step, the sum of the number of symbols of the second data block and the number of symbols in the error correction data block is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols of the second data block to the number of symbols in the error correction data block is less than or equal to 1:3, for example, the ratio of the number of symbols of the second data block to the number of symbols in the error correction data block is 1:3.

[0082] It can be understood that based on the data amount of the first data and the second data and the preset encoding mode, the number of the first data blocks and the second data blocks can be determined. In the present example, referring to the optional schematic diagram of the data processing procedure shown in FIG. 5, the data to be transmitted includes 512-bit first data and 32-bit second data, the ratio of the number of symbols of the second data blocks and the error correction data blocks is 1:3, and the encoding mode is RS8 (20, 17) for example. The first data blocks and the second data blocks together have 17 symbols, of which the first data blocks have 16 symbols, i.e. 128 bits; the second data blocks have 1 symbol, i.e. 8 bits; and the error correction data blocks have 3 symbols, i.e. 24 bits. The first data is divided into a plurality of first data blocks, and the second data is divided into a plurality of second data blocks, wherein the number of the first data blocks is the same as the number of the second data blocks. That is, the 512-bit first data is divided into 4 first data blocks, and the 32-bit second data is divided into 4 second data blocks. One first data block and one second data block form one data block to be transmitted.

[0083] With continued reference to FIG. 4, step S112 is performed: encoding the data block to be transmitted to generate an error correction data block corresponding to the data block to be transmitted.

[0084] The error correction data block is redundant data obtained based on a specific algorithm on the basis of the data block to be transmitted. One data block to be transmitted and the error correction data block corresponding thereto form an error correction data group, so that the data to be transmitted can be corrected based on the error correction data in the error correction data group.

[0085] Specifically, the number of symbols of the error correction data block is n-k, and the data bits and the information bits together have (n-k)*m, which can correct m bit data of t symbols in the data to be transmitted. Wherein, ((n-k) is a multiple of 3).

[0086] It can be seen that the present embodiment breaks through the traditional RS encoding theory (i.e. using 2t error correction symbols to correct t symbol errors, t being a positive integer), and realizes 3t error correction symbols to correct 2t symbol errors.

[0087] The number of the error correction data blocks is the same as the number of the first data blocks or the second data blocks. In the present example, continuing to refer to FIG. 5, the data to be transmitted includes 512-bit first data and 32-bit second data, and the ratio of the number of symbols of the second data blocks and the error correction data blocks is 1:3, and the encoding mode is RS8 (20, 17), and the first data blocks and the second data blocks have a total of 17 symbols. Among them, the first data block is 16 symbols, a total of 128 bits, and the second data block is 1 symbol, a total of 8 bits. The corresponding error correction data block is 3 symbols, a total of 24 bits. The 512-bit first data and the 32-bit second data are divided into 4 first data blocks and 4 second data blocks, and 4 error correction data blocks are generated correspondingly.

[0088] In a specific example, the encoding module can be configured in hardware, so as to calculate the error correction data blocks corresponding to the first data blocks and the second data blocks by using the encoding module. Referring to the optional schematic diagram of a hardware module provided by the embodiment of the present disclosure shown in FIG. 8, the encoding module is set to generate error correction data (also referred to as error correction code) based on the data to be transmitted.

[0089] Continuing to refer to FIG. 3, step S120 is performed: interleaving the error correction data group to obtain a target data block.

[0090] In the target data block, the effective data area interleaved from the first data and the redundant data area interleaved from the error correction data and the second data are included; wherein the redundant data area is transmitted based on the data channel of the redundant data, the redundant data area includes multiple rows of data, the second data and the error correction data are included in at least one row of data at the same time, and in at least one row of data, only the error correction data is included. The redundant data area includes multiple columns of data, and in at least one column of data, only the error correction data is arranged, and in at least one column of data, the error correction data and the second data are alternately arranged.

[0091] In order to adapt to the hardware bit width, the error correction data group can be interleaved and processed into a target data block conforming to the hardware bit width. Among them, based on the embodiment of the present disclosure, one symbol is averagely configured as 2 rows of data. For example, the data of one symbol in the first data is 01001010 (the symbol data is the first bit, the second bit... the eighth bit from left to right), and the data is expressed as 2 rows of data in the data block (for example, the odd bits of data are arranged in the first row in turn, and the even bits of data are arranged in the second row in turn; that is, the first row is 0011, and the second row is 1000).

[0092] The target data block can include one error correction data group or multiple error correction data groups, and the number of error correction data groups is determined based on the number of symbols in the error correction data group. For an error correction data group with an RS8 (20, 17) coding mode and 8-bit symbols, the target data block can be formed by interleaving 2 error correction data groups. For an error correction data group with an RS16 (20, 17) coding mode and 16-bit symbols, the target data block can be formed by interleaving 1 error correction data group.

[0093] It can be understood that in the hardware transmission channel, part of the transmission channels are used only for transmitting the first data, part of the transmission channels are used for transmitting the second data and the error correction data (the error correction data and the second data are arranged alternately), and part of the transmission channels are used only for transmitting the error correction data. The transmission channels used only for transmitting the first data are concentrated on one side to form an effective data area, and the transmission channels used for transmitting the second data and the error correction data and the transmission channels used only for transmitting the error correction data are concentrated on the other side to form a redundant data area. Correspondingly, in the specific interleaving process, the first data block is sequentially arranged on one side of the target data block based on the symbols to form the effective data area, and the second data block and the error correction data block are sequentially arranged on the other side of the target data block based on the symbols to form the redundant data area.

[0094] In the specific interleaving process, the target data block includes at least one error correction data group, and the data of the error correction data group can be arranged in sequence based on the order of the error correction data group. It should be noted that the first data block in the error correction data group should be configured separately from the second data block and the error correction data block, that is, the data in the first data block is arranged on one side of the target data block used for configuring the effective data area, and the data of the second data block and the error correction data block is arranged on the other side of the target data block used for configuring the redundant data area.

[0095] Referring to an optional schematic diagram of data interleaving shown in FIG. 6, the target data block includes two error correction data groups, namely a first error correction data group and a second error correction data group, and each error correction data group includes n symbols (n=20 is taken as an example in the figure). The first k-1 symbols are the symbols in the first data block (k=17 is taken as an example in the figure), one of the kth symbol to the nth symbol is the symbol in the second data block (the kth symbol is taken as an example in the figure), and the symbols in the error correction data block are the symbols in the kth symbol to the nth symbol except for the symbols in the second data block. The first (1) symbol represents the first symbol in the first error correction data group, the first (2) symbol represents the second symbol in the first error correction data group, the first (n) symbol represents the nth symbol in the first error correction data group, and so on. The second (n) symbol represents the nth symbol in the second error correction data group. n and k-1 are even numbers greater than 0.

[0096] The sequentially arranging of the target data block based on the order of the error correction data groups means that the first data block of the error correction data groups is sequentially arranged on one side for configuring the valid data area, and the second data block and the error correction data block of the error correction data groups are sequentially arranged on one side for configuring the redundant data area. Specifically, with reference to the foregoing example that the target data block includes two error correction data groups, the target data block is shown as follows:

[0097] In the target data block, the sequentially arranging is based on the order of the error correction data groups from top to bottom, and the first data block is sequentially arranged on one side for configuring the valid data area, and the second data block and the error correction data block are sequentially arranged on one side for configuring the redundant data area.

[0098] As shown in FIG. 6, the second data and the error correction data are included in at least one row of data on one side of the redundant data area (such as the data of the first row, the second row, the fifth row and the sixth row arranged from top to bottom in FIG. 6), and the error correction data is included in at least one row of data (such as the data of the third row, the fourth row, the seventh row and the eighth row arranged from top to bottom in FIG. 6); the error correction data is arranged in at least one column of data (such as the data of the first to fourth columns arranged from right to left in FIG. 6), and the error correction data and the second data are alternately arranged in at least one column of data (such as the data of the fifth to eighth columns arranged from right to left in FIG. 6).

[0099] With reference to the optional schematic diagram of a hardware module provided by the embodiment of the disclosure shown in FIG. 8, the encoding module is arranged to generate error correction data based on the to-be-transmitted data. The interleaving module is connected to the encoding module, so that after the encoding module generates the error correction data block, the interleaving of the to-be-transmitted data (the first data and the second data) and the error correction data can be further performed, thereby generating the target data block for transmission and saving to the memory.

[0100] In the target data block, the column data is aligned based on the hardware transmission channel, and when there are multiple target data blocks, the multiple target data blocks are aligned based on the column direction, so that the target data blocks are sequentially transmitted based on the hardware transmission channel.

[0101] With reference to FIG. 3, step S130 is performed: transmitting the target data block to a preset device based on a transmission rule of the target data block.

[0102] The to-be-transmitted data can refer to data ready for transmission, or data ready for saving. Correspondingly, the target data block obtained by processing the to-be-transmitted data can be used for transmission to a preset position (such as a data receiving end) or saving to the memory.

[0103] The transmission rule of the target data block can comprise a correspondence between each column of data and a hardware port, so that each column of data is transmitted based on different hardware ports. Further, the transmission rule can further comprise a number of target data blocks transmitted in a burst length, for example, when a burst length corresponds to a data amount of a plurality of target data blocks, data of the plurality of target data blocks is sequentially transmitted corresponding to the burst length. Referring to FIG. 7, the number of target data blocks transmitted in a burst length can be 2, and when a burst length corresponds to a data amount of 2 target data blocks, data of the 2 target data blocks is sequentially transmitted corresponding to the burst length.

[0104] It should be noted that the target data block obtained after processing of the data to be transmitted needs to be decoded and corrected after being transmitted to the data receiving end, so as to determine whether the data transmission process is incorrect and correct the incorrect data. The target data block obtained after processing of the data to be saved needs to be saved after being transmitted to the memory, and needs to be decoded and corrected when read, so as to determine whether the saved data is incorrect and correct the incorrect data.

[0105] It can be seen that the data processing method provided by the embodiment of the present disclosure adapts the sum of the number of symbols of the second data block and the number of symbols in the error correction data block to the data transmission amount of the data channel for transmitting redundant data, and in the data interleaving step, the error correction data and the second data are interleaved to obtain a redundant data area, and the redundant data area is transmitted based on the data channel for transmitting redundant data, so that the error correction data and the second data are simultaneously transmitted in the data channel for transmitting redundant data. Further, by making the ratio of the number of symbols of the second data block and the number of symbols of the error correction data block less than or equal to 1:3, and in the data interleaving step, the redundant data area of the target data block obtained by interleaving comprises second data and error correction data in at least one row of data, and only error correction data in at least one row of data, so as to ensure the data amount of the error correction data, thereby transmitting more data under the premise of ensuring the error correction capability.

[0106] In a further example, the embodiment of the present disclosure also provides a data processing method for correcting the data to be transmitted based on the error correction data in the target data block. Specifically, referring to another optional flowchart of the data processing method shown in FIG. 9, the data processing method comprises:

[0107] Step S200: obtaining a target data block.

[0108] The target data block is data received by a preset device or obtained from the preset device after being encoded and interleaved and transmitted to the preset device, for example, the target data block can be data received by a receiving end, or data saved in a memory and read from the memory.

[0109] The target data block is obtained based on error correction data group interleaving, for example, the target data block obtained by interleaving according to the method described in the foregoing embodiment; the error correction data group comprises a data block to be transmitted and a corresponding error correction data block, the data block to be transmitted comprises a first data block generated by first data and a second data block generated by second data; in the target data block, an effective data area interleaved by the first data and a redundant data area interleaved by the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel of the redundant data, the redundant data area comprises multiple rows of data, the second data and the error correction data are included in at least one row of data, and the error correction data is included in at least one row of data; the redundant data area comprises multiple columns of data, the error correction data is arranged in at least one column of data, and the error correction data and the second data are alternately arranged in at least one column of data.

[0110] In the process of obtaining the target data block, the transmission rule based on hardware can be used for obtaining. The transmission rule can comprise obtaining each column of data of the data block to be processed from different hardware ports based on the correspondence between each column of data and the hardware port. Specifically, different data in the target data block is transmitted based on different transmission channels, that is, in the hardware transmission channel, a part of the transmission channel is used for transmitting only the first data, a part of the transmission channel is used for transmitting the error correction data and the second data (the error correction data and the second data are alternately arranged), and a part of the transmission channel is used for transmitting only the error correction data. Correspondingly, in the specific obtaining process, the data in the first data block is obtained from the transmission channel for transmitting only the first data, the data in the error correction data block and the data in the second data block are obtained from the transmission channel for transmitting the error correction data and the second data, and the data in the error correction data block is obtained from the transmission channel for transmitting only the error correction data. Referring to another optional structure diagram of a hardware module shown in FIG. 10, taking reading data from the memory as an example, the first data, the second data, and the error correction data can be distinguished based on the transmission channel of the data when reading.

[0111] Further, the transmission rule can further comprise obtaining a corresponding number of target data blocks based on the number of target data blocks transmitted based on a burst length, for example, when a burst length corresponds to multiple (for example, 2) target data blocks, a plurality of (for example, 2) target data blocks are transmitted in sequence corresponding to a burst length.

[0112] In the column data in the target data block is aligned based on the hardware transmission channel, when there are multiple target data blocks, the multiple target data blocks are aligned based on the column direction, so that the target data blocks can be obtained in sequence based on the data transmission sequence in the hardware transmission channel.

[0113] It should be noted that when the target data block corresponding to the data of a burst length is multiple, that is, the number of target data blocks transmitted in a burst length is multiple, the storage grain data transmitted in a burst length corresponds to multiple target data block symbols, and the processing procedure corresponding to the present step can include: obtaining data of a burst length; based on the symbol length in the target data block, the data of the burst length is segmented into multiple target data blocks, and then the multiple target data blocks are obtained.

[0114] With continuous reference to FIG. 9, step S210 is performed: the target data block is deinterleaved to obtain an error correction data group.

[0115] The error correction data group includes a to-be-transmitted data block and a corresponding error correction data block, the to-be-transmitted data block includes a first data block generated by first data and a second data block generated by second data. Wherein, the first data block and the second data block are data blocks obtained by segmenting the to-be-transmitted data and conforming to the required data bit number of the preset encoding mode, and the error correction data block is a redundant data block obtained based on the data in the to-be-transmitted data block and based on a specific encoding algorithm.

[0116] In a specific deinterleaving process, the target data block includes at least one error correction data group, and the present step can determine the symbol data belonging to the same error correction data group and the corresponding arrangement order based on a preset data arrangement order (for example, the reverse order of the data arrangement order in the interleaving process).

[0117] Specifically, when the data of the error correction data group in the target data block is sequentially arranged based on the order of the error correction data group, the first data block and / or the second data block and / or the error correction data block in the error correction data group can be sequentially extracted.

[0118] Wherein, the arrangement mode of the first data block, the second data block and the error correction data block in the target data block is described in the foregoing description, based on the arrangement mode, the symbol arrangement mode of the target data block belonging to the same error correction data group can be determined, and thus the deinterleaving of the target data block can be performed based on the symbol arrangement mode.

[0119] With continuous reference to FIG. 9, step S220 is performed: based on the error correction data block in the error correction data group, the data error of the to-be-transmitted data block in the error correction data group is corrected.

[0120] The error correction data block is a redundant data block obtained based on the data in the to-be-transmitted data block and based on a specific encoding algorithm. Correspondingly, the to-be-transmitted data block can be corrected based on a specific decoding algorithm.

[0121] It can be understood that the specific encoding algorithm can correct the error of the data block to be transmitted based on the specific decoding algorithm corresponding thereto. In hardware, the specific decoding algorithm corresponding to the specific encoding algorithm is also determined. Accordingly, the specific decoding algorithm can be fixedly configured in hardware, for example, specific hardware can be configured to execute the specific decoding algorithm as a decoding module. Referring to FIG. 10, a decoding module is configured to decode data, and the decoding module can be connected to the deinterleaving module to decode the deinterleaved data.

[0122] Specifically, the data error of the data block to be transmitted in the error correction data group can be corrected in the step, which can include the following processes: based on the error correction data block in the error correction data group, the position of the error data in the data block to be transmitted is calculated; and the data error at the position of the error data in the data block to be transmitted is corrected.

[0123] It can be understood that based on the specific decoding algorithm, the first data in the first data block, the second data in the second data block and the error correction data in the error correction data block can be calculated to determine the position of the error data in the data block to be transmitted; and in binary data, the data is either "0" or "1", and therefore, after the position of the error data in the data block to be transmitted is determined, the data at the position can be corrected by converting the error data, for example, when the error data is "0", the data is converted to "1", or when the error data is "1", the data is converted to "0".

[0124] In an optional implementation, the method for calculating the position of the error data in the data block to be transmitted can be, for example, to determine the error position and error value of the error by using the syndrome data.

[0125] Taking the encoding RS8 (20, 17) as an example, the corresponding data block to be transmitted has a total of 17 symbols. Among them, the first data block is 16 symbols, a total of 128 bits; the second data block is 1 symbol, a total of 8 bits. The corresponding error correction data block is 3 symbols, a total of 24 bits. The specific implementation of determining the error position and error value of the error by using the syndrome data can be as follows:

[0126] (1) Calculate the syndrome; the syndrome data is (s0, s1, s2), wherein s0=2 0 e i +2 0 e j , s1=2 i e i +2 i+1 e j , s2=2 2i e i +2 2(i+1) e j,

[0127] where e i is the error value at error position i, e j is the error value at error position i+1.

[0128] (2) Constructing a polynomial equation, for example, a quadratic equation, ax 2 +bx+c=0, using the adjoint data, where a=2s0, b=3s1, c=s2. Thus, the error position and the error value can be solved based on the polynomial equation.

[0129] In some embodiments, the polynomial equation can be a quadratic equation. In other embodiments, other equations (e.g., a cubic equation, etc.) or a combination of different types of equations (e.g., a combination of a quadratic equation and a cubic equation, etc.) can be constructed using the adjoint data. In addition, the error position and the error value can be solved using methods other than equations (e.g., a look-up table, etc.) using the adjoint data.

[0130] According to the quadratic equation constructed above, ax 2 +bx+c=0, where a=2s0, b=3s1, c=s2. By the finite field quadratic equation solution, two solutions x0and x1of x can be solved, where the finite field, also called a galois field, is a field containing only a finite number of elements, for example, can be written as GF(2 n ), where n represents the number of bits of the elements in the field.

[0131] (3) Obtaining the two solutions x0and x1of the quadratic equation and determining the valid solution and the error position. Wherein, according to x=2 i , the value of i is obtained, and if i is even and i<20, the valid solution is x, and the error position is i and i+1. Wherein, when x0is the valid solution, the error position is i0and i0+1, and when x1is the valid solution, the error position is i1and i1+1.

[0132] It can be understood that when determining whether the two solutions x0and x1of the quadratic equation are valid solutions, the two solutions x0and x1of the quadratic equation need to be brought into x=2 i to solve the corresponding value of i, and only when i is even and i<20, the corresponding x is a valid solution, and thus the error position can be determined as i and i+1. For example, when determining whether x0is a valid solution, x0needs to be brought into x=2 i to obtain i0, and only when i0is even and i0<20, x0is a valid solution, and thus the error position can be determined as i0and i0+1. Similarly, when determining whether x1is a valid solution, x1needs to be brought into x=2 iOnly when i1 is even and i1<20, x1 is a valid solution, and then it can be determined that the error position is i1 and i1+1.

[0133] (4) Solving the error value according to the number of valid solutions, the number of valid solutions is different, and the process of solving the error value is also different. Therefore, the valid solutions are divided according to the number, which can be divided into the following three cases:

[0134] Case 1: The number of valid solutions is 0;

[0135] Case 2: The number of valid solutions is 1;

[0136] Case 3: The number of valid solutions is 2.

[0137] The following is a detailed description of solving the error value in the three cases of case 1, case 2 and case 3.

[0138] For case 1, if the number of valid solutions is 0 (x0 and x1 are not valid solutions), it indicates that the error occurred is an uncorrectable error, and the error correction process is ended.

[0139] For case 2, if the number of valid solutions is 1 (x0 is a valid solution, or x1 is a valid solution), the error value e i and the accompanying formula data are calculated according to the valid solution and the accompanying formula data. j Wherein:

[0140] e j = e i +s0; wherein, when x0 is a valid solution, x in is x0, when x1 is a valid solution, x in is x1.

[0141] In an optional implementation, the way to correct the data error of the error data position of the to-be-transmitted data block can be: XORing the data at position i with e i , and XORing the data at position i+1 with e j , to obtain the error-corrected data, wherein i and i+1 are error positions.

[0142] Wherein, when x0 is a valid solution, the error position is i0 and i0+1, and when x1 is a valid solution, the error position is i1 and i1+1.

[0143] For case 3, if the number of valid solutions is 2 (x0 and x1 are valid solutions), it is further determined whether the second data contains a check bit, according to whether the second data contains a check bit, it is divided into the following two cases:

[0144] Case 3.1, the number of valid solutions is 2 (x0 and x1 are valid solutions), and the second data contains check bits, then the error value is calculated according to the valid solution and the accompanying data and Wherein:

[0145] In an optional implementation, the way to correct the data error of the error data position in the to-be-transmitted data block can be: performing XOR operation between the data at i0 position and , performing XOR operation between the data at i0+1 position and , obtaining a first data group; performing XOR operation between the data at i1 position and , performing XOR operation between the data at i1+1 position and , obtaining a second data group; bringing the first data group and the second data group into check bit operation; if only one of the first data group and the second data group after operation is equal to the check bit, the data group is taken as the corrected data; if neither of the first data group and the second data group after operation is equal to the check bit, or both of the first data group and the second data group after operation are equal to the check bit, it indicates that the error is an uncorrectable error, and the error correction process is ended. Wherein, when x0 is a valid solution, the error positions are i0 and i0+1, and when x1 is a valid solution, the error positions are i1 and i1+1.

[0146] It should be noted that bringing the first data group and the second data group into check bit operation can be understood as that the check bits in the second data are obtained through a certain calculation method (for example, parity check), and the calculation method is performed on the first data group and the second data group.

[0147] Case 3.2, if the number of valid solutions is 2 (x0 and x1 are valid solutions), and the second data contains no check bits, it indicates that the error is an uncorrectable error, and the error correction process is ended.

[0148] The above method of calculating the position of the error data in the to-be-transmitted data block is only an optional example, and other ways can also be used for solving, and the present disclosure does not limit this.

[0149] In hardware, the error correction module can be fixedly configured in hardware to correct the errors in the to-be-transmitted data. Referring to FIG. 10, the error correction module connected to the decoding module is configured, so that the errors in the data can be corrected by the error correction module.

[0150] Continuing to refer to FIG. 9, step S230 is performed: generating to-be-transmitted data based on the to-be-transmitted data block after error correction.

[0151] The to-be-transmitted data can be understood as data waiting to be transmitted in a data transmission process, or data to be saved before being stored in the memory in a data storage process to the memory. In a specific example, when the to-be-transmitted data includes a plurality of first data blocks and second data blocks, the first data blocks and the second data blocks can be combined based on a preset rule to generate the to-be-transmitted data, so that the to-be-transmitted data can be transmitted to a target device, such as a CPU (Central Processing Unit) or the like.

[0152] Next, based on a specific example, the data processing method and its corresponding effects in the scenario of storing data into the memory are further described.

[0153] The error correction data group interleaving in this example can be two-way RS8 (20, 17) encoded error correction data group interleaving, or one-way RS16 (20, 17) encoded error correction data group interleaving; regardless of the interleaving method, the error of the entire storage grain can be corrected to achieve chipkill. The erroneous symbol data can be located in the same storage grain or in different storage grains.

[0154] The symbol bit number corresponding to the interleaving method in this example can be 8 bits, 16 bits, etc. Referring to the data structure reference diagram shown in FIG. 11 for transmitting a burst length to an X4 grain chip, the symbol data from left to right is 8 bits and 16 bits, respectively. The burst length can be 8 bits, 16 bits, etc. The diagram takes 16 bits as an example. When the symbol data is 8 bits, referring to the shaded area shown in symbol 3 in FIG. 11, a symbol is configured with an average of 2 rows of data (i.e., arranged in the row direction); when the symbol data is 16 bits, referring to the shaded area shown in symbol 4 in FIG. 11, a symbol is configured with an average of 4 rows of data (i.e., arranged in the row direction).

[0155] Taking the first data in the to-be-transmitted data as an example, the symbol bit number is 8 bits and 512 bits, FIG. 12 shows a data structure reference diagram for transmitting a burst length under four-way RS8 (20, 17) encoded error correction data group interleaving, wherein the first eight beats of Burst 0-7 correspond to the transmission of a target data block, and the last eight beats of Burst 8-15 correspond to the transmission of another target data block.

[0156] It can be seen that the 8-bit data corresponding to two adjacent shots of a storage grain is one 8-bit symbol, and there are two error correction data groups interleaved in the first eight shots. In the target data block, the left 32 columns are used to configure the first data, the right 8 columns are used to configure the second data and the error correction data, and in the specific storage chip, 0-7 (such as Data 0, Data 1, Data 2, Data 3, Data 4, Data 5, Data 6 and Data 7 in the figure) of the X4 grain chip can be used as the storage position corresponding to the first data of the target data block, and 8-9 (such as ECC 0 and ECC 1 in the figure) of the X4 grain chip can be used as the storage position corresponding to the second data and the error correction data of the target data block.

[0157] With reference to FIG. 12, 0-127 in the first data in the target data block is a first data block, 0-7 in the error correction data is a second data block, 8-31 in the error correction data is an error correction data block corresponding to the first data block and the second data block, the first data block, the second data block and the error correction data block can be error correction data group 0; 128-255 in the first data is a first data block, 32-39 in the error correction data is a second data block, 40-63 in the error correction data is an error correction data block corresponding to the first data block and the second data block, the first data block, the second data block and the error correction data block can be error correction data group 1.

[0158] In the target data block, each error correction data group uses RS8(20, 17) error correction code, which can correct any two adjacent 8-bit symbols, that is, any error of a storage grain can be corrected by using RS8(20, 17) error correction code.

[0159] Specifically, taking 0-7 and 64-71 in the first data as an example, which are in error (that is, a total of 2 8-bit symbols are in error, the grid shaded part in the figure), 0-7 and 64-71 in the original data belong to error correction data group 0, and based on one error correction data group, any two adjacent 8-bit symbols can be corrected, and the above error data can be corrected.

[0160] It can be understood that the data mapping and error correction capability of the target data block corresponding to the first eight shots and the last eight shots are completely consistent, and therefore, the scheme provided by the embodiments of the present disclosure can correct all errors of any storage grain and realize chipkill.

[0161] It can be seen that the data processing method provided by the embodiment of the present disclosure, by making the sum of the number of symbols of the second data block and the number of symbols in the error correction data block adapt to the data transmission amount of the data channel for transmitting redundant data, and in the data interleaving step, interleaving the error correction data and the second data to obtain a redundant data area, the redundant data area is transmitted based on the data channel for transmitting redundant data, so that the error correction data and the second data are transmitted simultaneously in the data channel for transmitting redundant data; and by making the ratio of the number of symbols of the second data block and the number of symbols of the error correction data block less than or equal to 1:3, and in the data interleaving step, the redundant data area of the target data block obtained by interleaving includes the second data and the error correction data in at least one row of data, and only includes the error correction data in at least one row of data, so as to ensure the data amount of the error correction data, thereby transmitting more second data under the premise of ensuring the error correction capability.

[0162] In the following, the data processing apparatus provided by the embodiment of the present disclosure is introduced, and the data processing apparatus described in the following can be considered as a software functional module or a hardware functional module required to be set to realize the data processing method provided by the embodiment of the present disclosure; the content of the data processing apparatus described in the following can be mutually corresponding and referred to the method content and the hardware module content described in the above.

[0163] In an optional implementation, FIG. 13 shows an optional block diagram of the data processing apparatus provided by the embodiment of the present disclosure, which is used to realize the data processing method with data interleaving, as shown in FIG. 13, the data processing apparatus can include:

[0164] The first data acquisition module 300 is configured to acquire to-be-transmitted data; wherein the to-be-transmitted data includes first data and second data.

[0165] The processing module 310 is configured to generate a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data, the to-be-transmitted data block includes a first data block generated by the first data and a second data block generated by the second data, and a to-be-transmitted data block and an error correction data block corresponding thereto form an error correction data group; wherein the sum of the number of symbols of the second data block and the number of symbols in the error correction data block adapts to the data transmission amount of the data channel for transmitting redundant data, and the ratio of the number of symbols of the second data block and the number of symbols of the error correction data block is less than or equal to 1:3.

[0166] The interleaving module 320 is configured to interleave the error correction data group to obtain a target data block, the target data block comprising an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is based on data channel transmission of the redundant data, and the redundant data area comprises multiple rows of data, at least one row of data comprising the second data and the error correction data, and at least one row of data comprising only the error correction data.

[0167] The data transmission module 330 is configured to transmit the target data block to a preset device based on a transmission rule of the target data block.

[0168] Optionally, the redundant data area comprises multiple columns of data, at least one column of data comprising only the error correction data, and at least one column of data comprising the error correction data and the second data alternately arranged.

[0169] Optionally, the processing module 310 is configured to generate a to-be-transmitted data block and an error correction data block corresponding to the to-be-transmitted data block based on the to-be-transmitted data, and can comprise:

[0170] The first data is divided into multiple first data blocks, and the second data is divided into multiple second data blocks, and a first data block and a second data block are a to-be-transmitted data block; wherein the number of the first data blocks is the same as the number of the second data blocks.

[0171] The to-be-transmitted data block is encoded to generate an error correction data block corresponding to the to-be-transmitted data block.

[0172] Optionally, the first data is divided into multiple first data blocks with a first preset number of bits, and the second data is divided into multiple second data blocks with a second preset number of bits.

[0173] Optionally, the target data block comprises at least one error correction data group, and the interleaving module 320 is configured to sequentially arrange the data of the error correction data group based on the order of the error correction data group to obtain the target data block.

[0174] Optionally, the target data block comprises two error correction data groups, namely a first error correction data group and a second error correction data group, each error correction data group comprising n symbols, the first k-1 symbols being symbols in the first data block, one of the kth symbol to the nth symbol being a symbol in the second data block, and the symbols in the error correction data block being symbols in the kth symbol to the nth symbol except for the symbols in the second data block.

[0175] wherein the first n symbol represents an n th symbol in the first error correction data group, the second n symbol represents an n th symbol in the second error correction data group, and n and k-1 are even numbers greater than 0.

[0176] Optionally, the first data is valid data, the second data is valid data, or one or more of identification data, attribute data, check data, and encryption information corresponding to the valid data.

[0177] Optionally, a burst length corresponds to data amounts of a plurality of target data blocks, and the data transmission module 330 is configured to transmit the target data blocks to a preset device based on a transmission rule of the target data blocks, specifically, sequentially transmitting a plurality of target data blocks in a burst length.

[0178] In an optional implementation, FIG. 14 shows an optional block diagram of another data processing apparatus provided by the embodiments of the present disclosure, which is used to implement a data processing method with data deinterleaving. As shown in FIG. 14, the data processing apparatus can include:

[0179] The second data acquisition module 400 is configured to acquire a target data block, the target data block being obtained based on error correction data group interleaving, the error correction data group including a to-be-transmitted data block and a corresponding error correction data block, the to-be-transmitted data block including a first data block generated by first data and a second data block generated by second data; the target data block including a valid data area obtained by first data interleaving and a redundant data area obtained by error correction data and second data interleaving; wherein the redundant data area is transmitted based on a data channel of redundant data, the redundant data area including a plurality of rows of data, the second data and the error correction data being included in at least one row of data, and the error correction data being included in at least one row of data.

[0180] The deinterleaving module 410 is configured to deinterleave the target data block to obtain an error correction data group.

[0181] The error correction module 420 is configured to correct data errors of the to-be-transmitted data block in the error correction data group based on an error correction data block in the error correction data group.

[0182] The to-be-transmitted data generation module 430 is configured to generate to-be-transmitted data based on the error-corrected to-be-transmitted data block.

[0183] Optionally, the redundant data area includes a plurality of columns of data, error correction data being arranged in at least one column of data, and the error correction data and the second data being alternately arranged in at least one column of data.

[0184] Optionally, the second data acquisition module 400 is configured to acquire a target data block, specifically, acquiring the target data block based on a hardware transmission rule.

[0185] The transmission rule comprises:

[0186] Based on the correspondence between each column of data and the hardware port, each column of data of the target data block is obtained from different hardware ports.

[0187] Based on the number of target data blocks of a burst length transmission, a corresponding number of target data blocks are obtained.

[0188] Optionally, the second data obtaining module 400 is configured to obtain target data blocks, and comprises:

[0189] Obtain data of a burst length;

[0190] Based on the symbol length in the target data block, the data of the burst length is divided into a plurality of target data blocks.

[0191] Optionally, the target data block comprises at least one error correction data group, and the deinterleaving module 410 is configured to deinterleave the target data block to obtain an error correction data group, specifically, based on a preset data arrangement order to determine the symbol data belonging to the same error correction data group and the corresponding arrangement order.

[0192] Optionally, the determination of the symbol data belonging to the same error correction data group and the corresponding arrangement order based on the preset data arrangement order comprises:

[0193] When the data of the error correction data group in the target data block is sequentially arranged based on the order of the error correction data group, the first data block and / or the second data block and / or the error correction block in the error correction data group are sequentially extracted.

[0194] Optionally, the error correction module 420 is configured to correct the data error of the to-be-transmitted data block in the error correction data group based on the error correction data block in the error correction data group, and the error correction module 420 comprises:

[0195] Based on the error correction data block in the error correction data group, the position of the error data in the to-be-transmitted data block is calculated;

[0196] Correct the data error at the error data position of the to-be-transmitted data block.

[0197] Optionally, the to-be-transmitted data generation module 430 is configured to generate to-be-transmitted data based on the error-corrected to-be-transmitted data block, specifically, based on a preset rule to combine the first data block and the second data block to generate the to-be-transmitted data, wherein the number of the first data blocks is the same as the number of the second data blocks.

[0198] The first data is valid data, the second data is valid data, or one or more of identification data, attribute data, check data, and encryption information corresponding to the valid data.

[0199] The embodiments of the present disclosure further provide a memory controller, which can be configured with the data processing apparatus with the interleaving module provided in the above embodiments, and / or the memory controller can be configured with the data processing apparatus with the deinterleaving module provided in the above embodiments.

[0200] The embodiments of the present disclosure further provide an electronic device, which can include the memory controller described above.

[0201] The embodiments of the present disclosure further provide a storage medium, which stores one or more computer executable instructions, and the one or more computer executable instructions, when executed, implement the data processing method with interleaving processing and / or the data processing method with deinterleaving processing in the embodiments of the present disclosure.

[0202] The embodiments of the present disclosure further provide a computer program product, which can include one or more computer executable instructions, and the one or more computer executable instructions, when executed, implement the data processing method with interleaving processing and / or the data processing method with deinterleaving processing in the embodiments of the present disclosure.

[0203] The above describes a plurality of embodiment schemes provided by the embodiments of the present disclosure, and each optional mode introduced by each embodiment scheme can be combined, cross-referenced in the case of no conflict, thereby extending a plurality of possible embodiment schemes, which can be considered as the embodiments disclosed and disclosed by the embodiments of the present disclosure.

[0204] Although the embodiments of the present disclosure are disclosed as above, the present disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, and therefore the protection scope of the present disclosure should be subject to the scope defined by the claims.

Claims

1. A data processing method, comprising: obtaining to-be-transmitted data; wherein the to-be-transmitted data comprises first data and second data; generating, based on the to-be-transmitted data, to-be-transmitted data blocks and error correction data blocks corresponding to the to-be-transmitted data blocks, the to-be-transmitted data blocks comprising first data blocks generated from the first data and second data blocks generated from the second data, a to-be-transmitted data block and an error correction data block corresponding thereto forming an error correction data group; wherein the sum of the number of symbols of the second data blocks and the number of symbols in the error correction data blocks is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols of the second data blocks to the number of symbols of the error correction data blocks is less than or equal to 1:3; interleaving the error correction data group to obtain a target data block, the target data block comprising an effective data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel for redundant data, the redundant data area comprises multiple rows of data, the second data and the error correction data are included in at least one row of data, and the error correction data is included in at least one row of data; and transmitting the target data block to a preset device based on a transmission rule of the target data block. The redundant data area comprises multiple columns of data, the error correction data is arranged in at least one column of data, and the error correction data and the second data are alternately arranged in at least one column of data. The step of generating, based on the to-be-transmitted data, to-be-transmitted data blocks and error correction data blocks corresponding to the to-be-transmitted data blocks comprises: dividing the first data into multiple first data blocks and the second data into multiple second data blocks, a first data block and a second data block forming a to-be-transmitted data block; wherein the number of the first data blocks is the same as the number of the second data blocks; and encoding the to-be-transmitted data blocks to generate error correction data blocks corresponding to the to-be-transmitted data blocks. The step of dividing the first data into multiple first data blocks and the second data into multiple second data blocks comprises: dividing the first data into multiple first data blocks having a first preset number of bits and dividing the second data into multiple second data blocks having a second preset number of bits. The target data block comprises at least one error correction data group, and the interleaving the error correction data group to obtain a target data block specifically comprises: sequentially arranging the data of the error correction data group based on the order of the error correction data group.

2. The data processing method of claim 1, wherein, The target data block comprises two error correction data groups, namely a first error correction data group and a second error correction data group, each of which comprises n symbols, the first k-1 symbols are symbols in the first data blocks, one of the kth symbol to the nth symbol is a symbol in the second data blocks, and the symbols in the kth symbol to the nth symbol except for the symbols in the second data blocks are symbols in the error correction data blocks.

3. The data processing method according to claim 1 or 2, wherein, wherein the first n symbol represents the nth symbol in the first error correction data group, the second n symbol represents the nth symbol in the second error correction data group, n and k-1 are even numbers greater than 0. ​ ​ 4. The data processing method of claim 3, wherein, ​ 5. The data processing method according to any one of claims 1 to 4, wherein, ​ 6. The data processing method of claim 5, wherein, ​ ​ 7. The data processing method according to any one of claims 1 to 6, wherein, The first data is valid data, the second data is valid data, or one or more of identification data, attribute data, check data, and encryption information corresponding to the valid data.

8. The data processing method according to any one of claims 1 to 7, wherein, A burst length corresponds to a data amount of a plurality of target data blocks, and the target data blocks are transmitted to a preset device based on a transmission rule of the target data blocks, including: sequentially transmitting a plurality of target data blocks in a burst length.

9. A data processing method, comprising: obtaining a target data block, the target data block being obtained based on error correction data group interleaving, the error correction data group comprising a to-be-transmitted data block and a corresponding error correction data block, the to-be-transmitted data block comprising a first data block generated by first data and a second data block generated by second data; in the target data block, a valid data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error correction data and the second data; wherein the redundant data area is transmitted based on a data channel of the redundant data, and the redundant data area comprises a plurality of rows of data, at least one row of data comprising both the second data and the error correction data, and at least one row of data comprising only the error correction data; de-interleaving the target data block to obtain an error correction data group; correcting data errors of the to-be-transmitted data block in the error correction data group based on the error correction data block in the error correction data group; generating to-be-transmitted data based on the to-be-transmitted data block after error correction.

10. The data processing method of claim 9, wherein, The redundant data area comprises a plurality of columns of data, at least one column of data comprising only error correction data, and at least one column of data comprising error correction data and second data alternately arranged.

11. The data processing method according to claim 9 or 10, wherein, The obtaining of the target data block comprises obtaining the target data block based on a hardware transmission rule; The transmission rule comprises: obtaining each column of data of the target data block from different hardware ports based on the correspondence between each column of data and the hardware ports; obtaining a corresponding number of target data blocks based on the number of target data blocks transmitted in a burst length.

12. The data processing method according to claim 9 or 10, wherein, The obtaining of the target data block comprises: obtaining data in a burst length; segmenting the data in the burst length into a plurality of target data blocks based on a symbol length in the target data block.

13. The data processing method according to any one of claims 9-12, wherein, The target data block comprises at least one error correction data group, and the de-interleaving of the target data block to obtain an error correction data group comprises determining symbol data belonging to the same error correction data group and the corresponding arrangement order based on a preset data arrangement order.

14. The data processing method of claim 13, wherein, The determination of symbol data belonging to the same error correction data group and the corresponding arrangement order based on a preset data arrangement order comprises: sequentially extracting a first data block and / or a second data block and / or an error correction data block in the error correction data group when the data of the error correction data group in the target data block is sequentially arranged based on the order of the error correction data group.

15. The data processing method according to any one of claims 9-14, wherein, The correction of data errors of the to-be-transmitted data block in the error correction data group based on the error correction data block in the error correction data group comprises: calculating the position of error data in the to-be-transmitted data block based on the error correction data block in the error correction data group; correcting the data error at the position of the error data in the to-be-transmitted data block.

16. The data processing method according to any one of claims 9-15, wherein, The generating of the to-be-transmitted data based on the error-corrected to-be-transmitted data block comprises: generating the to-be-transmitted data based on a preset rule of combining the first data block and the second data block, wherein the number of the first data blocks is the same as the number of the second data blocks.

17. The data processing method according to any one of claims 9-16, wherein, The first data is valid data, the second data is valid data, or one or more of identification data, attribute data, check data, and encryption information corresponding to the valid data. 18.A data processing apparatus, comprising: a first data acquisition module configured to acquire to-be-transmitted data; wherein the to-be-transmitted data comprises first data and second data; a processing module configured to generate, based on the to-be-transmitted data, to-be-transmitted data blocks and error-corrected data blocks corresponding to the to-be-transmitted data blocks, wherein the to-be-transmitted data blocks comprise first data blocks generated by the first data and second data blocks generated by the second data, a to-be-transmitted data block and an error-corrected data block corresponding thereto form an error-corrected data group, wherein the sum of the number of symbols of the second data blocks and the number of symbols in the error-corrected data blocks is adapted to the data transmission amount of a data channel for transmitting redundant data, and the ratio of the number of symbols of the second data blocks to the number of symbols of the error-corrected data blocks is less than or equal to 1:3; an interleaving module configured to interleave the error-corrected data group to obtain a target data block, wherein the target data block comprises a valid data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error-corrected data and the second data, and the redundant data area is transmitted based on a data channel for redundant data, and the redundant data area comprises multiple rows of data, at least one row of data comprises both the second data and the error-corrected data, and at least one row of data comprises only the error-corrected data; a data transmission module configured to transmit the target data block to a preset device based on a transmission rule of the target data block. 19.A data processing apparatus, comprising: a second data acquisition module configured to acquire a target data block, wherein the target data block is obtained by interleaving an error-corrected data group, the error-corrected data group comprises to-be-transmitted data blocks and error-corrected data blocks corresponding thereto, the to-be-transmitted data blocks comprise first data blocks generated by the first data and second data blocks generated by the second data, the target data block comprises a valid data area obtained by interleaving the first data and a redundant data area obtained by interleaving the error-corrected data and the second data, and the redundant data area is transmitted based on a data channel for redundant data, and the redundant data area comprises multiple rows of data, at least one row of data comprises both the second data and the error-corrected data, and at least one row of data comprises only the error-corrected data; a deinterleaving module configured to deinterleave the target data block to obtain the error-corrected data group; an error correction module configured to correct data errors of the to-be-transmitted data blocks in the error-corrected data group based on the error-corrected data blocks in the error-corrected data group; a to-be-transmitted data generation module configured to generate to-be-transmitted data based on the error-corrected to-be-transmitted data blocks. 20.A memory controller, wherein the memory controller is configured with the data processing apparatus of claim 18. and / or, The memory controller is configured with the data processing apparatus of claim 19.

21. An electronic device comprising the memory controller of claim 20.

22. A storage medium storing one or more computer-executable instructions, wherein, The one or more computer-executable instructions, when executed, implement the data processing method of any one of claims 1 to 8, and / or implement the data processing method of any one of claims 9 to 17.

23. A computer program product comprising one or more computer-executable instructions implementing the method of any one of claims 1 to 22. The one or more computer-executable instructions, when executed, implement the data processing method of any one of claims 1 to 8, and / or implement the data processing method of any one of claims 9 to 17.

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