Memory cell structure, manufacturing method therefor and ferroelectric memory

Abstract

Disclosed in the present disclosure are a memory cell structure, a manufacturing method therefor and a ferroelectric memory. The memory cell structure comprises: a switching transistor, which is located on a substrate; a forest structure, which comprises one or more columnar structures; a capacitor structure, the capacitor structure and the forest structure being located above the switching transistor, the capacitor structure covering the surface of the forest structure and comprising a first electrode and a second electrode, and the first electrode being electrically connected to a drain of the switching transistor; and a wiring layer, which is located above the capacitor structure and comprises a bit line and a board line, the board line being electrically connected to the second electrode of the capacitor structure, and the bit line being electrically connected to a source of the switching transistor.

Description

Memory cell structure and preparation method thereof, and ferroelectric memory TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of storage, in particular to a memory cell structure and preparation method thereof, and a ferroelectric memory. BACKGROUND

[0002] Ferroelectric memory (Ferroelectric Memory) is based on the spontaneous polarization and non-volatile characteristics of ferroelectric materials. After power failure, it can still maintain the stored data information for a long time, and the stored data information is not easy to lose. After power supply, information reading and writing operations can be performed. Ferroelectric memory has the advantages of high speed reading and writing, high durability, low power consumption, high uniformity, and radiation resistance, etc., and meets the development trend of non-volatile memory. It has been widely used in high-noise, high-temperature, and high-radiation working environments such as automotive electronics, industry, aerospace, etc.

[0003] After the ferroelectric material thin film reaches the saturated polarization under the condition of an applied electric field, it can still maintain a part of the polarization after the applied electric field is removed. The remaining polarization is called the residual polarization. The residual polarization is an important parameter reflecting the size of the storage window of the ferroelectric memory, and directly represents the ferroelectric performance of the ferroelectric memory. As ferroelectric memory gradually develops towards miniaturization, improving the residual polarization of ferroelectric materials per unit device area is an urgent problem to be solved in the development of ferroelectric memory. SUMMARY

[0004] A series of simplified concepts are introduced in the summary section. This will be further described in detail in the specific embodiments section. The summary section of the present disclosure does not mean to attempt to limit the key features and essential technical features of the claimed technical solutions, nor does it mean to attempt to determine the protection scope of the claimed technical solutions.

[0005] The present disclosure provides a memory cell structure, comprising: a switching transistor located on a substrate; a forest structure comprising one or more columnar structures; a capacitor structure located above the switching transistor and the forest structure, the capacitor structure covering the surface of the forest structure, the capacitor structure comprising a first electrode and a second electrode, wherein the first electrode is electrically connected to the drain of the switching transistor; a wiring layer located above the capacitor structure, the wiring layer comprising a bit line and a plate line, the plate line being electrically connected to the second electrode of the capacitor structure, and the bit line being electrically connected to the source of the switching transistor.

[0006] In some embodiments, the forest structure comprises a plurality of columnar structures arranged in a single row, a single column, or multiple rows and multiple columns.

[0007] In some embodiments, the capacitor structure further comprises a capacitor dielectric layer between the first electrode and the second electrode, the first electrode, the capacitor dielectric layer and the second electrode of the capacitor structure all cover the top surface of each of the one or more columnar structures, the sidewall of each of the columnar structures and the bottom of the gap between adjacent columnar structures.

[0008] In some embodiments, the second electrode is above the first electrode, or the second electrode is outside the first electrode.

[0009] In some embodiments, the memory cell structure further comprises: a first dielectric layer between the capacitor structure and the substrate, covering the switch transistor; a first conductive plug in the first dielectric layer, the top of the first conductive plug is electrically connected to the first electrode of the capacitor structure, and the bottom of the first conductive plug is electrically connected to the drain of the switch transistor; a second dielectric layer between the first dielectric layer and the wiring layer, covering the capacitor structure; a second conductive plug in the second dielectric layer, the bottom of the second conductive plug is electrically connected to the second electrode of the capacitor structure, and the top of the second conductive plug is electrically connected to the plate line.

[0010] In some embodiments, the forest structure comprises a plurality of columnar structures, the bottoms of the plurality of columnar structures in the forest structure are connected to each other.

[0011] In some embodiments, the forest structure comprises a plurality of columnar structures, the plurality of columnar structures in the forest structure are separated from each other.

[0012] In some embodiments, the capacitor structure is a planar capacitor, wherein the second electrode is above the first electrode; or the capacitor structure is a columnar capacitor, wherein the second electrode is outside the first electrode.

[0013] The present disclosure also provides a method for preparing a memory cell structure, comprising: providing a substrate, a switch transistor is formed on the substrate; forming a forest structure above the switch transistor, the forest structure comprises one or more columnar structures; forming a capacitor structure covering the forest structure, the capacitor structure comprises a first electrode and a second electrode, wherein the first electrode is electrically connected to the drain of the switch transistor; forming a wiring layer above the capacitor structure; etching the wiring layer to form a bit line and a plate line, the plate line is electrically connected to the second electrode of the capacitor structure, and the bit line is electrically connected to the source of the switch transistor.

[0014] In some embodiments, forming the forest structure above the switching transistor comprises: forming a first dielectric layer above the switching transistor, the first dielectric layer covering the switching transistor, the first dielectric layer isolating the switching transistor from the capacitor structure; forming a first conductive plug in the first dielectric layer, a bottom of the first conductive plug being electrically connected to the drain of the switching transistor; forming a forest structure material layer above the first dielectric layer; etching the forest structure material layer to form the forest structure, the forest structure not covering the first conductive plug.

[0015] In some embodiments, etching the forest structure material layer to form the forest structure comprises: performing plasma bombardment on the forest structure material layer to form a forest structure having multiple rows and multiple columns of columnar structures.

[0016] In some embodiments, forming the capacitor structure covering the forest structure comprises: sequentially forming a first electrode, a capacitor dielectric layer, and a second electrode, each of the first electrode, the capacitor dielectric layer, and the second electrode covering an upper surface of each of the one or more columnar structures, a sidewall of each of the columnar structures, and a bottom of a gap between adjacent columnar structures, the first electrode being in contact with the first conductive plug.

[0017] In some embodiments, the forest structure comprises a plurality of columnar structures, bottoms of the plurality of columnar structures in the forest structure being connected to each other.

[0018] In some embodiments, the forest structure comprises a plurality of columnar structures, the plurality of columnar structures in the forest structure being separated from each other.

[0019] The present disclosure also provides a ferroelectric memory comprising the memory cell structure of any of the above embodiments.

[0020] The memory cell structure and the method for preparing the same, and the ferroelectric memory provided by the present disclosure increase the surface area of the ferroelectric material per unit device area by forming a forest structure and covering the surface of the forest structure with a capacitor structure, thereby increasing the remanent polarization, increasing the storage window of the ferroelectric memory, and improving the performance of the ferroelectric memory. BRIEF DESCRIPTION OF DRAWINGS

[0021] The following drawings for the present disclosure are hereby incorporated as part of the present disclosure for the purpose of understanding the present disclosure. The embodiments of the present disclosure and the description thereof shown in the drawings are used to explain the principles of the present disclosure.

[0022] FIG. 1 is a flowchart of a method for preparing a memory cell structure according to an embodiment of the present disclosure.

[0023] FIGS. 2A-2D are cross-sectional schematic views of a structure obtained by sequentially performing steps of a method of fabricating a memory cell structure according to embodiments of the present disclosure.

[0024] FIG. 3 is a zoomed-in schematic view of a portion of FIG. 2D.

[0025] FIG. 4 is a schematic view of a forest structure according to embodiments of the present disclosure.

[0026] FIG. 5 is a cross-sectional schematic view of a memory cell structure according to embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] In the following description, numerous specific details are set forth to provide a more thorough explanation of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure can be practiced without one or more of these specific details.

[0028] It is to be understood that the present disclosure can be implemented in various forms without being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and fully convey the scope of the present disclosure to those skilled in the art. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals refer to like elements throughout.

[0029] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when an element is referred to as being "connected to" or "coupled to" another element or layer, it can be directly connected to the other element or layer or intervening elements or layers can be present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0030] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" and "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees, or at other orientations) and the spatial description terminology will be interpreted accordingly.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] For a thorough understanding of the present disclosure, reference will be made to the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0033] In order to improve the remanent polarization of ferroelectric material per unit device area, the present disclosure provides a preparation method of a storage cell structure, as shown in FIG. 1, comprising the following steps S110 to S140.

[0034] Step S110: providing a substrate, a switching transistor is formed on the substrate;

[0035] Step S120: forming a forest structure above the switching transistor;

[0036] Step S130: forming a capacitor structure covering the forest structure, the capacitor structure comprising a first electrode and a second electrode, wherein the first electrode is electrically connected with the drain of the switching transistor;

[0037] Step S140: forming a wiring layer above the capacitor structure, etching the wiring layer to form a bit line and a plate line, the plate line being electrically connected with the second electrode of the capacitor structure, and the bit line being electrically connected with the source electrode of the switch transistor.

[0038] The preparation method of the storage unit structure provided by the present disclosure increases the surface area of the ferroelectric material per unit device area by forming a forest structure and covering the surface of the forest structure with the capacitor structure, thereby increasing the residual polarization of the ferroelectric material per unit device area, increasing the storage window of the ferroelectric memory, and improving the performance of the ferroelectric memory.

[0039] In order to thoroughly understand the present disclosure, detailed steps and structures will be presented in the following description in order to illustrate the technical solutions proposed by the present disclosure. The preferred embodiments of the present disclosure are described in detail as follows, however, in addition to these detailed descriptions, the present disclosure can have other implementation manners.

[0040] The preparation method of the storage unit structure of the present disclosure will be described in detail with reference to FIGS. 2A to 2D, wherein FIGS. 2A to 2D show cross-sectional schematic diagrams of the storage unit structure obtained by sequentially implementing the steps of the preparation method of the storage unit structure of the present disclosure.

[0041] Exemplarily, the preparation method of the storage unit structure of the present disclosure includes the following steps S110 to S140.

[0042] Firstly, step S110 is performed to obtain the structure as shown in FIG. 2A. A substrate 200 is provided, and a switch transistor 210 is formed on the substrate 200.

[0043] Exemplarily, the substrate 200 can be any suitable semiconductor substrate, such as a silicon substrate. The substrate 200 can include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors. The substrate 200 can include a multi-layer structure composed of at least two semiconductor materials in Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compounds. The substrate 200 can include a silicon-on-insulator (SOI), a stacked silicon-on-insulator (SSOI), a stacked silicon germanium-on-insulator (S-SiGeOI), a silicon germanium-on-insulator (SiGeOI) or a germanium-on-insulator (GeOI). The substrate 200 can include double side polished wafers (DSP). The substrate 200 can include a ceramic substrate such as aluminum oxide, a quartz or glass substrate, etc.

[0044] The switch transistor can be a field effect transistor, such as an N-type field effect transistor, and the present disclosure does not limit the switch transistor.

[0045] Exemplarily, the step of forming the switch transistor 210 on the substrate can include the following steps:

[0046] A gate dielectric layer (not shown) is formed on the upper surface of the substrate 200. Specifically, the gate dielectric layer can be formed by a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process, and the like. The gate dielectric layer includes, but is not limited to, a silicon oxide layer.

[0047] A gate material layer is formed on the upper surface of the gate dielectric layer. Specifically, the gate material layer can be formed by a physical vapor deposition process or a chemical vapor deposition process, and the like. The gate material layer includes, but is not limited to, a doped polysilicon layer or a metal layer.

[0048] The gate material layer and the gate dielectric layer are etched to form a gate 211. In an embodiment of the present disclosure, the gate 211 of the switch transistor 210 is a word line.

[0049] Side walls can also be formed on both sides of the gate 211. Specifically, the side walls can be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process, and the like. The side walls include, but are not limited to, a silicon oxide layer, a silicon nitride layer, or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer).

[0050] The substrate 200 is ion implanted based on the gate 211 and the side walls to form a drain 212 and a source 213 on both sides of the gate 211 and the side walls, respectively. For example, the exposed regions on the substrate 200 are ion implanted to form the drain 212 and the source 213 on the substrate 200 in regions other than the gate 211 and the side walls, i.e., the drain 212 and the source 213 are located on both sides of the gate 211.

[0051] In an embodiment, after the drain 212 and the source 213 are formed, a step of forming a metal silicide (not shown) on the upper surfaces of the drain 212 and the source 213 can also be included. By forming a metal silicide on the upper surfaces of the drain 212 and the source 213, the contact resistance of the drain 212 and the source 213 to the conductive plug leading to them can be reduced.

[0052] Next, step S120 is performed to obtain the structure shown in FIG. 2B. A forest structure 230 is formed above the switch transistor 210. The forest structure 230 can include a nano-forest structure.

[0053] Exemplarily, forming the forest structure 230 above the switch transistor 210 comprises: forming a first dielectric layer 220 above the switch transistor 210, the first dielectric layer 220 covering the switch transistor 210, and the first dielectric layer 220 isolating the switch transistor 210 from the capacitor structure 240 formed in step S130; forming a first conductive plug 221 in the first dielectric layer 220, a bottom of the first conductive plug 221 being electrically connected to the drain 212 of the switch transistor; forming a forest structure material layer above the first dielectric layer 220, and etching the forest structure material layer to form the forest structure 230, the forest structure 230 comprising one or more columnar structures, and the first conductive plug 221 being exposed after forming the forest structure 230.

[0054] In one embodiment, as shown in FIG. 2B, a first dielectric layer 220 is formed above the switch transistor 210, the first dielectric layer 220 covering the switch transistor 210, and specifically, the first dielectric layer 220 can be formed by a physical vapor deposition process or a chemical vapor deposition process, etc., the first dielectric layer 220 being used to isolate the switch transistor 210 from the capacitor structure 240 formed in step S130, and the first dielectric layer 220 comprising but not limited to a silicon oxide layer. Next, the first dielectric layer 220 is etched to form a first interconnection via hole penetrating through the first dielectric layer 220, and specifically, the first interconnection via hole can be formed by a dry etching process, etc.; the first interconnection via hole is filled to form a first conductive plug 221, and specifically, the first conductive plug 221 is formed by an electroplating process, etc., and a material of the first conductive plug 221 comprising but not limited to tungsten or copper; a bottom of the first conductive plug 221 being electrically connected to the drain 212 (or a metal silicide on the surface of the drain) of the switch transistor.

[0055] In one embodiment, a forest structure material layer is formed above the first dielectric layer 220, the forest structure material layer can be a photoresist material such as polyimide (PI), etc., or a dielectric material such as silicon oxide or silicon nitride, etc., and the present disclosure does not make any limitation in this regard. The forest structure 230 is usually a plurality of rows and columns of columnar structures, as shown in FIG. 4, and the forest structure 230 with a plurality of rows and columns of columnar structures can be formed by plasma bombardment on the forest structure material layer. In addition, the forest structure 230 can also comprise a single columnar structure or a single row or single column of columnar structures, and the present disclosure does not make any limitation in this regard.

[0056] It should be noted that after forming the forest structure 230, the first conductive plug 221 needs to be exposed, so that the first conductive plug 221 is electrically connected to the first electrode of the capacitor structure 240 formed in step S130, to realize the electrical connection between the drain 212 of the switch transistor and the capacitor structure 240.

[0057] In one embodiment, as shown in FIG. 2B and FIG. 4, the forest structure 230 is an integral structure, the bottoms of the plurality of columnar structures are connected to each other. In forming such a forest structure 230, the forest structure material layer in other regions can be removed first, and only the forest structure material layer in the region where the forest structure is located is retained to expose the first conductive plug 221. Then the remaining forest structure material layer is etched or subjected to plasma bombardment, and the etching endpoint is controlled to retain the bottoms of the forest structure, so that the bottoms of the plurality of columnar structures are connected to each other. In this case, in order to expose the first conductive plug 221, the forest structure 230 is usually arranged on the outer side (i.e., the side away from the gate 211) of the first conductive plug 221.

[0058] In one embodiment, as shown in FIG. 5, the columnar structures of the forest structure 230 are separated from each other without connection. In forming such a forest structure 230, the forest structure material layer in other regions can be removed first, and only the forest structure material layer in the region where the forest structure is located is retained, and then the forest structure material layer is subjected to etching or other processes to expose the first conductive plug 221. In this case, the position of the forest structure 230 is not limited by the position of the first conductive plug 221, which is conducive to the integration of the device structure.

[0059] In addition, the cross section of the columnar structure of the forest structure 230 includes but is not limited to a circle, a rectangle, a square, or a triangle, etc., and the present disclosure does not limit this.

[0060] Next, step S130 is performed to obtain a structure as shown in FIG. 2C. The capacitor structure 240 covering the forest structure 230 is formed, the capacitor structure 240 including a first electrode 241 and a second electrode 243, wherein the first electrode 241 is electrically connected to the drain 212 of the switching transistor.

[0061] In one embodiment, the capacitor structure 240 can be a planar capacitor (including a deformed structure of the planar capacitor), in which case the second electrode 243 is located above the first electrode 241. The capacitor structure 240 can also be a columnar capacitor (including a deformed structure of the columnar capacitor), in which case the second electrode 243 is located on the outer side of the first electrode 241.

[0062] Exemplarily, with reference to FIG. 2C and FIG. 3, forming the capacitor structure 240 covering the forest structure 230 includes sequentially forming the first electrode 241, the capacitor dielectric layer 242, and the second electrode 243, all of which cover the upper surfaces of the one or more columnar structures, the sidewalls of the columnar structures, and the bottoms of the gaps between adjacent columnar structures, and the first electrode 241 is in contact with the first conductive plug 221.

[0063] In one embodiment, as shown in FIG. 2C and FIG. 3, a lower electrode layer, a capacitor dielectric layer and an upper electrode layer are sequentially formed on the surface of the first dielectric layer 220 and the forest structure 230; the lower electrode layer is used to form the first electrode 241 of the capacitor structure 240, specifically, the lower electrode layer can be formed by physical vapor deposition process, chemical vapor deposition process or electroplating process, etc., and the lower electrode layer is a metal layer; the capacitor dielectric layer is a HZO (Hf 1-x Zr x O2) ferroelectric thin film, and the thickness of the capacitor dielectric layer can be set according to actual needs; the upper electrode layer is used to form the second electrode 243 of the capacitor structure 240, specifically, the upper electrode layer can be formed by physical vapor deposition process, chemical vapor deposition process or electroplating process, etc., and the upper electrode layer is a metal layer, and the material of the upper electrode layer can be the same as that of the lower electrode layer. The lower electrode layer, the capacitor dielectric layer and the upper electrode layer are etched to form the capacitor structure 240; specifically, the lower electrode layer, the capacitor dielectric layer and the upper electrode layer can be etched by dry etching process, etc. The cross section of the capacitor structure 240 prepared by the above method is a continuous "J" shape, as shown in FIG. 2C.

[0064] Next, step S130 is performed to obtain the structure as shown in FIG. 2D. A wiring layer is formed above the capacitor structure 240, and the wiring layer is etched to form a bit line and a plate line, the plate line is electrically connected with the second electrode of the capacitor structure, and the bit line is electrically connected with the source of the switching transistor.

[0065] In one embodiment, as shown in FIG. 2D, a second dielectric layer 250 is formed on the capacitor structure 240, and the second dielectric layer 250 covers the capacitor structure 240, which is used to isolate the capacitor structure 240 from the wiring layer. The second dielectric layer 250 is etched to form a second interconnection via hole penetrating through the second dielectric layer 250, and the second dielectric layer 250 and the first dielectric layer 220 are etched to form a third interconnection via hole penetrating through the second dielectric layer 250 and the first dielectric layer 220, the second interconnection via hole is filled to form a second conductive plug 251, and the third interconnection via hole is filled to form a third conductive plug 252. The bottom of the second conductive plug 251 is electrically connected with the second electrode 243 of the capacitor structure, and the bottom of the third conductive plug 252 is electrically connected with the source 213 (or the metal silicide on the source surface) of the switching transistor.

[0066] In one embodiment, after the second dielectric layer 250 is formed, a step of annealing treatment is further included; since the hafnium oxide formed by conventional process does not have ferroelectricity, the annealing treatment is needed to make the capacitor dielectric layer form a special crystal phase to have ferroelectricity. Specifically, the annealing temperature in the annealing treatment process can range from 450°C to 750°C.

[0067] Next, a first wiring layer is formed above the second dielectric layer 250, the first wiring layer is etched to form the plate line 260 while also forming a plate line metal layer 261 that contacts the top of the third conductive plug 252. The top of the second conductive plug 251 is electrically connected to the plate line 260, achieving electrical connection of the plate line 260 to the capacitor structure 240.

[0068] Next, a third dielectric layer 270 is formed above the second dielectric layer 250, the third dielectric layer 270 covers the plate line 260 and the plate line metal layer 261. The third dielectric layer 270 is etched to form a fourth interconnection via that penetrates the third dielectric layer 270, the fourth interconnection via is filled to form a fourth conductive plug 271, the bottom of the fourth conductive plug 271 is electrically connected to the plate line metal layer 261.

[0069] Next, a second wiring layer is formed above the third dielectric layer 270, the second wiring layer is etched to form a bit line 280. The top of the fourth conductive plug 271 is electrically connected to the bit line 280, achieving electrical connection of the bit line 280 to the source 213 (or metal silicide on the source surface) of the switching transistor.

[0070] So far, the key steps of the preparation method of the storage unit structure of the present disclosure have been introduced. Other processes may also be required for complete device preparation, which will not be described here.

[0071] It is worth mentioning that the order of the above steps is only an example, and the order of the above steps can also be changed or alternated, etc. without conflict.

[0072] The present disclosure also provides a storage unit structure, as shown in FIG. 2D, comprising a switching transistor 210, a forest structure 230, a capacitor structure 240 and a wiring layer; wherein:

[0073] The switching transistor 210 is located on the substrate 200;

[0074] The capacitor structure 240 is located above the switching transistor 210, the capacitor structure 240 covers the surface of the forest structure 230, the capacitor structure 240 comprises a first electrode 241 and a second electrode 243, wherein the first electrode 241 is electrically connected to the drain 212 of the switching transistor;

[0075] The wiring layer is located above the capacitor structure 240, the wiring layer comprises a bit line 280 and a plate line 260, the plate line 260 is electrically connected to the second electrode 243 of the capacitor structure, and the bit line 280 is electrically connected to the source 213 of the switching transistor.

[0076] Exemplarily, the storage unit structure further comprises: a first dielectric layer 220 located between the capacitor structure 240 and the substrate 200 and covering the switch transistor 210; a first conductive plug 221 located in the first dielectric layer 220, a top of the first conductive plug 221 being electrically connected with the first electrode 241 of the capacitor structure 240, and a bottom of the first conductive plug 221 being electrically connected with the drain 212 of the switch transistor; a second dielectric layer 250 located between the first dielectric layer 220 and the wiring layer and covering the capacitor structure 240; and a second conductive plug 251 located in the second dielectric layer 250, a bottom of the second conductive plug 251 being electrically connected with the second electrode 243 of the capacitor structure 240, and a top of the second conductive plug 251 being electrically connected with the plate line 260.

[0077] Further, the storage unit structure further comprises: a third conductive plug 252 located in the first dielectric layer 220 and the second dielectric layer 250, a bottom of the third conductive plug 252 being electrically connected with the source 213 of the switch transistor, and a top of the third conductive plug 252 being electrically connected with the plate line metal layer 261; a third dielectric layer 270 located between the first wiring layer where the plate line 260 is located and the second wiring layer where the bit line 280 is located, for making the plate line 260 and the bit line 280 at different heights; and a fourth conductive plug 271 located in the third dielectric layer 270, a bottom of the fourth conductive plug 271 being electrically connected with the plate line metal layer 261, and a top of the fourth conductive plug 271 being electrically connected with the bit line 280.

[0078] Exemplarily, the forest structure comprises one or more columnar structures, and the columnar structures are arranged in a single row, a single column, or multiple rows and multiple columns.

[0079] In an embodiment, the forest structure 230 can be made of photoresist material such as polyimide (PI) or dielectric material such as silicon oxide or silicon nitride, which is not limited in the present disclosure. The forest structure 230 is usually a multi-row and multi-column columnar structure as shown in FIG. 4. In addition, the forest structure 230 can also comprise a single columnar structure or columnar structures arranged in a single row or a single column, which is not limited in the present disclosure.

[0080] It should be noted that after forming the forest structure 230, the first conductive plug 221 needs to be exposed to be electrically connected with the first electrode 241 of the capacitor structure 240, so as to realize the electrical connection between the drain 212 of the switch transistor and the capacitor structure 240.

[0081] In one embodiment, as shown in FIG. 2D and FIG. 4, the forest structure 230 is an integral structure, and the bottoms of the plurality of columnar structures are connected to each other. In this case, in order to make the forest structure 230 not cover the first conductive plug 221, the forest structure 230 is usually arranged at the outer side (i.e., the side away from the gate 211) of the first conductive plug 221.

[0082] In one embodiment, as shown in FIG. 5, the columnar structures of the forest structure 230 are separated from each other without connection. In this case, the position of the forest structure 230 is not limited by the position where the first conductive plug 221 is located, which is conducive to the integration of the device structure.

[0083] In addition, the cross section of the columnar structure of the forest structure 230 includes but is not limited to a circle, a rectangle, a square, or a triangle, etc., and the present disclosure does not limit this.

[0084] Exemplarily, the surface of the forest structure 230 covered by the capacitor structure 240 includes that the capacitor structure includes a first electrode 241, a second electrode 243, and a capacitor dielectric layer 242 between the first electrode 241 and the second electrode 243, and the first electrode 241, the capacitor dielectric layer 242, and the second electrode 243 of the capacitor structure all cover the upper surface of the one or more columnar structures, the sidewall of the columnar structure, and the bottom of the gap between adjacent columnar structures.

[0085] In one embodiment, as shown in FIG. 2D and FIG. 3, the first electrode 241 and the second electrode 243 of the capacitor structure 240 are both metal layers, and the materials of the first electrode 241 and the second electrode 243 are the same. The capacitor dielectric layer is a HZO (Hf 1-x Zr x O2) ferroelectric film, and the thickness of the capacitor dielectric layer can be set according to actual needs. The cross section of the capacitor structure 240 is a continuous "J" shape, as shown in FIG. 2C.

[0086] In one embodiment, the capacitor structure 240 can be a planar capacitor (including a deformed structure of the planar capacitor), in which case the second electrode is located above the first electrode. The capacitor structure 240 can also be a columnar capacitor (including a deformed structure of the columnar capacitor), in which case the second electrode is located at the outer side of the first electrode.

[0087] The present disclosure also provides a ferroelectric memory including the memory cell structure as described above.

[0088] The memory cell structure and the preparation method thereof, and the ferroelectric memory provided by the present disclosure increase the surface area of the ferroelectric material per unit device area by forming a forest structure and making a capacitor structure cover the surface of the forest structure, thereby increasing the remanent polarization, increasing the storage window of the ferroelectric memory, and improving the performance of the ferroelectric memory.

[0089] The present disclosure has been described through the above-described embodiments, but it should be understood that the above-described embodiments are only for the purpose of example and illustration, and are not intended to limit the present disclosure to the scope of the described embodiments. Furthermore, those skilled in the art can understand that the present disclosure is not limited to the above-described embodiments, and various modifications and changes can be made according to the teachings of the present disclosure, and these modifications and changes all fall within the scope of the present disclosure claimed. The scope of protection of the present disclosure is defined by the attached claims and their equivalent scope.

Claims

1. A storage cell structure, characterized in that, include: A switching transistor, wherein the switching transistor is located on a substrate; A forest structure, the forest structure comprising one or more columnar structures; A capacitor structure and a forest structure are located above the switching transistor, the capacitor structure covering the surface of the forest structure, the capacitor structure including a first electrode and a second electrode, wherein the first electrode is electrically connected to the drain of the switching transistor; A wiring layer, located above the capacitor structure, includes bit lines and board lines. The plate wire is electrically connected to the second electrode of the capacitor structure. The bit line is electrically connected to the source of the switching transistor.

2. The storage cell structure as described in claim 1, characterized in that, The forest structure includes multiple columnar structures, which are arranged in a single row, a single column, or multiple rows and columns.

3. The storage cell structure as described in claim 1, characterized in that, The capacitor structure further includes a capacitor dielectric layer located between the first electrode and the second electrode. The first electrode, the capacitor dielectric layer, and the second electrode of the capacitor structure all cover the upper surface of each of the one or more columnar structures, the sidewalls of each of the columnar structures, and the bottom of the gaps between adjacent columnar structures.

4. The storage cell structure as described in claim 1, characterized in that, The second electrode is located above the first electrode, or, The second electrode is located outside the first electrode.

5. The storage cell structure as described in claim 1, characterized in that, Also includes: A first dielectric layer is located between the capacitor structure and the substrate, and covers the switching transistor; A first conductive plug is located within the first dielectric layer. The top of the first conductive plug is electrically connected to the first electrode of the capacitor structure, and the bottom of the first conductive plug is electrically connected to the drain of the switching transistor. The second dielectric layer is located between the first dielectric layer and the wiring layer, and covers the capacitor structure; The second conductive plug is located within the second dielectric layer. The bottom of the second conductive plug is electrically connected to the second electrode of the capacitor structure, and the top of the second conductive plug is electrically connected to the plate line.

6. The storage cell structure as described in claim 1, characterized in that, The forest structure includes multiple columnar structures, and the bases of the multiple columnar structures are connected to each other in the forest structure.

7. The storage cell structure as described in claim 1, characterized in that, The forest structure includes multiple columnar structures, which are separated from each other.

8. The storage cell structure as described in claim 1, characterized in that, The capacitor structure is a planar capacitor, wherein the second electrode is located above the first electrode; or The capacitor structure is a cylindrical capacitor, wherein the second electrode is located outside the first electrode.

9. A method for fabricating a memory cell structure, characterized in that, include: A substrate is provided on which switching transistors are formed; A forest structure is formed above the switching transistor, the forest structure comprising one or more columnar structures; A capacitor structure is formed covering the forest structure, the capacitor structure including a first electrode and a second electrode, wherein the first electrode is electrically connected to the drain of the switching transistor; A wiring layer is formed above the capacitor structure; The wiring layer is etched to form bit lines and board lines, the board lines being electrically connected to the second electrode of the capacitor structure, and the bit lines being electrically connected to the source of the switching transistor.

10. The method for fabricating the memory cell structure as described in claim 9, characterized in that, Forming a forest structure above the switching transistor includes: A first dielectric layer is formed on the switching transistor, the first dielectric layer covers the switching transistor, and the first dielectric layer isolates the switching transistor from the capacitor structure; A first conductive plug is formed in the first dielectric layer, and the bottom of the first conductive plug is electrically connected to the drain of the switching transistor. A forest structure material layer is formed on the first medium layer; The forest structure material layer is etched to form the forest structure, which does not cover the first conductive plug.

11. The method for fabricating the memory cell structure as described in claim 10, characterized in that, Etching the forest structure material layers to form the forest structure includes: The forest structure material layer is bombarded with plasma to form a forest structure with multiple rows and columns of columnar structure.

12. The method for fabricating the memory cell structure as described in claim 10, characterized in that, The capacitive structure forming the forest structure includes: A first electrode, a capacitor dielectric layer, and a second electrode are formed sequentially. The first electrode, the capacitor dielectric layer, and the second electrode all cover the upper surface of each of the one or more columnar structures, the sidewall of each of the columnar structures, and the bottom of the gap between adjacent columnar structures. The first electrode is in contact with the first conductive plug.

13. The method for fabricating the memory cell structure as described in claim 9, characterized in that, The forest structure includes multiple columnar structures, and the bases of the multiple columnar structures are connected to each other in the forest structure.

14. The method for fabricating the memory cell structure as described in claim 9, characterized in that, The forest structure includes multiple columnar structures, which are separated from each other.

15. A ferroelectric memory, characterized in that, The storage cell structure includes any one of claims 1 to 8.

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