Terminal structure of semiconductor device and manufacturing method therefor, semiconductor device, power module, power electronic device, and vehicle

Abstract

A terminal structure of a semiconductor device and a manufacturing method therefor, a semiconductor device, a power module, a power electronic device, and a vehicle. The terminal structure of the semiconductor device comprises: a substrate of a first conductivity type; an epitaxial layer of the first conductivity type, the epitaxial layer being located on the substrate in a first direction; and a field limiting ring structure, the field limiting ring structure being located in the epitaxial layer in the first direction, the field limiting ring structure being disposed around an active region, the field limiting ring structure comprising a first well region of a second conductivity type, a plurality of doped regions of the first conductivity type are provided in the first well region, and the plurality of doped regions of the first conductivity type are arranged at intervals in a second direction perpendicular to the first direction.

Description

Terminal structure of semiconductor device and manufacturing method thereof, semiconductor device, power module, power electronic device and vehicle

[0001] The present application claims priority from the Chinese patent application No. 202410866923.9 filed on June 28, 2024, and entitled "Terminal structure of semiconductor device and manufacturing method thereof, semiconductor device, power module, power electronic device and vehicle", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the technical field of power devices, in particular to a terminal structure of semiconductor device and manufacturing method thereof, semiconductor device, power module, power electronic device and vehicle. BACKGROUND

[0003] The active region of the power semiconductor device bears the PN junction of the withstand voltage, which is approximately a planar junction, and can bear a higher withstand voltage, while the edge of the active region will cause the PN junction to have a lower withstand voltage due to the concentration effect of the electric field, which severely limits the withstand voltage value of the power device. Therefore, in order to improve the maximum withstand voltage of the power device, a ring of terminal structure needs to be added at the edge of the active region to alleviate the concentration effect of the electric field at the edge of the active region. The existing terminal technology field ring field plate terminal usually uses field ring voltage division to make the voltage drop over a longer distance to withstand high voltage.

[0004] DISCLOSURE

[0005] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the first object of the present application is to propose a terminal structure of semiconductor device, which can improve the surface doping and surface electric field distribution, reduce the electric field peak and leakage, and improve the efficiency of the terminal structure, thereby maintaining high withstand voltage under smaller size of the terminal structure.

[0006] The second object of the present application is to propose a semiconductor device.

[0007] The third object of the present application is to propose a power module.

[0008] The fourth object of the present application is to propose a power electronic device.

[0009] The fifth object of the present application is to propose a vehicle.

[0010] The sixth object of the present application is to propose a method for manufacturing a terminal structure of semiconductor device.

[0011] To achieve the above object, the semiconductor device terminal structure provided by the first aspect of the present application comprises: a substrate of a first conduction type; an epitaxial layer of the first conduction type, which is located on the substrate in a first direction; and a field limiting ring structure, which is located in the epitaxial layer in the first direction, and which surrounds an active region, and which comprises a first well region of a second conduction type, and which is provided with a plurality of doped regions of the first conduction type in the first well region, and which are arranged in a second direction perpendicular to the first direction.

[0012] The semiconductor device terminal structure provided by the present application can combine the first well region of the second conduction type and the plurality of doped regions of the first conduction type in the epitaxial layer in the field limiting ring structure, which is equivalent to introducing different conduction type columns of different doping concentrations arranged alternately, and by using the charge compensation principle, the different conduction type columns can be well depleted in the blocking state, so as to improve the surface doping and surface electric field distribution, reduce the electric field peak and leakage, improve the efficiency of the terminal structure, effectively reduce the size of the terminal structure, and thus obtain higher withstand voltage in the same terminal structure size. For the same semiconductor device, the small-size terminal structure can reserve more space for the active region of the chip, and reduce the proportion of the chip area occupied by the terminal structure.

[0013] In addition, by arranging the first well region in the epitaxial layer in the field limiting ring structure, the first well region can offset a part of the electric field of the epitaxial layer, so as to reduce the influence of the epitaxial layer doping on the charge balance of the charge compensation region, and further improve the withstand voltage of the terminal structure.

[0014] In some embodiments of the present application, the plurality of doped regions of the first conduction type are annular doped regions surrounding the entire active region.

[0015] In some embodiments of the present application, each of the doped regions of the first conduction type surrounds the active region, and each of the doped regions of the first conduction type comprises a plurality of first conduction type sub-doped regions arranged at intervals.

[0016] In some embodiments of the present application, the first conduction type sub-doped region is a first conduction type columnar sub-doped region.

[0017] In some embodiments of the present application, in the second direction, distances between adjacent ones of the plurality of doped regions of the first conductivity type are equal; or in the second direction, distances between adjacent ones of the plurality of doped regions of the first conductivity type gradually increase in a direction away from the active region; or in the second direction, distances between adjacent ones of the plurality of doped regions of the first conductivity type gradually decrease in a direction away from the active region.

[0018] In some embodiments of the present application, the field-limiting ring structure further comprises: a second well region of the second conductivity type, the second well region being located in the epitaxial layer in the first direction, the second well region being located on a side of the first well region close to the active region, the second well region being connected with the first well region. Wherein, the second well region functions as a main junction, which can provide a current extraction location for the termination and a placement location for the gate of the power MOSFET.

[0019] In some embodiments of the present application, the field-limiting ring structure further comprises: a cutoff ring region, the cutoff ring region being located at an end of the epitaxial layer away from the active region in the second direction and being spaced apart from the first well region.

[0020] In some embodiments of the present application, the first well region, the second well region, each of the doped regions, and the cutoff ring region each extend into the epitaxial layer in a direction close to the substrate from a surface thereof away from the substrate.

[0021] In some embodiments of the present application, the termination structure of the semiconductor device further comprises: an oxide layer, the oxide layer being located on a side of the first well region, the second well region, the plurality of doped regions, and the cutoff ring region away from the substrate in the first direction and covering a portion of the first well region, a portion of the second well region, the plurality of doped regions, and a portion of the cutoff ring region.

[0022] In some embodiments of the present application, the termination structure of the semiconductor device further comprises: a gate, the gate comprising a first gate portion and a second gate portion connected with each other, the first gate portion being located on a side of the oxide layer away from the substrate in the first direction.

[0023] In some embodiments of the present application, the termination structure of the semiconductor device further comprises: a plurality of polycrystalline field plates, the plurality of polycrystalline field plates being located on a side of the oxide layer away from the substrate in the first direction, the plurality of polycrystalline field plates being spaced apart from the second gate and from each other in the second direction.

[0024] In some embodiments of the present application, the oxide layer comprises: a first oxide layer, the first oxide layer is located on a side of the first well region, a plurality of the doped regions and the cutoff ring region away from the substrate in the first direction and continuously extends along the second direction, a side of the first oxide layer away from the substrate in the first direction is provided with the second gate part and the plurality of polycrystalline field plates, and the first oxide layer covers the first well region, the plurality of the doped regions and the part of the cutoff ring region.

[0025] In some embodiments of the present application, the oxide layer further comprises: a second oxide layer, the second oxide layer is connected with the first oxide layer, the second oxide layer is located on a side of the second well region away from the substrate in the first direction and between the second well region and the first gate part; wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer. Wherein, by setting the first oxide layer to be thicker, a higher breakdown voltage can be withstood; while the second oxide layer is thicker, the threshold voltage will be too large, and even the semiconductor device can not be turned on.

[0026] In some embodiments of the present application, the terminal structure of the semiconductor device further comprises: a protective layer, the protective layer is located on a side of the field limiting ring structure away from the substrate in the first direction.

[0027] In some embodiments of the present application, the protective layer comprises: a third oxide layer, the third oxide layer is located on a side of the second well region, the gate, the first oxide layer, the plurality of the polycrystalline field plates and the cutoff ring region away from the substrate in the first direction and continuously extends along the second direction, for covering a part of the second well region, the gate, the first oxide layer, the plurality of the polycrystalline field plates and a part of the cutoff ring region.

[0028] In some embodiments of the present application, the protective layer further comprises: an active region metal, the active region metal comprises a first active region metal part and a second active region metal part, the first active region metal part and the second active region metal part are connected, the first active region metal part is located on a side of the second well region away from the substrate in the first direction, and the second active region metal part is located on a side of the third oxide layer away from the substrate in the first direction. Wherein, the second active region metal part functions as a metal field plate, and by setting the metal field plate, the electric field at the main junction, i.e. the second well region, can be reduced.

[0029] In some embodiments of the present application, the terminal structure of the semiconductor device further comprises: a cutoff ring metal, the cutoff ring metal comprising a first cutoff ring metal portion and a second cutoff ring metal portion, the first cutoff ring metal portion being connected with the second cutoff ring metal portion, the first cutoff ring metal portion being located on a side of the third oxide layer away from the substrate in the first direction, the first cutoff ring metal portion being spaced apart from the second active region metal portion in the second direction, the second cutoff ring metal portion being located on a side of the cutoff ring region away from the substrate in the first direction, a side of the second cutoff ring metal portion away from the active region being flush with a side of the cutoff ring region away from the active region.

[0030] To achieve the above object, the semiconductor device according to the second aspect of the present application comprises: an active region; and the terminal structure of the semiconductor device according to any one of the above embodiments, the terminal structure of the semiconductor device being arranged around the active region.

[0031] The semiconductor device according to the embodiments of the present application can improve the surface doping and the surface electric field distribution, and can also reduce the electric field peak and the leakage current, thereby improving the efficiency of the semiconductor device. The size of the terminal structure is relatively small as a whole, so that a higher withstand voltage can be obtained under the same size of the terminal structure. For the same semiconductor device, the small-size terminal structure can reserve more space for the active region of the chip, thereby reducing the proportion of the chip area occupied by the terminal structure.

[0032] To achieve the above object, the power module according to the third aspect of the present application comprises the semiconductor device according to the second aspect of the above embodiments.

[0033] The power module according to the embodiments of the present application comprises the semiconductor device according to the above embodiments. By improving the structure of the semiconductor device, the efficiency and the withstand voltage of the semiconductor device are improved, thereby improving the efficiency and the withstand voltage of the power module.

[0034] To achieve the above object, the power electronic device according to the fourth aspect of the present application comprises the power module according to the third aspect of the above embodiments.

[0035] The power electronic device according to the embodiments of the present application comprises the power module according to the above embodiments. By improving the efficiency of the semiconductor device, the efficiency and the withstand voltage of the power module are improved, thereby effectively improving the efficiency and the performance of the power electronic device.

[0036] To achieve the above object, the vehicle according to the fifth aspect of the present application comprises the semiconductor device according to the above embodiments.

[0037] According to the vehicle provided by the embodiments of the present application, by adopting the semiconductor device of the above embodiments, the efficiency of the semiconductor device is improved, the performance of the vehicle and the withstand voltage of the circuit structure in the vehicle are improved, and the safety of the vehicle is improved.

[0038] To achieve the above object, the sixth aspect of the present application provides a method for manufacturing a terminal structure of a semiconductor device, comprising: forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, the epitaxial layer being located on the substrate in a first direction; and forming a field limiting ring structure surrounding an active region in a region of the epitaxial layer away from the substrate, comprising: forming a first well region of a second conductivity type in the region of the epitaxial layer away from the substrate; and forming a plurality of doped regions of the first conductivity type spaced apart in a second direction perpendicular to the first direction within the first well region.

[0039] According to the method for manufacturing a terminal structure of a semiconductor device provided by the embodiments of the present application, by combining the first well region of the second conductivity type and the plurality of doped regions of the first conductivity type in the field limiting ring structure, a column of different conductivity types with different doping concentrations is introduced, and the column of different conductivity types is well depleted by using the charge compensation principle, so that the surface doping and the surface electric field distribution are improved, the electric field peak and the leakage are reduced, the efficiency of the terminal structure is improved, and the size of the terminal structure is effectively reduced, so that a higher withstand voltage is obtained under the same size of the terminal structure, and more space is reserved for the active region of the chip by using the terminal structure with a smaller size, and the proportion of the chip area occupied by the terminal structure is reduced.

[0040] In addition, by arranging the first well region in the epitaxial layer in the field limiting ring structure, the first well region can offset a part of the electric field of the epitaxial layer, so that the influence of the epitaxial layer doping on the charge balance of the charge compensation region is reduced, and the withstand voltage of the terminal structure is further improved.

[0041] In some embodiments of the present application, forming the first well region of the second conductivity type in the region of the epitaxial layer away from the substrate comprises: performing ion implantation of the second conductivity type on the surface of the epitaxial layer away from the substrate in the first direction and performing high-temperature annealing to form the first well region of the second conductivity type.

[0042] In some embodiments of the present application, forming the plurality of doped regions of the first conductivity type spaced apart in the second direction perpendicular to the first direction within the first well region comprises: performing ion implantation of the first conductivity type in a plurality of spaced-apart implantation regions within the first well region and performing high-temperature annealing to form the plurality of doped regions of the first conductivity type.

[0043] In some embodiments of the present application, the distance between two adjacent doping regions satisfies:

[0044] wherein, Na is the doping concentration of the doping region; W a is the width of the doping region, Nd is the doping concentration of the first well region, W d is the distance between two adjacent doping regions, i is the i-th doping region, and n is the total number of the doping regions, n.

[0045] In some embodiments of the present application, the field limiting ring structure surrounding the active region is formed in the region of the epitaxial layer away from the substrate, further comprising: ion implantation on the end of the epitaxial layer away from the active region in the second direction to form a cutoff ring region.

[0046] In some embodiments of the present application, the field limiting ring structure surrounding the active region is formed in the region of the epitaxial layer away from the substrate, further comprising: forming an oxide layer on the side of the first well region, the plurality of doping regions, and the cutoff ring region away from the substrate, the oxide layer covering the first well region, a portion of the epitaxial layer, the plurality of doping regions, and a portion of the cutoff ring region; forming a gate on the side of the oxide layer away from the substrate; and forming a plurality of polycrystalline field plates on the side of the oxide layer away from the substrate, the plurality of polycrystalline field plates being spaced apart from the gate in the second direction and spaced apart from each other.

[0047] In some embodiments of the present application, forming an oxide layer on the side of the first well region, the plurality of doping regions, and the cutoff ring region away from the substrate comprises: forming a first oxide layer continuously extending in the second direction on the side of the plurality of doping regions and the cutoff ring region away from the substrate; and forming a second oxide layer on the side of the epitaxial layer close to the active region and away from the substrate, the second oxide layer being connected to the first oxide layer.

[0048] In some embodiments of the present application, forming a gate on the side of the oxide layer away from the substrate comprises: forming a first gate portion on the side of the second oxide layer away from the substrate; and forming a second gate portion on the side of the first oxide layer away from the substrate, the first oxide layer covering the first well region, the plurality of doping regions, and the portion of the cutoff ring region, wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

[0049] In some embodiments of the present application, the field limiting ring structure surrounding the active region is formed in the region of the epitaxial layer away from the substrate, further comprising: forming a plurality of polycrystalline field plates on the side of the first oxide layer away from the substrate.

[0050] In some embodiments of the present application, the method for manufacturing the termination structure of the semiconductor device, further comprises: forming a field limiting ring structure surrounding the active region in the region of the epitaxial layer away from the substrate, further comprising: performing ion implantation of the second conductive type on the surface of the second oxide layer close to the substrate, the surface of the epitaxial layer away from the substrate, and the side of the first well region close to the active region to form a second well region of the second conductive type, the second well region being connected with the first well region.

[0051] In some embodiments of the present application, the method for manufacturing the termination structure of the semiconductor device, further comprises: forming a third oxide layer continuously extending along the second direction on the side of the second well region away from the substrate, the gate, the oxide layer, the plurality of polycrystalline field plates, and the part of the cutoff ring region, the third oxide layer being used for covering a part of the second well region, the gate, the oxide layer, the plurality of polycrystalline field plates, and a part of the cutoff ring region; and forming a first active region metal part on the side of the second well region away from the substrate, and forming a second active region metal part on the side of the third oxide layer away from the substrate, the first active region metal part and the second active region metal part being connected.

[0052] In some embodiments of the present application, the method for manufacturing the termination structure of the semiconductor device, further comprises: forming a cutoff ring metal on the side of the third oxide layer away from the substrate and the side of the cutoff ring region away from the substrate.

[0053] Additional aspects and advantages of the present application will be made apparent from the following description of embodiments, which proceeds with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0054] The above and / or additional aspects and advantages of the present application will become apparent and be readily appreciated from the following description of embodiments, taken in conjunction with the accompanying drawings, in which:

[0055] FIG. 1 is a schematic diagram of a termination structure of a semiconductor device according to an embodiment of the present application;

[0056] FIG. 2 is a schematic diagram of a termination structure of a semiconductor device according to another embodiment of the present application;

[0057] FIG. 3 is a top view of a semiconductor device according to an embodiment of the present application;

[0058] FIG. 4 is a top view of a semiconductor device according to another embodiment of the present application;

[0059] FIG. 5 is a schematic diagram of surface electric field distribution of a simulated extracted termination structure and a classical field ring field plate termination structure according to an embodiment of the present application;

[0060] FIG. 6 is a block diagram of a semiconductor device according to an embodiment of the present application;

[0061] FIG. 7 is a block diagram of a power module according to an embodiment of the present application;

[0062] FIG. 8 is a block diagram of a power electronic device according to an embodiment of the present application;

[0063] FIG. 9 is a block diagram of a vehicle according to an embodiment of the present application;

[0064] FIG. 10 is a schematic diagram of a preparation process of a termination structure of a semiconductor device according to an embodiment of the present application;

[0065] FIG. 11 is a schematic diagram of a preparation process of a termination structure of a semiconductor device according to another embodiment of the present application;

[0066] FIG. 12 is a schematic diagram of a preparation process of a termination structure of a semiconductor device according to yet another embodiment of the present application.

[0067] Reference signs: 1000: vehicle; 2000: power electronic device; 200: power module; 100: semiconductor device; 10: termination structure of semiconductor device; 20: active region; 1: substrate; 2: epitaxial layer; 3: field limiting ring structure; 31: first well region; 32: doped region; 33: second well region; 34: stop ring region; 35: oxide layer; 36: gate; 37: polycrystalline field plate; 41: third oxide layer; 42: active region metal; 43: stop ring metal; 351: first oxide layer; 352: second oxide layer; 361: first gate part; 362: second gate part; 421: first active region metal part; 422: second active region metal part; 431: first stop ring metal part; 432: second stop ring metal part. DETAILED DESCRIPTION

[0068] In the related art, a power semiconductor device is difficult to be depleted due to a high field ring doping concentration, resulting in low termination efficiency and large size. In addition, uneven surface electric field distribution is prone to avalanche, resulting in increased leakage current. In view of this, the embodiments of the present application provide a termination structure of a semiconductor device and a manufacturing method thereof, a semiconductor device, a power module, a power electronic device and a vehicle, which can improve surface doping and surface electric field distribution, reduce electric field peak value and leakage current, and improve the efficiency of the termination structure, thereby maintaining high withstand voltage under a small size of the termination structure.

[0069] The embodiments of the present application will be described in detail below, and the embodiments described with reference to the accompanying drawings are exemplary.

[0070] The terminal structure of a semiconductor device according to embodiments of the present application is described below with reference to FIGS. 1-5. FIG. 1 is a schematic diagram of a terminal structure of a semiconductor device according to one embodiment of the present application, where FIG. 1 is merely a basic schematic, and the terminal structure of the semiconductor device 10 includes a substrate 1 of a first conductivity type, an epitaxial layer 2 of the first conductivity type, and a field limiting ring structure 3.

[0071] The terminal structure of a semiconductor device 10 according to embodiments of the present application can be specifically understood in conjunction with FIG. 2, which is a schematic diagram of a terminal structure of a semiconductor device according to another embodiment of the present application.

[0072] As shown in FIG. 2, the epitaxial layer 2 is located on the substrate 1 in a first direction, and the field limiting ring structure 3 is located in the epitaxial layer 2 in the first direction. The epitaxial layer 2 is located on the substrate 1 in the first direction. The epitaxial layer 2 and the substrate 1 differ in concentration, with the substrate 1 being better doped, and the epitaxial layer 2 and the substrate 1 also differ in price and growth rate. It can be understood that the substrate 1 serves as the substrate of the entire power device.

[0073] The field limiting ring structure 3 surrounds the active region, and the field limiting ring structure 3 includes a first well region 31 of a second conductivity type, and a plurality of doped regions 32 of the first conductivity type are arranged in the first well region 31.

[0074] In the embodiments of the present application, FIG. 1 only shows a cross section of the terminal structure of the semiconductor device 10, and in fact, the field limiting ring structure 3 is a closed surrounding structure arranged in a circle around the periphery of the chip.

[0075] The terminal structure of a semiconductor device 10 according to embodiments of the present application has the first well region 31 in the epitaxial layer 2 in the field limiting ring structure 3, and a plurality of doped regions 32 of the first conductivity type are arranged in the first well region 31. The first well region 31 of the second conductivity type and the plurality of doped regions 32 of the first conductivity type are combined, which is equivalent to introducing different conductivity type columns of different doping concentrations arranged alternately. By using the charge compensation principle, in the blocking state, the different conductivity type columns can be well depleted, thereby improving the surface doping and surface electric field distribution, and the charges of the P columns and the N columns can be depleted with each other, which can also reduce the electric field peak and the leakage, improve the efficiency of the terminal structure of the semiconductor device 10, effectively reduce the size of the terminal structure of the semiconductor device 10, and thus obtain higher withstand voltage in the same size of the terminal structure of the semiconductor device 10, and for the same semiconductor device, the small size of the terminal structure of the semiconductor device 10 can reserve more space for the active region of the chip, and reduce the proportion of the terminal structure of the semiconductor device 10 in the chip area.

[0076] In addition, by adding the first well region 31, the first well region 31 can offset a part of the electric field of the epitaxial layer 2, so as to reduce the influence of the epitaxial layer 2 doping on the charge balance of the charge compensation region, and further improve the withstand voltage of the terminal structure 10 of the semiconductor device.

[0077] In some embodiments, the plurality of first-conductivity-type doped regions 32 are each a ring-shaped doped region surrounding the whole source region. Specifically, as shown in FIG. 3, which is a top view of a semiconductor device according to an embodiment of the present application, when the first-conductivity-type doped regions 32 are prepared, openings are formed on the first well region 31 and the first-conductivity-type impurities are implanted, the implantation openings of the plurality of first-conductivity-type doped regions 32 of the terminal structure 10 of the semiconductor device can be set as strips, and each strip surrounds the active region 20 to finally form a plurality of ring-shaped structures.

[0078] Alternatively, in other embodiments, as shown in FIG. 4, which is a top view of a semiconductor device according to another embodiment of the present application, each first-conductivity-type doped region 32 surrounds the active region, and each first-conductivity-type doped region 32 includes a plurality of first-conductivity-type sub-doped regions arranged at intervals.

[0079] It can be understood that, when the first-conductivity-type doped regions 32 are prepared, openings are formed on the first well region 31 and the first-conductivity-type impurities are implanted, the implantation openings of the plurality of first-conductivity-type doped regions 32 of the terminal structure 10 of the semiconductor device can be set as squares, and only a part of the first-conductivity-type doped regions 32 are shown in FIG. 4. The plurality of square first-conductivity-type doped regions 32 are arranged around the active region 20, and the plurality of square first-conductivity-type doped regions 32 finally form a plurality of ring-shaped structures.

[0080] It can be understood that the second conductivity type can be P type, and the first conductivity type can be N type, and the plurality of first conductivity type doped regions 32 are arranged in the first well region 31, which is equivalent to that the plurality of first conductivity type doped regions 32 and the first well region 31 form the different conductivity type columns with different doping concentrations arranged alternately. As shown in FIG. 5, it is a schematic diagram of surface electric field distribution of the terminal structure extracted by simulation according to an embodiment of the present application and a classic field ring field plate terminal structure. In the diagram, curve A is an electric field distribution curve of the terminal structure 10 of the semiconductor device extracted by simulation according to an embodiment of the present application, and curve B is an electric field distribution curve of a classic field ring field plate terminal structure 0. As can be seen from the diagram, the terminal structure 10 of the semiconductor device according to the embodiment of the present application can significantly improve the surface electric field distribution. By introducing the different conductivity type columns with low doping concentration arranged alternately, i.e., preparing the P columns and N columns arranged alternately, and by using the charge compensation principle, in the blocking state, the different conductivity type columns can be well depleted, the electric field distribution is changed from the triangular distribution in the traditional device structure to the rectangular distribution, the surface doping and the surface electric field distribution are improved, the electric field peak value and the leakage current are reduced, the terminal efficiency is improved, the size of the terminal structure 10 of the semiconductor device is reduced, and a higher withstand voltage is obtained in the same size of the terminal structure 10 of the semiconductor device.

[0081] In some embodiments of the present application, in combination with FIGS. 2-4, in the second direction, the distance between adjacent doped regions 32 in the plurality of first conductivity type doped regions 32 can be equal; or in the second direction, the distance between adjacent doped regions 32 in the plurality of first conductivity type doped regions 32 can gradually increase in the direction away from the active region; or in the second direction, the distance between adjacent doped regions 32 in the plurality of first conductivity type doped regions 32 can gradually decrease in the direction away from the active region.

[0082] In some embodiments of the present application, by reasonably setting the distance between adjacent doped regions 32, the P columns and N columns arranged alternately are reasonably arranged, and then the electric field distribution and depletion condition in the terminal structure 10 of the semiconductor device are planned, so as to improve the electric field distribution and reduce the electric field peak.

[0083] In some embodiments of the present application, as shown in FIG. 2, the field limiting ring structure 3 further includes a second well region 33 of the second conductivity type, the second well region 33 is located in the epitaxial layer 2 in the first direction, the second well region 33 is located on the side of the first well region 31 close to the active region, and the second well region 33 is connected with the first well region 31. The second well region 33 functions as a main junction, and the size of the second well region 33 can be selected according to actual design needs, which is not limited specifically herein. The second well region 33 provides a current leading-out position and a power MOSFET gate placement position for the terminal.

[0084] In some embodiments, the field-limiting ring structure 3 further comprises a cutoff ring region 34 located at an end of the epitaxial layer 2 away from the active region in the second direction and spaced apart from the first well region 31. The first well region 31, the second well region 33, the plurality of doped regions 32, and the cutoff ring region 34 each extend into the epitaxial layer 2 from a surface thereof away from the substrate 1 in a direction towards the substrate 1.

[0085] In some embodiments, as shown in FIG. 2, the termination structure 10 of the semiconductor device further comprises an oxide layer 35, a gate 36, and a plurality of polysilicon field plates 37. The oxide layer 35 is located on a side of the first well region 31, the second well region 33, the plurality of doped regions 32, and the cutoff ring region 34 away from the substrate 1 in the first direction and covers a portion of the first well region 31, the second well region 33, the plurality of doped regions 32, and the cutoff ring region 34. Specifically, the oxide layer 35 comprises a first oxide layer 351 and a second oxide layer 352. The first oxide layer 351 is located on a side of the first well region 31, the plurality of doped regions 32, and the cutoff ring region 34 away from the substrate 1 in the first direction and continuously extends in the second direction. The first oxide layer 351 is a field oxide layer. The first oxide layer 351 is provided with the second gate portion 362 and the plurality of polysilicon field plates 37 on a side thereof away from the substrate 1 in the first direction. The first oxide layer 351 covers a portion of the first well region 31, the plurality of doped regions 32, and the cutoff ring region 34.

[0086] The second oxide layer 352 is a gate oxide layer. The second oxide layer 352 is located on a side of the second well region 33 away from the substrate 1 in the first direction and between the second well region 33 and the first gate portion 361. The second oxide layer 352 is connected to the first oxide layer 351. The thickness of the first oxide layer 351 is greater than the thickness of the second oxide layer 352. It can be understood that, since the first oxide layer 351 is a field oxide layer, a thicker field oxide layer can withstand a higher breakdown voltage. Since the second oxide layer 352 is a gate oxide layer, a thicker gate oxide layer can result in a threshold voltage that is too large, and even can cause the semiconductor device to be unable to turn on.

[0087] The gate 36 comprises the first gate portion 361 and the second gate portion 362 connected to each other. The first gate portion 361 is located on a side of the oxide layer 35 away from the substrate 1 in the first direction. The plurality of polysilicon field plates 37 are located on a side of the oxide layer 35 away from the substrate 1 in the first direction. The plurality of polysilicon field plates 37 are spaced apart from the second gate 36 in the second direction and spaced apart from each other. The plurality of polysilicon field plates 37 are made of the same material as the gate 36.

[0088] As shown in FIG. 2, the termination structure 10 of the semiconductor device further comprises a protective layer located on a side of the field-limiting ring structure 3 away from the substrate 1 in the first direction. Specifically, the protective layer comprises a third oxide layer 41 and an active region metal 42. The protective layer is not shown in FIG. 2.

[0089] The third oxide layer 41 is located on the side of the second well region 33, the gate 36, the first oxide layer 351, the plurality of polycrystalline field plates 37 and the part of the stop ring region 34 away from the substrate 1 in the first direction and continuously extends along the second direction, for covering a part of the second well region 33, the gate 36, the first oxide layer 351, the plurality of polycrystalline field plates 37 and a part of the stop ring region 34. The active region metal 42 includes a first active region metal part 421 and a second active region metal part 422, the first active region metal part 421 and the second active region metal part 422 are connected, the first active region metal part 421 is located on the side of the second well region 33 away from the substrate 1 in the first direction, and the second active region metal part 422 is located on the side of the third oxide layer 41 away from the substrate 1 in the first direction. The second active region metal part 422 functions as a metal field plate, and the electric field at the main junction, i.e. the second well region 33, can be reduced by setting the metal field plate.

[0090] As shown in FIG. 2, the termination structure 10 of the semiconductor device further includes a stop ring metal 43, the stop ring metal 43 includes a first stop ring metal part 431 and a second stop ring metal part 432, the first stop ring metal part 431 and the second stop ring metal part 432 are connected, the first stop ring metal part 431 is located on the side of the third oxide layer 41 away from the substrate 1 in the first direction, the first stop ring metal part 431 is spaced apart from the second active region metal part 422 in the second direction, the second stop ring metal part 432 is located on the side of the stop ring region 34 away from the substrate 1 in the first direction, and the side of the second stop ring metal part 432 away from the active region 20 is flush with the side of the stop ring region 34 away from the active region 20.

[0091] An embodiment of the present application also provides a semiconductor device, as shown in FIG. 6, which is a block diagram of a semiconductor device according to an embodiment of the present application. The semiconductor device 100 includes an active region 20 and a termination structure 10 of the semiconductor device according to the above embodiment, and the termination structure 10 of the semiconductor device is arranged around the active region 20. Specifically, the semiconductor device 100 of the embodiment of the present application can be understood with reference to FIGS. 3 and 4, which will not be described here again.

[0092] According to the semiconductor device 100 of the embodiment of the present application, by adopting the terminal structure 10 of the semiconductor device of the above embodiment, the surface doping and the surface electric field distribution can be improved, the electric field peak and the leakage current can be reduced, and the efficiency of the semiconductor device 100 can be improved. The size of the terminal structure 10 of the semiconductor device formed above is relatively small as a whole, so that a higher withstand voltage can be obtained in the same size of the terminal structure 10 of the semiconductor device, and for the same semiconductor device 100, the terminal structure 10 of the semiconductor device with a small size can reserve more space for the active region 20 of the chip, and the proportion of the chip area occupied by the terminal structure 10 of the semiconductor device can be reduced.

[0093] The embodiment of the present application also proposes a power module, as shown in FIG. 7, which is a block diagram of the power module according to an embodiment of the present application, wherein the power module 200 includes the semiconductor device 100 according to the above embodiment.

[0094] The power module 200 according to the embodiment of the present application includes the semiconductor device 100 of the above embodiment, by improving the structure of the semiconductor device 100, the efficiency and the withstand voltage of the semiconductor device 100 can be improved, and the efficiency and the withstand voltage of the power module 200 can be improved.

[0095] The embodiment of the present application also proposes an electric power electronic device, as shown in FIG. 8, which is a block diagram of the electric power electronic device according to an embodiment of the present application, wherein the electric power electronic device 2000 includes the power module 200 according to the above embodiment.

[0096] The electric power electronic device 2000 according to the embodiment of the present application adopts the power module 200 of the above embodiment, by improving the efficiency of the semiconductor device 100, the efficiency and the withstand voltage of the power module 200 can be improved, and the efficiency and the performance of the electric power electronic device 2000 can be effectively improved.

[0097] The embodiment of the present application also proposes a vehicle, as shown in FIG. 9, which is a block diagram of the vehicle according to an embodiment of the present application, wherein the vehicle 1000 includes the semiconductor device 100 according to the above embodiment.

[0098] The vehicle 1000 according to the embodiment of the present application adopts the semiconductor device 100 of the above embodiment, by improving the efficiency of the semiconductor device 100, the performance of the vehicle and the withstand voltage of the circuit structure in the vehicle can be improved, and the safety of the vehicle 1000 can be improved.

[0099] In some embodiments of the present application, a method for manufacturing a termination structure of a semiconductor device is also provided. The manufacturing process of the termination structure of the semiconductor device according to the embodiments of the present application can be understood in combination with FIG. 10. FIG. 10 is a schematic diagram of the manufacturing process of the termination structure of the semiconductor device according to an embodiment of the present application.

[0100] First, an epitaxial layer 2 of a first conductivity type is formed on a substrate 1 of the first conductivity type, and the epitaxial layer 2 is located on the substrate 1 in a first direction.

[0101] Specifically, the substrate 1 of the first conductivity type, which is P-type, can be provided first. The structure and manufacturing method according to the embodiments of the present application are applicable to materials such as Si and SiC that can be used to manufacture power devices. Single crystal silicon can be selected as the substrate 1, and a (100) / (001) surface can be selected for subsequent processes. The substrate 1 is subjected to surface cleaning to remove impurity particles, and an epitaxial layer 2 of the first conductivity type is grown to a certain thickness. The thickness of the epitaxial layer 2 is 80-120 μm, and the dose is 1e13-1e14 / cm3, which is determined according to the voltage withstand requirement.

[0102] Then, a field limiting ring structure 3 surrounding an active region is formed in a region of the epitaxial layer 2 away from the substrate 1.

[0103] This step specifically includes: forming a first well region 31 of a second conductivity type in a region of the epitaxial layer 2 away from the substrate 1; and forming a plurality of doped regions 32 of the first conductivity type spaced apart in a second direction perpendicular to the first direction within the first well region 31.

[0104] As shown in FIG. 10, the second conductivity type is N-type. The first well region 31 can be formed in the epitaxial layer 2 by ion implantation. The first well region 31 of the second conductivity type is formed in a region of the epitaxial layer 2 away from the substrate 1, including: performing ion implantation of the second conductivity type on the surface of the epitaxial layer 2 away from the substrate 1 in the first direction and performing high-temperature annealing to form the first well region 31 of the second conductivity type. Specifically, the termination is subjected to ion implantation of the second conductivity type to form a well structure of a different conductivity type from the epitaxial layer 2, i.e., the first well region 31. The implantation dose is 1e12-4e12, and high-temperature annealing at 115°C / 180 min is performed.

[0105] Further, as shown in Fig. 11, a schematic diagram of a preparation process of a termination structure of a semiconductor device according to another embodiment of the present application is shown. The first conductive type doped regions 32 spaced along the second direction perpendicular to the first direction are formed in the first well region 31, including: performing ion implantation of the first conductive type in the plurality of spaced apart implantation regions in the first well region 31, and performing high temperature annealing to form the plurality of first conductive type doped regions 32. Further, ion implantation is performed at the end of the epitaxial layer 2 away from the active region in the second direction to form the termination ring region 34.

[0106] Specifically, as shown in Fig. 11, the resist layer is deposited on the surface of the epitaxial layer 2 and etched, and the resist layer can be photoresist. The first well region 31 surface resist layer forms implantation windows with gradually decreasing spacing from the active region 20 to the field limiting ring structure 3, or forms implantation windows with equal spacing, or forms implantation windows with gradually increasing spacing from the active region 20 to the field limiting ring structure 3, and performs ion implantation of the first conductive type to form the first conductive type region in the first well region 31, and performs annealing to form the plurality of first conductive type doped regions 32 and the termination ring region 34. The implantation dose is 9e12-3e13, and the high temperature annealing is performed at 105-115°C for 180-360min, and the annealing temperature can be selected as 115°C.

[0107] Further, in some embodiments, the spacing between the two adjacent doped regions 32 satisfies formula (1-1), where Na is the doping concentration of the doped region 32; W a W is the width of the doped region 32, Nd is the doping concentration of the first well region 31, W d W is the distance between the two adjacent doped regions 32, i is the i-th doped region 32, and n is the total number of doped regions 32, n.

[0108] According to the method for manufacturing a termination structure of a semiconductor device according to the embodiments of the present application, by combining the first well region of the second conductive type and the plurality of first conductive type doped regions in the field limiting ring structure, a column of different conductive type with different doping concentrations is introduced, and the different conductive type columns can be well depleted by using the charge compensation principle, so as to improve the surface doping and surface electric field distribution, reduce the electric field peak and leakage, improve the efficiency of the termination structure, and effectively reduce the size of the termination structure, so that a higher withstand voltage is obtained under the same termination structure size, and for the same semiconductor device, the small size termination structure can reserve more space for the active region of the chip, and reduce the proportion of the chip area occupied by the termination structure.

[0109] In addition, by arranging the first well region in the epitaxial layer in the field limiting ring structure, the first well region can offset a part of the electric field of the epitaxial layer, so as to reduce the influence of the epitaxial layer doping on the charge balance of the charge compensation region, and further improve the withstand voltage of the terminal structure.

[0110] In some embodiments of the present application, as shown in FIG. 12, a schematic diagram of a preparation process of a terminal structure of a semiconductor device according to yet another embodiment of the present application is shown. In the terminal structure, the field limiting ring structure 3 surrounding the active region is formed in the region of the epitaxial layer 2 away from the substrate 1, and further comprising: forming an oxide layer 35 on the side of the first well region 31, the plurality of doped regions 32 and the cutoff ring region 34 away from the substrate 1, the oxide layer 35 covering the first well region 31, a part of the epitaxial layer 2, the plurality of doped regions 32 and a part of the cutoff ring region 34.

[0111] Specifically, forming the oxide layer 35 on the side of the first well region 31, the plurality of doped regions 32 and the cutoff ring region 34 away from the substrate 1 includes: forming a first oxide layer 351 continuously extending along the second direction on the side of the plurality of doped regions 32 and the cutoff ring region 34 away from the substrate 1. The first oxide layer 351 covers the first well region 31, the plurality of doped regions 32 and a part of the cutoff ring region 34. And forming a second oxide layer 352 on the side of the epitaxial layer 2 close to the active region 20 and away from the substrate 1, and the second oxide layer 352 is connected with the first oxide layer 351. Wherein, the thickness of the second oxide layer 352 is less than the thickness of the first oxide layer 351.

[0112] Further, forming a gate 36 on the side of the oxide layer 35 away from the substrate 1; and forming a plurality of polycrystalline field plates 37 on the side of the oxide layer 35 away from the substrate 1, the plurality of polycrystalline field plates 37 are arranged in the second direction and spaced apart from each other. Forming the gate 36 on the side of the oxide layer 35 away from the substrate 1 includes: forming a first gate part 361 on the side of the second oxide layer 352 away from the substrate 1; and forming a second gate part 362 on the side of the first oxide layer 351 away from the substrate 1. Forming the plurality of polycrystalline field plates 37 on the side of the first oxide layer 351 away from the substrate 1.

[0113] Specifically, depositing and etching polycrystalline silicon on the upper surface of the oxide layer 35 to form the gate 36 and the plurality of polycrystalline field plates 37, the positions of the plurality of polycrystalline field plates 37 are on both sides of the left boundary of the plurality of doped regions 32.

[0114] In some embodiments, the field limiting ring structure 3 surrounding the active region is formed in the region of the epitaxial layer 2 away from the substrate 1, and the method further comprises forming a second well region 33 of the second conductivity type by ion implantation of the second conductivity type on the surface of the epitaxial layer 2 away from the substrate 1 and on the surface of the second oxide layer 352 close to the substrate 1, on the side of the first well region 31 close to the active region. Specifically, the ion implantation of the second conductivity type is performed to form the well structure of the different conductivity type, i.e., the second well region 33, in the termination structure 10 of the semiconductor device, with an injection dose of 1e13-1e14, and high-temperature annealing is performed at 115°C / 105min.

[0115] In some embodiments of the present application, the preparation process of the third oxide layer 41, the active region metal 42, and the cutoff ring metal 43 in the embodiments of the present application can be understood in combination with FIG. 2.

[0116] Specifically, the method for manufacturing the termination structure of the semiconductor device further comprises forming a third oxide layer 41 extending continuously in the second direction on the side of the second well region 33, the gate 36, the oxide layer 35, the plurality of polycrystalline field plates 37, and the cutoff ring region 34 away from the substrate 1, the third oxide layer 41 being used to cover a part of the second well region 33, the gate 36, the oxide layer 35, the plurality of polycrystalline field plates 37, and a part of the cutoff ring region 34; and forming a first active region metal part 421 on the side of the second well region 33 away from the substrate 1 and a second active region metal part 422 on the side of the third oxide layer 41 away from the substrate 1, the first active region metal part 421 and the second active region metal part 422 being connected.

[0117] Further, the method for manufacturing the termination structure of the semiconductor device further comprises forming a cutoff ring metal 43 on the side of the third oxide layer 41 away from the substrate 1 and on the side of the cutoff ring region 34 away from the substrate 1, to finally form the termination structure 10 of the semiconductor device as shown in FIG. 2.

[0118] Based on the above, according to the method for manufacturing the termination structure of the semiconductor device according to the embodiments of the present application, the prepared termination structure 10 of the semiconductor device utilizes the charge compensation principle, the first well region 31 and the doped region 32 form the alternating P column and N column, in the blocking state, the charges of the P column and the N column are consumed by each other, and the electric field distribution changes from the triangular distribution in the traditional device structure to the rectangular distribution, thereby effectively improving the electric field distribution and reducing the electric field peak. In addition, by increasing the first well region 31, the influence of the doping of the epitaxial layer 2 on the charge balance of the charge compensation region is reduced, further improving the withstand voltage of the termination structure 10 of the semiconductor device, and reducing the proportion of the chip area occupied by the termination structure 10 of the semiconductor device while improving the withstand voltage of the termination structure 10 of the semiconductor device.

[0119] Other configurations and operations of the vehicle 1000, the semiconductor device 100, and the terminal structure 10 of the semiconductor device according to the embodiments of the present application are known to those skilled in the art, and thus will not be described in detail herein.

[0120] In the description of the present specification, the description referring to the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the exemplary description of the above terms does not necessarily mean the same embodiment or example.

[0121] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions, and alterations can be made hereto without departing from the principles and spirit of the application, and the scope of the present application is defined by the claims and their equivalents.

Claims

1. A termination structure for a semiconductor device, wherein, Comprising: a substrate (1) of a first conductivity type; an epitaxial layer (2) of the first conductivity type, the epitaxial layer (2) being located on the substrate (1) in a first direction; and a field-limiting ring structure (3) located in the epitaxial layer (2) in the first direction, the field-limiting ring structure (3) being arranged to surround an active region (20), the field-limiting ring structure (3) comprising a first well region (31) of a second conductivity type, a plurality of doped regions (32) of the first conductivity type being provided within the first well region (31), the plurality of doped regions (32) of the first conductivity type being spaced apart in a second direction perpendicular to the first direction.

2. The termination structure of a semiconductor device according to claim 1, wherein the plurality of doped regions (32) of the first conductivity type are each annular doped regions surrounding the entire active region (20).

3. The termination structure for a semiconductor device according to claim 1, wherein each of the doped regions (32) of the first conductivity type is arranged to surround the active region (20), and each of the doped regions (32) of the first conductivity type comprises a plurality of sub-doped regions of the first conductivity type arranged to be spaced apart from each other.

4. The termination structure for a semiconductor device according to claim 3, wherein the sub-doped regions of the first conductivity type are cylindrical sub-doped regions of the first conductivity type.

5. The termination structure of a semiconductor device according to any one of claims 1-4, wherein in the second direction, distances between adjacent ones of the plurality of doped regions (32) of the first conductivity type are equal; or in the second direction, distances between adjacent ones of the plurality of doped regions (32) of the first conductivity type gradually increase in a direction away from the active region (20); or in the second direction, distances between adjacent ones of the plurality of doped regions (32) of the first conductivity type gradually decrease in a direction away from the active region (20).

6. The termination structure for a semiconductor device according to any one of claims 1 to 5, wherein the field-limiting ring structure (3) further comprises: a second well region (33) of the second conductivity type, the second well region (33) being located in the epitaxial layer (2) in the first direction, the second well region (33) being located on a side of the first well region (31) proximate to the active region (20), the second well region (33) being connected with the first well region (31).

7. The termination structure for a semiconductor device according to claim 6, wherein the field-limiting ring structure (3) further comprises: a cutoff ring region (34) located at an end of the epitaxial layer (2) in the second direction away from the active region (20) and spaced apart from the first well region (31).

8. The termination structure for a semiconductor device according to claim 7, wherein the first well region (31), the second well region (33), each of the doped regions (32), and the cutoff ring region (34) each extend into the epitaxial layer (2) in a direction proximate to the substrate (1) from a surface thereof distal to the substrate (1).

9. The termination structure for a semiconductor device according to claim 7 or 8, wherein, Further comprising: An oxide layer (35) is located on a side of the first well region (31), the second well region (33), the plurality of doped regions (32) and the cutoff ring region (34) away from the substrate (1) in the first direction and covers the first well region (31), a part of the second well region (33), the plurality of doped regions (32) and a part of the cutoff ring region (34).

10. The termination structure for a semiconductor device according to claim 9, wherein, Further comprising: A gate (36) comprising a first gate part (361) and a second gate part (362) connected to each other, the first gate part (361) being located on a side of the oxide layer (35) away from the substrate (1) in the first direction.

11. The termination structure for a semiconductor device according to claim 10, wherein, Further comprising: A plurality of polycrystalline field plates (37) located on a side of the oxide layer (35) away from the substrate (1) in the first direction, the plurality of polycrystalline field plates (37) being spaced apart from the second gate part (362) and each other in the second direction.

12. The termination structure for a semiconductor device according to claim 11, wherein, The oxide layer (35) comprises: A first oxide layer (351) located on a side of the first well region (31), the plurality of doped regions (32) and the cutoff ring region (34) away from the substrate (1) in the first direction and continuously extending along the second direction, a side of the first oxide layer (351) away from the substrate (1) in the first direction being provided with the second gate part (362) and the plurality of polycrystalline field plates (37), the first oxide layer (351) covering the first well region (31), the plurality of doped regions (32) and the part of the cutoff ring region (34).

13. The termination structure for a semiconductor device according to claim 12, wherein, The oxide layer (35) further comprises: A second oxide layer (352) connected to the first oxide layer (351), the second oxide layer (352) being located on a side of the second well region (33) away from the substrate (1) in the first direction and between the second well region (33) and the first gate part (361); Wherein, a thickness of the first oxide layer (351) is greater than a thickness of the second oxide layer (352).

14. The termination structure for a semiconductor device according to claim 12, wherein, Further comprising: A protective layer located on a side of the field limiting ring structure (3) away from the substrate (1) in the first direction.

15. The termination structure for a semiconductor device according to claim 14, wherein, The protective layer comprises: A third oxide layer (41) located on a side of the second well region (33), the gate (36), the first oxide layer (351), the plurality of polycrystalline field plates (37) and the cutoff ring region (34) away from the substrate (1) in the first direction and continuously extending along the second direction, for covering a part of the second well region (33), the gate (36), the first oxide layer (351), the plurality of polycrystalline field plates (37) and a part of the cutoff ring region (34).

16. The termination structure for a semiconductor device according to claim 15, wherein, The protective layer further comprises: An active region metal (42) comprising a first active region metal portion (421) and a second active region metal portion (422), the first active region metal portion (421) and the second active region metal portion (422) being connected, the first active region metal portion (421) being located on a side of the second well region (33) in the first direction away from the substrate (1), the second active region metal portion (422) being located on a side of the third oxide layer (41) in the first direction away from the substrate (1).

17. The termination structure for a semiconductor device according to claim 16, wherein, Further comprising: A termination ring metal (43) comprising a first termination ring metal portion (431) and a second termination ring metal portion (432), the first termination ring metal portion (431) and the second termination ring metal portion (432) being connected, the first termination ring metal portion (431) being located on a side of the third oxide layer (41) in the first direction away from the substrate (1), the first termination ring metal portion (431) being spaced apart from the second active region metal portion (422) in the second direction, the second termination ring metal portion (432) being located on a side of the termination ring region (34) in the first direction away from the substrate (1), a side of the second termination ring metal portion (432) away from the active region (20) being flush with a side of the termination ring region (34) away from the active region (20).

18. A semiconductor device, wherein, Comprising: An active region (20); and The termination structure (10) of the semiconductor device according to any one of claims 1-17, the termination structure (10) of the semiconductor device being arranged around the active region (20).

19. A power module, wherein, Comprising the semiconductor device (100) according to claim 18.

20. A power electronic device, wherein, Comprising the power module (200) according to claim 19.

21. A vehicle, wherein, Comprising the semiconductor device (100) according to claim 18.

22. A method for fabricating a termination structure for a semiconductor device, wherein, Comprising: forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, the epitaxial layer being located on the substrate in a first direction; forming a field-limiting ring structure around an active region in a region of the epitaxial layer away from the substrate, comprising: forming a first well region of a second conductivity type in the region of the epitaxial layer away from the substrate; and forming a plurality of doped regions of the first conductivity type spaced apart in a second direction perpendicular to the first direction within the first well region.

23. The method for manufacturing a termination structure of a semiconductor device according to claim 22, wherein, forming a first well region of a second conductivity type in a region of the epitaxial layer away from the substrate, comprising: performing ion implantation of the second conductivity type on a surface of the epitaxial layer in the first direction away from the substrate and performing high-temperature annealing to form the first well region of the second conductivity type.

24. The method for manufacturing a termination structure of a semiconductor device according to claim 22 or 23, wherein, forming a plurality of doped regions of the first conductivity type spaced apart in the second direction perpendicular to the first direction within the first well region, comprising: performing ion implantation of the first conductivity type in a plurality of spaced-apart implantation regions within the first well region and performing high-temperature annealing to form the plurality of doped regions of the first conductivity type.

25. The method for manufacturing a termination structure of a semiconductor device according to any one of claims 22 to 24, wherein, The interval between two adjacent doping regions satisfies: Wherein, Na is the doping concentration of the doping region; Wa is the width of the doping region; Nd is the doping concentration of the first well region; Wd is the distance between two adjacent doping regions; i is the ith doping region; n is the total number of the doping regions.

26. The method for manufacturing a termination structure of a semiconductor device according to any one of Claims 22-25, wherein, Forming a field limiting ring structure surrounding the active region in the region of the epitaxial layer away from the substrate, further comprising: Ion implantation is performed on the end of the epitaxial layer away from the active region in the second direction to form a cutoff ring region.

27. The method for manufacturing a termination structure of a semiconductor device according to claim 26, wherein, Forming a field limiting ring structure surrounding the active region in the region of the epitaxial layer away from the substrate, further comprising: Forming an oxide layer on the side of the first well region, the plurality of doping regions and the cutoff ring region away from the substrate, the oxide layer covering the first well region, a part of the epitaxial layer, the plurality of doping regions and a part of the cutoff ring region; Forming a gate on the side of the oxide layer away from the substrate; and Forming a plurality of polycrystalline field plates on the side of the oxide layer away from the substrate, the plurality of polycrystalline field plates being spaced apart from the gate in the second direction and spaced apart from each other.

28. The method for manufacturing a termination structure of a semiconductor device according to claim 27, wherein, Forming an oxide layer on the side of the first well region, the plurality of doping regions and the cutoff ring region away from the substrate, comprising: Forming a first oxide layer continuously extending in the second direction on the side of the plurality of doping regions and the cutoff ring region; and Forming a second oxide layer on the side of the epitaxial layer close to the active region and away from the substrate, the second oxide layer being connected with the first oxide layer.

29. The method for manufacturing a termination structure of a semiconductor device according to claim 28, wherein, Forming a gate on the side of the oxide layer away from the substrate, comprising: Forming a first gate part on the side of the second oxide layer away from the substrate; and Forming a second gate part on the side of the first oxide layer away from the substrate, the first oxide layer covering the first well region, the plurality of doping regions and the part of the cutoff ring region, wherein the thickness of the first oxide layer is greater than the thickness of the second oxide layer.

30. The method for manufacturing a termination structure of a semiconductor device according to Claim 29, wherein, Forming a field limiting ring structure surrounding the active region in the region of the epitaxial layer away from the substrate, further comprising: Forming a plurality of polycrystalline field plates on the side of the first oxide layer away from the substrate.

31. The method for manufacturing a termination structure of a semiconductor device according to claim 30, wherein, Forming a field limiting ring structure surrounding the active region in the region of the epitaxial layer away from the substrate, further comprising: Performing ion implantation of the second conductive type on the surface of the second oxide layer close to the substrate, the surface of the epitaxial layer away from the substrate and the side of the first well region close to the active region to form a second well region of the second conductive type, the second well region being connected with the first well region.

32. The method for manufacturing a termination structure of a semiconductor device according to claim 31, wherein, Further comprising: Forming a third oxide layer continuously extending in the second direction on the side of the second well region, the gate, the oxide layer, the plurality of polycrystalline field plates and the cutoff ring region away from the substrate, the third oxide layer being used to cover a part of the second well region, the gate, the oxide layer, the plurality of polycrystalline field plates and a part of the cutoff ring region; and Further comprising: A first active region metal part is formed on a side of the second well region away from the substrate, and a second active region metal part is formed on a side of the third oxide layer away from the substrate, the first active region metal part and the second active region metal part being connected.

33. The method for manufacturing a termination structure of a semiconductor device according to claim 32, wherein, Also included are: A cutoff ring metal is formed on a side of the third oxide layer away from the substrate and on a side of the cutoff ring region away from the substrate.

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