Display substrate and driving method therefor, and display device

Abstract

A display substrate (1100) and a driving method therefor, and a display device (1000). The display substrate (1100) comprises a plurality of input signal lines (41), a plurality of columns of pixel circuits (100), a plurality of first signal line groups (10), a plurality of first multiplexing circuits, and a plurality of second multiplexing circuits. Each first signal line group (10) comprises at least two first signal lines (11), wherein one first signal line (11) is electrically connected to one column of pixel circuits (100). Each first multiplexing circuit is electrically connected to one input signal line (41) and all first signal lines (11) in one first signal line group (10). Each second multiplexing circuit is electrically connected to one input signal line (41) and all first signal lines (11) in one first signal line group (10). One input signal line (41) is electrically connected to one first multiplexing circuit and one second multiplexing circuit, respectively, and at least two first signal lines (11) in one first signal line group (10) are electrically connected to one first multiplexing circuit and one second multiplexing circuit, respectively.

Description

Display substrate, driving method thereof and display device

[0001] This application claims priority to Chinese Patent Application No. 202410834046.7, filed on June 25, 2024, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display substrate, a driving method thereof and a display device. BACKGROUND

[0003] Touch and Display Driver Integration (TDDI) display products are one of the current mainstream screen display technologies. TDDI products are widely used in various display products due to their more sensitive touch technology, lighter and thinner appearance, and lower cost advantage. SUMMARY

[0004] In one aspect, a display substrate is provided. The display substrate includes a plurality of input signal lines, a plurality of pixel circuits, and a plurality of first signal line groups. One of the first signal line groups includes at least two first signal lines, and one of the first signal lines is electrically connected to one of the pixel circuits. The display substrate further includes a plurality of first multiplexing circuits and a plurality of second multiplexing circuits. One of the first multiplexing circuits is electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, and the first multiplexing circuit controls electrical connection between the input signal line and one of the first signal lines in the same time period. One of the second multiplexing circuits is electrically connected to one of the input signal lines and the at least two first signal lines of one of the first signal line groups, and the second multiplexing circuit controls electrical connection between the input signal line and at least one of the first signal lines in the same time period. One of the input signal lines is electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits, and the at least two first signal lines of one of the first signal line groups are electrically connected to one of the first multiplexing circuits and one of the second multiplexing circuits.

[0005] In some embodiments, the first signal line group includes M first signal lines, the first multiplexing circuit and the second multiplexing circuit are electrically connected with the M first signal lines, and M is greater than or equal to 2. The display substrate further includes N second signal line groups. The second signal line group includes M second signal lines, the M second signal lines of the second signal line group are electrically connected with one of the first multiplexing circuits, and one of the second signal lines controls electrical connection between one of the first signal lines and the input signal line; and N is greater than or equal to 2. The plurality of first multiplexing circuits are alternately connected with the N second signal line groups.

[0006] In some embodiments, the display substrate further includes P third signal line groups. The third signal line group includes M third signal lines, the M third signal lines of the third signal line group are electrically connected with one of the second multiplexing circuits, and one of the third signal lines controls electrical connection between the input signal line and one of the first signal lines; and P is greater than or equal to 1.

[0007] In some embodiments, the number of the second signal line groups is the same as the number of the third signal line groups, and the plurality of second multiplexing circuits are alternately electrically connected with the P third signal line groups.

[0008] In some embodiments, the display substrate includes one of the third signal line groups, and the plurality of second multiplexing circuits are electrically connected with the third signal line group.

[0009] In some embodiments, the display substrate further includes one third signal line. The third signal line is electrically connected with the second multiplexing circuit, and the third signal line controls electrical connection between the input signal line and the M first signal lines electrically connected with the same second multiplexing circuit in the same time period.

[0010] In some embodiments, the first multiplexing circuit and the second multiplexing circuit each include a plurality of first thin film transistors. One of the source and the drain of the first thin film transistor is electrically connected with the input signal line, and the other is electrically connected with the first signal line; and the width-length ratio of at least one of the first thin film transistors is greater than or equal to 200 μm / 3.5 μm.

[0011] In some embodiments, the first multiplexing circuit and the second multiplexing circuit each include a plurality of first thin film transistors. One of the source and the drain of the first thin film transistor is electrically connected with the input signal line, and the other is electrically connected with the first signal line; and the width-length ratio of at least one of the first thin film transistors is greater than or equal to 200 μm / 3.5 μm.

[0012] In some embodiments, the first thin film transistors are arranged in multiple rows along a first direction, at least two adjacent rows of the first thin film transistors partially overlap in the first direction, and adjacent two first thin film transistors belonging to the adjacent two rows are arranged staggered in a second direction. The first direction is the arrangement direction of a column of the pixel circuits, and the second direction is the arrangement direction of multiple columns of the pixel circuits.

[0013] In some embodiments, the display substrate includes multiple gate lines. The gate line includes a main body portion and a gate portion alternately connected along the second direction. Along the first direction, the gate portion is flush with one end of the main body portion, and the other end of the gate portion protrudes from the edge of the main body portion. One of the gate lines is connected with one row of the first thin film transistors, and one of the gate portions forms a gate of one of the first thin film transistors. The gate portions of adjacent two gate lines protrude from the two sides of the main body portion opposite to the first direction; the multiple gate lines are divided into multiple pairs, one pair including two adjacent gate lines, and the gate portions of the two gate lines of one pair protrude in a direction close to each other. Two rows of the first thin film transistors connected with the two gate lines of one pair partially overlap in the first direction, and two rows of the first thin film transistors connected with adjacent two gate lines of adjacent two pairs do not overlap in the first direction.

[0014] In some embodiments, the first multiplexing circuit includes two of the first thin film transistors; and / or, the second multiplexing circuit includes two of the first thin film transistors.

[0015] In some embodiments, the input signal line is configured to be electrically connected with a driving chip. And / or, at least one of the pixel circuit, the first multiplexing circuit and the second multiplexing circuit includes an oxide thin film transistor.

[0016] In another aspect, a driving method of a display substrate is provided for driving the display substrate in any of the above embodiments. The driving method includes: in the screen-on display mode, the first multiplexing circuit controls the electrical connection between the input signal line and one of the first signal lines in the same period. In the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection between the input signal line and at least one of the first signal lines in the same period.

[0017] In some embodiments, the first signal line group includes M first signal lines, the second multiplexing circuit is electrically connected with the M first signal lines, and M≥2. The display substrate further includes P third signal line groups, each of which includes M third signal lines. The second multiplexing circuit is electrically connected with the M third signal lines of the third signal line group, and P≥1. The driving method includes: in the screen-off wake-up mode, the second multiplexing circuit controls electrical connection between the input signal line and one first signal line in the same time period.

[0018] In some embodiments, the driving method further includes: in the screen-on display mode, the first multiplexing circuit and the second multiplexing circuit alternately control electrical connection between the input signal line and one first signal line in different display frames.

[0019] In some embodiments, the driving method further includes: in the screen-off wake-up mode, the first multiplexing circuit and the second multiplexing circuit both control electrical connection between the same input signal line and the same first signal line in the same time period, and the first multiplexing circuit and the second multiplexing circuit control electrical connection between the same input signal line and different first signal lines in different time periods of one frame period.

[0020] In some embodiments, the first signal line group includes M first signal lines, the second multiplexing circuit is electrically connected with the M first signal lines, and M≥2; the display substrate includes one third signal line, which is electrically connected with the second multiplexing circuit. The driving method further includes: in the screen-on display mode, the second multiplexing circuit controls electrical circuit cutoff between the input signal line and the at least two first signal lines of one signal line group; and in the screen-off wake-up mode, the second multiplexing circuit controls electrical connection between the input signal line and the at least two first signal lines of one signal line group in the same time period.

[0021] In another aspect, a display device is provided. The display device includes a driving chip and the display substrate in any of the above embodiments. The driving chip is electrically connected with the input signal line of the display substrate and is configured to transmit a data signal to the data signal terminal. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly introduced as follows. Obviously, the drawings in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0023] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0024] FIG. 2 is a constituent structural diagram of a display device according to some embodiments;

[0025] FIG. 3 is a display residual image of a display substrate in the related art;

[0026] FIG. 4 is a principle analysis diagram of a display residual image of a display substrate in the related art;

[0027] FIG. 5 is a structural diagram of a display substrate according to some embodiments;

[0028] FIG. 6 is an equivalent circuit diagram of a display substrate according to some embodiments;

[0029] FIG. 7 is another equivalent circuit diagram of a display substrate according to some embodiments;

[0030] FIG. 8 is still another equivalent circuit diagram of a display substrate according to some embodiments;

[0031] FIG. 9 is a structural diagram of a display substrate according to some embodiments;

[0032] FIG. 10 is a partial enlarged view of the A area in FIG. 9;

[0033] FIG. 11 is the mobility, positive and negative threshold voltage drift of a transistor using high mobility oxide material in different thicknesses of a semiconductor layer. DETAILED DESCRIPTION

[0034] The technical solutions in some embodiments of the present disclosure will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by those skilled in the art are within the scope of protection of the present disclosure.

[0035] Unless the context clearly requires otherwise, throughout the description and the claims, the term "comprise," and variations thereof (e.g., "comprises" and "comprising"), will be construed to be inclusive in a manner consistent with the term's plain meaning, namely, "including but not limited to." In describing the description, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example" or "some examples," and the like, mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the disclosure, but that it can not be included in other embodiments or examples. The illustrative appearance of the foregoing terms in various places in the description are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0036] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description and should not be construed as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0037] In describing some embodiments, "coupled" and "connected," and variations thereof, can be used. The term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components have direct physical contact or electrical contact. The term "coupled" or "communicatively coupled" can also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0038] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0039] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0040] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected" is, optionally, interpreted as meaning "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0041] Use of "adapted to" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps not specifically recited.

[0042] Additionally, use of "based on" means open and inclusive, as the process, step, calculation, or other action based on a stated condition or value can actually be based on additional conditions or values beyond those stated.

[0043] As used herein, "about," "approximately," or "circa" includes the recited value and the average value within an acceptable range of deviation from the stated value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).

[0044] As used herein, "parallel," "perpendicular," "equal" includes the recited condition and conditions that approximate the recited condition, the approximation being within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can be within an acceptable deviation of, for example, 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also be within an acceptable deviation of, for example, 5°. "Equal" includes absolute equality and near equality, where near equality can be within an acceptable deviation of, for example, less than or equal to 5% of either of the two quantities being compared.

[0045] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0046] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0047] Referring to FIG. 1, embodiments of the disclosure provide a display device, and the display device 1000 is a product having an image display function. Exemplarily, the display device 1000 can be any device displaying images whether moving (e.g., video) or fixed (e.g., still image) and whether text or image.

[0048] In some embodiments, the display device described above can be an Augmented Reality (AR) device, a Virtual Reality (VR) device, or a Mixed Reality (MR) device. Alternatively, in other embodiments, the display device described above can also be a television, a notebook computer, a tablet computer, a Personal Digital Assistant (PDA), a mobile phone, a watch, a clock, a calculator, a GPS receiver / navigator, a camera, a display of a camera view (e.g., a display of a rear view camera in a vehicle), a wearable device, an in-vehicle display, a flight display, or any product or component having a display function.

[0049] In some embodiments, the display device 1000 can be a liquid crystal display (LCD) or an organic light-emitting diode (OLED) display or a quantum dot light emitting diode (QLED) display, etc. in terms of the light-emitting type of the display device 1000. In terms of the form of the display device 1000, the display device 1000 can be a flat display device or a curved display device, etc. In terms of the shape of the display device 1000, the display device 1000 can be rectangular or circular, etc. Hereinafter, some embodiments of the present disclosure will be schematically described by taking a rectangular and flat liquid crystal display device as an example, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical idea is applied.

[0050] In some embodiments, referring to FIG. 2, the display device 1000 can include a display substrate 1100 and a driving chip 1200. Of course, the structure of the display device 1000 is not limited thereto, and will not be listed one by one here; for example, the display device 1000 can also include a camera and a fingerprint recognition sensor, etc., so that the display device 1000 can realize various functions such as photographing, video recording, or fingerprint recognition, etc.

[0051] The display substrate 1100 includes a display area AA and a peripheral area BB disposed around the display area AA. The display area AA refers to a region of the display substrate 1100 for displaying an image, and the display area AA includes a plurality of sub-pixels P, which are the smallest light-emitting units in the display substrate 1100. The peripheral area BB can be used to dispose signal traces (such as power signal lines, clock signal lines, etc.), driving circuits (such as gate driving circuits), and binding portions, etc. Of course, the structure and function of the peripheral area BB are not limited thereto, and will not be listed one by one here. The driving chip 1200 can be disposed in the peripheral area of the display substrate 1100 and is in binding connection with the display substrate 1100.

[0052] The plurality of sub-pixels P can include at least two types of sub-pixels emitting different color light, which is conducive to the display substrate to realize color display. In one example, the plurality of sub-pixels P can include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light. The sub-pixel P can include a pixel circuit 100, and the display substrate 1100 includes a plurality of pixel circuits 100, one pixel circuit 100 being configured to drive one sub-pixel P to emit light.

[0053] Continuing to refer to FIG. 2, the plurality of pixel circuits 100 are arranged in columns along a first direction Y, and the display substrate 1100 includes a plurality of columns of pixel circuits 100 arranged at intervals along a second direction X. That is, the first direction Y refers to the arrangement direction of a column of pixel circuits, and the second direction X refers to the arrangement direction of a plurality of columns of pixel circuits; and the first direction Y intersects the second direction X, for example, the first direction Y and the second direction X are perpendicular to each other.

[0054] As shown in FIG. 2, the display substrate 1100 further includes a plurality of first signal line groups 10, one first signal line group 10 includes at least two first signal lines 11 (two are taken as an example in FIG. 2), and one first signal line 11 is electrically connected to one column of pixel circuits 100.

[0055] At least two first signal lines 11 of the first signal line group 10 can be arranged adjacently (as shown in FIG. 6), that is, at least two first signal lines 11 of one signal line group 10 can be electrically connected to at least two columns of pixel circuits arranged adjacently; or at least two first signal lines 11 of the first signal line group 10 can be arranged at intervals (as shown in FIG. 7), that is, at least two first signal lines 11 of one signal line group 10 can be electrically connected to at least two columns of pixel circuits arranged at intervals.

[0056] In some embodiments, at least part of the plurality of first signal line groups 10 are arranged in the display area AA, and the first signal line 11 can be a data signal line for example, and the first signal line 11 is used to transmit a data signal to one column of pixel circuits 100. Hereinafter, the embodiments of the present disclosure are exemplarily described taking the first signal line 11 as a data signal line as an example.

[0057] In some embodiments, as shown in FIG. 2, the pixel circuit 100 can include a second thin film transistor T20, the control electrode of the second thin film transistor T20 is electrically connected to the scan signal line 12, one of the source electrode and the drain electrode is electrically connected to the first signal line 11, and the other is electrically connected to the pixel electrode.

[0058] In some embodiments, in the case that the display substrate is a liquid crystal display substrate, the pixel circuit 100 can further include a common electrode, a capacitor can be formed between the pixel electrode and the common electrode, and an electric field can be generated between the pixel electrode and the common electrode during the process of image display of the display substrate. The electric field can drive the liquid crystal molecules of the liquid crystal layer to deflect, so as to adjust the light transmittance of each sub-pixel, and then perform picture display.

[0059] The pixel circuit 100 can include an oxide thin-film transistor (OTFT). For example, the second thin-film transistor T20 can be an oxide thin-film transistor. The oxide thin-film transistor has a low leakage current, which is conducive to reducing the leakage current of the pixel circuit 100, simplifying the circuit structure of the pixel circuit 100, improving the aperture ratio of the array substrate, and improving the light transmittance of the display substrate.

[0060] In some embodiments, the driving chip 1200 can be a source driver IC, which is a chip used to transmit data signals to the plurality of first signal lines 11 of the plurality of first signal line groups 10. In order to reduce the cost of the driving chip 1200, a multiplexer (MUX) can be arranged in the peripheral area BB and between the driving chip 1200 and the display area AA, so as to reduce the number of signals (such as data signals) output by the driving chip 1200 (at the same time), thereby reducing the cost of the driving chip 1200 and the manufacturing cost of the display substrate 1100.

[0061] In some embodiments, the driving chip 1200 can also be a touch and display driver integrated chip (TDDI chip). In this case, the display substrate 1100 can be a display substrate with a touch function, which can also be referred to as a TDDI display substrate. For example, when the display substrate 1100 is a liquid crystal display substrate, the display substrate 1100 can include an array substrate and a color film substrate (also referred to as a counter substrate) arranged opposite to each other, and a liquid crystal layer and a touch structure (In cell) arranged between the array substrate and the color film substrate. For example, the touch structure can be arranged on the array substrate, i.e., the touch structure is located between the array substrate and the liquid crystal layer.

[0062] When the driving chip 1200 is a TDDI chip, the driving chip 1200 can be used to transmit data signals to the plurality of first signal lines 11 included in the plurality of first signal line groups 10, and can also be used to transmit touch signals to the touch structure. In order to reduce the cost of the driving chip 1200, a multiplexer (MUX) can also be arranged in the peripheral area BB and between the driving chip 1200 and the display area AA, so as to reduce the number of signals (such as data signals) output by the driving chip 1200 (at the same time), thereby reducing the cost of the driving chip 1200 and the manufacturing cost of the display substrate 1100.

[0063] In some embodiments, when the display substrate 1100 includes a touch function, the display substrate 1100 can have a low power wake up gesture (LPWG) function. The low power wake up gesture function is a special function of the TDDI display substrate, which can support the sliding operation of the screen when the display substrate is in the sleep black state (Sleep in), such as a user can directly wake up some functions or corresponding software of the display substrate by a preset gesture. However, the low power wake up gesture function still consumes a certain amount of power without using the display substrate (in the sleep black state). In order to both retain the low power wake up gesture function and achieve the purpose of power saving, in the low power wake up gesture mode, the touch signal is continuously provided to the touch electrode in the TDDI display substrate, while the display function and the charge pump module of the driving chip 1200 are both turned off, so as to reduce the power consumption of the TDDI display substrate, and rely on the voltage of the external power supply to drive the touch structure in the low power wake up gesture mode. The highest voltage of the driving chip 1200 is the VSP voltage input from the front end (such as +6V), and the lowest voltage is the VSN voltage input from the front end (such as -6V).

[0064] At present, the related display product (TDDI display substrate) will have a large area display residue (as shown in FIG. 3) after the reliability test and in the low power wake up gesture mode. Moreover, the longer the time stays in the low power wake up gesture mode, the more serious the residue phenomenon is. The inventors have found that one of the important reasons for the above-mentioned residue problem is that, as shown in FIG. 4, after the display substrate is subjected to the reliability test, the transistors of the multiplexing circuit MUX are right-shifted (the on-state voltage of the transistor becomes larger, and the on-state current decreases) due to the long-time work of the transistors. Therefore, in the subsequent case that the display substrate is in the low power wake up gesture mode, the transistors of the multiplexing circuit MUX cannot be fully turned on, so that when the driving chip 1200 transmits the data signal to the first signal line 11, the data signal on the input signal line 41 cannot be completely loaded (transmitted) to the first signal line 11, resulting in that the data signal received on the first signal line 11 is obviously distorted, and the data signal transmitted to the pixel circuit is also distorted, and thus a voltage difference is generated between the pixel electrode and the common electrode. The voltage difference causes the liquid crystal of the liquid crystal layer to deflect, and then the light leakage phenomenon occurs in the black screen mode, resulting in the occurrence of the above-mentioned residue problem.

[0065] Referring to FIG. 5, in order to solve the above-mentioned technical problem, the display substrate 1100 provided by the embodiments of the present disclosure further includes a plurality of input signal lines 41, a plurality of first multiplexing circuits MUX1 and a plurality of second multiplexing circuits MUX2.

[0066] A first multiplexing circuit MUX1 is electrically connected with an input signal line 41 and at least two (all) first signal lines 11 of a first signal line group 10. The first multiplexing circuit MUX1 controls the electrical connection of the input signal line 41 and one first signal line 11 in the same period; in other words, the first multiplexing circuit MUX1 can only turn on the input signal line 41 and one first signal line 11 of the first signal line group 10 in the same period (at the same time) so that the input signal line 41 transmits a data signal to each first signal line 11 individually.

[0067] Exemplarily, the number of first multiplexing circuits MUX1, the number of input signal lines 41 and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected with one first multiplexing circuit MUX1, and different input signal lines 41 are electrically connected with different first multiplexing circuits MUX1. One first multiplexing circuit MUX1 is electrically connected with one first signal line group 10, and different first multiplexing circuits MUX1 are electrically connected with different first signal line groups 10.

[0068] A second multiplexing circuit MUX2 is electrically connected with an input signal line 41 and at least two (all) first signal lines 11 of a first signal line group 10, and the second multiplexing circuit MUX2 controls the electrical connection of the input signal line 41 and at least one first signal line 11 in the same period. In other words, the first multiplexing circuit MUX1 can turn on the input signal line 41 and at least one first signal line 11 of the first signal line group 10 in the same period so that the input signal line 41 transmits a data signal to each first signal line 11 individually or synchronously to multiple first signal lines 11.

[0069] Exemplarily, the number of second multiplexing circuits MUX2, the number of input signal lines 41 and the number of first signal line groups 10 are equal. One input signal line 41 is electrically connected with one second multiplexing circuit MUX2, and different input signal lines 41 are electrically connected with different second multiplexing circuits MUX2. One second multiplexing circuit MUX2 is electrically connected with one first signal line group 10, and different second multiplexing circuits MUX2 are electrically connected with different first signal line groups 10.

[0070] Continuing to refer to FIG. 5, an input signal line 41 is electrically connected to a first multiplexing circuit MUX1 and a second multiplexing circuit MUX2 respectively, and at least two first signal lines 11 of a first signal line group 10 are electrically connected to the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 respectively. The input signal line 41 can transmit a control signal to the first signal lines 11 of the same first signal line group 10 through the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 respectively. In this way, different driving methods can be used to drive the display substrate 1100 to select one of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 to work at different times. On the one hand, it is beneficial to reduce the working time of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2, reduce the risk of right drift of transistors of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2, and reduce or completely eliminate the problem of display residue of the display substrate 1100.

[0071] In some embodiments of the present disclosure, in order to simplify the description, the electrical connection between the first multiplexing circuit MUX1 and / or the second multiplexing circuit MUX2 control input signal line 41 and the first signal line 11 is described as the first multiplexing circuit MUX1 and / or the second multiplexing circuit MUX2 working.

[0072] Exemplarily, the display substrate 1100 can include a bright screen display mode and an off-screen wake-up mode.

[0073] In the case where the second multiplexing circuit MUX2 controls the electrical connection between the input signal line 41 and a first signal line 11 in the same period. One of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 can be used to work in the bright screen display mode and the off-screen wake-up mode respectively. For example, in the bright screen display mode, the first multiplexing circuit MUX1 controls the electrical connection between the input signal line 41 and a first signal line 11 in the same period, and in the off-screen wake-up mode, the second multiplexing circuit MUX2 controls the electrical connection between the input signal line 41 and a first signal line 11 in the same period.

[0074] Since all the sub-pixels display the same gray scale in the screen-off wake-up mode (0 gray scale in the screen-off state), the same size of data signal can be transmitted to all the pixel circuits 100. Based on this, the second multiplexing circuit MUX2 can control the electrical connection between the input signal line 41 and at least two first signal lines 11 at the same time. In this case, the electrical connection between the input signal line 41 and one first signal line 11 at the same time can be controlled by the first multiplexing circuit MUX1 in the screen-on display mode, and the electrical connection between the input signal line 41 and one first signal line 11 at the same time can be controlled by the second multiplexing circuit MUX2 in the screen-off wake-up mode.

[0075] It should be noted that the driving method of the display substrate 1100 is not limited to the above two specific embodiments, and as long as the same technical idea is adopted, the embodiments of the present disclosure will not be listed one by one.

[0076] In some embodiments, referring to FIGS. 5-8, the first signal line group 10 includes M first signal lines 11, and the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 are electrically connected to the M first signal lines 11 included in the first signal line group 10, that is, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 are 1:M; wherein M≥2. Exemplarily, the value of M can be 2, 3, 4, or 6, and the embodiments of the present disclosure will not be listed one by one. In this way, the number of data signals output by the driving chip 1200 (at the same time) can be reduced, thereby reducing the cost of the driving chip 1200 and the preparation cost of the display substrate. Moreover, as the value of M increases, the number of data signals output by the driving chip 1200 (at the same time) decreases.

[0077] Wherein, referring to FIGS. 5-8, the value of M in the drawings provided by the embodiments of the present disclosure is exemplarily described as 2, but the embodiments of the present disclosure are not limited thereto, and the value of M can be set arbitrarily according to needs. The embodiments of the present disclosure are exemplarily described below with the value of M as 2.

[0078] In some embodiments, referring to FIG. 6, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 each include M (2) first thin film transistors T10. One of the source and drain of the first thin film transistor T10 is electrically connected to the input signal line 41, and the other is electrically connected to one first signal line 11. The first thin film transistor T10 can control the electrical connection between the input signal line 41 and the first signal line 11.

[0079] In some embodiments, the first multiplexing circuit MUX1 includes two first thin film transistors T10. And / or, the second multiplexing circuit MUX2 includes two first thin film transistors T10.

[0080] In some embodiments, at least one of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 comprises an oxide thin film transistor. Exemplarily, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 each comprise a first thin film transistor T10 which is an oxide thin film transistor. The oxide thin film transistor has a low leakage current, which is conducive to reducing the leakage current of the first thin film transistor T10.

[0081] Referring to FIG. 6, the substrate 1100 further comprises N second signal line groups 20. Each second signal line group 20 comprises M second signal lines 21, and the M second signal lines 21 of each second signal line group 20 are electrically connected to a first multiplexing circuit MUX1, and one second signal line 21 controls the electrical connection between one first signal line 11 and the input signal line 41. Wherein, N≥2; Exemplarily, N can be 2, 3 or 4, etc., and the embodiments of the present disclosure do not enumerate them one by one. Wherein, the plurality of first multiplexing circuits MUX1 are alternately electrically connected to the N second signal line groups 20. In this way, it is conducive to reducing the load on each second signal line group 20 and reducing the voltage drop on the second signal line 21.

[0082] Exemplarily, the second signal line 21 can be a gate line, and the second signal line 21 is configured to control the electrical connection between the input signal line 41 and the first signal line 11. For example, the second signal line 21 is configured to form a gate (control electrode) of the first thin film transistor T10, thereby controlling the conduction and cutoff of the first thin film transistor T10.

[0083] The M second signal lines 21 of the second signal line group 20 correspond to the M first thin film transistors T10 of the first multiplexing circuit MUX1 respectively, and one second signal line 21 is used to form a gate of one first thin film transistor T10. As shown in FIG. 6, when the value of M is 2, one second signal line group 20 comprises two second signal lines 21, and the two second signal lines 21 are respectively connected to the gates of the two first thin film transistors T10 of the first multiplexing circuit MUX1.

[0084] Exemplarily, N can be 2, that is, the display substrate 1100 includes two second signal line groups 20, and the plurality of first multiplexing circuits MUX1 are alternately electrically connected with the N second signal line groups 20, which can be that each first multiplexing circuit MUX1 is alternated once, for example, from left to right, the odd (or even) first multiplexing circuit MUX1 is electrically connected with the second signal line group 20 close to the display area, and the even (or odd) first multiplexing circuit MUX1 is electrically connected with the second signal line group 20 away from the display area. It can also be that each plurality (such as every 2, 3, 4 or other number) of first multiplexing circuits MUX1 is alternated once.

[0085] In some embodiments, in the bright screen display mode, the first multiplexing circuit MUX1 can be used to transmit the data signal to the first signal line 11, and the N second signal line groups 20 can be used to control the first multiplexing circuit MUX1, which can reduce the load on the second signal line group 20, reduce the voltage drop on the second signal line 21, and thus fully open the first thin film transistor T10 included in the first multiplexing circuit MUX1, which is conducive to the data signal transmitted on the input signal line 41 being fully written to the first signal line 11.

[0086] In some embodiments, referring to FIGS. 6 and 7, the display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, the M third signal lines 31 of the third signal line group 30 are electrically connected with a second multiplexing circuit MUX2, and one third signal line 31 controls the electrical connection between the input signal line 41 and the first signal line 11. Wherein, P≥1. Exemplarily, P can be 1, 2 or 3, and the embodiments of the present disclosure do not list them one by one.

[0087] Exemplarily, the third signal line 31 can be a gate line, and the third signal line 31 is configured to control the electrical connection between the input signal line 41 and the first signal line 11. For example, the third signal line 31 is configured to form the gate (control electrode) of the first thin film transistor T10 of the second multiplexing circuit MUX2, thereby controlling the conduction and cutoff of the first thin film transistor T10.

[0088] The M third signal lines 31 of the third signal line group 30 correspond to the M first thin film transistors T10 of the second multiplexing circuit MUX2 respectively, and one third signal line 31 is used to form the gate of one first thin film transistor T10. As shown in FIGS. 6 and 7, in the case where M is 2, one third signal line group 30 includes two third signal lines 31, and the two third signal lines 31 are respectively connected with the gates of the two first thin film transistors T10 of the second multiplexing circuit MUX2.

[0089] As shown in FIG. 7, when P is equal to 1, that is, the display substrate 1100 includes one third signal line group 30, and each of the plurality of second multiplexing circuits MUX2 is electrically connected to the M third signal lines 31 of the third signal line group 30. In this way, the number of third signal line groups 30 can be reduced, the control difficulty of the driving chip can be reduced, the structure of the display substrate 1100 can be simplified, and the width of the peripheral area can be reduced.

[0090] When P is greater than 1, for example, P can be equal to 2 or 3, that is, the display substrate 1100 includes a plurality of third signal line groups 30. The plurality of second multiplexing circuits MUX2 are alternately electrically connected to the P third signal line groups 30. In this way, the load on each second signal line group 20 can be reduced, and the voltage drop on the second signal line 21 can be reduced.

[0091] In one example, as shown in FIG. 6, P can be equal to 2, that is, the display substrate 1100 includes two third signal line groups 30. The plurality of second multiplexing circuits MUX2 are alternately electrically connected to the two third signal line groups 30, for example, each first multiplexing circuit MUX1 is alternated once, such as along the second direction X, the odd (or even) second multiplexing circuit MUX2 is connected to the first (close to the display area AA) third signal line group 30, and the even (or odd) second multiplexing circuit MUX2 is connected to the second (far from the display area AA) third signal line group 30. In this way, the load on each second signal line group 20 can be reduced, and the voltage drop on the second signal line 21 can be reduced. Alternatively, each plurality (for example, every 2, 3, 4, or other number) of second multiplexing circuits MUX2 can be alternated once.

[0092] In some embodiments, when P is greater than 1, that is, the display substrate 1100 includes a plurality of third signal line groups 30. At this time, the number of third signal line groups 30 can be equal to the number of second signal line groups 20 (as shown in FIG. 6), and the plurality of second multiplexing circuits MUX2 are alternately electrically connected to the P third signal line groups 30. In this way, the connection mode of the plurality of first multiplexing circuits MUX1 and the plurality of second multiplexing circuits MUX2 is completely the same, and the plurality of first multiplexing circuits MUX1 and the plurality of second multiplexing circuits MUX2 are redundantly arranged.

[0093] In some embodiments, when P is greater than 1, that is, the display substrate 1100 includes a plurality of third signal line groups 30, the number of third signal line groups 30 can also be different from the number of second signal line groups 20 (not shown in the figure), for example, the number of third signal line groups 30 can be greater than the number of second signal line groups 20; or the number of third signal line groups 30 can be less than the number of second signal line groups 20.

[0094] In the case where P is greater than 1, that is, the display substrate 1100 includes multiple third signal line groups 30, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 can work in an alternative manner in any display mode, or the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 work in an alternative manner in any display mode.

[0095] For example, in the bright screen display mode, one of the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 works, and in the screen-off wake-up mode, the other of the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 works. That is, in the same display mode, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 work in an alternative manner, and in different display modes, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 work in an alternative manner. In this way, picture sticking can be avoided when the mode is switched.

[0096] For example, in any mode, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 work in an alternative manner, such as, in the bright screen display mode, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 alternately transmit data signals required for at least one frame of picture; for example, the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 work in an alternative manner every 1 frame (or 2 frames, 3 frames, 4 frames, 60 frames, etc. according to the need). In this way, the working time of the multiple first multiplexing circuits MUX1 and the multiple second multiplexing circuits MUX2 can be shortened, the opening time of the first thin film transistor T10 can be reduced, and the risk of drift of the first thin film transistor T10 can be effectively reduced.

[0097] It can be understood that the driving method of the display substrate provided by the embodiments of the present disclosure is not limited thereto, as long as the same technical idea is adopted.

[0098] In some embodiments, referring to FIG. 8, the display substrate 1100 includes one third signal line 31, which is electrically connected with all the second multiplexing circuits MUX2. The third signal line 31 controls the electrical connection of the input signal line 41 and the M first signal lines 11 included in the first signal line group 10 in the same time period and with the same second multiplexing circuit MUX2, that is, the third signal line 31 simultaneously connects or disconnects the input signal line 41 and the M first signal lines 11.

[0099] Exemplarily, as shown in FIG. 8, the third signal line 31 can be a gate line, and the third signal line 31 is configured to control the electrical connection between the input signal line 41 and all the first signal lines 11 of one first signal line group 10. Exemplarily, the third signal line 31 is configured to form the gate (control electrode) of all the first thin film transistors T10 of the second multiplexing circuit MUX2, thereby controlling the turn-on and turn-off of all the first thin film transistors T10. For example, one third signal line 31 is used to form the gate of M first thin film transistors T10. In this way, the number of third signal line groups 30 can be greatly reduced, the control difficulty of the driving chip can be reduced, the structure of the display substrate 1100 can be simplified, and the width of the peripheral area can be reduced.

[0100] Exemplarily, in the case where the display substrate 1100 includes one third signal line 31, the plurality of second multiplexing circuits MUX2 can work in the screen-off wake-up mode, at this time, all the pixel circuits 100 in the display area AA display the same gray scale (0 gray scale), the same size of data signals can be transmitted to the pixel circuits 100 synchronously, therefore, all the first thin film transistors T10 of the second multiplexing circuit MUX2 can be turned on synchronously, based on this, the plurality of second multiplexing circuits MUX2 can be controlled by one third signal line 31.

[0101] In some embodiments, referring to FIGS. 9 and 10, in the case where the plurality of first multiplexing circuits MUX1 and the plurality of second multiplexing circuits MUX2 each include a plurality of first thin film transistors T10, the width-length ratio (W / L) of the first thin film transistor T10 is greater than or equal to 200 μm / 3.5 μm, that is, the width-length ratio of the channel structure of the first thin film transistor T10 is greater than or equal to 200 μm / 3.5 μm. In this way, the charging capability of the first thin film transistor T10 can be improved, that is, the current gain of the first thin film transistor T10 can be improved, and the delay of the signal transmission of the first multiplexing circuit MUX1 and the plurality of second multiplexing circuits MUX2 can be reduced. Exemplarily, the width-length ratio of the first thin film transistor T10 can be 200 μm / 3.5 μm, 250 μm / 3.5 μm, 300 μm / 3.5 μm, 320 μm / 3.5 μm, or 350 μm / 3.5 μm, and the like, and the embodiments of the present disclosure will not be enumerated one by one.

[0102] In some embodiments, the width-length ratio of the first thin film transistor T10 can be 320 μm / 3.5 μm. At this time, the charging capability of the first thin film transistor T10 can be greatly improved, and the risk of drift of the first thin film transistor T10 can be reduced.

[0103] Exemplarily, as shown in FIG. 9 and FIG. 10, the display substrate 1100 can include a plurality of gate lines GL, wherein the plurality of gate lines GL can include the second signal line 21 and the third signal line 31, in other words, the second signal line 21 and the third signal line 31 can both be gate lines GL. In addition, each gate line GL includes a main body portion 42 and a gate portion 43 alternately connected along the second direction X. One gate portion 43 is configured to form a gate of one first thin film transistor T10.

[0104] The display substrate 1100 further includes a substrate, referring to FIG. 10, the first thin film transistor T10 further includes a semiconductor pattern 44 disposed on a side of the gate portion 43 close to the substrate, a normal projection of the gate portion 43 on the substrate partially overlaps a normal projection of the semiconductor pattern 44 on the substrate, and in the semiconductor pattern 44, a part on the substrate that overlaps the normal projection of the gate portion 43 on the substrate forms a channel structure 441, a dimension of the channel structure 441 in the first direction Y is a width W of the first thin film transistor T10, a dimension of the channel structure 441 in the second direction X is a length L of the first thin film transistor T10, and a width-length ratio W / L of the first thin film transistor T10 refers to a ratio between the width W and the length L of the channel structure 441.

[0105] In the semiconductor pattern 44, a part on the substrate that overlaps the normal projection of the gate portion 43 on the substrate forms a channel structure 441, a dimension of the channel structure 441 in the first direction Y is a width W of the first thin film transistor T10, a dimension of the channel structure 441 in the second direction X is a length L of the first thin film transistor T10, and a width-length ratio W / L of the first thin film transistor T10 refers to a ratio between the width W and the length L of the channel structure 441.

[0106] Exemplarily, referring to FIG. 10, the gate portion 43 can include a plurality of sub-portions 431 spaced apart along the second direction X, the plurality of sub-portions 431 all extend along the first direction Y, a normal projection of one sub-portion 431 on the substrate forms one channel structure 441 with a normal projection of the semiconductor pattern 44 on the substrate, and the length L of the channel structure 441 refers to a dimension of a part in each semiconductor pattern 44 that overlaps the normal projection of one sub-portion 431 along the second direction X, i.e., a dimension of each channel structure 441 alone.

[0107] As shown in FIG. 10, the plurality of sub-portions 431 are connected head to tail to form an S-shaped structure, and a slit 433 with an opening 432 can be formed between two adjacent sub-portions 431, and the openings 432 of two adjacent slits 433 face in opposite directions. The first thin film transistor T10 further includes a source and a drain located in the slit 433, and the source and the drain are connected to the semiconductor pattern 44 through the slit 433.

[0108] In some embodiments, referring to FIGS. 9 and 10, the size D1 of the body portion 42 is less than the size D2 of the gate portion 43 in the first direction Y, which is conducive to increasing the size of the gate portion 43 in the first direction Y, increasing the width-length ratio of the first thin film transistor T10, increasing the charging capacity of the first thin film transistor T10, i.e., increasing the on-state current of the first thin film transistor T10, and reducing the risk of drift of the first thin film transistor T10.

[0109] As shown in FIG. 9, the plurality of first thin film transistors T10 are arranged in multiple rows in the first direction Y, and one gate line GL is electrically connected to one row of first thin film transistors T10, or in other words, the plurality of first thin film transistors T10 electrically connected to the same gate line GL form one row of first thin film transistors T10. At least two adjacent rows of first thin film transistors T10 partially overlap in the first direction Y, that is, at least two adjacent rows of first thin film transistors T10 in the plurality of rows of first thin film transistors T10 partially overlap in the first direction Y. This can greatly reduce the space of the plurality of rows of first thin film transistors T10 in the first direction Y, which is conducive to reducing the size of the frame area and achieving a narrow frame of the display substrate 1100.

[0110] In this application, the partial overlap of the two adjacent rows of first thin film transistors T10 in the first direction Y means that the two adjacent rows of first thin film transistors T10 jointly occupy the same part of the space of the display substrate 1100 in the first direction Y, or in other words, the projections of the two adjacent rows of first thin film transistors T10 in the second direction X partially overlap. For example, in FIG. 9, the first and second rows and the third and fourth rows of first thin film transistors T10 are considered to partially overlap in the first direction Y, and the second and third rows of first thin film transistors T10 are considered not to overlap in the first direction Y.

[0111] Continuing to refer to FIG. 9, the two adjacent first thin film transistors T10 belonging to two adjacent rows are staggered in the second direction X, which is conducive to optimizing the arrangement space of the first thin film transistors T10, increasing the arrangement density of the first thin film transistors T10, greatly reducing the size of the space occupied by the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 in the peripheral area, and thereby reducing the width of the peripheral area, which is conducive to achieving a narrow frame of the display substrate 1100.

[0112] In some embodiments, as shown in FIG. 9, the body part 42 and the gate part 43 are flush at one end in the first direction Y, and the other end of the gate part 43 protrudes (extends) beyond the edge of the body part 42. The gate part 43 of two adjacent gate lines GL protrudes towards the two sides opposite to the first direction Y compared to the body part 42. The plurality of gate lines GL are divided into a plurality of pairs, one pair including two adjacent gate lines GL, and the gate parts 43 of the two gate lines GL of one pair protrude towards each other. Two rows of first thin film transistors T10 connected to the two gate lines GL of one pair partially overlap in the first direction Y, and two rows of first thin film transistors T10 connected to two adjacent gate lines GL of two adjacent pairs do not overlap in the first direction Y. In this way, the arrangement space of the first thin film transistors T10 is optimized, the arrangement density of the first thin film transistors T10 is improved, the size of the space occupied by the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 in the peripheral area is greatly reduced, and the width of the peripheral area is reduced, which is beneficial to the realization of narrow frame of the display substrate.

[0113] Exemplarily, as shown in FIG. 9, the four gate lines GL are sequentially divided into a first gate line, a second gate line, a third gate line and a fourth gate line from top to bottom. The four gate lines GL are divided into two groups, the first gate line and the second gate line form one group, and the third gate line and the fourth gate line form another group. Among them, the gate part 43 of the first gate line protrudes downward along the first direction Y compared to the body part 42, and the gate part 43 of the second gate line protrudes upward along the first direction Y compared to the body part 42. Two rows of first thin film transistors T10 connected to the first gate line and the second gate line partially overlap in the first direction Y. Two rows of first thin film transistors T10 connected to the second gate line and the third gate line do not overlap in the first direction Y.

[0114] In some embodiments, the semiconductor pattern 44 can employ a high mobility metal oxide semiconductor (HMOS) material, which is beneficial to improve the electron mobility of the semiconductor pattern 44 and the on-state current of the first thin film transistor T10. In addition, the high mobility metal oxide semiconductor material also has good light stability, which is beneficial to improve the light stability of the first thin film transistor T10. The high mobility metal oxide semiconductor material includes but is not limited to rare earth element doped IZO and IGZO, and the concentration of the rare earth element doping can be between 0.1% and 2%. However, due to the small optical band gap Eg of the high mobility metal oxide semiconductor material, the electrons in the high mobility metal oxide semiconductor material can absorb part of the visible light band to produce electron transition, resulting in that the transistor irradiated by the backlight will be turned on in advance, and new defects will be added under light irradiation. As shown in FIG. 11, long-time application of positive voltage (PBTS shown in FIG. 11) to the transistor causes the threshold voltage to drift positively, and long-time application of negative voltage (NBTS shown in FIG. 11) to the transistor causes the threshold voltage to drift negatively. The higher the mobility, the more serious the negative drift, which limits the application of the high mobility metal oxide semiconductor material. Since the technical solution provided by the embodiments of the present disclosure can improve and even completely eliminate the residual problem, it is beneficial to realize the wide application of high mobility.

[0115] Some embodiments of the present disclosure also provide a driving method of the display substrate 1100 for driving the display substrate described in any of the above embodiments. The display substrate includes a bright screen display mode and a screen-off wake-up mode. Of course, the display substrate can also include other display modes, which are not listed one by one here.

[0116] The driving method of the display substrate 1100 includes:

[0117] In the bright screen display mode, the first multiplexing circuit MUX1 controls the electrical connection of the input signal line 41 and one first signal line in the same period.

[0118] In the screen-off wake-up mode, the second multiplexing circuit MUX2 controls the electrical connection of the input signal line and at least one first signal line in the same period.

[0119] Based on the above driving method, the display substrate 1100 can control the electrical connection between the input signal line 41 and the first signal line 11 in the same period by using the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 respectively in different display modes. In this way, even if the first thin film transistor T10 of the first multiplexing circuit MUX1 drifts (such as right drift) after a long time of bright screen display (such as reliability test), after switching to the screen-off wake-up mode, since the first multiplexing circuit MUX1 is no longer used, but the second multiplexing circuit MUX2 is used to control the electrical connection between the input signal line 41 and the first signal line 11 in the same period, the drift of the first thin film transistor T10 of the first multiplexing circuit MUX1 will not affect the electrical connection between the input signal line 41 and the first signal line 11, that is, it will not cause the problem of distortion of the data signal during the process of the second multiplexing circuit MUX2, thereby reducing the risk of residual of the display substrate.

[0120] In some embodiments, referring to FIGS. 6 and 7, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX2 is electrically connected with the M first signal lines, and M≥2. The display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and one second multiplexing circuit MUX2 is electrically connected with the M third signal lines 31 of the third signal line group 30; wherein P≥1.

[0121] At this time, the driving method of the display substrate further includes:

[0122] In the screen-off wake-up mode, the second multiplexing circuit MUX2 controls the electrical connection between the input signal line 41 and one first signal line 11 in the same period. That is, the second multiplexing circuit MUX2 is only used to turn on the input signal line 41 and one first signal line 11 in one first signal line group 10 in the same period.

[0123] In some embodiments, referring to FIGS. 6 and 7, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX2 is electrically connected with the M first signal lines, and M≥2. The display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and one second multiplexing circuit MUX2 is electrically connected with the M third signal lines 31 of the third signal line group 30; wherein P≥1.

[0124] At this time, the driving method of the display substrate further includes:

[0125] In the bright screen display mode, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 alternately electrically connect the input signal line 41 with a first signal line 11 in different display frames. In this way, the total number of times and the total time length that the first thin film transistor T10 of the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 are turned on in the bright screen display mode can be reduced, thereby reducing the risk of drift of the first thin film transistor T10, improving the accuracy of data signal transmission in the bright screen display mode, and ensuring that the picture displayed by the display substrate will not be distorted in the long-time bright screen display mode.

[0126] In some embodiments, referring to FIGS. 6 and 7, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX2 is electrically connected with the M first signal lines 11, where M≥2. The display substrate 1100 further includes P third signal line groups 30. The third signal line group 30 includes M third signal lines 31, and one second multiplexing circuit MUX2 is electrically connected with the M third signal lines 31 of the third signal line group 30; where P≥1.

[0127] At this time, the driving method of the display substrate further includes:

[0128] In the screen-off wake-up mode, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 both control the electrical connection between the same input signal line 41 and the same first signal line 11 in the same time period. The first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 control the electrical connection between the same input signal line and different first signal lines in different time periods of one frame period.

[0129] That is, the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 work simultaneously, and the two first thin film transistors T10 belonging to the first multiplexing circuit MUX1 and the second multiplexing circuit MUX2 are connected in parallel. At this time, it is beneficial to improve the on-state current of the two first thin film transistors T10, reduce the risk of distortion of the data signal in the process of passing through the two first thin film transistors T10, and reduce the risk of residual display of the display substrate.

[0130] In some embodiments, referring to FIG. 8, the first signal line group 10 includes M first signal lines 11, and the second multiplexing circuit MUX2 is electrically connected with the M first signal lines 11, where M≥2. The display substrate 1100 includes one third signal line 31, and the third signal line 31 is electrically connected with the second multiplexing circuit MUX2.

[0131] At this time, the driving method of the display substrate further includes:

[0132] In the bright display mode, the second multiplexing circuit MUX2 controls the input signal line 41 and all the first signal lines 11 of the first signal line group 10 to be disconnected.

[0133] In the screen-off wake-up mode, the second multiplexing circuit MUX2 controls the electrical connection between the input signal line 41 and at least two first signal lines in the same period.

[0134] That is, in the case that the display substrate 1100 only includes one third signal line 31, and in the bright display mode, the second multiplexing circuit MUX2 does not work, and the electrical connection between the input signal line 41 and the first signal line 11 is controlled by the first multiplexing circuit MUX1. And in the screen-off wake-up mode, the second multiplexing circuit MUX2 simultaneously connects the input signal line 41 and all the first signal lines 11 of the first signal line group 10. At this time, in this way, the number of the third signal line group 30 can be greatly reduced, the control difficulty of the driving chip can be reduced, the structure of the display substrate 1100 can be simplified, and the width of the peripheral area can be reduced.

[0135] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can think of a combination or replacement between the embodiments, and a change or replacement of the technical features within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: Multiple input signal lines, multiple columns of pixel circuits, and multiple first signal line groups, wherein a first signal line group includes at least two first signal lines, and one first signal line is electrically connected to a column of the pixel circuits; as well as, Multiple first multiplexing circuits, each first multiplexing circuit being electrically connected to at least two first signal lines of an input signal line and a first signal line group, wherein the first multiplexing circuit controls the electrical connection of the input signal line to a first signal line at the same time. Multiple second multiplexing circuits, each second multiplexing circuit being electrically connected to one of the input signal lines and at least two of the first signal lines of a first signal line group, wherein the second multiplexing circuit controls the electrical connection of the input signal line to at least one of the first signal lines at the same time period; One of the input signal lines is electrically connected to a first multiplexing circuit and a second multiplexing circuit, respectively, and at least two of the first signal lines of a first signal line group are electrically connected to a first multiplexing circuit and a second multiplexing circuit, respectively.

2. The display substrate according to claim 1, wherein, The first signal line group includes M first signal lines, and both the first multiplexing circuit and the second multiplexing circuit are electrically connected to the M first signal lines, where M ≥ 2; The display substrate further includes N second signal line groups; each second signal line group includes M second signal lines, the M second signal lines of the second signal line group are electrically connected to a first multiplexed circuit, and one second signal line controls the electrical connection between one first signal line and the input signal line; N≥2; The plurality of first multiplexing circuits are alternately connected to N second signal line groups.

3. The display substrate according to claim 2, further comprising: P third signal line groups, each third signal line group comprising M third signal lines, wherein the M third signal lines of each third signal line group are electrically connected to a second multiplexing circuit, and one of the third signal lines controls the electrical connection between the input signal line and a first signal line; P≥1.

4. The display substrate according to claim 3, wherein, The number of the second signal line group is the same as the number of the third signal line group, and the plurality of second multiplexing circuits are alternately electrically connected to P of the third signal line groups.

5. The display substrate according to claim 3, wherein, The display substrate includes a third signal line group, and the plurality of second multiplexing circuits are all electrically connected to the third signal line group.

6. The display substrate according to claim 2, further comprising: A third signal line, which is electrically connected to the second multiplexing circuit, controls the electrical connection of the input signal line and M first signal lines that are electrically connected to the same second multiplexing circuit at the same time.

7. The display substrate according to any one of claims 1 to 6, wherein, Both the first multiplexing circuit and the second multiplexing circuit include a plurality of first thin-film transistors, one of the source and drain of the first thin-film transistors being electrically connected to the input signal line, and the other being electrically connected to the first signal line; at least one of the first thin-film transistors has a width-to-length ratio greater than or equal to 200μm / 3.5μm.

8. The display substrate according to any one of claims 1 to 6, wherein, Both the first multiplexing circuit and the second multiplexing circuit include a plurality of first thin-film transistors, one of the source and drain of the first thin-film transistors being electrically connected to the input signal line and the other being electrically connected to the first signal line; at least one of the first thin-film transistors has a width and length of 320μm / 3.5μm.

9. The display substrate according to claim 7 or 8, wherein, The plurality of first thin-film transistors are arranged in multiple rows along a first direction, at least two adjacent rows of first thin-film transistors partially overlap in the first direction, and adjacent two first thin-film transistors belonging to adjacent rows are staggered in the second direction; the first direction is the arrangement direction of a column of the pixel circuits, and the second direction is the arrangement direction of multiple columns of the pixel circuits.

10. The display substrate according to claim 9, wherein, The display substrate includes multiple gate lines, each gate line including a main body portion and a gate portion alternately connected along the second direction. Along the first direction, one end of the gate portion is flush with one end of the main body portion, and the other end of the gate portion protrudes from the edge of the main body portion. One gate line is connected to a row of first thin-film transistors, and one gate portion forms the gate of one first thin-film transistor. The gate portions of two adjacent gate lines protrude to the opposite sides of the main body in the first direction; the multiple gate lines are divided into multiple pairs, each pair including two adjacent gate lines, and the gate portions of the two gate lines in a pair protrude toward each other in a direction that approaches each other. Two rows of the first thin-film transistors connected to a pair of gate lines partially overlap in the first direction, while two rows of the first thin-film transistors connected to two adjacent pairs of adjacent gate lines do not overlap in the first direction.

11. The display substrate according to any one of claims 7 to 10, wherein, The first multiplexing circuit includes two of the first thin-film transistors; and / or, the second multiplexing circuit includes two of the first thin-film transistors.

12. The display substrate according to any one of claims 1 to 11, wherein, The input signal line is configured to be electrically connected to the driver chip; and / or, At least one of the pixel circuit, the first multiplexing circuit, and the second multiplexing circuit includes an oxide thin-film transistor.

13. A driving method for a display substrate as described in any one of claims 1 to 12, wherein the display substrate includes a screen-on display mode and a screen-off wake-up mode; the driving method includes: In the bright screen display mode, the first multiplexing circuit controls the electrical connection between the input signal line and a first signal line at the same time. In the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection between the input signal line and at least one of the first signal lines during the same time period.

14. The driving method according to claim 13, wherein, The first signal line group includes M first signal lines, and the second multiplexing circuit is electrically connected to the M first signal lines, where M ≥ 2; the display substrate also includes P third signal line groups; the third signal line group includes M third signal lines, and the second multiplexing circuit is electrically connected to the M third signal lines of the third signal line group; where P ≥ 1; The driving method includes: In the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection between the input signal line and one of the first signal lines during the same time period.

15. The driving method according to claim 14, wherein, The driving method further includes: In the bright screen display mode, the first multiplexing circuit and the second multiplexing circuit alternately control the electrical connection between the input signal line and one of the first signal lines in different display frames.

16. The driving method according to claim 14 or 15, wherein, The driving method further includes: In the screen-off wake-up mode, both the first multiplexing circuit and the second multiplexing circuit control the electrical connection between the same input signal line and the same first signal line during the same time period, and the first multiplexing circuit and the second multiplexing circuit control the electrical connection between the same input signal line and different first signal lines during different time periods within a frame period.

17. The driving method according to claim 13, wherein, The first signal line group includes M first signal lines, and the second multiplexing circuit is electrically connected to the M first signal lines, where M ≥ 2; the display substrate includes a third signal line, which is electrically connected to the second multiplexing circuit. The driving method further includes: In the bright screen display mode, the second multiplexing circuit controls the circuit between at least two first signal lines of the input signal line and the signal line group to be cut off; In the screen-off wake-up mode, the second multiplexing circuit controls the electrical connection of at least two first signal lines of the input signal line and a signal line group during the same time period.

18. A display device, comprising: The display substrate as described in any one of claims 1 to 12; The driver chip is electrically connected to the input signal line of the display substrate and is configured to transmit data signals to the data signal terminal.

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