Processing result write-back method and system

Abstract

The present application relates to the field of write-back of processor results, and to a processing result write-back method and system. The method comprises: using a transition cache unit to receive a processing result from at least one processing core, and on the basis of a FIFO algorithm, writing the processing result into a target memory. By performing unified scheduling on write-back operations of a plurality of processing cores by means of the transition cache unit and the FIFO algorithm, the transition cache unit reduces direct data exchange between the plurality of processing cores and the target memory, thereby reducing the probability of conflicts.

Description

Processing result write-back method and system TECHNICAL FIELD

[0001] The present application relates to the field of processing result write-back, and in particular to a processing result write-back method and system. BACKGROUND

[0002] When a processor executes an instruction, it directly reads the required data from the main memory, and after the operation is completed, the result is written back to the main memory.

[0003] With the popularity of multi-core processors, multiple processing cores simultaneously interact with the main memory. In particular, when one or more processing cores read data from the main memory and one or more processing cores write data to the main memory, data transmission conflicts and efficiency may be caused. SUMMARY

[0004] In order to reduce data transmission conflicts, the present application provides a processing result write-back method and system.

[0005] In a first aspect, the present application provides a processing result write-back method, comprising:

[0006] receiving processing results from at least one processing core using a transition cache unit,

[0007] writing the processing results to a target memory.

[0008] By adopting the above technical solution, the transition cache unit reduces direct data interaction between multiple processing cores and the target memory, and reduces the probability of conflict.

[0009] Preferably, writing the processing results to the target memory is implemented based on a FIFO algorithm.

[0010] By adopting the above technical solution, the processing results are sorted according to the FIFO algorithm, and the processing results are sequentially written to the target memory according to the sorting results, ensuring that only one processing result is written at a time, thereby reducing write conflicts.

[0011] Preferably, the processing results include address data and result data, and writing the processing results to the target memory includes writing the result data to the target memory based on the address data.

[0012] In a second aspect, the present application provides a processing result write-back system, comprising a transition cache unit and a target memory, the transition cache unit being configured to receive processing results from at least one processing core and write the processing results to the target memory.

[0013] By adopting the above technical solution, the transition cache unit reduces direct data interaction between multiple processing cores and the target memory, and reduces the probability of conflict.

[0014] Preferably, the processing result write-back system further comprises a plurality of processing cores, and the processing results of all the processing cores are sent to the transition cache unit.

[0015] By adopting the above technical solution, the transition cache unit receives the processing results of all the processing cores, avoids direct data interaction between all the processing cores and the target memory, and reduces the conflict probability.

[0016] Preferably, the transition cache unit is configured to write the processing results into the target memory based on a FIFO algorithm.

[0017] By adopting the above technical solution, the processing results are sorted according to the FIFO algorithm, and the processing results are written into the target memory in sequence according to the sorting result, so that only one processing result is written at a time, and the write conflict is reduced.

[0018] Preferably, the processing result comprises address data and result data, and the transition cache unit is configured to write the result data into the target memory based on the address data.

[0019] In summary, the present application has at least one of the following beneficial effects:

[0020] 1. The transition cache unit is introduced to receive the processing results of all the processing cores, so that the processing results can be efficiently and stably received and stored;

[0021] 2. The FIFO algorithm is applied in the transition cache unit to ensure that the processing results are written back to the target memory in the correct order;

[0022] 3. The write-back operations of multiple processing cores are uniformly scheduled by the transition cache unit and the FIFO algorithm, the transition cache unit reduces the direct data interaction between multiple processing cores and the target memory, and the conflict probability is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0023] Fig. 1 is a structural block diagram of a processing result write-back system.

[0024] Reference signs: 1, processing core; 2, main memory; 3, transition cache unit. DETAILED DESCRIPTION

[0025] The present application will be further described in detail below with reference to the accompanying drawings.

[0026] Referring to Fig. 1, the present application discloses a processing result write-back system, which comprises a processing core 1, a main memory 2, a transition cache unit 3 and a target memory.

[0027] The processing core 1 is provided with multiple. The processing core 1 is used for reading required data directly from the main memory 2 when executing instructions. All processing cores 1 send processing results to the transition cache unit 3 after operation is completed. The processing results include address data and result data.

[0028] The transition cache unit 3 is used for receiving processing results from at least one processing core 1. The transition cache unit 3 is used for writing the processing results into a target memory based on a FIFO algorithm.

[0029] Specifically, the transition cache unit 3 is used for writing the result data into the target memory based on the address data. The target memory is determined based on the address data. The target memory can be the main memory 2 or other designated memory.

[0030] The embodiment of the application further discloses a processing result write-back method, comprising:

[0031] The processing result write-back method comprises the following steps:

[0032] The processing result write-back method comprises the following steps:

[0033] The processing result write-back method comprises the following steps:

[0034] The processing result write-back method comprises the following steps:

[0035] The transition cache unit 3 is introduced to receive processing results of all processing cores 1, so that the processing results can be efficiently and stably received and stored;

[0036] The FIFO algorithm is applied in the transition cache unit 3, so that the processing results can be written back to the target memory in correct order;

[0037] The transition cache unit 3 and the FIFO algorithm are used to uniformly schedule write-back operations of multiple processing cores 1. The transition cache unit 3 reduces direct data interaction between the multiple processing cores 1 and the target memory, and reduces the conflict probability.

[0038] The above are preferred embodiments of the application, and do not limit the protection scope of the application. Any equivalent changes made on the basis of the structure, shape and principle of the application should be covered within the protection scope of the application.

Claims

1. A method for writing back processing results, characterized in that, include: The processing results from at least one processing core (1) are received using a transition buffer unit (3). The processing result is written to the target memory.

2. The method for writing back the processing result according to claim 1, characterized in that, The process of writing the processing result into the target memory is implemented based on the FIFO algorithm.

3. The method for writing back the processing result according to claim 1, characterized in that, The processing result includes address data and result data, and The step of writing the processing result into the target memory includes: The result data is written to the target memory based on the address data.

4. A system for writing back processing results, characterized in that, It includes a transition cache unit (3) and a target memory, wherein the transition cache unit (3) is used to receive processing results from at least one processing core (1) and write the processing results into the target memory.

5. The system for writing back the processing result according to claim 4, characterized in that, It also includes several processing cores (1). The processing results of all the processing cores (1) are sent to the transition buffer unit (3).

6. The system for writing back the processing result according to claim 4, characterized in that, The transition buffer unit (3) is used to write the processing result into the target memory based on the FIFO algorithm.

7. The system for writing back the processing result according to claim 4, characterized in that, The processing result includes address data and result data. The transition cache unit (3) is used to write the result data into the target memory based on the address data.

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