Miniaturized diode

Abstract

The present application provides a miniaturized diode, comprising a first semiconductor layer, an I-type semiconductor layer, a second semiconductor layer, an electrode layer, and a dielectric layer, wherein the dielectric layer and the second semiconductor layer are located between the electrode layer and the I-type semiconductor layer; a first electrode in the electrode layer is located on the side of the second semiconductor layer facing away from the first semiconductor layer, and a field plate in the electrode layer is located on the side of the dielectric layer facing away from the first semiconductor layer; an isolation portion formed of an insulating material is provided in the I-type semiconductor layer, the isolation portion has a first orthographic projection on the surface of the first semiconductor layer, the first electrode has a second orthographic projection on the surface of the first semiconductor layer, and the first orthographic projection surrounds the second orthographic projection. A field limiting ring is omitted by means of the field plate and the isolation portion, and the miniaturization of a semiconductor device is achieved; and the isolation portion can increase the reserved space of a scribe region, reduce the risk of electric leakage, and improve the reliability and stability of the semiconductor device.

Description

A miniaturized diode

[0001] Cross-reference to Related Applications

[0002] This application claims priority to the Chinese Patent Application No. 202410875164.2, filed on June 29, 2024, and entitled "A miniaturized diode", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of semiconductor technology, and in particular to a miniaturized diode. BACKGROUND

[0004] The current high-voltage and high-power diode includes an N-type semiconductor layer, a P-type semiconductor layer and an electrode layer which are sequentially stacked, and the electrode layer is provided with a connected anode and a field plate; wherein the diode includes two types of stepped and planar, for the stepped diode, the P-type semiconductor layer can be etched into the N-type semiconductor layer, thereby forming a step, the dielectric protection film continuously covers the side and bottom surfaces of the step, and the field plate continuously covers part of the dielectric protection film, forming a stepped field plate; although the diode of this structure can improve the breakdown resistance, there is a problem of PN junction field area diffusing to the scribing area, which leads to the need to reserve a larger space for the scribing area, and also increases the risk of leakage, ultimately leading to the difficulty in realizing the miniaturization of the diode, and may also reduce the stability and reliability of the diode. For the planar diode, the P-type semiconductor layer can be formed in the upper surface of the N-type semiconductor layer, and the field plate can be replaced by a field limiting ring, the field limiting ring is generally provided with multiple and formed in the upper surface of the N-type semiconductor layer by ion implantation, and the field limiting ring is located at the periphery of the P-type semiconductor layer, which leads to a larger area of the terminal area including the field limiting ring, which is not conducive to the miniaturization of the diode.

[0005] Therefore, how to reduce the occupied area of the terminal area, realize the miniaturization of the diode, and improve the stability and reliability of the diode has become a problem to be solved. SUMMARY

[0006] The present application provides a miniaturized diode, which not only can reduce the occupied area of the terminal area, realize the miniaturization of the diode, but also can improve the stability and reliability of the diode.

[0007] In a first aspect, an embodiment of the present application provides a semiconductor device, which can include: a first semiconductor layer, an I-type semiconductor layer, a second semiconductor layer and an electrode layer which are sequentially stacked, the first semiconductor layer and the second semiconductor layer being different in doping type; the semiconductor device further includes a dielectric layer which is located between the electrode layer and the I-type semiconductor layer in parallel with the second semiconductor layer; the electrode layer includes a first electrode and a field plate which are connected, the first electrode being located on a side of the second semiconductor layer away from the first semiconductor layer, and the field plate being located on a side of the dielectric layer away from the first semiconductor layer; the I-type semiconductor layer is provided with an isolation portion formed of an insulating material, the isolation portion having a first orthogonal projection on a surface of the first semiconductor layer, and the first electrode having a second orthogonal projection on the surface of the first semiconductor layer, the first orthogonal projection surrounding the second orthogonal projection.

[0008] In the prior art, the field limiting ring can reduce the electric field peak value of the active region and improve the breakdown resistance, but the setting of the field limiting ring occupies a large terminal area (for example, the field limiting ring is usually formed by ion implantation, which occupies a large area; in addition, a space is required between multiple field limiting rings, which occupies more area), which makes it impossible to realize the miniaturization design of the semiconductor device. In the present application, the field plate is spaced apart from the I-type semiconductor layer by the dielectric layer, so that the field plate can also reduce the electric field peak value of the active region and improve the breakdown resistance. In addition, the isolation portion can isolate the space charge region and the scribing area, and isolate the active region and the scribing area, so that the PN junction field region avoids diffusing to the scribing area, thereby greatly increasing the reserved space of the scribing area and effectively reducing the risk of electric leakage. In this way, by setting the field plate and the isolation portion, the electric field peak value can be reduced and the breakdown resistance can be improved, and the risk of electric leakage can be reduced, so that the requirements for reliability and stability of the semiconductor device (such as a diode) can be met. At the same time, under the condition of meeting the requirements for reliability and stability, since the field limiting ring does not need to be set, the problem of area increase caused by setting the field limiting ring can be avoided, so that the occupied area of the terminal region can be reduced to realize the miniaturization of the semiconductor device.

[0009] Illustratively, the field limiting ring is usually located in the semiconductor layer, and is generally formed in the semiconductor layer by an ion implantation device. Since the field limiting ring does not need to be set, the ion implantation device is not needed to manufacture the field limiting ring. In the present application, the isolation portion can be made of an insulating material, and the field plate is part of the electrode layer, so the field plate can be made of a conductive material. Therefore, the isolation portion and the field plate do not need to be prepared by the ion implantation device, so that the manufacturing cost of the semiconductor device can be reduced, the manufacturing difficulty can be reduced, and the manufacturing method of the second semiconductor layer is not limited, and any method that can be implemented can be used.

[0010] It should be understood that the semiconductor device comprises an active region, a terminal region and a dicing region, the terminal region surrounds the active region, and the dicing region is located between the terminal regions of two adjacent semiconductor devices to facilitate cutting to form independent chips; taking the first semiconductor layer as an N-type semiconductor layer and the second semiconductor layer as a P-type semiconductor layer as an example, at this time, the I-type semiconductor layer and the N-type semiconductor layer are both N-type doped layers, only the doping concentration of the I-type semiconductor layer is different from that of the N-type semiconductor layer, and the doping concentration of the N-type semiconductor layer is higher than that of the I-type semiconductor layer. At this time, the active region is the region where the P-type semiconductor layer is located, the space charge region is the region where the interface between the P-type semiconductor layer and the I-type semiconductor layer is located, and the terminal region is the region where the field plate and the isolation portion are located. Alternatively, the first semiconductor layer can also be a P-type semiconductor layer, and correspondingly, the second semiconductor layer is an N-type semiconductor layer, which is not shown in the figure, the I-type semiconductor layer and the P-type semiconductor layer are both P-type doped layers, only the doping concentration of the I-type semiconductor layer is different from that of the P-type semiconductor layer, and the doping concentration of the P-type semiconductor layer is higher than that of the I-type semiconductor layer. At this time, the active region is the region where the N-type semiconductor layer is located, the space charge region is the region where the interface between the N-type semiconductor layer and the I-type semiconductor layer is located, and the terminal region is the region where the field plate and the isolation portion are located.

[0011] Furthermore, the side surface of the first semiconductor layer away from the I-type semiconductor layer can be provided with a second electrode; if the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, the first electrode is an anode, and the second electrode is a cathode; if the first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, the first electrode is a cathode, and the second electrode is an anode.

[0012] For the first electrode and the field plate, the part of the electrode layer corresponding to the second semiconductor layer is the first electrode, the part of the electrode layer corresponding to the dielectric layer is the field plate, and the whole formed by the direct connection of the first electrode and the field plate is the electrode layer, so the first electrode and the field plate can be regarded as two parts of the whole electrode located on different structures, and the two parts can be formed in the same manufacturing process, only the effects are different because they are located on different structures, and then the two parts are named as the first electrode and the field plate respectively.

[0013] Optionally, the height of the isolation portion can be set to be equal to the thickness of the I-type semiconductor layer, that is, the isolation portion penetrates the I-type semiconductor layer along the thickness direction of the I-type semiconductor layer, so that the space charge region and the dicing region can be effectively isolated, and the active region and the dicing region can be effectively isolated, thereby effectively improving the withstand voltage of the semiconductor device. Alternatively, the height of the isolation portion can also be set to be less than the thickness of the I-type semiconductor layer, and the isolation portion is located on the side of the I-type semiconductor layer facing the electrode layer, so that the space charge region and the dicing region can be isolated, and the active region and the dicing region can be isolated, and the manufacturing difficulty of the isolation portion can be reduced, and the manufacturing cost can be reduced.

[0014] In addition, the width of the isolation portion can be set to 1-10 microns, and can be set according to actual needs, which is not limited herein. For example, when the width of the isolation portion is small, the manufacturing difficulty can be increased, and therefore, the width of the isolation portion can be set to be larger to reduce the manufacturing difficulty. When the width of the isolation portion is large, the size of the termination region and the semiconductor device can be increased, and therefore, the width of the isolation portion can be set to be smaller to reduce the size of the semiconductor device.

[0015] Optionally, the field plate can include the following settings:

[0016] Setting 1: planar field plate.

[0017] Exemplarily, the field plate can be set as a planar field plate. The field plate of this structure is different from the stepped field plate and the double-layer field plate. The field plate of this structure is characterized in that it is arranged in a flat plate shape on the side surface of the dielectric layer away from the substrate, and the side surface of the dielectric layer away from the substrate is a flat surface. In this way, the field plate can improve the breakdown voltage of the semiconductor device, reduce the electric field peak of the PN junction, improve the performance of the semiconductor device, and reduce the manufacturing difficulty and cost of the semiconductor device.

[0018] At this time, the positional relationship between the isolation portion and the field plate can include: the isolation portion and the field plate do not overlap in the orthographic projection on the surface of the first semiconductor layer, and the distance between the first orthographic projection toward one side of the second orthographic projection and the orthographic projection of the field plate on the surface of the first semiconductor layer can be set to be greater than 0 and not greater than 10 microns, so as to reduce the size of the termination region and the semiconductor device. Alternatively, the side edge of the orthographic projection of the isolation portion on the surface of the first semiconductor layer (i.e., the first orthographic projection) toward the second semiconductor layer is a first edge, the side edge of the orthographic projection of the field plate on the surface of the first semiconductor layer away from the first electrode is a second edge, and the first edge overlaps the second edge. Alternatively, the second edge is located in the first orthographic projection. Alternatively, the first orthographic projection is located in the orthographic projection of the field plate on the surface of the first semiconductor layer. The positional relationship between the isolation portion and the field plate can be set according to actual needs to meet the needs of different application scenarios.

[0019] Setting 2: stepped field plate.

[0020] Exemplarily, the medium layer is provided with a groove on the side surface facing the field plate, the groove surrounds the first electrode, and the part of the field plate is located in the groove. The corner of the second semiconductor layer facing the medium layer and the I-type semiconductor layer is a breakdown weak area. Since a part of the step-type field plate is located in the groove, the step-type field plate is closer to the breakdown weak area, can effectively protect the breakdown weak area, and reduce the electric field peak value of the breakdown weak area, so as to further improve the withstand voltage performance of the semiconductor device, so as to be suitable for use in a high-voltage scene. Moreover, the step-type field plate in the embodiment of the present application does not need to etch the I-type semiconductor layer and the first semiconductor layer when being manufactured, so as to reduce the process difficulty of etching and improve the etching efficiency.

[0021] Further, the groove has a third orthographic projection on the surface of the first semiconductor layer, the first orthographic projection surrounds the third orthographic projection, that is, the first orthographic projection is a closed structure surrounding the third orthographic projection, in other words, the isolation portion surrounds the groove, and the groove surrounds the first electrode, so that the isolation portion is located on the side of the groove away from the second semiconductor layer; if the side of the groove away from the second semiconductor layer is regarded as the outer side of the groove, and the side of the groove facing the second semiconductor layer is regarded as the inner side of the groove, the isolation portion is located on the outer side of the groove, so as to effectively isolate the space charge region and the scribe region, and isolate the active region and the scribe region, further reduce the risk of electric leakage, and further improve the withstand voltage value, reliability and stability of the semiconductor device, so as to achieve the design requirement of the withstand voltage in a smaller area.

[0022] Moreover, the distance between the bottom surface of the groove and the I-type semiconductor layer can be set to 0.1 μm-3 μm, so that the part of the field plate located in the groove can effectively protect the breakdown weak area, avoid the protection effect on the breakdown weak area being reduced due to the field plate being far away from the breakdown weak area, and further improve the withstand voltage performance of the semiconductor device. The specific value of the distance between the bottom surface of the groove and the I-type semiconductor layer can be set according to actual needs, which is not limited herein. Moreover, the thickness of the second semiconductor layer can be not less than 3 μm, but the upper limit of the thickness of the second semiconductor layer can be set according to actual needs, which is not limited herein.

[0023] Setting mode three: double-layer type field plate.

[0024] Exemplarily, the conductive part is arranged in the medium layer and surrounds the first electrode, and the conductive part is connected with the electrode layer. The conductive part in the double-layer field plate is closer to the breakdown weak area, can effectively protect the breakdown weak area, reduce the electric field peak value of the breakdown weak area, and thus can further improve the withstand voltage performance of the semiconductor device, so as to be suitable for use in high-voltage scenes. Moreover, the double-layer field plate in the embodiment of the present application does not need to etch the I-type semiconductor layer and the first semiconductor layer when being manufactured, so as to reduce the process difficulty of etching and improve the etching efficiency.

[0025] Further, the conductive part has a fourth orthographic projection on the first semiconductor layer, and the first orthographic projection surrounds the fourth orthographic projection, that is, the first orthographic projection is a closed structure surrounding the fourth orthographic projection, in other words, the isolation part surrounds the conductive part, and the conductive part surrounds the first electrode, so that the isolation part is located on the side of the conductive part away from the second semiconductor layer; if the side of the conductive part away from the second semiconductor layer is regarded as the outer side of the conductive part, and the side of the conductive part toward the second semiconductor layer is regarded as the inner side of the conductive part, the isolation part is located on the outer side of the conductive part, which can effectively isolate the space charge region and the scribing area, and isolate the active area and the scribing area, further reduce the risk of electric leakage, and further improve the withstand voltage, reliability and stability of the semiconductor device, so as to achieve the design requirement of withstand voltage in a smaller area.

[0026] Moreover, the positional relationship between the conductive part and the field plate can include that the orthographic projection of the conductive part on the first semiconductor layer is located in the orthographic projection of the field plate on the first semiconductor layer; or the orthographic projection of the conductive part on the first semiconductor layer partially overlaps with the orthographic projection of the field plate on the first semiconductor layer; or the orthographic projection of the conductive part on the first semiconductor layer does not overlap with the orthographic projection of the field plate on the first semiconductor layer. That is, when the orthographic projection of the conductive part on the first semiconductor layer is located in the orthographic projection of the field plate on the first semiconductor layer, and the orthographic projection of the conductive part on the first semiconductor layer partially overlaps with the orthographic projection of the field plate on the first semiconductor layer, the orthographic projection of the conductive part on the first semiconductor layer can overlap with the orthographic projection of the field plate on the first semiconductor layer, which can reduce the occupied area of the terminal area, and thus can reduce the size of the semiconductor device.

[0027] In addition, the distance between the conductive part and the I-type semiconductor layer can be set to 0.1-3 μm. In this way, the breakdown weak area located in the conductive part can be effectively protected, and the protection effect of the breakdown weak area can be reduced due to the long distance between the conductive part and the breakdown weak area, so as to further improve the withstand voltage performance of the semiconductor device. The specific value of the distance between the conductive part and the I-type semiconductor layer can be set according to actual needs, which is not limited herein. Moreover, the thickness of the second semiconductor layer can be not less than 3 μm, but the upper limit of the thickness of the second semiconductor layer can be set according to actual needs, which is not limited herein.

[0028] In summary, when the field plate is arranged, any one of the above setting mode one, setting mode two and setting mode three can be selected according to actual needs, and the specific limitation is not made here to meet the needs of different application scenarios.

[0029] Optionally, the material for manufacturing the electrode layer can include any conductive material known to those skilled in the art, for example but not limited to, the material for manufacturing the electrode layer includes: metal aluminum, metal copper, metal silver, etc., and the specific limitation is not made here.

[0030] Optionally, the thickness of the first semiconductor layer at any position can be set to be the same, or the thickness of the corresponding part of the first semiconductor layer to the second semiconductor layer can be greater than that of the remaining part, so that the side surface of the first semiconductor layer towards the I-type semiconductor layer is a stepped surface. Similarly, the thickness of the I-type semiconductor layer at any position can also be set to be the same, or the thickness of the corresponding part of the I-type semiconductor layer to the second semiconductor layer can be greater than that of the remaining part, so that the side surface of the I-type semiconductor layer towards the second semiconductor layer is a stepped surface, or when the side surface of the first semiconductor layer towards the I-type semiconductor layer is a stepped surface, the thickness of the corresponding part of the I-type semiconductor layer to the second semiconductor layer can also be less than that of the remaining part, so that the side surface of the I-type semiconductor layer towards the second semiconductor layer is a flat surface. The thickness of the first semiconductor layer and the I-type semiconductor layer can be set according to actual needs, and the specific limitation is not made here.

[0031] In a second aspect, the embodiments of the present application also provide a manufacturing method of a semiconductor device, which is used to manufacture the semiconductor device as introduced in the above first aspect and any one of the embodiments of the first aspect. The manufacturing method can include: sequentially forming an I-type semiconductor layer and a second semiconductor layer on a first semiconductor layer; wherein the doping types of the first semiconductor layer and the second semiconductor layer are different; performing etching processing on the second semiconductor layer, retaining the second semiconductor layer in the active region, etching away the second semiconductor layer outside the active region and exposing the I-type semiconductor layer; etching the exposed I-type semiconductor layer, so that a hole structure for manufacturing an isolation part is formed in the exposed I-type semiconductor layer, and the hole structure surrounds the second semiconductor layer; forming a dielectric layer, so that the dielectric layer is located on the exposed I-type semiconductor layer, the manufacturing material of the dielectric layer fills the hole structure, and thus the filled hole structure serves as the isolation part; forming an electrode layer, wherein the electrode layer located on the second semiconductor layer is a first electrode, and the electrode layer located on the dielectric layer is a field plate. Exemplarily, the material for forming the dielectric layer can be but not limited to any insulating material, so that the hole structure is filled with insulating material, and thus the hole structure filled with insulating material can form the isolation part.

[0032] Therefore, by arranging the field plate and the isolation portion, the withstand voltage of the semiconductor device can be improved, the reliability and stability of the semiconductor device can be improved, and the area of the terminal region can be reduced, thereby realizing the miniaturization design of the semiconductor device.

[0033] Optionally, the method for forming the dielectric layer can include the following methods.

[0034] The first method can include: forming a first insulating layer with a first thickness, and performing etching treatment on the first insulating layer, so as to etch away the first insulating layer in the active region and retain the first insulating layer outside the active region; wherein the material of the first insulating layer fills the hole structure, so that the filled hole structure serves as the isolation portion; the first thickness is less than the thickness of the second semiconductor layer; forming a second insulating layer with a second thickness, and performing etching treatment on the second insulating layer, so as to etch away the second insulating layer in the active region and retain the second insulating layer outside the active region, and form a through hole penetrating along the thickness direction of the second insulating layer outside the active region; wherein the sum of the first thickness and the second thickness is equal to the thickness of the second semiconductor layer, the first insulating layer and the second insulating layer outside the active region constitute the dielectric layer, and the through hole is used to form the groove in the dielectric layer. At this time, when the field plate is formed, part of the field plate is located in the groove, and the other part extends out of the groove, so that the field plate is a stepped field plate, thereby further improving the withstand voltage performance of the semiconductor device, so as to be suitable for use in high-voltage scenarios.

[0035] In the first method, the material of the first insulating layer and the second insulating layer is different, and under the same etching condition, the etching rate of the first insulating layer is greater than the etching rate of the second insulating layer, so that the first insulating layer can serve as the etching stop layer of the second insulating layer, thereby avoiding the over-etching phenomenon and improving the operability of the production. Alternatively, the material of the first insulating layer and the second insulating layer can be the same, and at this time, the probability of over-etching can be reduced by controlling the etching rate.

[0036] The second kind: the forming process can include: forming a first insulating layer with a first thickness, and performing etching treatment on the first insulating layer, etching away the first insulating layer in the active region, and retaining the first insulating layer outside the active region; wherein the material of the first insulating layer fills the hole structure, so that the filled hole structure serves as an isolation part; the first thickness is smaller than the thickness of the second semiconductor layer; forming a conductive layer, and performing etching treatment on the conductive layer to form a conductive part on the first insulating layer in the terminal; forming a second insulating layer with a second thickness, and performing etching treatment on the second insulating layer, etching away the second insulating layer in the active region, retaining the second insulating layer outside the active region, and forming a through hole penetrating along the thickness direction of the second insulating layer outside the active region; wherein the sum of the first thickness and the second thickness is equal to the thickness of the second semiconductor layer, the first insulating layer and the second insulating layer outside the active region constitute a dielectric layer, and the through hole exposes the conductive part. At this time, when the field plate is formed, the material of the field plate can fill the through hole to realize the electrical connection between the field plate and the conductive part, so that the field plate is a double-layer field plate, thereby further improving the withstand voltage performance of the semiconductor device, so as to be suitable for use in high-voltage scenes.

[0037] Similarly, in the forming process of the second kind, the material setting of the first insulating layer and the second insulating layer can refer to the related introduction in the forming process of the first kind, and the repeated parts will not be described herein.

[0038] Of course, the forming process of the dielectric layer is not limited to the first kind and the second kind given above, but can also be other ways that can be realized by those skilled in the art, which are not limited herein.

[0039] Optionally, the manufacturing method can further include: forming a second electrode on the side of the first semiconductor layer away from the I-type semiconductor layer, thereby forming a semiconductor device such as a diode.

[0040] It should be understood that, since the principle of solving the problem of the manufacturing method is similar to the principle of solving the problem of the semiconductor device, the implementation and technical effects of the manufacturing method can refer to the implementation and technical effects of the semiconductor device, and the repeated parts will not be described herein.

[0041] In a third aspect, the embodiments of the present application also provide an electronic device, which can include: a shell, and a semiconductor device as described in the first aspect and any one of the embodiments of the first aspect, and the semiconductor device is arranged in the shell. In this way, on the basis of the improved performance of the semiconductor device, the performance of the electronic device is also improved.

[0042] It should be understood that, since the principle of solving the problem of the electronic device is similar to the principle of solving the problem of the semiconductor device, the implementation and technical effects of the electronic device can refer to the implementation and technical effects of the semiconductor device, and the repeated parts will not be described herein. BRIEF DESCRIPTION OF DRAWINGS

[0043] Fig. 1 is a structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0044] Fig. 2 is a structural schematic diagram of a step-type diode provided by the prior art;

[0045] Fig. 3 is a structural schematic diagram of a planar diode provided by the prior art;

[0046] Fig. 4 is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application;

[0047] Fig. 5 is a sectional view of Fig. 4 along the direction of n1-n2;

[0048] Fig. 6 is a schematic diagram of the positional relationship between a field plate and an isolation portion provided by an embodiment of the present application;

[0049] Fig. 7 is a structural schematic diagram of another semiconductor device provided by an embodiment of the present application;

[0050] Fig. 8 is a sectional view of Fig. 7 along the direction of n3-n4;

[0051] Fig. 9 is a sectional view of a semiconductor device provided by an embodiment of the present application;

[0052] Fig. 10 is a sectional view of another semiconductor device provided by an embodiment of the present application;

[0053] Fig. 11 is a potential distribution diagram of a diode provided by an embodiment of the present application and provided with an isolation portion and a double-layer field plate;

[0054] Fig. 12 is a potential distribution diagram of a diode provided by an embodiment of the present application and not provided with an isolation portion;

[0055] Fig. 13 is a test diagram of a leakage current provided by an embodiment of the present application;

[0056] Fig. 14 is a manufacturing flowchart of a semiconductor device provided by an embodiment of the present application.

[0057] Reference signs: 10-first semiconductor layer, 20-I-type semiconductor layer, 30-second semiconductor layer, 40-electrode layer, 41-first electrode, 42-field plate, 50- dielectric layer, 51-trench, 60-isolation portion, 70-second electrode, 80-conductive portion, Q1-active region, Q2-terminal region, Q3-dicing region, T1-first orthogonal projection, T2-second orthogonal projection, T3-third orthogonal projection, y1-first edge, y2-second edge, b1-side wall of the trench close to the second semiconductor layer, b2-trench bottom, b3-side wall of the trench away from the second semiconductor layer, b4, b5-surfaces of the dielectric layer away from the I-type semiconductor layer, 100-housing, 200-circuit board, 300-semiconductor device. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0059] It should be noted that the same reference numerals in the accompanying drawings of this application denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but may be modified as needed, and all such modifications are included within the scope of protection of this application. The accompanying drawings of this application are for illustrating relative positional relationships only and do not represent actual scale.

[0060] To facilitate understanding of the technical solutions provided in the embodiments of this application, the application scenarios will be explained first below.

[0061] The semiconductor devices provided in this application can be widely used in various electronic devices. These electronic devices can include various terminal devices and electronic components. Terminal devices may include, but are not limited to, smartphones, smart TVs, smart TV set-top boxes, smartwatches, personal computers (PCs), wearable devices, smart broadband devices, etc. Electronic components may include, but are not limited to, wireless networks, fixed networks, servers, and other telecommunications equipment, as well as chip modules, memory devices, etc., which are not listed here.

[0062] Figure 1 illustrates a schematic diagram of a semiconductor device applied within an electronic device. Referring to Figure 1, the electronic device includes a housing 100 and a circuit board 200 disposed within the housing 100, with the semiconductor device 300 mounted on the circuit board 200. Taking a MIMO (Multiple-Input Multiple-Output) base station in a wireless network as an example, the semiconductor device can be a diode with high voltage and high power performance. This type of diode can be used in RF switches, transceiver switching switches, or phase shifter switches in a MIMO base station. Current high-voltage, high-power diodes include: an N-type semiconductor layer, a P-type semiconductor layer, and an electrode layer stacked sequentially. The electrode layer contains a connected anode and a field plate. The diodes include stepped and planar types.

[0063] Referring to the step-type diode shown in FIG. 2, the P-type semiconductor layer can be etched into the N-type semiconductor layer to form a step (as shown by the dashed line in FIG. 2), the dielectric protection film continuously covers the side surface and the bottom surface of the step, and the field plate continuously covers part of the dielectric protection film to form a step-type field plate. Although the diode with such a structure can improve the breakdown resistance, the PN junction field region diffuses to the scribe region, which leads to the need to reserve a large space for the scribe region and increases the risk of electric leakage, ultimately adversely affecting the miniaturization of the diode and possibly reducing the stability and reliability of the diode.

[0064] Referring to the planar diode shown in FIG. 3, the P-type semiconductor layer can be formed on the upper surface of the N-type semiconductor layer, where the upper surface of the N-type semiconductor layer can be understood as the side surface of the N-type semiconductor layer away from the cathode shown in FIG. 3, and the field plate can be replaced by a field limiting ring, which is generally provided with a plurality of field limiting rings formed on the upper surface of the N-type semiconductor layer by ion implantation, and the field limiting ring is located at the periphery of the P-type semiconductor layer, which leads to a large area of the terminal region including the field limiting ring, which is not conducive to the miniaturization of the diode.

[0065] Therefore, the embodiments of the present application provide a semiconductor device such as a diode, which can not only reduce the occupied area of the terminal region to realize the miniaturization of the diode, but also improve the stability and reliability of the diode.

[0066] The embodiments will be described below in conjunction with specific examples.

[0067] FIGS. 4 and 5 exemplarily show a structure of a semiconductor device provided by the present application, referring to FIGS. 4 and 5, FIG. 5 is a cross-sectional view along the direction of n1-n2 shown in FIG. 4, the semiconductor device can include a first semiconductor layer 10, an I-type semiconductor (i.e., intrinsic semiconductor) layer 20, a second semiconductor layer 30 and an electrode layer 40 which are sequentially stacked, the doping type of the first semiconductor layer 10 is different from that of the second semiconductor layer 30; the semiconductor device further includes a dielectric layer 50 which is located between the electrode layer 40 and the I-type semiconductor layer 20 side by side with the second semiconductor layer 30, the thickness of the dielectric layer 50 and the second semiconductor layer 30 can be the same, of course, they can also be different, which can be set according to actual needs, and here is not specifically limited.

[0068] The electrode layer 40 includes the connected first electrode 41 and the field plate 42, the first electrode 41 is located on the side of the second semiconductor layer 30 away from the first semiconductor layer 10, and the field plate 42 is located on the side of the dielectric layer 50 away from the first semiconductor layer 10; wherein the part of the electrode layer 40 corresponding to the second semiconductor layer 30 (i.e. the part of the electrode layer 40 whose vertical projection coincides with the second semiconductor layer 30) is the first electrode 41, and the part of the electrode layer 40 remaining after removing the first electrode 41 is the field plate 42, and the whole formed by the direct connection of the first electrode 41 and the field plate 42 is the electrode layer 40, so the first electrode 41 and the field plate 42 can be regarded as two parts of the whole electrode located on different structures, and the two parts are usually formed in the same manufacturing process, but because they are located on different structures, their functions are different, and then the two parts are named as the first electrode 41 and the field plate 42 respectively, and different patterns are used in FIG. 4 and FIG. 5, which is only used to distinguish the first electrode 41 and the field plate 42, and does not mean that the manufacturing materials of the first electrode 41 and the field plate 42 are different.

[0069] The I-type semiconductor layer 20 is provided with an isolation part 60 formed by an insulating material, the isolation part 60 has a first orthographic projection T1 on the surface of the first semiconductor layer 10, the first electrode 41 has a second orthographic projection T2 on the surface of the first semiconductor layer 10, the first orthographic projection T1 surrounds the second orthographic projection T2, in other words, the first orthographic projection T1 is a closed structure surrounding the second orthographic projection T2, and the outline shape of the first orthographic projection T1 and the second orthographic projection T2 is not limited to the quadrilateral shown in FIG. 4, but can also be circular, elliptical or other shapes, which can be designed according to actual needs.

[0070] It should be understood that, as shown in FIG. 4 and FIG. 5, the semiconductor device comprises an active region Q1, a termination region Q2 and a dicing region Q3, wherein in FIG. 4, the region in the solid line box x1 other than the active region Q1 is the termination region Q2, so the termination region Q2 surrounds the active region Q1, and the dicing region Q3 is located between the termination regions Q2 of two adjacent semiconductor devices, so as to form independent chips after cutting. Taking the first semiconductor layer 10 as an N-type semiconductor layer and the second semiconductor layer 30 as a P-type semiconductor layer as an example, at this time, the I-type semiconductor layer 20 and the N-type semiconductor layer are both N-type doped layers, only the doping concentration of the I-type semiconductor layer 20 is different from that of the N-type semiconductor layer, and the doping concentration of the N-type semiconductor layer is higher than that of the I-type semiconductor layer 20, so as to form a PIN structure. At this time, the active region Q1 is the region where the P-type semiconductor layer is located, and the space charge region is the region where the interface between the P-type semiconductor layer and the I-type semiconductor layer 20 is located, so the region indicated by Q1 in FIG. 4 can also represent the space charge region, and the termination region Q2 is the region where the field plate 42 and the isolation part 60 are located. Alternatively, the first semiconductor layer 10 can also be a P-type semiconductor layer, and correspondingly, the second semiconductor layer 30 is an N-type semiconductor layer, which is not shown, the I-type semiconductor layer 20 and the P-type semiconductor layer are both P-type doped layers, only the doping concentration of the I-type semiconductor layer 20 is different from that of the P-type semiconductor layer, and the doping concentration of the P-type semiconductor layer is higher than that of the I-type semiconductor layer 20, so as to form a PIN structure. At this time, the active region Q1 is the region where the N-type semiconductor layer is located, and the space charge region is the region where the interface between the N-type semiconductor layer and the I-type semiconductor layer 20 is located, so the region indicated by Q1 in FIG. 4 can also represent the space charge region, and the termination region Q2 is the region where the field plate 42 and the isolation part 60 are located.

[0071] The field limiting ring in the prior art can reduce the electric field peak of the active region Q1 and improve the breakdown resistance, but the setting of the field limiting ring occupies a large terminal region Q2 area (for example, the field limiting ring is usually formed by ion implantation, which occupies a large area; and a space is also needed between multiple field limiting rings, which occupies more area), which prevents the miniaturization design of the semiconductor device. In the present application, the field plate 42 is spaced apart from the I-type semiconductor layer 20 by the dielectric layer, so that the field plate 42 can reduce the electric field peak of the active region Q1 and improve the breakdown resistance; in addition, the isolation portion 60 can isolate the space charge region and the scribing region Q3, and isolate the active region Q1 and the scribing region Q3, so that the PN junction field region avoids diffusing to the scribing region Q3, thereby greatly increasing the reserved space of the scribing region Q3 and effectively reducing the risk of electric leakage; in this way, by setting the field plate 42 and the isolation portion 60, the electric field peak can be reduced and the breakdown resistance can be improved, and the risk of electric leakage can be reduced, so that the reliability and stability requirements of the semiconductor device (such as a diode) can be met. At the same time, under the condition of meeting the reliability and stability requirements, since the field limiting ring does not need to be set, the problem of area increase caused by setting the field limiting ring can be avoided, so that the occupied area of the terminal region Q2 can be reduced to realize the miniaturization of the semiconductor device.

[0072] Exemplarily, the field limiting ring is usually located in the semiconductor layer, and is generally formed in the semiconductor layer by an ion implantation device. Since the field limiting ring does not need to be set, the ion implantation device is not needed to manufacture the field limiting ring. The isolation portion 60 in the present application can be made of an insulating material, and the field plate 42 is part of the electrode layer 40, so the field plate 42 can be made of a conductive material. Therefore, the isolation portion 60 and the field plate 42 do not need to be prepared by the ion implantation device, so that the manufacturing cost of the semiconductor device can be reduced, the manufacturing difficulty can be reduced, and the manufacturing method of the second semiconductor layer 30 does not need to be limited, and any achievable method known to those skilled in the art can be used.

[0073] Exemplarily, the first semiconductor layer 10 can be provided with a second electrode 70 on the side surface away from the I-type semiconductor layer 20; if the first semiconductor layer 10 is an N-type semiconductor layer, the second semiconductor layer 30 is a P-type semiconductor layer, the first electrode 41 is an anode, and the second electrode 70 is a cathode, as shown in FIG. 5; if the first semiconductor layer 10 is a P-type semiconductor layer, the second semiconductor layer 30 is an N-type semiconductor layer, the first electrode 41 is a cathode, and the second electrode 70 is an anode, and no diagram is given.

[0074] As shown in FIG. 5, the height d1 of the isolation portion 60 can be set equal to the thickness of the I-type semiconductor layer 20, i.e., the isolation portion 60 penetrates the I-type semiconductor layer 20 along the thickness direction of the I-type semiconductor layer 20, so as to effectively isolate the space charge region from the scribe region Q3 and isolate the active region Q1 from the scribe region Q3, thereby effectively improving the withstand voltage of the semiconductor device. Alternatively, the height d1 of the isolation portion 60 can also be set less than the thickness of the I-type semiconductor layer 20, and the isolation portion 60 is located at the side of the I-type semiconductor layer 20 facing the electrode layer 40, which is not shown in the figure, so as to not only isolate the space charge region from the scribe region Q3 and isolate the active region Q1 from the scribe region Q3, but also reduce the difficulty of manufacturing the isolation portion 60 and reduce the manufacturing cost. It should be understood that in combination with FIG. 5, the height and the thickness can be understood as the length along the z direction.

[0075] The width d2 of the isolation portion 60 can be set to 1-10 microns, which can be set according to actual needs and is not limited herein. For example, when the width of the isolation portion 60 is small, the manufacturing difficulty can be increased, so as to set the width of the isolation portion 60 larger in order to reduce the manufacturing difficulty. Alternatively, when the width of the isolation portion 60 is large, the size of the termination region Q2 is increased, thereby increasing the size of the semiconductor device, so as to set the width of the isolation portion 60 smaller in order to reduce the size of the semiconductor device. It should be understood that in combination with FIG. 5, the width can be understood as the length along the arrangement direction of the P-type semiconductor layer and the dielectric layer 50.

[0076] Continuing to refer to FIG. 5, the field plate 42 can be set as a planar field plate, which is different from the stepped field plate and the double-layer field plate. The field plate 42 of this structure is characterized by being arranged in a flat plate shape on the side surface of the dielectric layer 50 away from the substrate, and the side surface of the dielectric layer 50 away from the substrate is a flat surface. In this way, the field plate 42 can improve the breakdown voltage of the semiconductor device, reduce the electric field peak value of the PN junction, improve the performance of the semiconductor device, and reduce the manufacturing difficulty and manufacturing cost of the semiconductor device.

[0077] For the positional relationship between the isolation portion 60 and the field plate 42, the following positional relationship can be provided: the isolation portion 60 and the field plate 42 do not overlap in the first positive projection on the surface of the first semiconductor layer, as shown in (a) of FIG. 6, and the distance d3 between the first positive projection T1 toward one side of the second positive projection T2 and the positive projection of the field plate 42 on the surface of the first semiconductor layer can be greater than 0 and not greater than 10 microns, so as to reduce the size of the terminal region and further reduce the size of the semiconductor device; or, the positive projection of the isolation portion 60 on the surface of the first semiconductor layer (i.e., the first positive projection T1) has a side edge y1 toward the second semiconductor layer, the positive projection of the field plate 42 on the surface of the first semiconductor layer has a side edge y2 away from the first electrode, and the first edge and the second edge overlap, as shown in (b) of FIG. 6; or, the second edge y2 is located within the first positive projection T1, as shown in (c) of FIG. 6; or, the first positive projection T1 is located within the positive projection of the field plate 42 on the surface of the first semiconductor layer, as shown in (d) of FIG. 6. The positional relationship between the isolation portion 60 and the field plate 42 can be set according to actual needs to meet the needs of different application scenarios.

[0078] The material for manufacturing the electrode layer 40 can include any conductive material known to those skilled in the art, such as but not limited to aluminum, copper, silver, etc., without specific limitation.

[0079] For example, the thickness of the first semiconductor layer 10 at any position can be set to be the same; or the thickness of the first semiconductor layer 10 corresponding to the second semiconductor layer 30 can be greater than the thickness of the remaining portion, so that the side surface of the first semiconductor layer 10 toward the I-type semiconductor layer 20 is a stepped surface. Similarly, the thickness of the I-type semiconductor layer 20 at any position can also be set to be the same; or the thickness of the I-type semiconductor layer 20 corresponding to the second semiconductor layer 30 can be greater than the thickness of the remaining portion, so that the side surface of the I-type semiconductor layer 20 toward the second semiconductor layer 30 is a stepped surface; or, when the side surface of the first semiconductor layer 10 toward the I-type semiconductor layer 20 is a stepped surface, the thickness of the I-type semiconductor layer 20 corresponding to the second semiconductor layer 30 can be less than the thickness of the remaining portion, so that the side surface of the I-type semiconductor layer 20 toward the second semiconductor layer 30 is a flat surface. The thickness of the first semiconductor layer 10 and the I-type semiconductor layer 20 can be set according to actual needs, without specific limitation.

[0080] FIGS. 7 and 8 exemplarily show a structure schematic diagram of another semiconductor device provided by the present application. Referring to FIGS. 7 and 8, the structure of the semiconductor device in this embodiment is basically similar to that of the semiconductor device described in the foregoing embodiments of FIGS. 4 to 6, except that the structure of the field plate 42 is different. In this embodiment, the field plate 42 is a stepped field plate.

[0081] For example, referring to FIG. 7 and FIG. 8, FIG. 8 is a sectional view of FIG. 7 along the direction of n3-n4, FIG. 8(a) is a schematic diagram of the structure when each structure is integrated together, and FIG. 8(b) is a schematic diagram of the structure in which the field plate and the dielectric layer are separated, and the trench in the dielectric layer can be clearly seen in FIG. 8(b); wherein the side surface of the dielectric layer 50 facing the field plate 42 (i.e. the top surface of the dielectric layer 50 shown in FIG. 8(a)) is provided with a trench 51, the trench 51 surrounds the first electrode 41, that is, the trench 51 is a closed structure surrounding the first electrode 41, and the contour shape of the trench 51 in the orthogonal projection of the surface of the first semiconductor layer 10 is not limited to that shown in FIG. 7, and can also be other shapes, as long as a closed structure surrounding the first electrode 41 can be formed. In addition, part of the field plate 42 is arranged in the trench 51, so that the field plate 42 is a stepped field plate; wherein, as shown in FIG. 8(b), the trench 51 can be regarded as dividing the surface of the dielectric layer 50 away from the I-type semiconductor layer into two parts, one part of the surface (such as surface b4) is located between the trench 51 and the second semiconductor layer, and the other part of the surface (such as surface b5) is located on the side of the trench 51 away from the second semiconductor layer, at this time: part of the field plate 42 can cover the surface b4 and the side wall b1 of the trench 51 close to the second semiconductor layer, or part of the field plate 42 can cover the surface b4, the side wall b1 of the trench 51 close to the second semiconductor layer, and at least part of the groove bottom b2; or, part of the field plate 42 can cover the surface b4, the side wall b1 of the trench 51 close to the second semiconductor layer, the groove bottom b2, and the side wall b3 of the trench 51 away from the second semiconductor layer; or, the field plate 42 can cover the surface b4, the side wall b1 of the trench 51, the groove bottom b2, the side wall b3 of the trench 51, and part of the surface b5; the positional relationship between the field plate 42 and the trench 51 can be set according to actual needs, and is not limited herein.

[0082] In FIG. 8(a), the area shown by the dashed line circle x2 is a breakdown weak area, and because part of the field plate 42 is located in the trench 51, the stepped field plate is closer to the breakdown weak area, can effectively protect the breakdown weak area, reduce the electric field peak value of the breakdown weak area, and thus the breakdown voltage performance of the semiconductor device can be further improved, so as to be suitable for use in high-voltage scenarios. In addition, the stepped field plate in the embodiment of the present application does not need to etch the I-type semiconductor layer 20 and the first semiconductor layer 10 when being manufactured, so as to reduce the process difficulty of etching and improve the efficiency of etching.

[0083] Further, the trench 51 has a third orthogonal projection T3 on the surface of the first semiconductor layer 10, and the first orthogonal projection T1 surrounds the third orthogonal projection T3, that is, the first orthogonal projection T1 is a closed structure surrounding the third orthogonal projection T3, in other words, the isolation portion 60 surrounds the trench 51, and the trench 51 surrounds the first electrode 41, so that the isolation portion 60 is located on the side of the trench 51 away from the second semiconductor layer 30; if the side of the trench 51 away from the second semiconductor layer 30 is regarded as the outer side of the trench 51, and the side of the trench 51 toward the second semiconductor layer 30 is regarded as the inner side of the trench 51, then the isolation portion 60 is located on the outer side of the trench 51, so that the space charge region and the scribe region can be effectively isolated, and the active region and the scribe region can be effectively isolated, thereby further reducing the risk of electric leakage, and further improving the withstand voltage, reliability and stability of the semiconductor device, so that the design requirement of the withstand voltage in a smaller area can be achieved.

[0084] As shown in (a) of FIG. 8, the distance d4 between the bottom surface of the trench 51 and the I-type semiconductor layer 20 can be set to 0.1-3 μm, so that the part of the field plate 42 located in the trench 51 can effectively protect the breakdown weak region, so as to avoid the decrease of the protection effect of the field plate 42 on the breakdown weak region due to the long distance between the field plate 42 and the breakdown weak region, thereby further improving the withstand voltage performance of the semiconductor device. The specific value of d4 can be set according to actual needs, which is not limited herein. In addition, the thickness of the second semiconductor layer 30 can be not less than 3 μm, but the upper limit of the thickness of the second semiconductor layer 30 can be set according to actual needs, which is not limited herein.

[0085] In addition, the distance d5 between the trench 51 and the second semiconductor layer 30 can be set to be greater than zero, but the specific value of d5 can be set according to actual needs; for example, when d5 is set to be larger, the occupied area of the terminal region will be increased, if it is required to reduce the occupied area of the terminal region, d5 can be set to be smaller; when d5 is set to be smaller, the breakdown weak region can be effectively protected, if it is required to increase the protection effect, d5 can be set to be smaller; when d5 is set to be smaller, the second semiconductor layer 30 can be damaged during the manufacturing of the trench 51, so in order to avoid such damage, d5 can be set to be larger.

[0086] It should be understood that the structure of the semiconductor device in the embodiment is similar to the structure of the semiconductor device described in the foregoing embodiments of FIGS. 4-6, and the relevant descriptions can be referred to the foregoing embodiments, and the repeated descriptions are not described herein.

[0087] FIG. 9 and FIG. 10 exemplarily show a structural schematic diagram of another semiconductor device provided in the present application. Referring to FIG. 9 and FIG. 10, the structure of the semiconductor device in this embodiment is basically similar to that of the semiconductor device introduced in the foregoing embodiments of FIG. 4 to FIG. 6, except that the structure of the field plate 42 is different. In this embodiment, the field plate 42 is a double-layer type field plate.

[0088] Exemplarily, referring to FIG. 9 and FIG. 10, the conductive part 80 is arranged in the dielectric layer 50, and the conductive part 80 is connected with the electrode layer 40. The conductive part 80 surrounds the first electrode 41, that is, the conductive part 80 is a closed structure surrounding the first electrode 41. The contour shape of the first projection of the conductive part 80 on the surface of the first semiconductor layer 10 is not limited, as long as it can form a closed structure surrounding the first electrode 41. In this way, a double-layer type field plate is formed.

[0089] When the conductive part 80 is connected with the electrode layer 40, it can include that the conductive part 80 is connected with the field plate 42, or the conductive part 80 is connected with the first electrode 41, or the conductive part 80 is connected with the field plate 42 and the first electrode 41 respectively. The specific design can be made according to actual needs, which is not limited here.

[0090] In FIG. 9, the area shown by the dashed line circle x3 is a breakdown weak area. The conductive part 80 in the double-layer type field plate is closer to the breakdown weak area, which can effectively protect the breakdown weak area and reduce the electric field peak value of the breakdown weak area, so as to further improve the withstand voltage performance of the semiconductor device, so as to be suitable for use in high-voltage scenarios. Moreover, the double-layer type field plate in the embodiment of the present application does not need to etch the I-type semiconductor layer 20 and the first semiconductor layer 10 when being made, so as to reduce the process difficulty of etching and improve the efficiency of etching.

[0091] Further, the conductive part 80 has a fourth projection on the first semiconductor layer 10. The first projection surrounds the fourth projection, that is, the first projection is a closed structure surrounding the fourth projection. In other words, the isolation part 60 surrounds the conductive part 80, and the conductive part 80 surrounds the first electrode 41, so that the isolation part 60 is located on the side of the conductive part 80 away from the second semiconductor layer 30. If the side of the conductive part 80 away from the second semiconductor layer 30 is regarded as the outer side of the conductive part 80, and the side of the conductive part 80 toward the second semiconductor layer 30 is regarded as the inner side of the conductive part 80, then the isolation part 60 is located on the outer side of the conductive part 80. In this way, the space charge region and the scribe region can be effectively isolated, and the active region and the scribe region can be effectively isolated, so as to further reduce the risk of electric leakage, and further improve the withstand voltage value, reliability and stability of the semiconductor device, so as to achieve the design requirement of the withstand voltage in a smaller area.

[0092] For example, if the withstand voltage requirement is 450V, the length of the terminal region of the diode provided with the field limiting ring needs to reach 130 microns; while the length of the terminal region of the diode provided with the isolation portion and the double-layer field plate only needs to reach 25 microns, which is reduced by about 100 microns compared with the diode provided with the field limiting ring, so that the size of the terminal region can be effectively reduced by providing the isolation portion and the double-layer field plate, and thus the size of the semiconductor device is reduced. Moreover, for the area design of the die applied in the actual product, when the radius of the active region is 65 microns, the technical solution provided with the isolation portion and the double-layer field plate has obvious advantages compared with the technical solution provided with the field limiting ring, not only the wafer utilization rate is improved, but also the performance of the semiconductor device is improved. It should be understood that when the semiconductor device is manufactured, a plurality of semiconductor devices are manufactured on a larger substrate, and a scribe area is provided between adjacent semiconductor devices, and then scribing and cutting are performed, so as to cut each semiconductor device, and each semiconductor device cut can be called a die.

[0093] With reference to the electric potential distribution diagram of the diode provided with the isolation portion and the double-layer field plate shown in FIG. 11, the electric potential distribution diagram of the diode without the isolation portion shown in FIG. 12, and the leakage current test diagram shown in FIG. 13, the curve s1 in FIG. 13 represents the corresponding leakage current curve when the isolation portion is provided, the curve s2 in FIG. 13 represents the corresponding leakage current curve when the isolation portion is not provided, and the left region of the dashed line 1 in FIGS. 11 and 12 represents the space charge region before expansion. It can be found from the results shown in the figures that the space charge region expands to the right, when the scribe area is located to the right of the isolation portion in FIGS. 11 and 12, the isolation portion can effectively prevent the space charge region from expanding to the right of the scribe area, and thus avoid the diffusion of the electric field to the scribe area, so that the reserved space of the scribe area is greatly increased; and under the same cathode voltage, the absolute value of the anode current in the curve s1 is smaller than the absolute value of the anode current in the curve s2, which indicates that the corresponding leakage current is smaller when the isolation portion is provided, so that the isolation portion can effectively reduce the size of the leakage current, and thus the total leakage current generated by the space charge region is reduced.

[0094] It should be understood that the conductive portion is shown in FIGS. 11 and 12, but other structures of the double-layer field plate are not shown. Here, the conductive portion is used to represent that the diode with the double-layer field plate and the isolation portion is simulated for convenience.

[0095] The positional relationship between the conductive part 80 and the field plate 42 can be set as follows: as shown in FIG. 9, the orthographic projection of the conductive part 80 on the first semiconductor layer 10 is located within the orthographic projection of the field plate 42 on the first semiconductor layer 10; or, as shown in FIG. 10, the orthographic projection of the conductive part 80 on the first semiconductor layer 10 partially overlaps the orthographic projection of the field plate 42 on the first semiconductor layer 10; or, as shown in FIG. 11, the orthographic projection of the conductive part 80 on the first semiconductor layer 10 does not overlap the orthographic projection of the field plate 42 on the first semiconductor layer 10. That is, when the orthographic projection of the conductive part 80 on the first semiconductor layer 10 is located within the orthographic projection of the field plate 42 on the first semiconductor layer 10, or when the orthographic projection of the conductive part 80 on the first semiconductor layer 10 partially overlaps the orthographic projection of the field plate 42 on the first semiconductor layer 10, the orthographic projection of the conductive part 80 on the first semiconductor layer 10 can overlap the orthographic projection of the field plate 42 on the first semiconductor layer 10, which can reduce the area occupied by the terminal region, and thus can reduce the size of the semiconductor device.

[0096] The distance d6 between the conductive part 80 and the I-type semiconductor layer 20 can be set to 0.1 μm-3 μm. This can effectively protect the weak breakdown area from the conductive part 80, avoid the protection effect of the field plate 42 on the weak breakdown area from being reduced due to the long distance between the field plate 42 and the weak breakdown area, and thus further improve the withstand voltage performance of the semiconductor device. The specific value of d6 can be set according to actual needs, which is not limited herein. In addition, the thickness of the second semiconductor layer 30 can be not less than 3 μm, but the upper limit of the thickness of the second semiconductor layer 30 can be set according to actual needs, which is not limited herein.

[0097] In addition, the distance d7 between the conductive part 80 and the second semiconductor layer 30 can be set to be greater than zero, but the specific value of d7 can be set according to actual needs. For example, when d7 is set to be small, the weak breakdown area can be effectively protected, and if the protection effect needs to be increased, d7 can be set to be smaller. When d7 is set to be small, the second semiconductor layer 30 can be damaged during the manufacture of the conductive part 80, so in order to avoid such damage, d7 can be set to be larger.

[0098] It should be understood that the structure of the semiconductor device in the embodiment is similar to the structure of the semiconductor device described in the foregoing embodiments of FIGS. 4-6, and the relevant description can be referred to in the foregoing embodiments, and the repeated description is not repeated.

[0099] FIG. 14 shows a schematic diagram of a manufacturing process of a semiconductor device provided by the present application. Referring to FIG. 14, the manufacturing process can include:

[0100] Step S1: as shown in (a) of FIG. 14, a lightly doped N-type semiconductor layer with a certain thickness is formed on one side surface of a heavily doped N-type semiconductor substrate; wherein the heavily doped N-type semiconductor substrate can be used as a first semiconductor layer, and the lightly doped N-type semiconductor layer can be used as an I-type semiconductor layer;

[0101] Step S2: as shown in (a) of FIG. 14, a P-type semiconductor layer with a certain thickness is formed on the lightly doped N-type semiconductor layer; wherein the P-type semiconductor layer can be used as a second semiconductor layer;

[0102] Step S3: as shown in (a) of FIG. 14, an etching process is used to etch the second semiconductor layer, so that the second semiconductor layer in the active region reserved by pre-division is retained, and the second semiconductor layer outside the active region is etched away to expose the I-type semiconductor layer;

[0103] Step S4: as shown in (b) of FIG. 14, the exposed I-type semiconductor layer is etched to form a first through hole penetrating along the thickness direction thereof, and the first semiconductor layer can be exposed through the first through hole;

[0104] Step S5: as shown in (c) of FIG. 14, an insulating material such as silicon oxide, silicon nitride, aluminum oxide or aluminum nitride is used to form a first insulating layer with a first thickness f1, and the manufacturing material of the first insulating layer fills the first through hole; wherein the first thickness f1 is less than the thickness f0 of the second semiconductor layer, and the filled first through hole can be used as an isolation part;

[0105] Step S6: as shown in (c) of FIG. 14, an etching process is used to etch the first insulating layer to etch away the first insulating layer in the active region to expose the second semiconductor layer, and the first insulating layer outside the active region is retained;

[0106] Step S7: as shown in (d) of FIG. 14, an insulating material such as silicon oxide, silicon nitride, aluminum oxide or aluminum nitride is used to continue to form a second insulating layer with a second thickness f2; wherein the sum of the first thickness f1 and the second thickness f2 is equal to the thickness f0 of the second semiconductor layer, and the materials of the first insulating layer and the second insulating layer can be different or the same;

[0107] Step S8: Continue as shown in (d) of FIG. 14, the second insulating layer is etched by using an etching process to etch away the second insulating layer in the active region to expose the second semiconductor layer, and the second insulating layer outside the active region is retained, at the same time, a second through hole is formed in the second insulating layer, and the second through hole exposes the first insulating layer; wherein the first insulating layer exposed by the second through hole can be used as the bottom surface of the trench, and the sidewall of the second through hole can be used as the sidewall of the trench, so the trench in the dielectric layer is formed based on the second through hole; the first insulating layer and the second insulating layer constitute the dielectric layer;

[0108] Step S9: As shown in (e) of FIG. 14, a metal layer is formed by using but not limited to conductive metal, and the metal layer is in direct contact with the second semiconductor layer; then the metal layer is etched to etch away the part of the metal layer outside the active region and the terminal region, so that this part of the metal layer located on the second semiconductor layer serves as an anode, at this time the anode can be used as the first electrode, and this part of the metal layer located in the terminal region serves as a field plate, and part of the field plate in the terminal region is located in the trench;

[0109] Step S10: As shown in (f) of FIG. 14, another metal layer is formed on the other side surface of the first semiconductor layer by using but not limited to conductive metal, and the metal layer is used to form the cathode of the semiconductor device, at this time the cathode can be used as the second electrode.

[0110] In this way, by performing the above steps S1 to S10, the semiconductor device with the step-type field plate and the isolation part can be formed, so that the occupied area of the terminal region can be reduced, thereby realizing the miniaturization of the semiconductor device. Moreover, the isolation part can isolate the space charge region and the dicing area, and isolate the active region and the dicing area, so that the PN junction field region avoids diffusing to the dicing area, thereby greatly increasing the reserved space of the dicing area, effectively reducing the risk of leakage, and also improving the withstand voltage of the semiconductor device, improving the reliability and stability of the semiconductor device. In addition, the withstand voltage performance of the semiconductor device can be further improved to be suitable for use in high-voltage scenarios.

[0111] Moreover, when forming the dielectric layer and filling the first through hole, a glass passivation process is not required, so the stress of the wafer can be reduced, and the yield of the semiconductor device can be improved.

[0112] The application also provides another process for manufacturing a semiconductor device, which is basically similar to the process introduced in FIG. 14 of the foregoing embodiment, and the difference is that:

[0113] (1) Step S1 in the embodiment described in FIG14 above is adjusted to: a lightly doped P-type semiconductor layer with a certain thickness is formed on one side surface of a heavily doped P-type semiconductor substrate; wherein, the heavily doped P-type semiconductor substrate can be used as the first semiconductor layer and the lightly doped P-type semiconductor layer can be used as the I-type semiconductor layer.

[0114] (2) Step S2 in the embodiment described in FIG14 above is adjusted to: an N-type semiconductor layer with a certain thickness is formed on the lightly doped P-type semiconductor layer; wherein the N-type semiconductor layer can be used as a second semiconductor layer.

[0115] It should be understood that the semiconductor device fabrication process in this embodiment is similar to the fabrication process described in Figure 14 of the previous embodiment. Please refer to the relevant descriptions in the previous embodiments. Repeated parts will not be repeated.

[0116] This application also provides another semiconductor device fabrication process, which is basically similar to the fabrication process described in Figure 14 of the foregoing embodiments, with the following differences:

[0117] (1) In the embodiment described in Figure 14 above, step A1 is added between steps S6 and S7. Step A is: using, but not limited to, a conductive metal, to form a metal layer with a certain thickness; then using an etching process to etch the metal layer so that a conductive part is formed on the first insulating layer in the terminal area, while the metal layers at other locations are etched away.

[0118] (2) Step S8 in the embodiment described in FIG14 above is adjusted to: using an etching process to etch the second insulating layer to etch away the second insulating layer in the active region and expose the second semiconductor layer, while retaining the second insulating layer outside the active region, and forming a second through hole in the second insulating layer that penetrates its thickness, and exposing the conductive part of the second through hole.

[0119] (3) Step S9 in the embodiment described in FIG14 above is adjusted to: using, but not limited to, a conductive metal to form a metal layer, and the metal layer is in direct contact with the second semiconductor layer; then the metal layer is etched to etch away the part of the metal layer outside the active region and the terminal region, so that the part of the metal layer above the second semiconductor layer serves as the anode. At this time, the anode can serve as the first electrode, and the part of the metal layer in the terminal region serves as the field plate. The material used to make the field plate in the terminal region will fill the second via and connect with the conductive part.

[0120] It should be understood that the semiconductor device fabrication process in this embodiment is similar to the fabrication process described in Figure 14 of the previous embodiment. Please refer to the relevant descriptions in the previous embodiments. Repeated parts will not be repeated.

[0121] It is apparent that a person skilled in the art can make various changes and modifications to the embodiments of the application without departing from the scope of the application. Therefore, if these modifications and changes of the embodiments of the application belong to the scope of the claims of the application and their equivalent technologies, the application also intends to include these modifications and changes.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor layer, a type I semiconductor layer, a second semiconductor layer, and an electrode layer are stacked sequentially, wherein the first semiconductor layer and the second semiconductor layer have different doping types; The semiconductor device further includes a dielectric layer, which is located side-by-side with the second semiconductor layer between the electrode layer and the type I semiconductor layer; The electrode layer includes a first electrode and a field plate connected together. The first electrode is located on the side of the second semiconductor layer opposite to the first semiconductor layer, and the field plate is located on the side of the dielectric layer opposite to the first semiconductor layer. An isolation portion formed of insulating material is disposed within the type I semiconductor layer. The isolation portion has a first orthographic projection on the surface of the first semiconductor layer, and the first electrode has a second orthographic projection on the surface of the first semiconductor layer. The first orthographic projection surrounds the second orthographic projection.

2. The semiconductor device as claimed in claim 1, characterized in that, The isolation portion extends through the type I semiconductor layer along its thickness direction.

3. The semiconductor device as described in claim 1 or 2, characterized in that, The dielectric layer has a groove on one side of its surface facing the field plate, the groove surrounds the first electrode, and a portion of the field plate is located within the groove.

4. The semiconductor device as described in claim 3, characterized in that, The trench has a third orthographic projection on the surface of the first semiconductor layer, and the first orthographic projection surrounds the third orthographic projection.

5. The semiconductor device as described in claim 3 or 4, characterized in that, The distance between the bottom surface of the trench and the type I semiconductor layer is 0.1 μm-3 μm.

6. The semiconductor device as claimed in claim 1 or 2, characterized in that, A conductive portion is disposed within the dielectric layer, the conductive portion surrounds the first electrode, and the conductive portion is connected to the electrode layer.

7. The semiconductor device as claimed in claim 6, characterized in that, The conductive portion has a fourth orthographic projection on the first semiconductor layer, and the first orthographic projection surrounds the fourth orthographic projection.

8. The semiconductor device as claimed in claim 6 or 7, characterized in that, The conductive portion overlaps with the orthographic projection of the field plate onto the first semiconductor layer.

9. The semiconductor device according to any one of claims 6-8, characterized in that, The distance between the conductive part and the type I semiconductor layer is 0.1 μm-3 μm.

10. An electronic device, characterized in that, include: The housing and the semiconductor device as described in any one of claims 1-9, wherein the semiconductor device is disposed within the housing.

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