Chip, manufacturing method therefor and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided in the embodiments are a chip, a manufacturing method therefor and an electronic device, which utilize protective layers to prevent etching gas used for etching sacrificial layers from entering sources and drains, so as to prevent the problem of short circuits between gates and sources and between gates and drains, as well as the problem of point discharge occurred on gates. The chip comprises a substrate and a gate-all-around transistor provided on the substrate. The gate-all-around transistor comprises a channel layer, a gate structure, a source and a drain. The gate structure comprises a gate surrounding the channel layer, and a gate dielectric layer used for isolating the gate from the channel layer. The source and the drain are respectively disposed at two ends of the channel layer. The chip further comprises a dielectric material and a protective layer. The dielectric material is arranged between the source and the gate structure, and between the drain and the gate structure; the space between the dielectric material and the gate structure is filled with the protective layer; the protective layer is made of a material different from the materials of the dielectric material, the source and the drain; and the protective layer fully covers sidewalls of the dielectric material.

Description

Chip, preparation method thereof and electronic device

[0001] The present application claims priority to the Chinese patent application No. 202410819289.3, filed on June 24, 2024, entitled "Chip, preparation method thereof and electronic device", the whole content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor technology, and in particular to a chip, a preparation method thereof and an electronic device. BACKGROUND

[0003] Gate-all-around field effect transistor (GAAFET) is the most competitive transistor structure of the next generation advanced node due to its excellent electrostatic control performance, short channel effect inhibition and dynamic performance, and its process is compatible with the existing fin field effect transistor (FinFET) process.

[0004] In the process of the gate-all-around field effect transistor, when the channel layer of the gate-all-around field effect transistor is released, the sacrificial layer on the upper and lower surfaces of the channel layer needs to be removed. However, in the process of etching the sacrificial layer, the etching gas used to remove the sacrificial layer is easy to overflow to the formed source and drain, causing the source and drain to be mis-etched, and the etching gas forms a leakage path in the source and drain. The gate dielectric layer and the gate formed subsequently will extend to the leakage path of the above-mentioned source and drain. However, since the leakage path is relatively narrow, the gate dielectric layer cannot completely wrap the gate at the leakage path, causing the gate to extrude from the gate dielectric layer and contact the source and drain, resulting in short circuit failure of the gate-all-around field effect transistor. SUMMARY

[0005] In order to solve the above technical problems, the present application provides a chip, a preparation method thereof and an electronic device, which use a protective layer to block the etching gas used to etch the sacrificial layer from entering the source and drain, so as to prevent the short circuit problem between the gate and the source and drain, and the problem of sharp tip discharge of the gate.

[0006] In a first aspect, the present application provides a chip, which comprises a substrate, a ring gate transistor disposed on the substrate, the ring gate transistor comprising a channel layer, a gate structure, a source and a drain. The gate structure comprises a gate electrode surrounding the channel layer, and a gate dielectric layer for isolating the gate electrode from the channel layer; the source and the drain are respectively disposed at two ends of the channel layer. The chip further comprises a dielectric material and a protective layer, wherein the dielectric material is disposed between the source and the gate structure, and between the drain and the gate structure; the protective layer is filled between the dielectric material and the gate structure; the material of the protective layer is different from the material of the dielectric material, the source and the drain, and the protective layer completely covers the sidewall of the dielectric material.

[0007] In the present application, the material of the protective layer is different from the material of the dielectric material, and is also different from the material of the source and the drain, so that the etching selectivity ratio of the protective layer to the sacrificial layer is different from the etching selectivity ratio of the source, the drain, the dielectric material to the sacrificial layer. The material of the protective layer can be selected to be larger than the etching selectivity ratio of the sacrificial layer, so that the protective layer is not damaged by the etching gas used to etch the sacrificial layer during the etching process of the sacrificial layer. In this way, the protective layer can completely cover the sidewall of the dielectric material (i.e., the sidewall of the dielectric material in contact with the protective layer), so as to block the etching gas used to etch the sacrificial layer from entering the source and the drain. On the one hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material, the source and the drain, so that the subsequently formed gate electrode is squeezed out of the gate dielectric layer in the narrow leakage channel, resulting in a short circuit between the gate electrode and the source and the drain. On the other hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material, so that the subsequently formed gate electrode forms a small tip in the leakage channel, so as to avoid the occurrence of a sharp tip discharge of the gate electrode, thereby avoiding a high electric field.

[0008] In some possible implementation manners, it is considered that, in the case that the chip does not comprise the protective layer, the channel layer is in contact with the gate dielectric layer and the dielectric material respectively; in the case that the chip comprises the protective layer, the protective layer is in contact with the gate dielectric layer, the dielectric material and the channel layer respectively. That is, the structure in contact with the protective layer is the same as the structure in contact with the channel layer. Therefore, optionally, the material of the protective layer is the same as the material of the channel layer. In this case, the material of the protective layer is a semiconductor material. In this way, even if the additional protective layer is not removed, the protective layer will not have a negative impact on the performance of the ring gate transistor, and also has a small impact on the stress of the structure in the ring gate transistor. On this basis, since the additional protective layer does not need to be removed, the preparation process of the ring gate transistor is simplified.

[0009] In some possible implementation manners, the ring gate transistor is a P-type transistor, and the materials of the source and the drain include germanium silicon. The material of the sacrifice layer also generally includes germanium silicon, and therefore, the source and the drain containing germanium silicon are very easy to be etched by mistake in the process of etching the sacrifice layer.

[0010] However, the material of the channel layer of the P-type transistor can include silicon, and the etching selectivity of silicon to germanium silicon is large, and therefore, silicon can also be selected as the material of the protection layer, that is, the materials of the channel layer and the protection layer both include silicon, so that the source and the drain are protected from being etched by mistake by using the protection layer in the case that the materials of the source and the drain and the material of the sacrifice layer both include germanium silicon.

[0011] In some possible implementation manners, as mentioned above, the etching selectivity of silicon to germanium silicon can be more than 100, and therefore, silicon can be selected as the material of the protection layer. In this case, the amount of silicon used to deposit the protection layer is small, and the thickness of the protection layer in the direction from the source to the drain is small. In this way, the protection layer does not occupy too much position of the dielectric material, and avoids the parasitic capacitance between the gate and the source and the parasitic capacitance between the gate and the drain from being increased due to the too much reduction of the thickness of the dielectric material with a small dielectric constant.

[0012] Optionally, the thickness of the dielectric material in the direction from the source to the drain is in the range of [5nm, 10nm]; and / or, the thickness of the protection layer in the direction from the source to the drain is in the range of (0, 3nm].

[0013] In a second aspect, the present application provides a chip manufacturing method, including: sequentially forming a channel layer, a protection layer and a dielectric material of a ring gate transistor on a substrate; forming a source and a drain of the ring gate transistor, and the source and the drain are arranged at two ends of the channel layer; the material of the protection layer is different from the materials of the dielectric material, the source and the drain; forming a gate structure; the gate structure includes a gate electrode surrounding the channel layer and a gate dielectric layer for isolating the gate electrode and the channel layer; the dielectric material is located between the source and the gate structure, and between the drain and the gate structure; the protection layer is located between the dielectric material and the gate structure, and the protection layer completely covers the sidewall of the dielectric material.

[0014] In the present application, the material of the protective layer is not only different from the dielectric material, but also different from the material of the source electrode and the drain electrode, so that the etching selectivity ratio of the protective layer and the sacrificial layer is different from the etching selectivity ratio of the source electrode, the drain electrode, the dielectric material and the sacrificial layer. The material with a larger etching selectivity ratio than the sacrificial layer can be selected as the material of the protective layer, so that the protective layer is not damaged by the etching gas used to etch the sacrificial layer during the etching process of the sacrificial layer. In this way, the protective layer can completely cover the sidewall of the dielectric material (i.e. the sidewall of the dielectric material in contact with the protective layer), so as to block the etching gas used to etch the sacrificial layer from entering the source electrode and the drain electrode. On the one hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material, the source electrode and the drain electrode, so that the subsequently formed gate is squeezed out of the gate dielectric layer in the narrow leakage channel, resulting in a short circuit between the gate and the source electrode and the drain electrode. On the other hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material, so that the subsequently formed gate forms a small tip in the leakage channel to avoid the occurrence of tip discharge of the gate, thereby avoiding a high electric field.

[0015] In some possible implementation manners, sequentially forming a channel layer, a protective layer, a dielectric material and a sacrificial layer of a ring gate transistor on a substrate includes: forming the channel layer and the sacrificial layer in a stacked manner on the substrate; the channel layer includes a lower surface facing the substrate and an upper surface away from the substrate, and the sacrificial layer covers the lower surface and the upper surface. The sacrificial layer is partially removed in a direction from the source electrode to the drain electrode and a direction from the drain electrode to the source electrode to obtain a sacrificial layer intermediate pattern and a first hollow part at two ends of the sacrificial layer intermediate pattern. The protective layer and the dielectric material are sequentially filled in the first hollow part. Compared with a related inner spacer isolation process, the protective layer needs to be filled in the first hollow part before the dielectric material is formed after the first hollow part is formed.

[0016] In some possible implementation manners, after the source electrode and the drain electrode of the ring gate transistor are formed and before the gate structure is formed, the chip manufacturing method further includes: etching the sacrificial layer intermediate pattern to form a second hollow part under the protection of the protective layer, the second hollow part being located between adjacent protective layers. The gate structure is formed in the second hollow part. Compared with the prior art, since the protective layer completely covers the sidewall of the dielectric material, the protective layer can protect the dielectric material, the source electrode and the drain electrode when the sacrificial layer intermediate pattern is etched.

[0017] In order to realize that the protective layer completely covers the sidewall of the dielectric material, in some possible implementation manners, the etching selectivity ratio of the source electrode, the drain electrode and the dielectric material to the sacrificial layer is less than the etching selectivity ratio of the protective layer to the sacrificial layer. Optionally, the etching selectivity ratio of the protective layer to the sacrificial layer is greater than 100.

[0018] In this way, in the present application, the dielectric material, the material of the source electrode and the material of the drain electrode are not changed, and in the prior art, the dielectric material, the source electrode and the drain electrode are mis-etched by the etching gas used for etching the sacrificial layer. However, in the present application, the etching selectivity of the protective layer to the sacrificial layer is large, so that the etching gas used for etching the sacrificial layer is blocked from being transmitted to the dielectric material, thereby avoiding the dielectric material, the source electrode and the drain electrode from being mis-etched.

[0019] In some possible implementation manners, the etching selectivity of the dielectric material to the sacrificial layer is smaller than the etching selectivity of the source electrode and the drain electrode to the sacrificial layer, and smaller than the etching selectivity of the protective layer to the sacrificial layer, so as to avoid the source electrode and the drain electrode from being etched by the etching gas as much as possible when the sacrificial layer is etched, thereby causing the gate electrode to directly contact the source electrode and the drain electrode.

[0020] In some possible implementation manners, the channel layer is in contact with the gate dielectric layer and the dielectric material in the case where the chip does not include the protective layer, and the protective layer is in contact with the gate dielectric layer, the dielectric material and the channel layer in the case where the chip includes the protective layer. That is, the structure in contact with the protective layer is the same as the structure in contact with the channel layer. Therefore, optionally, the material of the protective layer is the same as the material of the channel layer. In this case, the material of the protective layer is a semiconductor material. In this way, even if the additional protective layer is not removed, the protective layer does not have a negative impact on the performance of the ring-gate transistor, and also has a small impact on the structural stress in the ring-gate transistor. On this basis, since the additional protective layer does not need to be removed, the preparation process of the ring-gate transistor is simplified.

[0021] In some possible implementation manners, the ring-gate transistor is a P-type transistor, and the material of the source electrode and the drain electrode includes germanium silicon. The material of the sacrificial layer also generally includes germanium silicon, so that the source electrode and the drain electrode including germanium silicon are very easy to be mis-etched by the etching gas in the process of etching the sacrificial layer.

[0022] However, the material of the channel layer of the P-type transistor can include silicon, and the etching selectivity of silicon to germanium silicon is large, so that silicon can be selected as the material of the protective layer, that is, the material of the channel layer and the material of the protective layer both include silicon, so that in the case where the material of the source electrode and the drain electrode and the material of the sacrificial layer both include germanium silicon, the protective layer is used to protect the source electrode and the drain electrode from being mis-etched.

[0023] In a third aspect, the present application provides an electronic device, including a circuit board and the chip of the first aspect, wherein the chip is arranged on the circuit board.

[0024] The third aspect and any kind of implementation manner of the third aspect correspond to the first aspect and any kind of implementation manner of the first aspect respectively. The technical effects corresponding to the third aspect and any kind of implementation manner of the third aspect can refer to the technical effects corresponding to the first aspect and any kind of implementation manner of the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS

[0025] FIG. 1a is a structure diagram of a planar transistor provided by the related art;

[0026] FIG. 1b is a structure diagram of a fin field effect transistor provided by the related art;

[0027] FIG. 1c is a structure diagram of a ring gate transistor provided by the related art;

[0028] FIG. 1d is a sectional view of A1-A2 direction in FIG. 1c;

[0029] FIG. 2a is a defect diagram of a ring gate transistor in the related art;

[0030] FIG. 2b is an enlarged view of A area in FIG. 2a;

[0031] FIG. 3 is a structure diagram of a ring gate transistor provided by an embodiment of the present application;

[0032] FIG. 4 is a structure diagram of a ring gate transistor provided by an embodiment of the present application;

[0033] FIG. 5 is an enlarged view of B area in FIG. 4;

[0034] FIG. 6 is a preparation flow chart of a chip provided by an embodiment of the present application;

[0035] FIG. 7a is a preparation process chart of a chip provided by an embodiment of the present application;

[0036] FIG. 7b is a preparation process chart of a chip provided by an embodiment of the present application;

[0037] FIG. 7c is a preparation process chart of a chip provided by an embodiment of the present application;

[0038] FIG. 7d is a preparation process chart of a chip provided by an embodiment of the present application;

[0039] FIG. 7e is a preparation process chart of a chip provided by an embodiment of the present application;

[0040] FIG. 7f is a preparation process chart of a chip provided by an embodiment of the present application.

[0041] Reference signs: 10-substrate; 11-channel layer; 12-source electrode; 13-drain electrode; 14-gate dielectric layer; 15-gate electrode; 21-dielectric material; 22-protection layer; 30-sacrificial layer; 301-intermediate pattern in the sacrificial layer. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without creative work under the premise that the embodiments in the present application are within the scope of protection of the present application.

[0043] The term “and / or” in the present application is only used to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone.

[0044] The terms “first” and “second” and the like in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, rather than to describe a specific order of the target objects.

[0045] In the embodiments of the present application, the words “exemplary” or “for example” are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as “exemplary” or “for example” in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words “exemplary” or “for example” is intended to present relevant concepts in a specific way.

[0046] In the description of the embodiments of the present application, unless otherwise specified, the meaning of “a plurality of” is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.

[0047] The embodiments of the present application provide an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, a device containing a ring gate transistor.

[0048] Consumer electronics such as mobile phones, tablet computers, notebook computers, personal computers (PCs), personal digital assistants (PDAs), smart wearables (e.g., smart watches, smart bands, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics such as smart door locks, televisions, smart speakers, refrigerators, robotic vacuum cleaners, etc. Vehicle electronics such as car navigation systems, car displays, etc. Financial terminal products such as automated teller machines (ATMs), self-service terminals, etc. Communication electronics such as servers, memories, radars, base stations, etc. Communication equipment containing ring-gate transistors.

[0049] For the convenience of description, the following takes a mobile phone as an example of an electronic device. The mobile phone can include a circuit board, which is provided with a processor and a memory, etc. The memory includes a plurality of memory cells, which include transistors and capacitors. The transistors include a channel layer, a source, a drain, a gate, and a gate dielectric layer.

[0050] FIG. 1a shows a planar transistor, whose gate 15 covers one surface of the channel layer.

[0051] FIG. 1b shows a FinFET, in which the gate 15 spans three surfaces of the channel layer, improving the control ability of the gate 15. Several iterations between the 22 nm to 5 nm nodes of the FinFET have made it have a smaller fin critical dimension (Fin CD), a higher fin height, and a tighter fin pitch (Fin Pitch), thus achieving stronger, smaller, and more efficient performance goals. However, as the size is further reduced, the FinFET exhibits serious leakage, short channel effect (SCE), dynamic threshold voltage V th It is difficult to control, the carrier mobility decreases, the manufacturing cost rises sharply, and a series of problems occur.

[0052] Fig. 1c and Fig. 1d show a ring gate transistor, the gate 15 of which surrounds the channel layer 11 and covers four surfaces of the channel layer 11, which can cope with the problem of intensified short channel effect caused by very small process nodes (e.g. below 7 nm). The ring gate transistor is outstanding among many alternatives because of its excellent electrostatic control performance, short channel effect suppression and dynamic performance, and its process is highly compatible with the existing FinFET process, and is currently the most competitive transistor structure for the next generation of advanced nodes.

[0053] However, the ring gate transistor is not without drawbacks. In the process of channel release of the channel layer 11 of the ring gate transistor, the sacrificial layer on the upper and lower surfaces of the channel layer 11 needs to be completely removed. After the sacrificial layer is completely removed, the distance between the gate 15 and the source 12 and the drain 13 is reduced. According to the formula of capacitance, the distance between the gate 15 and the source 12 and the drain 13 is reduced, the parasitic capacitance formed between the gate 15 and the source 12 and the drain 13 will increase sharply, which will reduce the alternating current performance of the ring gate transistor and increase the resistance-capacitance delay (RC Delay) of the ring gate transistor.

[0054] In order to ensure that the size of the parasitic capacitance between the gate 15 and the source 12 and the drain 13 is within a controllable range, an inner spacer process (ISP) will be used between the source 12 and the drain 13 and the gate 15. The main purpose of the process is to use a dielectric material with lower dielectric constant to fill and replace a part of the high dielectric material (gate dielectric layer 14) closer to the source 12 and the drain 13, to reduce part of the parasitic capacitance, and thus reduce the RC Delay.

[0055] Increasing the dielectric material, the process of channel release of the channel layer 11 of the ring gate transistor includes inner spacer hole etching, inner spacer dielectric material deposition, and etching of the sacrificial layer (channel release process). In the etching of the sacrificial layer process, the dielectric material of the inner spacer is used to isolate the source 12 and the drain 13, and the remaining sacrificial layer is etched. However, according to the process known in the industry, the dielectric material isolation process of the inner spacer as a whole is not mature, and there are many process risk points, such as incomplete etching of the sacrificial layer, and partial residues at the interface between the sacrificial layer and the channel layer 11.

[0056] In order to completely remove the sacrificial layer, an over-etching process can be used to etch the remaining sacrificial layer during the subsequent via releasing process. However, as shown in FIG. 2a and FIG. 2b, the etching gas used to over-etch the sacrificial layer tends to overflow to the formed source 12 and drain 13, causing the dielectric material 21, source 12 and drain 13 to be etched by mistake, and the etching gas forms a leakage path in the dielectric material 21, source 12 and drain 13, and the subsequently formed gate dielectric layer 14 and gate 15 will extend to the leakage path. However, since the leakage path is relatively narrow, the gate dielectric layer 14 cannot completely wrap the gate 15 at the leakage path, causing the gate 15 to extrude from the gate dielectric layer 14 and contact the source 12 and drain 13, resulting in short circuit failure of the ring gate transistor.

[0057] Based on this, as shown in FIG. 3, an embodiment of the present application provides a chip, which includes a substrate 10, a ring gate transistor, a dielectric material 21 and a protective layer 22 disposed on the substrate 10.

[0058] The ring gate transistor includes a channel layer 11, a gate structure, a source 12 and a drain 13. The gate structure includes a gate 15 surrounding the channel layer 11, and a gate dielectric layer 14 for isolating the gate 15 from the channel layer 11, which can also be said that the gate dielectric layer 14 is disposed between the channel layer 11 and the gate 15. The source 12 and drain 13 are respectively disposed at two ends of the channel layer 11 and contact the sidewalls of the channel layer 11. In addition, the gate structure surrounds the channel layer 11 except for the two sidewalls.

[0059] The dielectric material 21 is disposed between the source 12 and the gate structure, and between the drain 13 and the gate structure. As mentioned above, by using a dielectric material 21 with a lower dielectric constant, the parasitic capacitance between the gate 15 and the source 12, and the parasitic capacitance between the gate 15 and the drain 13 can be reduced.

[0060] The protection layer 22 is made of material different from the dielectric material 21 and the source electrode 12 and the drain electrode 13, so that the etching selectivity ratio of the protection layer 22 to the sacrificial layer is different from the etching selectivity ratio of the source electrode 12, the drain electrode 13 and the dielectric material 21 to the sacrificial layer. The material of the protection layer 22 can be selected to have a larger etching selectivity ratio to the sacrificial layer, so that the protection layer 22 is not damaged by the etching gas used to etch the sacrificial layer during the etching of the sacrificial layer. In this way, the protection layer 22 can completely cover the sidewall of the dielectric material 21 (i.e. the sidewall of the dielectric material 21 in contact with the protection layer 22), so that the etching gas used to etch the sacrificial layer is blocked by the protection layer 22 from entering the source electrode 12 and the drain electrode 13. On the one hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material 21, the source electrode 12 and the drain electrode 13, so that the subsequently formed gate electrode 15 is squeezed out of the gate dielectric layer 14 in the narrow leakage channel, resulting in a short circuit between the gate electrode 15 and the source electrode 12 and the drain electrode 13. On the other hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material 21, so that the subsequently formed gate electrode 15 forms a small tip in the leakage channel to avoid the gate electrode 15 from generating a tip discharge to cause a high electric field.

[0061] In some possible implementations, as mentioned above, the material of the protection layer 22 can be selected to have a larger etching selectivity ratio to the sacrificial layer. To achieve that the protection layer 22 completely covers the sidewall of the dielectric material 21, the etching selectivity ratio of the protection layer 22 to the sacrificial layer can be greater than the etching selectivity ratio of the dielectric material 21, the source electrode 12 and the drain electrode 13 to the sacrificial layer.

[0062] In this way, in the case that the material of the dielectric material 21, the source electrode 12 and the drain electrode 13 is not changed in the present application compared with the related art, although the dielectric material 21, the source electrode 12 and the drain electrode 13 are mis-etched by the etching gas used to etch the sacrificial layer in the prior art, in the present application, the protection layer 22 has a larger etching selectivity ratio to the sacrificial layer, so that the etching gas used to etch the sacrificial layer is blocked from transmitting to the dielectric material 21, and the dielectric material 21, the source electrode 12 and the drain electrode 13 are prevented from being mis-etched.

[0063] Further, the etching selectivity ratio of the dielectric material 21 to the sacrificial layer is smaller than the etching selectivity ratio of the source electrode 12 and the drain electrode 13 to the sacrificial layer, and smaller than the etching selectivity ratio of the protection layer 22 to the sacrificial layer, so that the source electrode 12 and the drain electrode 13 are etched by the etching gas to the least extent during the etching of the sacrificial layer, so that the gate electrode 15 directly contacts the source electrode 12 and the drain electrode 13.

[0064] In some possible implementation manners, the material type of the protective layer 22 is not limited in the embodiments of the present application, which can be a conductive material, or a semiconductor material, or an insulating material, as long as the protective layer 22 is not damaged by the etching gas used for etching the sacrificial layer, and can completely cover the sidewall of the dielectric material 21.

[0065] It is considered that, in the case where the chip does not contain the protective layer 22, the channel layer 11 is in contact with the gate dielectric layer 14 and the dielectric material 21 respectively; and in the case where the chip contains the protective layer 22, the channel layer 14 is in contact with the gate dielectric layer 14, the dielectric material 21 and the channel layer 14 respectively. That is, the structure in contact with the protective layer 22 is the same as the structure in contact with the channel layer 11. Therefore, as shown in FIG. 4, the material of the protective layer 22 can be selected as the same as the channel layer 11, that is, the material of the protective layer 22 is the same as the material of the channel layer 11, and in this case, the material of the protective layer 22 is a semiconductor material. In this way, even if the additional protective layer 22 is not removed, the protective layer 22 will not have a negative impact on the performance of the ring gate transistor, and also has a smaller impact on the structural stress in the ring gate transistor. On this basis, since the additional protective layer 22 does not need to be removed, the preparation process of the ring gate transistor is simplified.

[0066] In some possible implementation manners, the ring gate transistor can be an N-type transistor, or a P-type transistor. In the case where the ring gate transistor is a P-type transistor, the material of the source 12 and the drain 13 can include germanium silicon SiGe, and boron is doped in the germanium silicon to achieve its conductivity. The material of the sacrificial layer also generally includes germanium silicon SiGe, and therefore, in the process of etching the sacrificial layer, the source 12 and the drain 13 which also contain germanium silicon SiGe are very easy to be mis-etched by the etching gas.

[0067] However, the material of the channel layer 11 of the P-type transistor can include silicon Si, and the etching selectivity of silicon Si to germanium silicon SiGe is large, so silicon Si can also be selected as the material of the protective layer 22, so that in the case where the material of the source 12 and the drain 13 of the P-type transistor and the material of the sacrificial layer both include germanium silicon SiGe, the protective layer 22 is used to protect the source 12 and the drain 13 from being mis-etched.

[0068] In some embodiments, considering that the dielectric material 21, the protective layer 22 and the gate structure are all arranged on the side of the channel layer 11 facing the substrate 10 and the side of the channel layer 11 away from the substrate 10, the additional protective layer 22 occupies part of the position of the dielectric material 21 and / or the gate structure. If the protective layer 22 occupies part of the position of the gate structure, the overlapping area of the gate 15 and the channel layer 11 will be reduced, thereby causing the gate control ability of the gate 15 to decrease.

[0069] To solve the problem, as shown in FIG. 5, the present application proposes to reduce the thickness d1 of the dielectric material 21 in the direction from the source electrode 12 to the drain electrode 13, so that the additional protective layer 22 occupies part of the position of the dielectric material 21.

[0070] On this basis, the greater the etching selectivity ratio of the protective layer 22 to the sacrificial layer, the smaller the thickness d2 of the protective layer 22 can be. In other words, in the case of a large etching selectivity ratio of the protective layer 22 to the sacrificial layer, even a thin protective layer 22 will not be damaged by the gas used to etch the sacrificial layer. As mentioned above, the etching selectivity ratio of silicon Si to germanium silicon SiGe can be more than 100, so silicon Si can be used as the material of the protective layer 22. In this case, the amount of silicon Si used to deposit the protective layer 22 is small, and the thickness d2 of the protective layer 22 in the direction from the source electrode 12 to the drain electrode 13 is small. In this way, the protective layer 22 does not occupy too much of the position of the dielectric material 21, avoiding the problem that the thickness d1 of the dielectric material 21 is reduced too much, resulting in an increase in the parasitic capacitance between the gate electrode 15 and the source electrode 12 and the parasitic capacitance between the gate electrode 15 and the drain electrode 13.

[0071] Optionally, the thickness d1 of the dielectric material 21 in the direction from the source electrode 12 to the drain electrode 13 is in the range of [5nm, 10nm], for example, the thickness d1 of the dielectric material 21 is 5nm, 8nm, or 10nm. The thickness d2 of the protective layer 22 in the direction from the source electrode 12 to the drain electrode 13 is in the range of (0, 3nm], for example, the thickness d2 of the protective layer 22 is 0.5nm, 1nm, 1.8nm, or 3nm.

[0072] In another embodiment, the present application also provides a method for manufacturing a chip, as shown in FIG. 6, which can be implemented by the following steps:

[0073] S110, as shown in FIG. 7a, under the protection of the hard mask 40, a channel layer 11 and a sacrificial layer 30 are formed on the substrate 10, the channel layer 11 includes a lower surface facing the substrate 10 and an upper surface away from the substrate 10, and the sacrificial layer 30 covers the lower surface and the upper surface. Optionally, the material of the sacrificial layer 30 may, for example, include germanium silicon SiGe.

[0074] In some possible implementation manners, before step S110, the effective area where the channel layer 11 and the sacrificial layer 30 are located can be determined first; and after step S110 and before step S120, a dummy gate and a spacer can be formed on the side of the channel layer 11 and the sacrificial layer 30 away from the substrate 10.

[0075] In addition, in step S110, in addition to forming the channel layer 11 and the sacrificial layer 30, a trench etching of a stress source and drain process can be completed to form the source 12 and the drain 13 in the trench in a subsequent step S140; and the excess part of the channel layer 11 on the side away from the substrate 10 can be removed.

[0076] S120, as shown in FIG. 7b, the sacrificial layer 30 is partially removed in the direction from the source 12 to the drain 13 and the direction from the drain 13 to the source 12 to obtain the sacrificial layer middle pattern 301 and the first hollow part located at both ends of the sacrificial layer middle pattern 301.

[0077] In some possible implementation manners, step S120 can be completed in a dedicated machine table, for example, a remote plasma source (RPS) machine table, or a chemical machine table, etc. Both of the above two machine tables have a high SiGe-to-other materials etching selectivity, that is, the germanium silicon SiGe material can be quantitatively removed, but the process capability does not react with other materials.

[0078] S130, as shown in FIG. 7c and FIG. 7d, the protective layer 22 and the dielectric material 21 are sequentially filled in the first hollow part. At this time, the channel layer 11, the protective layer 22 and the dielectric material 21 of the ring gate transistor are formed on the substrate 10.

[0079] In some possible implementation manners, the process of forming the protective layer 22 is not limited in the embodiments of the present application, and optionally, the epitaxial growth process or the atomic layer deposition process can be used to deposit the protective layer 22.

[0080] S140, as shown in FIG. 7e, the source 12 and the drain 13 of the ring gate transistor are formed, and the source 12 and the drain 13 are arranged at both ends of the channel layer 11 and are in contact with the side wall of the channel layer 11. The material of the protective layer 22 is different from the materials of the dielectric material 21, the source 12 and the drain 13.

[0081] S150, as shown in FIG. 7f, under the protection of the protective layer 22, the sacrificial layer middle pattern 301 is etched to form the second hollow part located between the adjacent protective layers 22. In addition, the hard mask 40, the dummy gate and the spacer layer can be removed.

[0082] The protection layer 22 is located between the dielectric material 21 and the gate structure to be formed. Since the material of the protection layer 22 is different from the material of the dielectric material 21 and also different from the material of the source electrode 12 and the drain electrode 13, the etching selectivity of the protection layer 22 to the sacrificial layer is different from the etching selectivity of the dielectric material 21, the source electrode 12, the drain electrode 13 and the sacrificial layer. The material of the protection layer 22 can be selected to have a larger etching selectivity to the sacrificial layer, so that the protection layer 22 is not damaged by the etching gas used to etch the sacrificial layer during etching of the sacrificial layer. In this way, the protection layer 22 can completely cover the sidewall of the dielectric material 21 (i.e., the sidewall of the dielectric material 21 in contact with the protection layer 22), so that the etching gas used to etch the sacrificial layer is blocked by the protection layer 22 from entering the source electrode 12 and the drain electrode 13. On the one hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material 21, the source electrode 12 and the drain electrode 13, so that the subsequently formed gate electrode 15 is squeezed out of the gate dielectric layer 14 in the narrow leakage channel, resulting in a short circuit between the gate electrode 15 and the source electrode 12 and the drain electrode 13. On the other hand, the etching gas used to etch the sacrificial layer is prevented from etching a leakage channel in the dielectric material 21, so that the subsequently formed gate electrode 15 forms a small tip in the leakage channel to avoid the gate electrode 15 from generating a tip discharge, resulting in a high electric field.

[0083] In some possible implementation manners, as mentioned above, the material of the protection layer 22 can be selected to have a larger etching selectivity to the sacrificial layer. To achieve that the protection layer 22 completely covers the sidewall of the dielectric material 21, the etching selectivity of the protection layer 22 to the sacrificial layer can be greater than the etching selectivity of the dielectric material 21, the source electrode 12 and the drain electrode 13 to the sacrificial layer. For example, the etching selectivity of the protection layer to the sacrificial layer is greater than 100.

[0084] In this way, in the case that the material of the dielectric material 21 and the material of the source electrode 12 and the drain electrode 13 are not changed in the present application and in the related art, although the dielectric material 21 and the source electrode 12 and the drain electrode 13 are mis-etched by the etching gas used to etch the sacrificial layer in the prior art, in the present application, the protection layer 22 has a large etching selectivity to the sacrificial layer, so that the etching gas used to etch the sacrificial layer is blocked from being transmitted to the dielectric material 21, and the dielectric material 21, the source electrode 12 and the drain electrode 13 are prevented from being mis-etched.

[0085] In some possible implementation manners, the material type of the protection layer 22 is not limited in the embodiments of the present application, which can be a conductive material, or a semiconductor material, or an insulating material, as long as the protection layer 22 is not damaged by the etching gas used to etch the sacrificial layer 30 and can completely cover the sidewall of the dielectric material 21.

[0086] In the case that the chip does not contain the protective layer 22, the channel layer 11 is in contact with the gate dielectric layer 14 and the dielectric material 21 respectively; in the case that the chip contains the protective layer 22, the protective layer 11 is in contact with the gate dielectric layer 14, the dielectric material 21 and the channel layer 14 respectively. That is, the structure in contact with the protective layer 22 is the same as the structure in contact with the channel layer 11. Therefore, as shown in FIG. 4, the material of the protective layer 22 can be selected as the same as the channel layer 11, that is, the material of the protective layer 22 is the same as the material of the channel layer 11, and in this case, the material of the protective layer 22 is a semiconductor material. In this way, even if the additional protective layer 22 is not removed, the protective layer 22 will not have a negative impact on the performance of the ring gate transistor, and also has a smaller impact on the structural stress in the ring gate transistor. On this basis, since the additional protective layer 22 does not need to be removed, the preparation process of the ring gate transistor is simplified.

[0087] In some possible implementations, the ring gate transistor can be an N-type transistor or a P-type transistor. In the case that the ring gate transistor is a P-type transistor, the material of the source 12 and the drain 13 can include germanium silicon SiGe, and boron is doped in the germanium silicon to achieve its conductivity. The material of the sacrificial layer 30 also generally includes germanium silicon SiGe, so in the process of etching the sacrificial layer 30, the source 12 and the drain 13 which also contain germanium silicon SiGe are very easy to be mis-etched by the etching gas.

[0088] However, the material of the channel layer 11 of the P-type transistor can include silicon Si, and the etching selectivity of silicon Si is larger than that of germanium silicon SiGe, so silicon Si can also be selected as the material of the protective layer 22, so that in the case that the material of the source 12 and the drain 13 of the P-type transistor and the material of the sacrificial layer both include germanium silicon SiGe, the protective layer 22 is used to protect the source 12 and the drain 13 from being mis-etched.

[0089] S160, as shown in FIG. 3, a gate structure is formed in the second hollow part. The gate structure includes a gate 15 surrounding the channel layer 11, and a gate dielectric layer 14 for isolating the gate 15 and the channel layer 11. The dielectric material 21 is located between the source 12 and the gate structure, and between the drain 13 and the gate structure. The protective layer 22 is located between the dielectric material 21 and the gate structure, and the protective layer 22 can completely cover the sidewall of the dielectric material 21.

[0090] In some possible implementations, considering that the dielectric material 21, the protective layer 22 and the gate structure are all arranged on the side of the channel layer 11 facing the substrate 10 and the side of the channel layer 11 away from the substrate 10, the additional protective layer 22 occupies part of the position of the dielectric material 21 and / or the gate structure. If the protective layer 22 occupies part of the position of the gate structure, the overlapping area of the gate 15 and the channel layer 11 is reduced, and thus the gate control ability of the gate 15 is reduced.

[0091] To solve the problem, as shown in FIG. 5, the present application reduces the thickness d1 of the dielectric material 21 in the direction from the source electrode 12 to the drain electrode 13, so that the additional protective layer 22 occupies part of the position of the dielectric material 21.

[0092] On this basis, the greater the etching selectivity ratio of the protective layer 22 to the sacrificial layer, the smaller the thickness d2 of the protective layer 22 can be. In other words, in the case of a large etching selectivity ratio of the protective layer 22 to the sacrificial layer, even a thin protective layer 22 will not be damaged by the gas used to etch the sacrificial layer. As mentioned above, the etching selectivity ratio of silicon Si to germanium silicon SiGe is large, which can be more than 100. Therefore, silicon Si can be used as the material of the protective layer 22. In this case, the amount of silicon Si used to deposit the protective layer 22 is small, and the thickness d2 of the protective layer 22 in the direction from the source electrode 12 to the drain electrode 13 is small. In this way, the protective layer 22 does not occupy too much position of the dielectric material 21, so as to avoid that the thickness d1 of the dielectric material 21 with a small dielectric constant is reduced too much, and thus the parasitic capacitance between the gate 15 and the source electrode 12 and the parasitic capacitance between the gate 15 and the drain electrode 13 are both increased.

[0093] Optionally, the thickness d1 of the dielectric material 21 in the direction from the source electrode 12 to the drain electrode 13 ranges from 5 nm to 10 nm, for example, the thickness d1 of the dielectric material 21 is 5 nm, 8 nm or 10 nm. The thickness d2 of the protective layer 22 in the direction from the source electrode 12 to the drain electrode 13 ranges from 0 to 3 nm, for example, the thickness d2 of the protective layer 22 is 0.5 nm, 1 nm, 1.8 nm or 3 nm.

[0094] In addition, other explanations and benefits of the embodiments of the present application are the same as those of the chip in the previous embodiment, and will not be repeated here.

[0095] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above specific implementation, and the above specific implementation is only illustrative but not restrictive, and those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A chip, characterized in that, include: Substrate; A gate-around transistor disposed on the substrate; the gate-around transistor includes a channel layer, a gate structure, a source, and a drain; the gate structure includes a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate from the channel layer; the source and the drain are disposed at opposite ends of the channel layer; A dielectric material disposed between the source and the gate structure, and between the drain and the gate structure; A protective layer is filled between the dielectric material and the gate structure; the material of the protective layer is different from the materials of the dielectric material, the source electrode, and the drain electrode, and the protective layer completely covers the sidewalls of the dielectric material.

2. The chip according to claim 1, characterized in that, The protective layer is made of the same material as the channel layer.

3. The chip according to claim 1 or 2, characterized in that, The gate-ring transistor is a P-type transistor; The source and drain are made of germanium-silicon, and the channel layer and the protective layer are both made of silicon.

4. The chip according to any one of claims 1-3, characterized in that, Along the direction from the source to the drain, the thickness of the dielectric material ranges from [5 nm, 10 nm]; and / or, The thickness of the protective layer ranges from 0 to 3 nm along the direction from the source to the drain.

5. A method for fabricating a chip, characterized in that, include: A channel layer, a protective layer, and a dielectric material of a gate-ring transistor are sequentially formed on a substrate. The source and drain of the gate ring transistor are formed, and the source and drain are respectively disposed at both ends of the channel layer; the material of the protective layer is different from the dielectric material, the material of the source, and the material of the drain. A gate structure is formed; the gate structure includes a gate surrounding the channel layer, and a gate dielectric layer for isolating the gate from the channel layer; the dielectric material is located between the source and the gate structure, and between the drain and the gate structure; the protective layer is located between the dielectric material and the gate structure, and the protective layer completely covers the sidewalls of the dielectric material.

6. The method for fabricating a chip according to claim 5, characterized in that, The method of sequentially forming a channel layer, a protective layer, and a dielectric material for a gate-ring transistor on a substrate includes: A channel layer and a sacrificial layer are formed on the substrate in a stacked manner; the channel layer includes a lower surface facing the substrate and an upper surface facing away from the substrate, and the sacrificial layer covers the lower surface and the upper surface; The sacrificial layer is partially removed along the direction from the source to the drain and the direction from the drain to the source to obtain a middle pattern of the sacrificial layer and a first cutout portion, wherein the first cutout portion is located at both ends of the middle pattern of the sacrificial layer. The protective layer and the dielectric material are sequentially filled into the first hollowed-out portion.

7. The method for fabricating a chip according to claim 6, characterized in that, After forming the source and drain of the ring-gate transistor and before forming the gate structure, the chip fabrication method further includes: Under the protection of the protective layer, the pattern in the middle of the sacrificial layer is etched to form a second hollow portion, which is located between adjacent protective layers; The formation of the gate structure includes: The grating structure is formed in the second hollowed-out portion.

8. The method for fabricating a chip according to claim 7, characterized in that, The etching selectivity ratios of the source, the drain, the dielectric material, and the sacrificial layer are all less than the etching selectivity ratio of the protective layer and the sacrificial layer.

9. The method for fabricating a chip according to claim 8, characterized in that, The etching selectivity ratio of the dielectric material to the sacrificial layer is less than the etching selectivity ratio of the source, the drain and the sacrificial layer, and less than the etching selectivity ratio of the protective layer and the sacrificial layer.

10. The method for fabricating a chip according to any one of claims 5-8, characterized in that, The protective layer is made of the same material as the channel layer.

11. The method for fabricating a chip according to claim 10, characterized in that, The gate-ring transistor is a P-type transistor; The source and drain are made of germanium-silicon, and the channel layer and the protective layer are both made of silicon.

12. An electronic device, characterized in that, It includes a circuit board and a chip as described in any one of claims 1-4, wherein the chip is disposed on the circuit board.

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