Method for metallization of ultra-high aspect ratio through silicon via in three-dimensional integrated circuit

Abstract

The present invention belongs to the technical field of semiconductor manufacturing. Particularly disclosed is a method for metallization of an ultra-high aspect ratio through silicon via in a three-dimensional integrated circuit. The method specifically comprises the following steps: depositing an insulating layer on a surface of a substrate material and a through via by using atomic layer deposition (ALD) technology; depositing a barrier layer on the insulating layer by using atomic layer deposition technology, wherein the barrier layer is one or two of TiN and Ru; depositing a seed layer on the barrier layer by using atomic layer deposition technology; and electroplating copper on the deposited seed layer. The present invention uses the ALD copper seed layer deposition technology so as to deposit copper seed layers on various substrates, and uses a common acidic copper sulfate system electroplating solution so as to achieve better compatibility, establishing a process route for defect-free filling of ultra-high aspect ratio TSVs, thereby facilitating ultra-high-density interconnection in advanced packaging.

Description

A method for three-dimensional integrated circuit ultra-high aspect ratio through silicon via metallization

[0001] This application claims priority to:

[0002] The Chinese patent application No. 2024108175192, entitled "A method for three-dimensional integrated circuit ultra-high aspect ratio through silicon via metallization", filed with the China National Intellectual Property Office on June 24, 2024, is incorporated by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of semiconductor manufacturing, and specifically relates to a method for three-dimensional integrated circuit ultra-high aspect ratio through silicon via metallization. BACKGROUND

[0004] Moor's law leads to the increase of functional density in chips, which defines the number of interconnection devices in each chip area. As the minimum feature size of ICs decreases, the density of active devices increases. Since the area occupied by interconnection lines on the chip surface expands faster than the area required to accommodate active devices, device integration becomes more demanding. To solve this problem, current advanced packaging technologies mainly use multi-layer interconnection systems and 2.5D / 3D inter-chip interconnection technologies to achieve denser interconnections and higher performance. The key core of 2.5D / 3D integrated packaging is TSV (through silicon via) technology to achieve high bandwidth, low delay and low loss signal interconnection transmission in the three-dimensional direction of the chip, which is a key technology to break through the bottlenecks of high-performance chip memory wall, speed wall and power wall. TSV technology can greatly improve the interconnection density and performance of the chip, and significantly reduce the chip size and power consumption, etc.

[0005] At present, the TSV interconnection density has a large space for improvement, and the typical TSV diameter is about 10μm, and the aspect ratio is about 10:1. The reduction of the TSV diameter can not only reduce the occupied area and improve the interconnection density, but also can significantly reduce the stress near the Cu-TSV, so as to avoid affecting the device performance. The important semiconductor research institutions and leading enterprises in the world have begun to study the sub-micron diameter TSV technology. According to the TSV technology roadmap, the diameter of the future advanced TSV process is expected to be reduced to 1μm, and the aspect ratio reaches 20:1, so as to realize higher interconnection density and performance. According to the data of TSMC, if the vertical interconnection spacing of the chip stack is reduced from the existing 36μm to the future 0.9μm, the interconnection density can be increased by at least 3 orders of magnitude, and the communication speed of more than 10, the energy efficiency of 20 times and the bandwidth density of nearly 20,000 times can be realized. Reducing the size of the chip vertical interconnection TSV and improving the interconnection density will become an important engine to promote the continuous development of the chip to high performance and miniaturization, and lay a foundation for realizing higher communication speed, energy efficiency and bandwidth density. This also finds a new breakthrough direction for the field of high-end chip manufacturing in China, and it is urgent to promote the research and development of related technologies, and improve the technical level and market competitiveness of China in this field.

[0006] The patent CN202110841906.6 discloses a kind of basic copper electroplating solution, and the component of copper electroplating solution includes: copper ion, chloride ion, amino-carboxyl complexing agent, ester compound, glucose, phosphate ion, pH adjusting material, wherein the pH adjusting material is used to adjust the pH of the copper electroplating solution to be alkaline, and does not participate in chemical reaction.The use conditions of new plating solution are that the PH value is 9-10.5, the temperature is 38-45 DEG C, and finally high aspect ratio TSV filling is realized.However, using alkaline electroplating solution and higher temperature is different from commonly used acidic solution and room temperature, and the equipment needs to be modified accordingly, and the use scene is limited to a certain extent. SUMMARY

[0007] The present application aims to overcome the defects of the prior art and provide a method for metallization of ultra-high aspect ratio through silicon via in three-dimensional integrated circuit.

[0008] To achieve the above object, the technical scheme of the present application is as follows: a method for metallization of ultra-high aspect ratio through silicon via in three-dimensional integrated circuit, comprising the following steps:

[0009] (1) using Atomic layer deposition (ALD) atomic layer deposition technology to deposit an insulating layer on the surface of the substrate material and the through hole;

[0010] (2) Atomic layer deposition (ALD) is used to deposit a barrier layer on the insulating layer deposited in step (1), and the barrier layer is one or both of TiN and Ru;

[0011] (3) Atomic layer deposition (ALD) is used to deposit a seed layer on the barrier layer deposited in step (2);

[0012] (4) Copper is electroplated on the seed layer deposited in step (3).

[0013] In a preferred embodiment of the present application, the aperture of the through-hole packaging adapter is ≤ 2.5 μm, and the aspect ratio is ≥ 17:1.

[0014] In a preferred embodiment of the present application, the substrate material in step (1) includes but is not limited to silicon, titanium nitride, titanium, ruthenium, and glass.

[0015] In a preferred embodiment of the present application, the insulating layer in step (1) is silicon dioxide SiO2.

[0016] Further preferably, the ALD deposition precursor of SiO2 includes at least one of tris(dimethylamino)silane, bis(dimethylamino)silane, bis(tert-butylamino)silane, tris(dimethylamino)silane, diisopropylamine silane, and ozone (O3).

[0017] In a preferred embodiment of the present application, the barrier layer in step (2) is TiN+Ru, and a TiN layer is first deposited, and then a Ru layer is deposited.

[0018] The barrier layer has an adhesive effect, and can prevent copper from diffusing in silicon, thereby avoiding device leakage and affecting reliability.

[0019] In a preferred embodiment of the present application, the ALD deposition precursor of TiN includes at least one of titanium chloride, titanium iodide, titanium isopropyl alcohol, titanium tetrakis(dimethylamino), titanium tetrakis(diethylamino), tris(dimethylamino)cyclopentadienyl titanium, and ammonia (NH3), and the ALD deposition precursor of Ru includes at least one of RuCp2, Ru(EtCp)2, Ru(od)2, Ru(thd)3, Ru(DMBD)(CO)3, C 14 H 18 Ru, C 10 H 10 RuNH3, and at least one of O2 and O3.

[0020] In a preferred embodiment of the present application, the seed layer in step (3) is copper.

[0021] Further preferably, the ALD deposition precursor of copper comprises one of bis(dimethylamine-2-propanol) copper, bis(hexafluoroacetylacetonato) copper, N,N'-diisopropylethylamidinato copper, bis(hexafluoroacetylacetonato) copper, N,N'-di-tert-butylethylamidinato copper, one of diethyl zinc, trimethylaluminum, and hydrogen.

[0022] In a preferred embodiment of the present application, the electroplating copper plating solution in the step (4) comprises sulfuric acid, copper sulfate, chloride ion, brightener, inhibitor, leveler, the content of copper sulfate is 40-380 g / L, the content of sulfuric acid is 20-300 g / L, the content of chloride ion is 10-180 ppm, the content of brightener is 0.1-50 ppm, the content of inhibitor is 10-800 ppm, and the content of leveler is 0.1-50 ppm.

[0023] Further preferably, the brightener is one or more of sodium polydi-thio-propane sulfonate, sodium thiozolinyl di-thio-propane sulfonate, and sodium alcohol thio-propane sulfonate, the inhibitor is one or more of polyethylene glycol, polyoxyethylene lauryl ether, and PEG / PPG-17 / 6 copolymer, and the leveler is at least one of JGB and onium salt compound.

[0024] Further preferably, the onium salt compound is one or more of 1,3-di-mesityl imidazol-2-ylidene, 1,3-bis(2,6-diisopropylphenyl)imidazolidin-2-ylidene, 2-mesityl-5-methylimidazo[1,5-a]pyridinium chloride, and tetrafluoroborate troponium.

[0025] Compared with the prior art, the present application has the following beneficial effects:

[0026] 1. The present application adopts the ALD copper seed layer deposition technology, can deposit copper seed layer on different substrates, and adopts the common acidic copper sulfate system electroplating solution, has good compatibility, opens up the process route of defect-free filling of ultra-high aspect ratio TSV, and is beneficial to advanced packaging and ultra-high density interconnection.

[0027] The present application deposits TiN layer on the insulating layer through ALD, then deposits Ru layer, and finally obtains copper seed layer through ALD, which has good quality and low resistance, and is beneficial to TSV copper electroplating filling. BRIEF DESCRIPTION OF DRAWINGS

[0028] Fig. 1 is a TSV cross-sectional energy spectrum analysis diagram after copper seed layer deposition of example 1;

[0029] Fig. 2 is a TSV upper surface SEM diagram after copper seed layer deposition of example 1;

[0030] Fig. 3 is a TSV cross-sectional FIB-SEM diagram after copper electroplating of example 1. DETAILED DESCRIPTION

[0031] In order to make the objects, technical solutions and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings and specific embodiments. However, the protection scope of the present application is not limited to these embodiments. Identical reference signs in the specification represent identical elements, and similar reference signs represent similar elements.

[0032] In the description of the present application, it should be understood that the terms "upper", "lower", "front", "back", "left", "right", "horizontal", "vertical", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship shown in the perspective view of the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0033] Example 1

[0034] Deposition of an insulating layer: an insulating layer SiO2 is deposited on the surface of the substrate material silicon and the through hole by ALD;

[0035] Deposition of a barrier layer: a TiN layer is deposited on the above insulating layer by ALD, the precursors tetrakis(diethylamino)titanium and ammonia (NH3) are selected, and the thickness of the TiN layer is 15 nm; then a Ru layer is deposited on the surface of the TiN layer by ALD, the precursor is C 10 H 10 RuNH3 and O3, and the thickness of the Ru layer is 5 nm; a TiN+Ru barrier layer is obtained.

[0036] Deposition of a seed layer: a Cu layer is deposited on the above barrier layer by ALD, the precursors are N,N'-di-tert-butylacetamidine copper and hydrogen, and the thickness of the Cu layer is 6 nm;

[0037] Electroplating of copper: after the wafer is cleaned by plasma, it is wetted in vacuum and then enters the electroplating tank, and copper is electroplated on the seed layer Cu; the current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25°C;

[0038] Electroplating of copper: after the wafer is cleaned by plasma, it is wetted in vacuum and then enters the electroplating tank, and copper is electroplated on the seed layer Cu; the current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25°C;

[0039] Through hole specifications: the upper opening is 2.3 μm, the hole depth is 45 μm, and the aspect ratio is 19:1.

[0040] Figure 1 is a TSV cross-sectional element energy spectrum analysis diagram after copper seed layer deposition of Example 1; from Figure 1, it can be seen that the Cu seed layer can completely cover the entire TSV, providing a good conductive environment for subsequent electroplating. Figure 2 is a TSV upper surface SEM diagram after copper seed layer deposition of Example 1; from Figure 2, it can be seen that the opening of the TSV after deposition of the Cu seed layer is only about 2.3 μm. Figure 3 is a TSV cross-sectional FIB-SEM diagram after electroplating copper of Example 1; from Figure 3, it can be seen that the TSV achieves defect-free copper filling, indicating that the electroplating solution adopts a "from bottom to top" filling method, which has good filling capacity.

[0041] After depositing a TiN layer on the insulating layer SiO2 by ALD, then depositing a Ru layer, and finally obtaining a copper seed layer by ALD, the quality of the copper seed layer is good and the resistance is low, which is conducive to TSV electroplating copper filling.

[0042] Example 2

[0043] Deposition of insulating layer: depositing an insulating layer SiO2 on the surface of the substrate material silicon and the through hole by ALD;

[0044] Deposition of barrier layer: depositing a barrier layer TiN on the above insulating layer by ALD: selecting the precursor tetrakis (diethylamine) titanium and ammonia (NH3), and depositing a TiN layer with a thickness of 25 nm;

[0045] Deposition of seed layer: depositing Cu on the above barrier layer Ru by ALD, selecting the precursor as bis (hexafluoroacetylacetone) copper and diethyl zinc, and depositing a Cu layer with a thickness of 8 nm.

[0046] Electroplating copper: after the wafer is cleaned by plasma, it is wetted in vacuum and then enters the electroplating tank to electroplate copper on the seed layer Cu; the current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25°C.

[0047] Electroplating copper plating solution: the basic plating solution is copper sulfate 260 g / L, sulfuric acid 50 g / L, and chloride ion 60 ppm; the brightener is sodium polydithiopropanesulfonate 5 ppm, the inhibitor is polyethylene glycol 500 ppm, and the leveler is 1,3-bis (2,6-diisopropylphenyl) imidazolinone-2-yl 8 ppm.

[0048] Silicon through hole specification: upper opening 2.3 μm, hole depth 45 μm, aspect ratio 19:1.

[0049] Example 3

[0050] Deposition of insulating layer: depositing an insulating layer SiO2 on the surface of the substrate material silicon and the through hole by ALD;

[0051] Deposition of barrier layer: depositing a barrier layer Ru on the above insulating layer by ALD; selecting the precursor as C10 H 10 RuNH3and O2, depositing Ru layer thickness of 6 nm.

[0052] Depositing seed layer: depositing Cu on the above-mentioned barrier layer Ru by ALD; selecting the precursors as copper bis (hexafluoroacetylacetonate) and trimethylaluminum, and depositing Cu layer thickness of 5 nm.

[0053] Electroplating copper: after the wafer is subjected to plasma cleaning, the wafer is subjected to vacuum wetting to enter an electroplating tank, and copper is electroplated on the seed layer Cu; the current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25℃.

[0054] Through-hole specifications of silicon: upper opening of 2.3 μm, hole depth of 45 μm, and aspect ratio of 19:1.

[0055] Electroplating copper plating solution: the basic plating solution is copper sulfate 260 g / L, sulfuric acid 50 g / L, and chloride ion 50 ppm; the brightener is sodium polydithiobispropane sulfonate 5 ppm, the inhibitor is polyethylene glycol 400 ppm, and the leveler is 1,3-di-mesityl imidazol-2-yl 5 ppm.

[0056] Comparative Example 1

[0057] Directly depositing Cu seed layer on the surface of the silicon substrate material and the through-hole by ALD, selecting the precursors as copper bis (hexafluoroacetylacetonate) and trimethylaluminum, and depositing Cu layer thickness of 10 nm;

[0058] Electroplating copper: after the wafer is subjected to plasma cleaning, the wafer is subjected to vacuum wetting to enter an electroplating tank. The current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25℃.

[0059] Electroplating copper plating solution: the basic plating solution is copper sulfate 260 g / L, sulfuric acid 50 g / L, and chloride ion 50 ppm; the brightener is sodium polydithiobispropane sulfonate 5 ppm, the inhibitor is polyethylene glycol 400 ppm, and the leveler is 1,3-di-mesityl imidazol-2-yl 5 ppm.

[0060] Through-hole specifications of silicon: upper opening of 2.3 μm, hole depth of 45 μm, and aspect ratio of 19:1.

[0061] The results are that the ALD Cu resistance is relatively large, the copper layer obtained after electroplating appears fogging, is easy to fall off, and the like, and TSV defect-free copper filling cannot be achieved.

[0062] Comparative Example 2

[0063] Cu seed layer is deposited on the surface of glass substrate and through hole by ALD, and the precursors are copper bis (hexafluoroacetylacetone) and trimethylaluminum, and the thickness of Cu layer is 15nm;

[0064] Electroplating copper: after the wafer is cleaned by plasma, it is wetted in vacuum and then enters the electroplating tank. The current density is 0.3 ASD, the electroplating time is 30 min, the plating solution flow rate is 2 L / min, and the plating solution temperature is 25 DEG C.

[0065] Electroplating copper plating solution: the basic plating solution is copper sulfate 260 g / L, sulfuric acid 50 g / L, and chloride ion 50 ppm; the brightener is sodium polydithiopropanesulfonate 5 ppm, the inhibitor is polyethylene glycol 400 ppm, and the leveler is 1,3-di-mesityl imidazol-2-yl 5 ppm.

[0066] Through hole specifications of silicon: the upper opening is 2.3 microns, the hole depth is 45 microns, and the aspect ratio is 19:1.

[0067] The results show that the resistance of ALD Cu is relatively large, the copper layer obtained after electroplating appears fogging, is easy to fall off and the like, and the TSV defect-free copper filling cannot be realized.

[0068] The above examples are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing examples, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing examples, or make equivalent substitutions for part or all of the technical features; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application. Industrial applicability

[0069] The present application belongs to the technical field of semiconductor manufacturing, and specifically discloses a method for metallization of three-dimensional integrated circuit ultra-high aspect ratio through silicon via, which specifically comprises the following steps: depositing an insulating layer on the surface of a substrate material and a through hole by using atomic layer deposition technology; depositing a barrier layer on the insulating layer by using atomic layer deposition technology, the barrier layer being one or both of TiN and Ru; depositing a seed layer on the barrier layer by using atomic layer deposition technology; and electroplating copper on the deposited seed layer. The present application adopts ALD copper seed layer deposition technology, can deposit copper seed layer on different substrates, and adopts common acidic copper sulfate system electroplating solution, has good compatibility, breaks through the process route of ultra-high aspect ratio TSV defect-free filling, is beneficial to advanced packaging ultra-high density interconnection, and has industrial applicability.

Claims

1. A method for three-dimensional integrated circuit ultra-high aspect ratio through-silicon via metallization, characterized by, The method comprises the following steps: (1) depositing an insulating layer on the surface of a substrate material and a via hole by using ALD deposition technology; (2) depositing a barrier layer on the insulating layer deposited in step (1) by using ALD deposition technology, the barrier layer being one or both of TiN and Ru; (3) depositing a seed layer on the barrier layer deposited in step (2) by using ALD deposition technology; (4) electroplating copper on the seed layer deposited in step (3).

2. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The aperture of the via hole of the package adapter plate is ≤2.5 μm, and the aspect ratio is ≥17:

1.

3. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The insulating layer in step (1) is SiO2, and the substrate material comprises silicon and glass.

4. The method of ultra-high aspect ratio through-silicon via metallization of claim 2, wherein, The ALD deposition precursor of the SiO2 comprises ozone and at least one of tris(dimethylamino)silane, bis(diethylamino)silane, bis(tert-butylamino)silane, tris(dimethylamino)silane and diisopropylamine silane.

5. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The barrier layer in step (2) is TiN+Ru, and a TiN layer is deposited first, and then a Ru layer is deposited.

6. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The ALD deposition precursor of TiN in the step (2) comprises at least one of titanium chloride, titanium iodide, titanium isopropoxide, titanium tetra(dimethylamide), titanium tetra(diethylamide), tris(dimethylamide) cyclopentadienyl titanium, and ammonia; the ALD deposition precursor of Ru comprises RuCp2, Ru(EtCp)2, Ru(od)2, Ru(thd)3, Ru(DMBD)(CO)3, C 14 H 18 Ru, C 10 H 10 RuNH3, and at least one of O2 and O3.

7. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The seed layer in step (3) is copper, the ALD deposition precursor of the copper comprises at least one of bis(dimethylamine-2-propanol) copper, bis(hexafluoroacetylacetone) copper, N,N'-diisopropylacetamidinocopper, bis(hexafluoroacetylacetone) copper, N,N'-di-tert-butylacetamidinocopper, and at least one of diethyl zinc, trimethyl aluminum and hydrogen.

8. The method of ultra-high aspect ratio through-silicon via metallization of claim 1, wherein, The electroplating copper plating solution in step (4) comprises sulfuric acid, copper sulfate, chloride ions, brightener, inhibitor, leveling agent, the content of the copper sulfate is 40-380 g / L, the content of the sulfuric acid is 20-300 g / L, the content of the chloride ions is 10-180 ppm, the content of the brightener is 0.1-50 ppm, the content of the inhibitor is 10-800 ppm, and the content of the leveling agent is 0.1-50 ppm.

9. The method of ultra-high aspect ratio through-silicon via metallization of claim 8, wherein, The brightener is one or more mixtures of sodium polydithiopropyl sulfonate, sodium sultaine dithiopropyl sulfonate and sodium alcohol sulfyl propane sulfonate, the inhibitor is one or more mixtures of polyethylene glycol, polyoxyethylene lauryl ether and PEG / PPG-17 / 6 copolymer, and the leveling agent is at least one of JGB and onium salt compound.

10. The method of ultra-high aspect ratio through-silicon via metallization of claim 9, wherein, The onium salt compound is one or more mixtures of 1,3-di-mesityl imidazol-2-ylidene, 1,3-bis(2,6-diisopropylphenyl)imidazolidin-2-ylidene, 2-mesityl-5-methylimidazo[1,5-a]pyridinium chloride and tetrafluoroboric acid troponium.

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