Communication method inside chip, apparatus, chip, storage medium and program product

Abstract

Disclosed in the embodiments of the present disclosure are a communication method inside a chip, an apparatus, a chip, a storage medium and a program product. The communication method inside a chip comprises: when a sender transmits target data to a receiver, determining from a memory of a target chip at least one target cache area corresponding to the sender and capable of storing the target data; and, on the basis of a preset communication protocol, writing the target data into the at least one target cache area according to a preset storage format, the preset storage format comprising a cache area guidance used for indicating the next cache area.

Description

Communication method, device, chip, storage medium and program product inside chip

[0001] Cross-reference of related applications

[0002] The present disclosure is based on and claims priority to Chinese Patent Application No. 202410868030.8, filed on June 29, 2024, entitled "Communication method, device, chip, storage medium and program product inside chip", the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to, but is not limited to, the technical field of computer, and particularly relates to a communication method, device, chip, storage medium and program product inside chip. BACKGROUND

[0004] ZYNQ is a System on Chip (SoC) platform that combines Advanced RISC Machines (ARM) and Field Programmable Gate Array (FPGA) processors, and is particularly suitable for applications that require high-performance computing and customizable hardware logic, such as embedded systems, automotive control systems, and industrial control systems.

[0005] In applications built based on the ZYNQ platform, ARM is usually used to complete system-level data processing, and FPGA is used to complete data processing with high real-time requirements, so internal communication between ARM and FPGA is involved.

[0006] However, when communicating with FPGA, ARM needs to move data from a First In First Out (FIFO), Block Random Access Memory (BRAM), or Double Data Rate Synchronous Dynamic Random Access Memory (DDR) to an application-specified address, and in the case of a large amount of data, there is a problem of large system overhead and poor performance. SUMMARY

[0007] In view of this, the embodiments of the present disclosure at least provide a communication method, device, chip, storage medium and program product inside chip.

[0008] The technical solutions of the embodiments of the present disclosure are implemented as follows:

[0009] In one aspect, the embodiments of the present disclosure provide a chip-internal communication method, comprising: determining at least one target cache area corresponding to a sender and capable of storing target data from a memory of a target chip when the sender transmits the target data to a receiver; and writing the target data into the at least one target cache area according to a preset storage format based on a preset communication protocol, wherein the preset storage format comprises a cache area guide for indicating a next cache area.

[0010] It can be understood that the determination of the at least one target cache area required by the sender from the memory of the target chip when transmitting the target data means that a physical address inside the target chip is allocated to the sender for data transmission; in this way, the data interaction can be realized only by allocating the physical address of the memory inside the target chip to the sender for caching, and in the process of data interaction, multiple data transfers are not required, thereby reducing the system overhead and improving the data transmission efficiency and system performance. The writing of the target data into the at least one target cache area according to the preset storage format based on the preset communication protocol can realize the standardized writing of the data; and the cache area guide added during the writing helps to indicate the writing order of the target data in the target cache areas, which is convenient for subsequent guiding the receiver to read the target data from the multiple target cache areas. Thus, while realizing the data interaction between the sender and the receiver, the data transmission efficiency and system performance are improved, and the system overhead is reduced.

[0011] In some embodiments, the chip-internal communication method further comprises: determining at least one first physical address allocated to the sender based on the service requirement of the sender and the hardware configuration of the target chip; determining at least one first cache area corresponding to the sender based on the at least one first physical address; and setting the calling mode of the at least one first cache area in the preset communication protocol.

[0012] It can be understood that the allocation of the physical address of the target chip to the sender for data transmission can improve the data transmission rate of the sender compared to the use of external storage media. The setting of the calling mode of the at least one first cache area in the preset communication protocol can locate the at least one first cache area based on the preset communication protocol.

[0013] In some embodiments, the hardware configuration of the target chip comprises the distribution of the physical addresses of the memory; and the determination of the at least one first physical address allocated to the sender based on the service requirement of the sender and the hardware configuration of the target chip comprises: determining at least one second physical address that is not allocated based on the distribution of the physical addresses of the memory; and determining the at least one first physical address satisfying the service requirement of the sender from the at least one second physical address.

[0014] It can be understood that the unallocated physical addresses are determined according to the distribution of the physical addresses of the memory of the target chip, and then the physical addresses meeting the service requirements of the sender are determined from the unallocated physical addresses, so that the allocation of the physical addresses of the sender can be realized.

[0015] In some embodiments, the determining of the at least one first cache region corresponding to the sender based on the at least one first physical address comprises: determining a first division granularity based on the services processed by the sender and the data transmission requirements corresponding to each service; dividing the at least one first physical address according to the first division granularity to obtain at least one third physical address; and determining the at least one first cache region based on the at least one third physical address.

[0016] It can be understood that the physical addresses allocated to the sender are divided according to the first division granularity, and different data channels are formed to complement each other.

[0017] In some embodiments, the determining of the at least one first cache region based on the at least one third physical address comprises: determining a second division granularity based on the cache size required by each service when transmitting data each time; dividing the at least one third physical address according to the second division granularity to obtain at least one fourth physical address; and taking the storage space corresponding to the at least one fourth physical address as the at least one first cache region.

[0018] It can be understood that each data channel is divided into a plurality of small memories of the same size for caching according to the second division granularity, which can play a FIFO role.

[0019] In some embodiments, the determining of the at least one target cache region corresponding to the sender and capable of storing the target data from the memory of the target chip comprises: locating the at least one first cache region corresponding to the sender based on a preset communication protocol; and selecting at least one target cache region from the at least one first cache region corresponding to the sender based on the service to which the target data belongs and the writing situation of each first cache region.

[0020] It can be understood that at least one target cache region can be selected from the at least one first cache region according to the service to which the target data belongs and the writing situation of each first cache region, and the target data is written into the at least one target cache region according to a preset storage format.

[0021] In some embodiments, the selecting, from the at least one first cache area corresponding to the sending side, at least one target cache area based on the service to which the target data belongs and a write condition of each first cache area comprises: selecting, from the at least one first cache area, at least one second cache area based on the service to which the target data belongs; determining, from the at least one second cache area, at least one third cache area available based on an identification bit of the at least one second cache area; the identification bit representing whether the corresponding cache area has been written with data; and determining the at least one target cache area based on the at least one third cache area.

[0022] It can be understood that, since the cache areas corresponding to different services are different, the at least one second cache area corresponding to the service to which the target data belongs can be selected based on the service to which the target data belongs. The at least one third cache area available is selected based on the identification bit of the at least one second cache area, and then the at least one target cache area required by the target data is obtained.

[0023] In some embodiments, the writing, based on the preset communication protocol, the target data into the at least one target cache area according to the preset storage format comprises: determining whether the data transmission of the sending side can be performed at the current time based on the interrupt signal sent at a timing and an access period set for different objects; and in a case where the data transmission of the sending side can be performed at the current time, writing, based on the preset communication protocol, the target data into the at least one target cache area according to the preset storage format.

[0024] It can be understood that the interrupt signal sent at a timing and the access period set for different objects are used to restrict the access time of different objects, so as to avoid the problem of access conflict.

[0025] In some embodiments, the determining whether the data transmission of the sending side can be performed at the current time based on the interrupt signal sent at a timing and the access period set for different objects comprises: determining, based on a timing function of the target chip, a target time length at which the interrupt signal closest to the current time has been triggered; in a case where the target time length is in the access period of the sending side, determining that the data transmission of the sending side can be performed at the current time; and in a case where the target time length is in the access period of an object other than the sending side, determining that the data transmission of the sending side cannot be performed at the current time.

[0026] It can be understood that, according to the timing function of the target chip, the target time length at which the interrupt signal closest to the current time has been triggered can be determined, and then whether the data transmission of the sending side can be performed at the current time is determined according to the target time length.

[0027] In some embodiments, the writing of the target data into the at least one target cache area according to the preset storage format comprises: when the target data needs multiple cache areas for storage, dividing the target data based on the size of a single cache area to obtain multiple sub-data; sequentially writing the multiple sub-data into the at least one target cache area according to the preset storage format; and each target cache area includes the address of the next target cache area.

[0028] It can be understood that, in the case that the data amount of the target data is too large, the target data can be divided into multiple sub-data for caching.

[0029] In some embodiments, the preset storage format comprises an identification bit, a cache area guide, a net length, and payload data; the sequentially writing of the multiple sub-data into the at least one target cache area according to the preset storage format comprises: determining the jth target cache area corresponding to the ith sub-data and the (j+1)th target cache area corresponding to the (i+1)th sub-data; i and j are both positive integers greater than or equal to 1; writing the byte number of the ith sub-data, the ith sub-data, and the address of the (j+1)th target cache area into the jth target cache area as the net length, the payload data, and the cache area guide of the jth target cache area respectively; and after the writing, modifying the identification bit of the ith target cache area from a first identification value to a second identification value; the first identification value represents that the corresponding cache area has not been written with data, and the second identification value represents that the corresponding cache area can have been written with data.

[0030] It can be understood that, according to the cache area guide, the net length, the payload data, and the like, the caching of data can continuously determine the address of the next target cache area based on the cache area guide in the subsequent process, so as to read the data in the target cache area. After the writing, the frame identification bit of the target cache area is modified from the first identification value to the second identification value, so as to activate the target cache area, so that the target cache area is used only once and will not be repeatedly used, so as to prevent the data in the target cache area from being overwritten.

[0031] In one aspect, the disclosure embodiments provide a chip-internal communication method, which comprises: when a receiver acquires target data transmitted by a sender, locating the starting position of at least one target cache area based on the base address of the at least one target cache area indicated by a preset communication protocol; reading the target data from the at least one target cache area based on the starting position and the cache area guide in each target cache area; and the cache area guide is used to indicate the next cache area.

[0032] It can be understood that since the preset communication protocol can indicate the base address of the at least one target cache region, the first target cache region can be determined based on the base address of the at least one target cache region to locate the starting position of the at least one target cache region in the target chip; since the target data is written into the at least one target cache region, the cache region guide is added in each target cache region, and therefore, after the first target cache region is determined, the next target cache region can be constantly located and read based on the cache region guide in each target cache region to obtain the target data. In this way, when the sender and the receiver interact with each other, the external storage medium is not needed, and only the physical address of the internal memory of the target chip needs to be allocated to the sender for caching, so that the data interaction can be realized, and in the data interaction process, the data transfer needs to be performed multiple times, thereby reducing the system overhead and improving the data transmission efficiency and system performance.

[0033] In some embodiments, the reading of the target data from the at least one target cache region based on the starting position and the cache region guide in each target cache region includes: locating the first target cache region based on the starting position and reading the sub-data in the first target cache region; locating the second target cache region based on the cache region guide in the first target cache region and reading the sub-data in the second target cache region, and continuously locating and reading the sub-data in the next target cache region based on the cache region guide in the second target cache region until the target data is read from the at least one target cache region.

[0034] It can be understood that based on the cache region guide in each target cache region, the next target cache region can be constantly located to read the target data in the writing order.

[0035] In some embodiments, the reading of the sub-data in the first target cache region includes: determining whether the first target cache region has been written with data based on the identification bit of the first target cache region; in a case where it is determined that the first target cache region has been written with data, reading the sub-data in the first target cache region according to the net length of the first target cache region, and setting the identification bit of the first target cache region from the second identification value to the first identification value after the reading is completed; the first identification value represents that the corresponding cache region has not been written with data, and the second identification value represents that the corresponding cache region has been written with data.

[0036] It can be understood that before the reading, it can be determined whether each target cache region has been written with data according to the identification bit of each target cache region, and the reading of data is performed in a case where it is determined that the first target cache region has been written with data; in this way, the reading of data is performed after it is determined whether each target cache region is valid, which can improve the efficiency of data reading.

[0037] In another aspect, the embodiments of the present disclosure provide a chip-internal communication system, comprising a receiver and a transmitter;

[0038] The transmitter is configured to determine at least one target buffer area corresponding to the transmitter and capable of storing target data from a memory of a target chip when transmitting the target data to the receiver; and write the target data into the at least one target buffer area according to a preset storage format based on a preset communication protocol, wherein the preset storage format comprises a buffer area guide for indicating a next buffer area.

[0039] The receiver is configured to locate a starting position of the at least one target buffer area based on a base address of the at least one target buffer area indicated by the preset communication protocol when obtaining the target data transmitted by the transmitter; and read the target data from the at least one target buffer area based on the starting position and the buffer area guide in each target buffer area.

[0040] In another aspect, the embodiments of the present disclosure provide a chip-internal communication device, comprising a determination unit configured to determine at least one target buffer area corresponding to a transmitter and capable of storing target data from a memory of a target chip when the transmitter transmits the target data to a receiver; and a writing unit configured to write the target data into the at least one target buffer area according to a preset storage format based on a preset communication protocol, wherein the preset storage format comprises a buffer area guide for indicating a next buffer area.

[0041] In another aspect, the embodiments of the present disclosure provide a chip-internal communication device, comprising a determination unit configured to determine at least one target buffer area corresponding to a transmitter and capable of storing target data from a memory of a target chip when the transmitter transmits the target data to a receiver; and a writing unit configured to write the target data into the at least one target buffer area according to a preset storage format based on a preset communication protocol, wherein the preset storage format comprises a buffer area guide for indicating a next buffer area.

[0042] In another aspect, the embodiments of the present disclosure provide a chip, comprising a memory and a processor, wherein the memory stores a computer program capable of being run on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0043] In another aspect, the embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above method.

[0044] In yet another aspect, the embodiments of the present disclosure provide a computer program, including computer readable codes, when the computer readable codes are run in a chip, a processor in the chip executes part or all steps of the above method.

[0045] In yet another aspect, the embodiments of the present disclosure provide a computer program product, including a non-transitory computer readable storage medium storing a computer program, when the computer program is read and executed by a computer, part or all steps of the above method are implemented.

[0046] In the embodiments of the present disclosure, determining at least one target cache area required by the sender when transmitting the target data from the memory of the target chip refers to allocating a physical address inside the target chip to the sender for data transmission; in this way, only the physical address of the memory inside the target chip needs to be allocated to the sender for caching, so that data interaction can be realized, and in the process of data interaction, multiple data transfers are not required, thereby reducing system overhead and improving data transmission efficiency and system performance. Based on the preset communication protocol, the target data is written into the at least one target cache area according to the preset storage format, so that the standardized writing of data can be realized; and the cache area guide is added during writing, which is helpful to indicate the writing order of the target data in each target cache area, and facilitates subsequent guiding the receiver to read the target data from the multiple target cache areas. Thus, while realizing the data interaction between the sender and the receiver, the data transmission efficiency and system performance are improved, and the system overhead is reduced.

[0047] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, rather than limiting the technical solutions of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0048] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0049] FIG. 1 is a schematic diagram of an implementation process of a communication method inside a chip according to an embodiment of the present disclosure;

[0050] FIG. 2 is a schematic diagram of an implementation process of a communication method inside a chip according to an embodiment of the present disclosure;

[0051] FIG. 3 is a schematic diagram of an implementation process of a communication method inside a chip according to an embodiment of the present disclosure;

[0052] FIG. 4 is a schematic diagram of an implementation of memory distribution of OCR in a communication method inside a chip according to an embodiment of the present disclosure;

[0053] Fig. 5 is a schematic diagram of implementation of physical address division in a chip internal communication method according to an embodiment of the present disclosure;

[0054] Fig. 6 is a schematic diagram of implementation of physical address division in a chip internal communication method according to an embodiment of the present disclosure;

[0055] Fig. 7 is a schematic diagram of implementation of preset storage format in a chip internal communication method according to an embodiment of the present disclosure;

[0056] Fig. 8 is a schematic diagram of implementation of a chip internal communication method according to an embodiment of the present disclosure;

[0057] Fig. 9 is a schematic diagram of implementation of an interrupt signal in a chip internal communication method according to an embodiment of the present disclosure;

[0058] Fig. 10 is a schematic diagram of implementation of a chip internal communication method according to an embodiment of the present disclosure;

[0059] Fig. 11 is a schematic diagram of implementation of a chip internal communication method according to an embodiment of the present disclosure;

[0060] Fig. 12 is a schematic diagram of implementation of a data receiving process in a chip internal communication method according to an embodiment of the present disclosure;

[0061] Fig. 13 is a schematic diagram of implementation of a data sending process in a chip internal communication method according to an embodiment of the present disclosure;

[0062] Fig. 14 is a schematic diagram of a chip internal communication device according to an embodiment of the present disclosure;

[0063] Fig. 15 is a schematic diagram of a chip internal communication device according to an embodiment of the present disclosure;

[0064] Fig. 16 is a schematic diagram of a chip hardware entity according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0065] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below with reference to the drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0066] In the following description, "some embodiments" are described, which describe a subset of all possible embodiments, but it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0067] The terms "first / second / third" are only to distinguish similar objects, and do not represent a specific order of the objects. Understandably, the "first / second / third" can be interchanged with a specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0068] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the specification herein is for describing the present disclosure only and is not intended to be limiting of the present disclosure.

[0069] In order to better understand the communication method inside the chip provided by the embodiments of the present disclosure, the solutions in the related art will be described first.

[0070] With the increasing performance requirements of the power, automotive and other industries on embedded devices, using a system on chip (SoC) to replace a microcontroller unit (MCU) has become the preferred choice for embedded device development. Among them, the ZYNQ series, which combines ARM and FPGA processors, can run complex systems such as Linux and VxWorks, and can enhance real-time performance through FPGA, so it is widely used in SoC.

[0071] The ZYNQ series includes multiple ARM cores and a single FPGA core, which interact through an advanced extensible interface (AXI) bus. In actual device development, both the ARM and FPGA parts are usually used, with the former being used to complete system-related work and the latter being used to complete data processing with high real-time requirements, so internal communication between the two is involved.

[0072] Although the AXI bus itself provides two communication methods, advanced extensible interface-general purpose (AXI-GP) (low speed) and advanced extensible interface-high performance (AXI-HP) (high speed), there are certain limitations in actual use. For devices with high real-time requirements, the time overhead and performance of internal communication are of great importance.

[0073] In the existing development scheme based on the ZYNQ platform, FIFO and BRAM are usually used as media, and the AXI-GP interface is used for low-speed access. For internal communication of large data, DDR is used as media, and the AXI-HP interface is used for access. However, this way has the following disadvantages:

[0074] 1) Since the actual read-write rate of the AXI-GP interface is slow, the time of each address access is more than 250 nanoseconds, so the FIFO and BRAM which rely on address to obtain data will seriously affect the efficiency. The communication time is closely related to the data size, and for 1K bytes of data, more than 20 microseconds of overhead is required. Especially in a system with high real-time requirements (for example, a system with a real-time requirement of hundreds of microseconds), communication occupies a large part of the time, resulting in performance degradation.

[0075] 2) The data interaction using DDR as media can only ensure the synchronization of memory data, and does not provide a read-write mutual exclusion mechanism itself, and redundancy occurs data pollution. The traditional way is to use register address access for mutual exclusion, but the address access is also relatively inefficient, resulting in performance degradation.

[0076] 3) In the traditional communication method, the ARM side needs to perform data transfer, that is, to transfer data from FIFO, BRAM or DDR to the address specified by the application. In the case of large data, this data transfer also causes system overhead, resulting in overall performance degradation.

[0077] Therefore, the embodiment of the present disclosure provides a chip internal communication method to support high-speed data interaction between ARM and FPGA in the ZYNQ platform, so as to solve the problems of insufficient real-time performance and lack of cache in the existing internal communication. The method can be executed by a processor of a target chip. As shown in FIG. 1, the method includes the following steps 101 to 102:

[0078] In step 101, when transmitting target data to a receiving party, at least one target cache area corresponding to a sender and capable of storing the target data is determined from a memory of a target chip.

[0079] The target chip is a chip with software programmability and hardware programmability. The software programmability is provided by an ARM processor, and the hardware programmability is provided by an FPGA; that is, the target chip is a chip that combines an FPGA and an ARM processor. In a feasible implementation manner, the target chip can be a ZYNQ chip.

[0080] The sender refers to any component in the target chip that can be a data sender. The receiver refers to any component in the target chip that can be a data receiver. For example, the sender can be an ARM in a ZYNQ chip, and the receiver can be an FPGA in the ZYNQ chip. For another example, the sender can be an FPGA in a ZYNQ chip, and the receiver can be an ARM in the ZYNQ chip.

[0081] The memory of the target chip refers to a hardware device in the target chip for storing data and programs. In a possible implementation, the memory of the target chip can be one or more of an on-chip memory (OCM), a dynamic memory, a static memory, etc.

[0082] It should be noted that, since the purpose of the present disclosure is to provide a communication method in a target chip to ensure efficient data interaction between an ARM and an FPGA. Therefore, to ensure the efficiency of data interaction, OCM is selected as the physical medium in the data interaction process of the present disclosure.

[0083] The target data refers to data that the sender wants to transmit to the receiver. In a possible implementation, the target data can be one or more of a control instruction, an address signal, a clock signal, configuration data, an interrupt signal, a data signal, etc.

[0084] The at least one target cache area refers to one or more storage spaces required when the target data is cached. Since the target data sent by the sender is not immediately received and processed by the receiver, when the sender sends the target data, the sender needs to be allocated at least one target cache area to temporarily store the target data, so that the receiver can read the target data from the at least one target cache area after processing the current transaction.

[0085] In some embodiments, when the sender transmits the target data to the receiver, a segment of physical addresses can be determined from the OCR (memory) of the target chip, and the segment of physical addresses is used as the physical medium for the sender to transmit data to the receiver. These physical addresses are at least one target cache area required by the sender when transmitting the target data.

[0086] Step 102, based on the preset communication protocol, write the target data into the at least one target cache area according to a preset storage format; the preset storage format includes a cache area guide for indicating a next cache area.

[0087] The preset communication protocol refers to a pre-set communication protocol for maintaining data interaction between the sender and the receiver. In a possible implementation, the preset communication protocol can indicate a base address of at least one target cache region corresponding to the target data, and a storage format at the time of writing. The base address of the at least one target cache region is used to locate the position of the at least one target cache region in the target chip; and the storage format at the time of writing is used to write the target data according to a specific storage format, so as to read and write the target data.

[0088] The storage format at the time of writing (preset storage format) refers to the form in which the target data should be stored in the target cache region. The preset storage format can include a cache region guide and payload data. The cache region guide is used to indicate the address of the next cache region. The payload data is the data actually transmitted (for example, the target data).

[0089] In some embodiments, the code for accessing the base address of the at least one target cache region can be pre-set in the preset communication protocol, so that the starting position of the at least one target cache region in the target chip can be located based on the base address of the at least one target cache region indicated by the preset communication protocol.

[0090] In some embodiments, if the target data needs to be stored in multiple target cache regions, the target data needs to be stored in the multiple target cache regions in a scattered manner, and the writing order between the target cache regions needs to be considered at the time of storage. Specifically, at each time of storage, the address of the next target cache region can be determined, and the address of the next target cache region and the current data can be written into the current target cache region based on the preset communication protocol.

[0091] In some embodiments, if the target data only needs to be stored in one target cache region, in order to ensure the consistency of the data format, the address of the next target cache region can be filled with a preset character, and the preset character and the target data can be written into the target cache region. The preset character can be one or more characters that do not affect the target data. For example, the preset character can be a string of multiple characters all being 0 or all being 1.

[0092] In some embodiments, after the target data is written into the multiple target cache regions, the starting position of the at least one target cache region in the target chip can be located based on the base address of the at least one target cache region indicated by the preset communication protocol, the data in the at least one target cache region can be read in sequence based on the starting position and the cache region guide in each target cache region, and the target data can be obtained.

[0093] It should be noted that steps 101 to 102 can be executed by the processor of the target chip or by the sender with data processing capability. For example, when the ARM in the ZYNQ chip sends data to the FPGA, steps 101 to 102 can be executed by the ARM.

[0094] In the embodiments of the present disclosure, determining at least one target cache region required by the sender when transmitting the target data from the memory of the target chip means allocating a physical address inside the target chip to the sender for data transmission. In this way, only the physical address of the memory inside the target chip needs to be allocated to the sender for caching, so as to realize data interaction, and multiple data transfers are not required in the data interaction process, thereby reducing system overhead and improving data transmission efficiency and system performance. Writing the target data into the at least one target cache region according to the preset storage format based on the preset communication protocol can realize standardized writing of data, and adding a cache region guide when writing is helpful to indicating the writing order of the target data in each target cache region, facilitating subsequent guiding of the receiver to read the target data from the multiple target cache regions. Thus, while realizing data interaction between the sender and the receiver, the data transmission efficiency and system performance are improved, and the system overhead is reduced.

[0095] The embodiments of the present disclosure provide a communication method inside a chip, which can be executed by the processor of the target chip. As shown in FIG. 2, the method comprises the following steps 201 to 202:

[0096] Step 201: When the receiver acquires the target data transmitted by the sender, the starting position of the at least one target cache region is located based on the base address of the at least one target cache region indicated by the preset communication protocol.

[0097] The above-mentioned scheme in steps 101 to 102 is an operation required to be performed by the sender when transmitting the target data to the receiver, and the scheme in steps 201 to 202 is an operation required to be performed by the receiver when acquiring the target data transmitted by the sender.

[0098] In some embodiments, since the preset communication protocol can indicate the base address of the at least one target cache region, the starting position of the at least one target cache region in the target chip can be located based on the base address of the at least one target cache region indicated by the preset communication protocol. The starting position of the at least one target cache region in the target chip is the position of the first target cache region.

[0099] Step 202: Reading the target data from the at least one target cache region based on the starting position and the cache region guide in each target cache region; the cache region guide is used to indicate the next cache region.

[0100] In some embodiments, after the target data is written into the plurality of target cache areas, the starting position of the at least one target cache area in the target chip can be located based on the base address of the at least one target cache area indicated by the preset communication protocol, and the first target cache area is determined, the payload data in the first target cache area is read, the second target cache area is located based on the address of the next target cache area in the first target cache area, and the payload data in the second target cache area is read, the third target cache area is located based on the address of the next target cache area in the second target cache area, and so on, until the payload data in the plurality of target cache areas is read, and the target data is obtained.

[0101] It should be noted that steps 201 to 202 can be executed by a processor of the target chip or by a receiver with data processing capability in the target chip. For example, when the ARM in the ZYNQ chip sends data to the FPGA, steps 201 to 202 can be executed by the FPGA.

[0102] In the embodiments of the present disclosure, since the preset communication protocol can indicate the base address of the at least one target cache area, the starting position of the at least one target cache area in the target chip can be located based on the base address of the at least one target cache area, and the first target cache area is determined. Since the target data is written into the at least one target cache area, the cache area guide is added in each target cache area, and therefore, after the first target cache area is determined, the next target cache area can be continuously located and read based on the cache area guide in each target cache area, and the target data is obtained. In this way, when the sender and the receiver interact with data, an external storage medium is not needed, and only the physical address of the internal memory of the target chip needs to be allocated to the sender for caching, so that data interaction can be realized, and multiple data transfers are not needed in the data interaction process, thereby reducing system overhead and improving data transmission efficiency and system performance.

[0103] The data transmission process of the sender will be further described in detail below. As shown in FIG. 3, the method includes the following steps 301 to 307:

[0104] Step 301: Based on the business requirement of the sender and the hardware configuration of the target chip, at least one first physical address allocated to the sender is determined.

[0105] The business requirement refers to the storage requirement of the sender when processing the business. In a feasible implementation manner, the business requirement can include but is not limited to the business processed by the sender, the type of the business, and the cache area required by each business when processing.

[0106] When the sender is an ARM, the service requirement of the sender can refer to a system level service requirement; when the sender is an FPGA, the service requirement of the sender can refer to a service requirement with higher real-time requirement.

[0107] The hardware configuration of the target chip refers to the hardware resources possessed by the target chip. In a feasible implementation manner, the hardware configuration of the ZYNQ chip can include but is not limited to the memory, hard disk, solid state disk, OCM and the like possessed by the ZYNQ chip.

[0108] In a feasible implementation manner, the service requirement of the sender can be obtained through multiple tests, the hardware configuration of the target chip can be obtained through a basic input / output system (BIOS) query method, and the at least one first physical address allocated to the sender can be obtained by analyzing the service requirement of the sender and the hardware configuration of the target chip.

[0109] When the hardware configuration of the target chip includes the distribution of the physical address of the memory (for example, OCM), the specific implementation manner of step 301 can be: based on the distribution of the physical address of the memory, determining the at least one second physical address which is not allocated; from the at least one second physical address, determining the at least one first physical address which meets the service requirement of the sender.

[0110] The at least one second physical address refers to one or more physical addresses in the memory which are not allocated.

[0111] As shown in FIG. 4, the memory distribution of the ZYNQ chip is: DDR0 with an address range of 0000_0000-0007_FFFF and a size of 512 KB (kilobyte), DDR1 with an address range of 0008_0000-000F_FFFF and a size of 512 KB, DDR2 with an address range of 0010_0000-3FFF_FFFF and a size of 1023 MB (megabyte), OCM0 with an address range of FFFC_0000-FFFC_FFFF and a size of 64 KB, OCM1 with an address range of FFFD_0000-FFFD_FFFF and a size of 64 KB, OCM2 with an address range of FFFE_0000-FFFE_FFFF and a size of 64 KB, and OCM3 with an address range of FFFF_0000-FFFF_FFFF and a size of 64 KB.

[0112] In a feasible implementation, according to the OCM distribution in FIG. 4, an address segment with an address range of FFFC0000-FFFCFFFF can be agreed as a region for the ARM to transmit data to the FPGA, and an address segment with an address range of FFFD0000-FFFDFFFF can be agreed as a region for the FPGA to transmit data to the ARM.

[0113] In step 302, at least one first cache region corresponding to the sender is determined based on at least one first physical address.

[0114] In a feasible implementation, the at least one first cache region corresponding to the sender can be determined based on the service processed by the sender, the data transmission requirement corresponding to each service, and the at least one first physical address.

[0115] In a feasible implementation, the at least one first cache region corresponding to the sender can be determined based on the service processed by the sender, the data transmission requirement corresponding to each service, and the at least one first physical address.

[0116] The objects in the ZYNQ chip such as the ARM and the FPGA process various services, and the data transmission requirements corresponding to different services are also different. Therefore, the physical addresses can be divided according to the data transmission requirements corresponding to different services.

[0117] The first division granularity refers to the division granularity at the service level. The at least one third physical address refers to one or third physical addresses based on the division at the service level, that is, one third physical address represents the physical address corresponding to one service.

[0118] In a feasible implementation, the service processed by the sender and the data transmission requirement corresponding to each service can be determined by analyzing the service processing situation of the sender in a certain time period in the past.

[0119] As shown in FIG. 5, the first division granularity can be 4 KB; the OCM0 with an address range of 0xFFFC0000-0xFFFCFFFF can be divided into 16 channels according to the division granularity of 4 KB, for example, channel 1 with an address range of 0xFFFC0000-0xFFFC1000, channel 2 with an address range of 0xFFFC2000-0xFFFC3000, channel 3 with an address range of 0xFFFC2000-0xFFFC3000, and so on; each channel is a data channel constructed based on a physical address segment.

[0120] In a feasible implementation, the at least one third physical address can be directly allocated to the sender, and the at least one third physical address can be further divided according to the buffer size required by each data transmission, to serve as a FIFO.

[0121] The specific implementation of "determining the at least one first buffer area based on the at least one third physical address" can be: determining a second division granularity based on the buffer size required by each service in each data transmission; dividing the at least one third physical address based on the second division granularity to obtain at least one fourth physical address; and taking the storage space corresponding to the at least one fourth physical address as the at least one first buffer area.

[0122] The second division granularity is a division granularity at the data transmission layer. The at least one fourth physical address refers to one or more physical addresses divided based on the data transmission layer.

[0123] As shown in FIG. 6, the second division granularity can be 1 KB; channel 1 with an address range of FFFC0000-FFFC1000 can be further divided into four small memory blocks, buffer 1, buffer 2, buffer 3 and buffer 4, according to the division granularity of 1 KB, to serve as a FIFO. The address range of buffer 1 is 0xFFFC0000-0xFFFC0400, the address range of buffer 2 is 0xFFFC0400-0xFFFC0800, the address range of buffer 3 is 0xFFFC0800-0xFFFC0C00, and the address range of buffer 4 is 0xFFFC0C00-0xFFFC1000.

[0124] In step 303, a calling mode of the at least one first buffer area is set to a preset communication protocol.

[0125] In a feasible implementation, the OCM base address (the base address of the at least one first buffer area) allocated to the sender can be set by a register, the divided channel (the at least one third physical address) can be set to the FPGA by a register, and the buffer size (the size of the fourth physical address) can be set by a register. In this way, the base address of the at least one first buffer area corresponding to the sender can be obtained by accessing the register, and the at least one first buffer area can be located.

[0126] In the above embodiments, when the sender is an ARM, the allocation of the buffer area of the ARM can be implemented by the above steps 301 to 303; and when the receiver is an FPGA, the allocation of the buffer area of the FPGA can be implemented by the above steps 301 to 303.

[0127] Step 304, when transmitting the target data from the sender to the receiver, locating at least one first cache area corresponding to the sender based on the preset communication protocol.

[0128] In a possible implementation, the base address of the at least one first cache area corresponding to the sender can be determined based on the preset communication protocol and the register.

[0129] Step 305, selecting at least one target cache area from the at least one first cache area based on the service to which the target data belongs and the writing situation of each first cache area.

[0130] In some embodiments, the specific implementation of step 305 can be: selecting at least one second cache area from the at least one first cache area based on the service to which the target data belongs; determining at least one third cache area from the at least one second cache area based on the identification bit of the at least one second cache area; the identification bit representing whether the corresponding cache area has been written with data; and determining the at least one target cache area based on the at least one third cache area.

[0131] The identification bit represents whether the corresponding cache area has been written with data, that is, the identification bit represents whether the corresponding cache area is valid. In a possible implementation, the identification bit can be a frame header. The at least one second cache area refers to one or more cache areas corresponding to the service to which the target data belongs. The at least one third cache area refers to one or more cache areas corresponding to the service to which the target data belongs and not written with data.

[0132] In a possible implementation, when the data amount of the target data is small, one or more cache areas satisfying the data amount can be selected from the at least one third cache area; and when the data amount of the target data is large, the at least one third cache area can be used in a loop.

[0133] Step 306, determining whether the data transmission of the sender can be performed at the current time based on the timing interrupt signal and the access period set for different objects.

[0134] The interrupt signal is used to constrain the access of the ARM and the FPGA. The access period refers to the time period during which the corresponding object is allowed to access the memory of the target chip.

[0135] In a possible implementation, the interrupt period triggered by the interrupt signal can be set by means of a register, and it is specified that which part of the time in each interrupt period is processed by the ARM and which part of the time is processed by the FPGA. For example, each interrupt period includes 50 microseconds, the first 20 microseconds are processed by the ARM, and the last 30 microseconds are processed by the FPGA.

[0136] The specific implementation of step 306 can be: determining, based on the timing function of the target chip, a target time length in which the most recent interrupt signal has been triggered; determining that the current time can perform data transmission of the sender in the case that the target time length is in the access period of the sender; and determining that the current time cannot perform data transmission of the sender in the case that the target time length is in the access period of the remaining objects other than the sender.

[0137] The target time length refers to a time length in which the most recent interrupt signal has been triggered.

[0138] Since the real-time performance of the FPGA is high, which can reach nanosecond level (for example, 10 nanoseconds), a timer can be set inside the FPGA to implement the timing function of the target chip to determine the triggering time and the triggered time length of the interrupt signal.

[0139] In a feasible implementation, the target time length in which the most recent interrupt signal has been triggered can be determined according to the timer of the FPGA.

[0140] For example, if each interrupt period includes 50 microseconds, the first 20 microseconds are processed by the ARM, and the last 30 microseconds are processed by the FPGA, it is determined that the current time can perform data transmission of the ARM in the case that the sender is the ARM and the target time length is 18 microseconds, and it is determined that the current time cannot perform data transmission of the FPGA in the case that the sender is the FPGA and the target time length is 18 microseconds.

[0141] Step 307: in the case that the current time can perform data transmission of the sender, the target data is written into at least one target cache area according to a preset storage format based on a preset communication protocol.

[0142] The preset communication protocol can include the preset storage format. As shown in FIG. 7, the preset storage format can include a frame header, a next cache address, a data net length, and payload data. The frame header is used to determine whether the corresponding cache area is valid; the next cache address is used to indicate the address of the next cache area; the data net length is the number of bytes of valid data; and the payload data refers to the valid data, that is, the real transmitted data (for example, the target data).

[0143] In some embodiments, the specific implementation of step 307 can be: in the case that the target data needs multiple cache areas for storage, the target data is divided based on the size of a single cache area to obtain multiple sub-data; and the multiple sub-data are sequentially written into at least one target cache area according to the preset storage format.

[0144] The specific implementation of sequentially writing the plurality of sub-data into the at least one target cache area according to the preset storage format can be: determining an i-th sub-data corresponding j-th target cache area and an i+1-th sub-data corresponding j+1-th target cache area; i and j are positive integers greater than or equal to 1; writing the byte number of the i-th sub-data, the i-th sub-data, and the address of the j+1-th target cache area into the j-th target cache area as the net length, the payload data, and the cache area guide of the j-th target cache area, respectively; after writing, modifying the identification bit of the i-th target cache area from a first identification value to a second identification value; the first identification value represents that the corresponding cache area has not been written with data, and the second identification value represents that the corresponding cache area can have been written with data.

[0145] The cache area guide can be the next cache address. The first identification value can be a string of all 0s, and the second identification can be a string of all 1s.

[0146] In a possible implementation, for the first sub-data, the byte number of the first sub-data and the address of the second cache area corresponding to the second sub-data can be determined, and the address of the second cache area corresponding to the second sub-data, the byte number of the first sub-data, and the first sub-data are written into the net length, the payload data, and the cache area guide in the first target cache area, respectively, and after writing, the identification bit of the first target cache area is modified from the first identification value to the second identification value, to inform that the first target cache area has already stored data and cannot receive other data. For the second sub-data, the byte number of the second sub-data and the address of the third cache area corresponding to the third sub-data can be determined, and the address of the third cache area corresponding to the third sub-data, the byte number of the second sub-data, and the second sub-data are written into the net length, the payload data, and the cache area guide in the second target cache area, respectively, and after writing, the identification bit of the second target cache area is modified from the first identification value to the second identification value, to inform that the second target cache area has already stored data and cannot receive other data. This cycle is repeated until the target data is processed.

[0147] In the embodiment of the present disclosure, determining the at least one target cache area required by the sender when transmitting the target data from the memory of the target chip refers to allocating a physical address inside the target chip to the sender for data transmission. In this way, the sender only needs to allocate the physical address of the memory inside the target chip for caching, so as to realize data interaction, and during the data interaction process, multiple data transfers are not required, thereby reducing system overhead and improving data transmission efficiency and system performance. Writing the target data into the at least one target cache area according to the preset storage format based on the preset communication protocol can realize standardized writing of data, and adding a cache area guide when writing is helpful to indicating the writing order of the target data in each target cache area, thereby facilitating subsequent guiding of the receiver to read the target data from the multiple target cache areas. Thus, while realizing data interaction between the sender and the receiver, the data transmission efficiency and system performance are improved, and the system overhead is reduced.

[0148] The data transmission process of the receiver will be further described in detail below. As shown in FIG. 8, the method includes the following steps 801 to 803:

[0149] In step 801, when the receiver acquires the target data transmitted by the sender, the starting position of the at least one target cache area is located based on the base address of the at least one target cache area indicated by the preset communication protocol.

[0150] In step 802, the first target cache area is located based on the starting position, and the sub-data in the first target cache area is read.

[0151] In a feasible implementation manner, after locating the first target cache area based on the starting position of the at least one target cache area, whether the first target cache area has written data can be determined based on the frame header of the first target cache area, and in the case where it is determined that the first target cache area has written data, the sub-data in the first target cache area is read.

[0152] The specific implementation manner of "reading the sub-data in the first target cache area" in step 802 can be: in the case where it is determined that the frame header of the first target cache area is valid, the sub-data in the first target cache area is read according to the net length of the first target cache area, and after reading, the identification bit of the first target cache area is set from the second identification value to the first identification value; the first identification value represents that the corresponding cache area has not written data, and the second identification value represents that the corresponding cache area has written data.

[0153] In step 803, the second target cache area is located based on the cache area guide in the first target cache area, and sub-data in the second target cache area is read, and the next target cache area is located and sub-data in the next target cache area is read based on the cache area guide in the second target cache area, until at least one target cache area is read, and target data is obtained.

[0154] In the embodiment of the present disclosure, since the preset communication protocol can indicate the base address of the at least one target cache area, the starting position of the at least one target cache area in the target chip can be located based on the base address of the at least one target cache area, and the first target cache area is determined; since the target data is written into the at least one target cache area, the cache area guide is added in each target cache area, and therefore, after the first target cache area is determined, the next target cache area can be located and read based on the cache area guide in each target cache area, and the target data is obtained. In this way, when the sender and the receiver interact with each other, the external storage medium is not needed, and only the physical address of the internal memory of the target chip is allocated to the sender for caching, so that the data interaction can be realized, and in the data interaction process, the data transfer is not needed for multiple times, so that the system overhead is reduced, and the data transmission efficiency and the system performance are improved.

[0155] The data interaction process between the sender and the receiver will be introduced below. As shown in FIG. 10, the data interaction process can include the following steps 1001 to 1009.

[0156] In step 1001, the sender determines at least one first physical address allocated to the sender.

[0157] In step 1002, the sender determines at least one first cache area corresponding to the sender based on the at least one first physical address.

[0158] In step 1003, the sender sets the calling mode of the at least one first cache area in the preset communication protocol.

[0159] In step 1004, when the sender transmits target data to the receiver, the sender determines at least one target cache area required by the sender when the target data is transmitted from the memory of the target chip.

[0160] In step 1005, the sender determines whether the data transmission of the sender can be performed at the current time based on the interrupt signal sent in a timing manner and the access period set for different objects.

[0161] In step 1006, when the data transmission of the sender can be performed at the current time, the sender writes the target data into the at least one target cache area according to the preset storage format based on the preset communication protocol.

[0162] Step 1007, when the receiver acquires the target data transmitted by the sender, the receiver locates the starting position of the at least one target cache area based on the base address of the at least one target cache area indicated by the preset communication protocol.

[0163] Step 1008, the receiver locates the first target cache area based on the starting position, and reads the sub-data in the first target cache area.

[0164] Step 1009, the receiver locates the second target cache area based on the cache area guide in the first target cache area, and reads the sub-data in the second target cache area, and continues to locate and read the sub-data in the next target cache area based on the cache area guide in the second target cache area, until the target data is obtained by reading the at least one target cache area.

[0165] The application of the data processing method provided by the embodiment of the present disclosure in an actual scenario is described below.

[0166] The embodiment of the present disclosure designs an internal communication mechanism based on the interface of AXI-HP to support high-speed data interaction between ARM and FPGA in the ZYNQ platform. When accessing internal resources such as DDR or OCM, ARM and FPGA need to access through the AXI-HP interface.

[0167] Specifically, using the OCM inside the ZYNQ chip as a medium for data interaction is more efficient in reading and writing than the external DDR.

[0168] According to the OCM distribution of the ZYNQ platform shown in FIG. 4, the embodiment of the present disclosure agrees that the address segment of 0xFFFC0000-0xFFFCFFFF is the region for ARM to transfer data to FPGA, and the address segment of 0xFFFD0000-0xFFFDFFFF is the region for FPGA to transfer data to ARM.

[0169] At the same time, the storage size in the OCM is divided by a certain proportion to make different channels to interact data of different services. As shown in FIG. 5, if the 64KB OCM is divided by 4KB size, 16 channels can be obtained.

[0170] The biological memory in each channel is divided into multiple small memory blocks of the same size as cache, which plays the role of FIFO. As shown in FIG. 6, channel 1 is divided into 4 data cache areas of 1KB size.

[0171] A communication protocol is designed to maintain the data transfer of FIFO between ARM and FPGA. The protocol includes a frame header, the address of the next cache, the data net length (the number of bytes of valid information), and the payload data (substantial data).

[0172] In view of the OCM access conflict problem, the embodiment of the disclosure avoids the exception by restricting the access timing of the ARM and the FPGA. As shown in FIG. 9, the ARM is notified by the FPGA sending an interrupt signal periodically, and the access right is given to the ARM within a certain time (the time can be set) after the interrupt is generated, and then the FPGA handles it.

[0173] As shown in FIG. 11, the flow of the internal communication mechanism designed by the embodiment of the disclosure is as follows:

[0174] Step 1101, set the base address of the read-write OCM.

[0175] Initialization stage; the base address of the read-write OCM is set by the register to inform the FPGA of the position of the operation memory.

[0176] Step 1102, allocate the size of the channel and the cache.

[0177] Allocate the channel; for example, 16 channels are allocated with a size of 4KB, which is set in the FPGA by the register; the size of the cache is set by the register.

[0178] Step 1103, set the access period of the ARM and the FPGA.

[0179] Set the interrupt period and the constraint time of the access of the ARM and the FPGA, for example, set the interrupt to 50 microseconds, the first 20 microseconds are handled by the ARM, and the last 30 microseconds are handled by the FPGA.

[0180] Step 1104, FPGA timing and triggering of the interrupt signal.

[0181] During the runtime, the FPGA timing and interrupt are generated, and the ARM interacts the data through the OCM within 20 microseconds after receiving the interrupt.

[0182] Step 1105, judge whether the interrupt signal has been triggered.

[0183] If the interrupt signal has been triggered, execute step 1106; if the interrupt signal has not been triggered, continue to execute step 1105.

[0184] Step 1106, ARM handles the data.

[0185] Step 1107, judge whether the ARM access period has passed.

[0186] If the ARM access period has passed, execute step 1108; if the ARM access period has not passed, continue to execute step 1106. Specifically, the FPGA continues to time, and after the access period has passed, the access right of the OCM is given to the FPGA for data interaction.

[0187] Step 1108, the FPGA processes the data.

[0188] As shown in FIG. 12, the data receiving processing flow of the internal communication mechanism designed by the embodiment of the present disclosure is as follows:

[0189] Step 1201, judge whether the frame header of the current cache region is valid.

[0190] In the data receiving processing, first judge whether the frame header in the current cache is valid. If invalid, it means that no data has been received.

[0191] Step 1202, take out the data in the current cache region according to the net length.

[0192] When the frame header is valid, take out the data according to the length.

[0193] Step 1203, modify the frame header of the current cache region from the second identification value to the first identification value.

[0194] Empty the frame header (fill in 0).

[0195] Step 1204, take the next cache address in the current cache region as the base address for the next reading.

[0196] After completing the data receiving, update the next reading address in the current cache to the local, which is used for the next reading.

[0197] As shown in FIG. 13, the data sending processing flow of the internal communication mechanism designed by the embodiment of the present disclosure is as follows:

[0198] Step 1301, judge whether the frame header of the current cache region is invalid frame header.

[0199] The invalid frame header can be a string of all 0s. In the data sending processing, judge whether the frame header in the current cache is valid. If valid, it means that the data has not been read away.

[0200] Step 1302, write the data to be sent and the net length into the current cache region.

[0201] The frame header of 0 is regarded as invalid. Fill in the data to be sent and the length into the current cache region.

[0202] Step 1303, write the next cache address into the current cache region.

[0203] Step 1304, fill in the valid frame header in the current cache region.

[0204] The valid frame header can be a string of all 1s.

[0205] The embodiments of the present disclosure at least include the following innovative points: 1. The embodiments of the present disclosure propose an internal interaction mechanism taking OCM as a physical medium for data interaction. 2. The embodiments of the present disclosure design an internal communication mode, which divides the physical address into a business level and a data transmission level, constructs a cache area corresponding to different businesses, so as to ensure that ARM and FPGA can efficiently interact with data and have a certain cache function. 3. The embodiments of the present disclosure design the initialization and data read-write process of the entire internal communication.

[0206] The embodiments of the present disclosure can at least achieve the following technical effects: 1. Taking OCM as a physical medium for data interaction, the efficiency of data interaction between ARM and FPGA in the ZYNQ platform is improved. 2. By dividing the physical address into a business level and a data transmission level, a cache area corresponding to different businesses is constructed, which solves the problem of slow AXI-GP transmission and no cache for AXI-HP transmission in systems with high real-time requirements. 3. By setting the interrupt period and access period, the AXI-HP read-write conflict problem in systems with high real-time requirements is solved.

[0207] Based on the foregoing embodiments, the embodiments of the present disclosure provide a chip internal communication device, which includes units and modules included in each unit, and can be implemented by a processor in the chip. Of course, it can also be implemented by a specific logic circuit. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0208] FIG. 14 is a schematic diagram of the composition structure of a chip internal communication device according to an embodiment of the present disclosure. As shown in FIG. 14, the chip internal communication device 1400 includes a determination unit 1410 and a writing unit 1420, wherein: the determination unit 1410 is configured to determine at least one target cache area corresponding to a sender and capable of storing target data from a memory of a target chip when the sender transmits target data to a receiver; and the writing unit 1420 is configured to write the target data into the at least one target cache area according to a preset storage format based on a preset communication protocol; the preset storage format includes a cache area guide for indicating a next cache area.

[0209] In some embodiments, the determining unit 1410 is specifically configured to determine at least one first physical address allocated to the sender based on the service requirement of the sender and the hardware configuration of the target chip; determine at least one first cache region corresponding to the sender based on the at least one first physical address; and set a calling mode of the at least one first cache region to a preset communication protocol.

[0210] In some embodiments, the determining unit 1410 is specifically configured to determine at least one second physical address that is not allocated based on the distribution of the physical addresses of the memory; and determine at least one first physical address that meets the service requirement of the sender from the at least one second physical address.

[0211] In some embodiments, the determining unit 1410 is specifically configured to determine a first division granularity based on the service processed by the sender and the data transmission requirement corresponding to each service; divide the at least one first physical address according to the first division granularity to obtain at least one third physical address; and determine at least one first cache region based on the at least one third physical address.

[0212] In some embodiments, the determining unit 1410 is specifically configured to determine a second division granularity based on the cache size required by each service when transmitting data each time; divide the at least one third physical address according to the second division granularity to obtain at least one fourth physical address; and take a storage space corresponding to the at least one fourth physical address as the at least one first cache region.

[0213] In some embodiments, the determining unit 1410 is specifically configured to locate at least one first cache region corresponding to the sender based on a preset communication protocol; and select at least one target cache region from the at least one first cache region corresponding to the sender based on the service to which the target data belongs and the writing situation of each first cache region.

[0214] In some embodiments, the determining unit 1410 is specifically configured to select at least one second cache region from the at least one first cache region based on the service to which the target data belongs; determine at least one third cache region that can be used from the at least one second cache region based on an identification bit of the at least one second cache region; the identification bit represents whether the corresponding cache region has been written with data; and determine at least one target cache region based on the at least one third cache region.

[0215] In some embodiments, the writing unit 1420 is specifically configured to determine whether the data transmission of the sender can be performed at the current time based on a timing interrupt signal and an access time period set for different objects; and write the target data into the at least one target cache region according to a preset storage format based on a preset communication protocol in a case that the data transmission of the sender can be performed at the current time.

[0216] In some embodiments, the writing unit 1420 is specifically configured to: determine, based on a timing function of the target chip, a target time length at which an interrupt signal closest to a current time has triggered; determine that the current time can perform data transmission of the sender in a case where the target time length is in an access period of the sender; and determine that the current time cannot perform data transmission of the sender in a case where the target time length is in an access period of an object other than the sender.

[0217] In some embodiments, the writing unit 1420 is specifically configured to: in a case where the target data needs multiple cache regions for storage, divide the target data based on a size of a single cache region to obtain multiple sub-data; and write the multiple sub-data into at least one target cache region in a preset storage format in sequence, each target cache region including an address of a next target cache region.

[0218] In some embodiments, the writing unit 1420 is specifically configured to: determine an i-th target cache region corresponding to an i-th sub-data and an (i+1)-th target cache region corresponding to an (i+1)-th sub-data; i and j are positive integers greater than or equal to 1; write a byte number of the i-th sub-data, the i-th sub-data, and an address of the (i+1)-th target cache region into the j-th target cache region as a net length, payload data, and a cache region guide of the j-th target cache region, respectively; and after writing, modify an identification bit of the i-th target cache region from a first identification value to a second identification value; the first identification value represents that the corresponding cache region has not been written with data, and the second identification value represents that the corresponding cache region can have been written with data.

[0219] FIG. 15 is a schematic diagram of a component structure of a communication device inside a chip according to an embodiment of the present disclosure. As shown in FIG. 15, the communication device 1500 inside the chip includes a positioning unit 1510 and a reading unit 1520, wherein: the positioning unit 1510 is configured to, when a receiver acquires target data transmitted by a sender, locate a starting position of at least one target cache region based on a base address of the at least one target cache region indicated by a preset communication protocol; and the reading unit 1520 is configured to read the target data from the at least one target cache region based on the starting position and a cache region guide in each target cache region; the cache region guide is used to indicate a next cache region.

[0220] In some embodiments, the reading unit 1520 is specifically configured to: locate a first target cache area based on the start position, and read the sub-data in the first target cache area; locate a second target cache area based on the cache area guide in the first target cache area, and read the sub-data in the second target cache area, and continue to locate and read the sub-data in the next target cache area based on the cache area guide in the second target cache area until the target data is obtained by reading at least one target cache area.

[0221] In some embodiments, the reading unit 1520 is specifically configured to: determine whether the first target cache area has been written with data based on the identification bit of the first target cache area; in a case where it is determined that the first target cache area has been written with data, read the sub-data in the first target cache area according to the net length of the first target cache area, and set the identification bit of the first target cache area from the second identification value to the first identification value after reading is completed; the first identification value represents that the corresponding cache area has not been written with data, and the second identification value represents that the corresponding cache area has been written with data.

[0222] The descriptions of the above device embodiments are similar to those of the above method embodiments, and have similar beneficial effects to the method embodiments. In some embodiments, the device provided by the embodiments of the present disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiments. For technical details of the device embodiments of the present disclosure that are not disclosed, please refer to the descriptions of the method embodiments of the present disclosure.

[0223] It should be noted that, in the embodiments of the present disclosure, if the above-mentioned data processing method is realized in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a chip (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods of the embodiments of the present disclosure. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various media that can store program codes. Thus, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0224] The embodiments of the present disclosure provide a chip, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor executes the program to realize part or all of the steps in the above method.

[0225] The embodiment of the present disclosure provides a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement some or all steps of the above method. The computer readable storage medium can be transitory or non-transitory.

[0226] The embodiment of the present disclosure provides a computer program, which includes computer readable code. When the computer readable code runs in a chip, a processor in the chip executes some or all steps of the above method.

[0227] The embodiment of the present disclosure provides a computer program product, which includes a non-transitory computer readable storage medium storing a computer program. When the computer program is read and executed by a computer, some or all steps of the above method are implemented. The computer program product can be implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is embodied as a computer storage medium. In other embodiments, the computer program product is embodied as a software product, such as a software development kit (SDK) and the like.

[0228] It should be noted that the above description of various embodiments tends to emphasize the differences between various embodiments, and the same or similar parts can be referred to each other. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the above method embodiments, and has similar advantages. For technical details not disclosed in the device, storage medium, computer program and computer program product embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure.

[0229] It should be noted that FIG. 16 is a schematic diagram of a hardware entity of a chip in an embodiment of the present disclosure. As shown in FIG. 16, the hardware entity of the chip 1600 includes a processor 1601, a communication interface 1602 and a memory 1603, wherein:

[0230] The processor 1601 generally controls the overall operation of the chip 1600.

[0231] The communication interface 1602 can enable the chip to communicate with other terminals or servers through a network.

[0232] The memory 1603 is configured to store instructions and applications executable by the processor 1601, and can also cache data (e.g., image data, audio data, speech target data, and video target data) to be processed by the processor 1601 and modules in the chip 1600. The memory 1603 can be implemented by a FLASH or a Random Access Memory (RAM). The processor 1601, the communication interface 1602, and the memory 1603 can transmit data through the bus 1604.

[0233] It should be understood that every feature, structure, or characteristic mentioned throughout the specification in connection with an "embodiment" or "one embodiment" is meant to be included in at least one embodiment of the present disclosure. Therefore, the appearance of the phrases "in one embodiment" or "in an embodiment" in various places throughout the specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of steps / processes described above does not mean the order of execution, and the order of execution of the steps / processes should be determined by their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The sequence numbers of the above embodiments of the present disclosure are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0234] It should be noted that, in this document, the terms "comprises", "comprising", or any other variation thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or apparatus that comprises a list of elements does not only include those elements, but also includes other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0235] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative, for example, the division of units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed components can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0236] The units described as separate components above can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and part or all of the units can be selected as needed to achieve the purposes of the embodiments. In addition, the functional units in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.

[0237] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A communication method within a chip, the communication method within the chip comprising: When transmitting target data to the receiver, at least one target cache region corresponding to the sender and capable of storing the target data is determined from the memory of the target chip; Based on a preset communication protocol, the target data is written into at least one target cache area according to a preset storage format; The preset storage format includes a cache region bootstrap for indicating the next cache region.

2. The communication method within the chip according to claim 1, wherein, The communication method inside the chip also includes: Based on the sender's service requirements and the target chip's hardware configuration, at least one first physical address is determined to be allocated to the sender; Based on the at least one first physical address, at least one first cache region corresponding to the sender is determined; The calling method of the at least one first cache region is set to the preset communication protocol.

3. The communication method within the chip according to claim 2, wherein, The hardware configuration of the target chip includes the distribution of the physical addresses of the memory; The step of determining at least one first physical address to be allocated to the sender based on the sender's service requirements and the target chip's hardware configuration includes: Based on the distribution of physical addresses in the memory, at least one unallocated second physical address is determined; From the at least one second physical address, determine at least one first physical address that satisfies the service requirements of the sender.

4. The communication method within the chip according to claim 2 or 3, wherein, The step of determining at least one first cache region corresponding to the sender based on the at least one first physical address includes: Based on the services processed by the sender and the data transmission requirements corresponding to each service, the first division granularity is determined. The at least one first physical address is divided according to the first division granularity to obtain at least one third physical address; The at least one first cache region is determined based on the at least one third physical address.

5. The communication method within the chip according to claim 4, wherein, Determining the at least one first cache region based on the at least one third physical address includes: The second partitioning granularity is determined based on the buffer size required for each service during each data transmission. Based on the second partitioning granularity, the at least one third physical address is partitioned to obtain at least one fourth physical address; The storage space corresponding to the at least one fourth physical address shall be used as the at least one first cache region.

6. The communication method within the chip according to any one of claims 1 to 5, wherein, Determining at least one target cache region from the memory of the target chip that corresponds to the sender and is capable of storing the target data includes: Based on the preset communication protocol, locate at least one first buffer area corresponding to the sender; Based on the service to which the target data belongs and the write status of each first cache region, the at least one target cache region is selected from at least one first cache region corresponding to the sender.

7. The communication method within the chip according to claim 6, wherein, The step of selecting the at least one target cache region from at least one first cache region corresponding to the sender based on the service to which the target data belongs and the write status of each first cache region includes: Based on the service to which the target data belongs, at least one second cache region is selected from the at least one first cache region; Based on the identifier bits of the at least one second cache region, at least one usable third cache region is determined from the at least one second cache region; the identifier bits indicate whether the corresponding cache region has been written with data. Based on the at least one third cache region, the at least one target cache region is determined.

8. The communication method within the chip according to any one of claims 1 to 7, wherein, The step of writing the target data into the at least one target cache area according to a preset storage format based on a preset communication protocol includes: Based on the timed interrupt signals and the access periods set for different objects, it is determined whether the data transmission of the sender can be carried out at the current time; If data transmission by the sender is possible at the current moment, the target data is written into the at least one target cache area according to the preset communication protocol and the preset storage format.

9. The communication method within the chip according to claim 8, wherein, The determination of whether data transmission by the sender is possible at the current moment, based on timed interrupt signals and access periods set for different objects, includes: Based on the timing function of the target chip, determine the target duration for which the nearest interrupt signal has been triggered at the current time; If the target duration falls within the sender's access period, it is determined that the sender's data transmission can proceed at the current time. If the target duration falls within the access period of objects other than the sender, it is determined that data transmission by the sender cannot be performed at the current time.

10. The chip-internal communication method according to claim 8 or 9, wherein, The step of writing the target data into the at least one target cache area according to a preset storage format based on the preset communication protocol includes: When the target data requires storage in multiple cache areas, the target data is divided into multiple sub-data based on the size of a single cache area; The plurality of sub-data are sequentially written into the at least one target cache region according to the preset storage format; each target cache region includes the address of the next target cache region.

11. The chip-internal communication method according to claim 10, wherein, The preset storage format includes an identifier bit, a cache region header, a net length, and a net payload data; The step of sequentially writing the plurality of sub-data into the at least one target cache area according to the preset storage format includes: Determine the j-th target cache region corresponding to the i-th sub-data and the (j+1)-th target cache region corresponding to the (i+1)-th sub-data; i and j are both positive integers greater than or equal to 1; The number of bytes of the i-th sub-data, the i-th sub-data, and the address of the (j+1)-th target cache region are respectively used as the net length, net payload data, and cache region guide of the j-th target cache region, and written into the j-th target cache region; After writing, the identifier of the i-th target cache region is modified from the first identifier value to the second identifier value; the first identifier value indicates that the corresponding cache region has not been written to, and the second identifier value indicates that the corresponding cache region can be written to.

12. A communication method within a chip, the communication method within the chip comprising: When the receiver obtains the target data transmitted by the sender, it locates the starting position of the at least one target buffer area based on the base address of the at least one target buffer area indicated by the preset communication protocol. Based on the starting position and the cache region guidance in each target cache region, the target data is read from the at least one target cache region; The cache region guide is used to indicate the next cache region.

13. The communication method within the chip according to claim 12, wherein, The process of reading the target data from the at least one target cache region based on the starting position and the cache region guidance in each target cache region includes: Based on the starting position, locate the first target cache region and read the sub-data in the first target cache region; Based on the cache area in the first target cache area, guide the location of the second target cache area and read the sub-data in the second target cache area. Continue to guide the location and read the sub-data in the next target cache area based on the cache area in the second target cache area until all at least one target cache area has been read to obtain the target data.

14. The communication method within the chip according to claim 13, wherein, The step of reading sub-data from the first target cache region includes: Based on the identifier bit of the first target cache region, determine whether the first target cache region has been written with data; If it is determined that data has been written to the first target cache region, the sub-data in the first target cache region is read according to the net length of the first target cache region, and after reading, the identifier bit of the first target cache region is set from the second identifier value to the first identifier value; the first identifier value indicates that the corresponding cache region has not been written to, and the second identifier value indicates that the corresponding cache region has been written to.

15. An internal communication system for a chip, the internal communication system for a chip comprising: Receiver and sender; The sender is configured to determine, when transmitting target data to the receiver, at least one target cache region corresponding to the sender and capable of storing the target data from the memory of the target chip. Based on a preset communication protocol, the target data is written into the at least one target cache area according to a preset storage format, wherein the preset storage format includes a cache area guide for indicating the next cache area; The receiver is configured to locate the starting position of at least one target buffer area based on the base address of at least one target buffer area indicated by the preset communication protocol when acquiring the target data transmitted by the sender. Based on the starting position and the cache region guidance in each target cache region, the target data is read from the at least one target cache region.

16. A communication device within a chip, the communication device within the chip comprising: The determining unit is configured to determine at least one target cache region corresponding to the sender and capable of storing the target data from the memory of the target chip when the sender transmits target data to the receiver. The writing unit is configured to write the target data into the at least one target cache area according to a preset storage format based on a preset communication protocol; The preset storage format includes a cache region bootstrap for indicating the next cache region.

17. A communication device within a chip, the communication device within the chip comprising: The positioning unit is configured to locate the starting position of at least one target buffer area based on the base address of at least one target buffer area indicated by a preset communication protocol when the receiver obtains the target data transmitted by the sender. The reading unit is configured to read the target data from the at least one target cache region based on the starting position and the cache region in each target cache region; The cache region guide is used to indicate the next cache region.

18. A chip comprising a memory and a processor, the memory storing a computer program executable on the processor, the processor executing the program to implement the steps of the method of any one of claims 1 to 11 or 12 to 14.

19. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 11 or 12 to 14.

20. A computer program product comprising a computer program or instructions which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 11 or 12 to 14.

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