Multiport memory system with built-in contention management

Abstract

The present disclosure relates to a multiport memory system with built-in contention management comprising: a plurality of memory storage elements; a plurality of memory ports for accessing the plurality of memory storage elements through wordlines and bitlines connected to the memory storage elements, each memory storage element comprising a corresponding access circuitry for each memory port for reading and writing data from / to the memory storage element, wherein the corresponding access circuitry for each memory port is connected to a corresponding wordline and at least one corresponding bitline; contention management circuitry configured to detect contention when two or more memory ports request time-overlapping access to the same memory storage element and deassert the wordlines of all access circuitries of the memory storage element except one wordline. The disclosure further relates to a method of operating a multiport memory system with built-in contention management.

Description

[0001] Multiport memory system with built-in contention management

[0002] The present disclosure relates to a multiport memory system with built-in contention management and a method for operating the multiport memory system.

[0003] Background

[0004] A multiport memory is a type of computer memory that allows multiple accesses to the memory array simultaneously. Unlike traditional memories where only one access at a time is possible, multiport memories have multiple independent ports or interfaces through which data can be read from or written to the memory array concurrently.

[0005] In the context of a multiport memory, contention refers to the situation where multiple memory access requests conflict with each other, resulting in a contention or conflict for accessing the memory resources. Contention occurs when two or more access requests attempt to access the same memory location simultaneously, leading to potential data corruption or incorrect results if not properly managed.

[0006] To mitigate contention in multiport memories, various techniques are employed, including scheduling, synchronization, buffering etc. Solutions may also include handling of possible conflicting accesses by addressing them in the applications where they arise, for example, in parallel processing units accessing the same memory.

[0007] While these techniques are useful, they are also associated with a number of challenges, such as design complexity, overhead which causes increased power consumption and deadlock and race conditions.

[0008] Summary

[0009] The present disclosure relates to a multiport memory system with built-in contention management. The multiport memory system incorporates built-in contention management to address the challenges associated with contention in multiport memories. The multiport memory system comprises: a plurality of memory storage elements; a plurality of memory ports for accessing the plurality of memory storage elements through wordlines and bitlines connected to the memory storage elements, each memory storage element comprising access circuitry for each memory port for reading and writing data from / to the memory storage element, wherein the access circuitry for each memory port is connected to a wordline and at least one bitline; contention management circuitry configured to detect contention when two or more memory ports request time-overlapping access to the same memory storage element and de-assert the wordlines of all access circuitries of the memory storage element except one wordline.

[0010] In a development, at least one of the time-overlapping accesses is a write access, wherein the contention management circuitry is further configured to determine that at least one of the time-overlapping accesses is a write access.

[0011] The system's ability to identify write access during contention scenarios enables prioritization of write operations, which are typically critical for maintaining data coherency in multiport memory systems. The detection of write access during contention also allows for more sophisticated contention management strategies, such as delaying read operations to ensure that write operations are completed first, enhancing the overall stability of the system.

[0012] In a development, the system further comprises a contention management circuitry being further configured to de-assert the wordlines of all access circuitries of the memory storage element except the wordline connected to the access circuitry associated with the memory port requesting the last occurring write access.

[0013] Prioritizing the last occurring write access during contention ensures that the most up- to-date data is preserved, which is essential for applications where data freshness is critical. The system's ability to resolve contention by favoring the latest write access can also minimize the potential for data loss or stale data being read by other ports, thereby maintaining data accuracy.

[0014] In the multiport memory system, contention is mitigated by temporarily disabling the connection between all access transistors and their corresponding memory storage elements, except for one. This is achieved by de-asserting the wordlines connected to all but one of the access circuitries for a particular memory storage element. By allowing only one access path to be active at a time, the system ensures that only one memory port can read from or write to the contested memory storage element at any given moment.

[0015] This approach effectively resolves contention issues by temporarily restricting access to the memory storage element. By allowing only one port to access the memory at a time, the risk of conflicting write operations or data corruption that may occur with multiple ports accessing the same memory element simultaneously is eliminated.

[0016] The multiport memory system may further include features to detect and prioritize write accesses. Detection of write access is useful for preventing potential data corruption or loss, as write operations can modify data within the memory storage element. By recognizing that at least one of the overlapping access attempts is a write operation, the system can implement strategies to prioritize these operations, ensuring data integrity is maintained. This may involve temporarily delaying or queuing read operations or other write operations to process the write access in a manner that preserves data consistency.

[0017] In scenarios where multiple concurrent access attempts, including write operations, are identified, the contention management circuitry takes a further step to resolve contention. It de-asserts the wordlines of all access circuitries associated with the memory storage element, except for the one connected to the port requesting the most recent write access. This prioritizes the last occurring write access, which is crucial for maintaining system integrity or updating the system state. By allowing the last write request to proceed while temporarily halting other accesses, the system ensures that the most current and relevant data is stored in the memory.

[0018] The disclosed multiport memory system enhances its ability to manage complex contention scenarios involving multiple read and write operations. By intelligently prioritizing and sequencing these operations, especially giving precedence to the most recent write operations, the system maintains high efficiency and data integrity even under high loads or in highly concurrent environments.

[0019] The multiport memory may include comparison circuitry for comparing addresses to determine conflicting accesses, and access circuitry comprising access circuitry, such as a pair of access transistors. In conclusion, the disclosed multiport memory system provides an efficient solution for managing contention in multiport memories. By incorporating built-in contention management and prioritizing write accesses, the system ensures data integrity and high efficiency in highly concurrent environments.

[0020] Brief description of drawings

[0021] Various embodiments are described hereinafter with reference to the drawings. The drawings are examples of embodiments and are intended to illustrate some of the features of the presently disclosed multiport memory system with built-in contention management.

[0022] Fig. 1 shows an embodiment of the presently disclosed multiport memory system.

[0023] Fig. 2 shows an example of the presently disclosed contention management circuitry.

[0024] Fig. 3 shows an example of circuitry for handling input read and write data to and from a memory port.

[0025] Fig. 4 shows a further embodiment of the presently disclosed multiport memory system.

[0026] Fig. 5 shows an example of the interfaces of a multiport memory system.

[0027] Fig. 6 shows an example of a memory cell with access circuitry in the form of access transistors.

[0028] Fig. 7A shows an example of a conflicting write-write access on two memory ports and the handling of it in the multiport memory system.

[0029] Fig. 7B shows an example of a conflicting read-write access on two memory ports and the handling of it in the multiport memory system.

[0030] Fig. 8A shows an example of a conflicting read-write access on two memory ports and the handling of it in the multiport memory system.

[0031] Fig. 8B shows an example of a conflicting write-read access on two memory ports and the handling of it in the multiport memory system.

[0032] Fig. 9 shows an embodiment of the presently disclosed multiport memory system and an example of read and write buffers for two memory ports.

[0033] Fig. 10 shows an example of a flow chart for the presently disclosed method of operating a multiport memory system with built-in contention management.

[0034] Fig. 11 shows an example of a flow diagram for handling contention for a write operation.

[0035] Fig. 12 shows an example of a flow diagram for handling contention for a read operation. Fig. 13 shows examples of contention management circuitry logic.

[0036] Fig. 14 shows an example of contention management circuitry logic for a read-read scenario.

[0037] Fig. 15 shows an example of address comparison circuitry.

[0038] Fig. 16A-C show examples of signal arrival comparison circuitry.

[0039] Detailed description

[0040] Definitions

[0041] As used herein, the term "multiport memory system" refers to a system comprising memory storage elements and access circuitry for accessing different types of memory storage elements. The term shall be construed broadly to include all relevant memory types and memory storage elements.

[0042] As used herein, the term "contention management circuitry" refers to circuitry that is configured to detect a state of contention when two or more memory ports request time-overlapping access to the same memory storage element and provides a technical solution for handling the contention.

[0043] As used herein, the term “time-overlapping access" refers to access requests from two or more memory ports that occur at least partly within the same timeframe. It should be noted that such accesses are typically not perfectly synchronous. Instead, in practical systems, one access will usually occur slightly earlier than the other(s) due to variations in signal propagation delays, clock skew, or other physical factors inherent in the design of multiport memory systems.

[0044] The overlap may therefore include cases where a second access is initiated shortly after a first access but still falls within a defined contention window - a predetermined time range within which accesses are considered concurrent for the purposes of contention detection and management. The contention management circuitry may be configured to account for such timing variations and may be configured to determine the relative order of accesses. For example, in scenarios involving both read and write accesses, the circuitry can distinguish between the first and last occurring accesses and apply appropriate contention resolution strategies, such as de-asserting wordlines or copying data to buffers accordingly. The contention management circuitry may also be configured to distinguish between read and write operations. Access circuitry refers to circuitry for reading and / or writing data to the memory storage elements. The access circuitry may be implemented in any suitable way. Typically the access circuitry for each port includes one or more access transistors.

[0045] In some memory types there may be several access transistors for accessing a memory storage element. In such cases the access transistors may be parallel or serially connected, depending on the type of memory.

[0046] As used herein, the term "access transistor" may refer to a transistor that is configured to provide data access to a memory storage element, typically via a wordline and / or bitline. Solutions, in which there are more than one access transistor for accessing a memory storage element, are included as embodiments of the presently disclosed multiport memory system. In such solutions it is generally considered enough that at least one access transistor is connected to a wordline and a bitline. It can be noted that an access transistor does not necessarily have to be directly connected to a memory storage element. If there are, for example, two serially connected access transistors, any one of them can be connected to a wordline and a bitline. More generally, any reference to access transistor(s) can also be seen as a reference to the more general term access circuitry.

[0047] As used herein, the term "comparison circuitry" refers to circuitry for detecting whether the addresses of the memory ports are the same or whether the memory ports try to access the same memory storage element.

[0048] As used herein, the term "memory ports" refers to an interface through which a processor or other device can communicate with the memory in order to read from or write data to it.

[0049] As used herein, the term "voltage supplies" refers to circuitry for supplying voltage to the memory storage element and other circuitry of the multiport memory system.

[0050] As used herein, the term "precharge circuitry" refers to circuitry that is configured to prepare the memory for the next access operation, whether it's a read or write, for example, by resetting the bitlines to a known state. As used herein, the term "sense amplifiers" refers to circuitry configured to detect and amplify changes in voltages on the bitlines when reading data from the memory storage elements.

[0051] A "memory array" refers to a structured arrangement of memory storage elements cells in a grid of rows and columns.

[0052] As used herein, the term "time-overlapping access" may refer to an access by several memory ports that occur, at least partly, at the same time.

[0053] As used herein, the term "conflicting accesses" refers to an access to a memory storage element that is requested by one or more of the memory storage elements for reading and writing data from / to the same memory storage element.

[0054] Further details

[0055] The present disclosure relates to a multiport memory system with built-in contention management. It includes memory storage elements, memory ports, access circuitry, and contention management circuitry. The circuitry detects contention when multiple ports request overlapping access to the same memory storage element and de-asserts all wordlines except one.

[0056] A multiport memory system with built-in contention management is disclosed. It comprises memory storage elements, memory ports, and access circuitry. Contention management circuitry detects contention when multiple ports request overlapping access to the same memory storage element and de-asserts all wordlines except one. The system can prioritize write or read accesses, forward or copy data, and detect contention by comparing addresses. It may also include decoders, voltage supplies, precharge circuitry, sense amplifiers, and local read / write buffers.

[0057] In some embodiments, contention detection is based on address comparison between memory ports. The comparison may be performed by dedicated comparison circuitry configured to compare the exact addresses provided by each of the memory ports. If two or more memory ports present the same address, the system determines that the corresponding access requests target the same memory storage element, and a potential contention is identified. This address comparison may involve bitwise equality checks and can be implemented using logic gates, such as XOR and OR trees, to detect address matches efficiently.

[0058] The presently disclosed multiport memory system may be configured to distinguish between read and write accesses and to take action accordingly when contention is detected. The contention management circuitry may identify the type of each access and apply different strategies depending on whether the access is a read or a write, and on the relative order in which the accesses occur.

[0059] In one specific embodiment, the following behavior is implemented (first and second accesses in this case means that the first access is started before the second access and overlapping):

[0060] • If the first access is a write and the second access is a write, the first write is cancelled and the second write is allowed to proceed.

[0061] • If the first access is a read and the second access is a write, the first read is cancelled and the second write is allowed to proceed.

[0062] • If the first access is a read and the second access is a write, the write data from the second access is copied or forwarded to the memory port associated with the read access.

[0063] • If the first access is a write and the second access is a read, the write data from the first access is copied or forwarded to the memory port associated with the read access.

[0064] This behavior allows the system to maintain data coherency while handling contention efficiently. The copying or forwarding of write data to the read port may be performed using local read buffers or temporary registers.

[0065] Disclosed is a multiport memory system with built-in contention management. It includes memory storage elements, memory ports, and access circuitry for each port. Contention management circuitry detects contention when multiple ports request overlapping access to the same memory storage element and de-asserts all wordlines except one. The system can prioritize write or read accesses, forward or copy data, and detect contention by comparing addresses. It may also include decoders, voltage supplies, precharge circuitry, sense amplifiers, and local read / write buffers. The system can be a multiport RAM or ROM, and each memory storage element may comprise cross-coupled inverters and access circuitry. A method of operating the system is also disclosed. In a development, the system further comprises contention management circuitry configured to detect contention when two or more memory ports request timeoverlapping access to the same memory storage element(s) and, upon determining that all of the time-overlapping accesses are read accesses, de-assert the wordlines of all access circuitries of the memory storage element except the wordline connected to the access circuitry associated with the memory port requesting the first occurring read access.

[0066] By allowing the first occurring read access to proceed during contention involving only read operations, the system ensures fair access and reduces the likelihood of starvation for any particular memory port.

[0067] In a development, the system further comprises contention management circuitry being configured to, upon determining that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, forward or copy, directly or indirectly, write data from the last occurring write access to the memory port(s) requesting the read access(es).

[0068] This feature allows for seamless data synchronization between read and write operations, which is particularly beneficial in systems where multiple processors or agents need to access and modify shared data resources.

[0069] In a development, the system further comprises contention management circuitry configured to, upon determining that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, copy write data from the last occurring write access to a read buffer, from which it can be read by the memory port (s) requesting the read access(es).

[0070] This allows simultaneous read and write operations to overlap in time while maintaining consistency between read and write operations. The read access will read the latest data.

[0071] In one embodiment, at least two of the time-overlapping accesses may be write accesses comprising a first write access from a first memory port and a second write access from a second memory port, the first access from the first memory port starting before the second access from the second memory port, wherein the contention management circuitry is further configured to de-assert the wordline of the access circuitry for the first memory port. In this embodiment the contention management circuitry may optionally be configured to stop driving bitlines of the first write access from the first memory port when the second access form the second memory port is detected.

[0072] In a development, the system further comprises contention management circuitry being configured to, upon determining that all of the time-overlapping accesses are read accesses, copy read data from the first occurring read access to a read buffer, from which it can be read by the memory port (s) requesting the remaining read access(es).

[0073] This provides a mechanism for quick data retrieval for multiple read accesses by storing the data from the first read access in a read buffer, which can be accessed rapidly by subsequent reads.

[0074] In a development, the system further comprises contention management circuitry system comprising comparison circuitry comparing the addresses of the plurality of memory ports to detect access to the same memory storage element (s).

[0075] This enables proactive conflict resolution by identifying address overlaps early in the access process, which can lead to reduced wait times and improved memory access scheduling.

[0076] In a development, the system further comprises one or more row decoders; one or more column decoders, one or more voltage supplies and precharge circuitry.

[0077] In a development, the system further comprises sense amplifiers and / or local read and write buffers.

[0078] The inclusion of sense amplifiers enhances the reliability and speed of data retrieval by amplifying the signal from the memory cells, which is particularly beneficial for detecting data in low-signal environments.

[0079] The integration of local read and write buffers improves system performance by reducing latency and increasing throughput, as data can be temporarily stored close to the memory array, minimizing the time required for data transfer. The local read and write buffers can also be used for temporarily storing read and write data for contention scenarios.

[0080] In a development, the system further comprises at least a first port and a second port, wherein at least one of the multiple ports allows for read accesses and at least one of the multiple ports allows for write accesses.

[0081] In a development, the system further comprises at least a first port and a second port, wherein each of the multiple ports allow for both read and write operations.

[0082] The capability of each port to perform both read and write operations provides flexibility in data handling, allowing for dynamic allocation of tasks based on system requirements and improving resource utilization.

[0083] In a development, the system further comprises each of the plurality of memory ports having at least a number of address ports, a number of data ports, a clock port and enable ports for read and / or write operations.

[0084] Different memory types might have variations or additional specific signals, but the ones listed above are common in many memory interfaces, providing the basic framework for memory operation and control.

[0085] In a development, the system further comprises contention management circuitry being configured to determine which of a plurality of conflicting accesses that occurs first, and / or to determine in which order a plurality of conflicting accesses occur. Figs. 16A-C show three different examples of how signal arrival comparison circuitry can be implemented. The three implementations compares the timing of clock signals of the conflicting accesses.

[0086] By determining the order of conflicting accesses, the multiport memory system can handle different combinations (write access from first port followed by write access from second port, write access from first port followed by read access from second port, read access from first port followed by read access from second port, read access from first port followed by read access from second port) in different ways, for example by prioritizing one access type over another or by copying or forwarding data for in a certain way for a certain combination.

[0087] In a development, the system further comprises, if multiple conflicting accesses occur within a predetermined time range, the conflicting accesses being considered to occur at the same time.

[0088] In a development, the system further comprises an access from one of the plurality memory ports being always prioritized when conflicting access occur at the same time, and / or wherein the plurality memory ports are prioritized according to a predetermined order when conflicting access occur at the same time.

[0089] The prioritization of memory ports when conflicts occur may, for example, ensure deterministic access patterns, which is critical for real-time applications where predictable response times are necessary. The ability to establish a predetermined order of priority among memory ports also allows for customizable memory access management, catering to specific application needs and optimizing performance for the most critical tasks. For example, it can be used to reduce the likelihood of bottlenecks in high-demand scenarios, as the system can preferentially service the most important operations.

[0090] The present disclosure further relates to a multiport memory system with built-in contention management comprising: a plurality of memory storage elements ; a plurality of memory ports for accessing the plurality of memory storage elements through wordlines and bitlines connected to the memory storage elements, each memory storage element comprising access circuitry for each memory port for reading and writing data from / to the memory storage element, wherein the access circuitry for each memory port is connected to a wordline and at least one bitline; contention management circuitry configured to detect contention when two or more memory ports request time-overlapping access to the same memory storage element, wherein an access from one of the plurality memory ports is always prioritized when conflicting access occur at the same time, and / or wherein the plurality memory ports are prioritized according to a predetermined order when conflicting access occur at the same time.

[0091] The contention management circuitry may be configured to determine which of a plurality of conflicting accesses that occurs first, and / or to determine in which order a plurality of conflicting accesses occur.

[0092] The multiport memory system may be configured to prioritize accesses according to a predefined order if two or more accesses occur within a predefined time window.

[0093] The multiport memory may be a multiport random-access memory (RAM), such as an SRAM, a DRAM, an SDRAM, an MRAM or an RRAM, or a multiport read-only memory (ROM).

[0094] In a development, the system further comprises at least two memory ports, or at least three memory ports, or at least four memory ports, or at least six memory ports, or at least ten memory ports.

[0095] The technology is not limited to two memory ports. As a person skilled in the art would realize, the concept can be extended to any number of memory ports. The scalability of the system to support a varying number of memory ports provides flexibility in design, enabling the system to be customized for different levels of performance demands and allowing for future expansion as needed.

[0096] Specifically, the multiport memory system may comprise, for example, a two-port memory or a dual-port memory.

[0097] As would be understood by a person skilled in the art, the memory storage elements may be implemented in various ways. According to one example, each memory storage element comprises: a storage part comprising a first transistor, a second transistor, a third transistor and a fourth transistor forming first and second cross-coupled inverters, wherein the first and second cross-coupled inverters define a first storage node and an inverted first storage node; and an access part comprising at least two pairs of access transistors for reading and writing data from / to the first storage node and the inverted first storage node, wherein a first wordline and a first pair of complementary bitlines are connected to a first pair of access transistors and a second wordline and a second pair of complementary bitlines are connected to a second pair of access transistor. For certain memory storage elements, there may only be single access transistors.

[0098] The multiport memory system may further comprise circuitry configured to generate a contention signal for an access from one or more memory ports, the contention signal comprising a predetermined delay indicating a contention window in which the access is considered for contention.

[0099] The predetermined delay indicating a contention window helps in managing access conflicts by providing a clear timeframe in which contention resolution protocols can be applied, thus improving the overall efficiency of the memory system. The contention window may also serve as a mechanism to synchronize access attempts from multiple ports.

[0100] In a development, the system is configured to prioritize accesses according to a predefined order if two or more accesses occur within a predefined time window.

[0101] Prioritizing accesses according to a predefined order ensures that critical operations are serviced first, which can be essential for applications with real-time requirements or where certain tasks have higher priority.

[0102] The disclosure further relates to a method of operating a multiport memory system with built-in contention management, the method comprising the steps of: providing a multiport memory system comprising a plurality of memory storage elements and a plurality of memory ports for accessing the plurality of memory storage elements, wherein each memory storage element comprises at least one access transistor for each memory port for reading and writing data from / to the memory storage element, wherein at least one access transistor for each memory port is connected to a wordline and a bitline; determining if two or more memory ports request access to the same memory storage element (s) by comparing addresses of the plurality of memory ports of the multiport memory system; upon determining that two or more memory ports request access to the same memory storage element (s), de-asserting the wordlines of all access transistors of the memory storage element except one wordline.

[0103] The method of de-asserting the wordlines of all access transistors except one ensures that only a single port gains access to the memory storage element, thereby preventing data corruption due to simultaneous writes or reads.

[0104] By determining access conflicts through address comparison, the system can quickly resolve contention, minimizing the delay introduced by access arbitration and maintaining high-speed operation of the memory system.

[0105] The selective de-assertion of wordlines based on access requests allows for efficient use of the memory system's resources, as it prevents unnecessary activation of memory cells, which can save power and reduce wear on the memory elements.

[0106] The method enhances the reliability of the multiport memory system by providing a systematic approach to handling access conflicts, which can be critical in systems where data integrity and consistency are paramount.

[0107] A multiport memory system with built-in contention management, where the contention management circuitry is configured to detect contention when two or more memory ports request time-overlapping access to the same memory storage element and to determine if at least one of the time-overlapping accesses is a write access, further configured to de-assert the wordlines of all access transistors of the memory storage element except the wordline connected to the access transistor associated with the memory port requesting the last occurring write access.

[0108] A multiport memory system with built-in contention management, where each memory storage element comprises a storage part with first and second cross-coupled inverters defining a first storage node and an inverted first storage node, and an access part with at least two pairs of access transistors for reading and writing data, and the multiport memory system is a multiport random-access memory (RAM), such as an SRAM, a DRAM, an SDRAM, an MRAM or an RRAM, or a multiport read-only memory (ROM). A method of operating a multiport memory system with built-in contention management by providing a multiport memory system comprising a plurality of memory storage elements and memory ports, determining if two or more memory ports request access to the same memory storage elements by comparing addresses, de-asserting the wordlines of all access transistors of the memory storage element except one wordline, and further comprising circuitry configured to generate a contention signal for an access from one or more memory ports, the contention signal comprising a predetermined delay indicating a contention window in which the access is considered for contention.

[0109] Description of drawings

[0110] Various embodiments are described hereinafter with reference to the drawings. The drawings are examples of embodiments and are intended to illustrate some of the features of the presently disclosed multiport memory system with built-in contention management.

[0111] Fig. 1 shows an embodiment of the presently disclosed multiport memory system 100. multiport memory system 100 comprises contention management circuitry 114 and comparison circuitry. As can be seen, the multiport memory system 100 receives memory port signals, including write enable signals, from a number of memory ports and generates a number of WL contention signals.

[0112] Fig. 2 shows an example of the presently disclosed contention management circuitry 114. In the example, a number of WL_en signals are used to control the enabling of the wordlines of the memory array 126.

[0113] Fig. 3 shows an example of circuitry for handling input read and write data to and from a memory port. In the figure it is exemplified how write data can be placed in write buffer 121. When reading data, data can either be read from a read buffer 120 or copied / forwarded from the write buffer 121 depending on the contention case.

[0114] Fig. 4 shows a further embodiment of the presently disclosed multiport memory system 100. The multiport memory system 100 comprises a memory array 126 comprising a plurality of memory storage elements 101 , which are accessed through wordlines 103 and bitlines 102. There are two memory ports 115, decoding and comparison circuitry 114 and contention management circuitry 104. The multiport memory system 100 optionally comprises voltage supply 117, precharge circuitry 118 and sense amplifiers 125.

[0115] Fig. 5 shows an example of the interfaces of a multiport memory system 100. In the example both memory ports comprise ADDR, D, CLK, EN and WREN pins.

[0116] Fig. 6 shows an example of a memory storage element 101 with access transistors 112 and 113. There is access circuitry 105 in the form of a first transistor 106, a second transistor 107, a third transistor 108 and a fourth transistor 109.

[0117] Fig. 7A shows an example of a conflicting write-write access on two memory ports and the handling of it in the multiport memory system. In fig. 7A there are two conflicting write accesses on the first and second memory ports. When the write access on the second port PORT 2 occurs, the wordline for the access of the first port PORT 1 is de-asserted.

[0118] Fig. 7B shows an example of a conflicting read-write access on two memory ports and the handling of it in the multiport memory system. In fig. 7B there is a read access on PORT 1 followed by a conflicting write access on PORT 2. When the write access on the second port PORT2 occurs, the wordline for the access of the first port PORT 1 is de-asserted.

[0119] Fig. 8A shows an example of a conflicting read-write access on two memory ports and the handling of it in the multiport memory system. In fig. 8A there is a read access on PORT 1 followed by a conflicting write access on PORT 2. The write data from the second port PORT 2 is copied to a read buffer.

[0120] Fig. 8B shows an example of a conflicting write-read access on two memory ports and the handling of it in the multiport memory system. In fig. 8B there is a write access on PORT1 followed by a conflicting read access on PORT 2. The write data from the first port PORT 1 is copied to a read buffer.

[0121] Fig. 9 shows an embodiment of the presently disclosed multiport memory system 100 and an example of read buffer 120 and 122 and write buffers 121 and 123 for two memory ports PORT 1 and PORT2. The figure shows a memory array 126, bitlines 102, a first port read buffer 120, a first port write buffer 121 , a second port read buffer 122 and a second port write buffer 123. Fig. 10 shows an example of a flow chart for the presently disclosed method 200 of operating a multiport memory system 100 with built-in contention management. Three steps are shown: providing 201 a multiport memory system 100 comprising a plurality of memory storage elements 101 and a plurality of memory ports 115 for accessing the plurality of memory storage elements 101 , wherein each memory storage element 101 comprises at least one access transistor 112 for each memory port 115 for reading and writing data from / to the memory storage element 101, wherein each access transistor 112 is connected to a wordline 103 and a bitline 102; determining 202 if two or more memory ports 115 request access to the same memory storage element 101(s) by comparing addresses of the plurality of memory ports 115 of the multiport memory system 100; and upon determining 202 that two or more memory ports 115 request access to the same memory storage element 101 (s), and de-asserting 203 the wordlines 103 of all access transistors of the memory storage element 101 except one wordline 103.

[0122] Fig. 11 shows an example of a flow diagram for handling contention for a write operation. For a new incoming write operation it is first checked whether there is a conflict. If there is no conflict the operation can just continue. If there is conflict it is checked whether the other ongoing operation is a write operation. If this is the case the wordline associated with the first access is de-asserted and the second write access is allowed to finish. If the first access is instead a read access it is checked whether the sense amplifiers are active. If that is the case the write access is allowed to finish. If the sense amplifiers are not active, the wordline associated with the first access is deasserted. Write data for the second access can then be copied to a read buffer for the port associated with the read access.

[0123] Fig. 12 shows an example of a flow diagram for handling contention for a read operation. For a new incoming read operation it is first checked whether there is a conflict. If there is no conflict the operation can just continue. If there is conflict it is checked whether the ongoing operation is a write operation. If this is the case write data for the first write access is copied to a read buffer for the memory port associated with the read access. If the first access is a read access it is repeatedly checked whether the first read access has finished. When it has finished, read data from the first access is copied to a read buffer for the second port. Fig. 13 shows examples of contention management circuitry logic 104. It can be seen in the examples that WE signals can be used to determine which, if any, of the accesses are write access. Further control signals, such as priority, can be used in the process of generating wordline signals.

[0124] Fig. 15 shows an example of comparison circuitry for comparing the addresses of the plurality of memory ports to detect access to the same memory storage element. This can implemented as a tree of gates. In the specific examples the first level of the tree comprises XOR gates and the following levels OR gates.

[0125] Reference numeral list

[0126] 100 multiport memory system

[0127] 101 memory storage element

[0128] 102 bitline

[0129] 103 wordline

[0130] 104 contention management circuitry

[0131] 105 access circuitry

[0132] 106 first transistor

[0133] 107 second transistor

[0134] 108 third transistor

[0135] 109 fourth transistor

[0136] 110 first storage node

[0137] 111 inverted first storage node

[0138] 112; 113 access transistor

[0139] 114 comparison circuitry

[0140] 115 memory port

[0141] 116 column decoders

[0142] 117 voltage supplies

[0143] 118 precharge circuitry

[0144] 120 first port read buffer

[0145] 121 first port write buffer

[0146] 122 second port read buffer

[0147] 123 second port write buffer

[0148] 124 row decoders

[0149] 125 sense amplifiers 126 memory array

[0150] 200 method of operating a multiport memory system

[0151] 201 providing a multiport memory system

[0152] 202 determining if two or more memory ports request access to the same memory storage element

[0153] 203 de-asserting the wordlines of all access transistors of the memory storage element except one wordline

[0154] Further details

[0155] 1. A multiport memory system (100) with built-in contention management comprising: a plurality of memory storage elements (101); a plurality of memory ports (115) for accessing the plurality of memory storage elements (101) through wordlines (103) and bitlines (102) connected to the memory storage elements (101), each memory storage element (101) comprising access circuitry for each memory port (115) for reading and writing data from / to the memory storage element (101), wherein the access circuitry for each memory port (115) is connected to a wordline (103) and at least one bitline (102); contention management circuitry (104) configured to detect contention when two or more memory ports (115) request time-overlapping access to the same memory storage element (101) and de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except one wordline (103).

[0156] 2. The multiport memory system (100) according to item 1 , wherein at least one of the time-overlapping accesses is a write access, wherein the contention management circuitry (104) is further configured to determine that at least one of the time-overlapping accesses is a write access.

[0157] 3. The multiport memory system (100) according to item 2, wherein the contention management circuitry (104) is further configured to de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except the wordline (103) connected to the access circuitry associated with the memory port (115) requesting the last occurring write access. 4. The multiport memory system (100) according to item 1, wherein the contention management circuitry (104) is configured to detect contention when two or more memory ports (115) request time-overlapping access to the same memory storage element(s) and, upon determining (202) that all of the time-overlapping accesses are read accesses, de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except the wordline (103) connected to the access circuitry associated with the memory port (115) requesting the first occurring read access.

[0158] 5. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) is configured to, upon determining (202) that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, forward or copy, directly or indirectly, write data from the last occurring write access to the memory port(s) requesting the read access(es).

[0159] 6. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) is configured to, upon determining (202) that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, copy write data from the last occurring write access to a read buffer (120), from which it can be read by the memory port(s) (115) requesting the read access(es).

[0160] 7. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) is configured to, upon determining (202) that all of the time-overlapping accesses are read accesses, forward or copy, directly or indirectly, read data from the first occurring read access to the memory port (s) (115) requesting the remaining read access(es).

[0161] 8. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) is configured to, upon determining (202) that all of the time-overlapping accesses are read accesses, copy read data from the first occurring read access to a read buffer (120), from which it can be read by the memory port(s) (115) requesting the remaining read access(es). 9. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) system comprises comparison circuitry (114) comparing the addresses of the plurality of memory ports (115) to detect access to the same memory storage element(s) (101).

[0162] 10. The multiport memory system (100) according to any one of the preceding items, comprising one or more row decoders (124); one or more column decoders (116), one or more voltage supplies (117) and precharge circuitry (118).

[0163] 11. The multiport memory system (100) according to any one of the preceding items, comprising sense amplifiers (125) and / or local read and write buffers.

[0164] 12. The multiport memory system (100) according to any one of the preceding items, wherein the multiport memory system (100) has multiple ports, the multiple ports comprising at least a first port and a second port, wherein at least one of the multiple ports allows for read accesses and at least one of the multiple ports allows for write accesses.

[0165] 13. The multiport memory system (100) according to any one of the preceding items, wherein the multiport memory system (100) has multiple ports, the multiple ports comprising at least a first port and a second port, wherein each of the multiple ports allow for both read and write operations.

[0166] 14. The multiport memory system (100) according to any one of the preceding items, wherein each of the plurality of memory ports (115) have at least a number of address ports, a number of data ports, a clock port and enable ports for read and / or write operations.

[0167] 15. The multiport memory system (100) according to any one of the preceding items, wherein the contention management circuitry (104) is configured to determine which of a plurality of conflicting accesses that occurs first, and / or to determine in which order a plurality of conflicting accesses occur. 16. The multiport memory system (100) according to item 14, wherein, if multiple conflicting accesses occur within a predetermined time range, the conflicting accesses are considered to occur at the same time.

[0168] 17. The multiport memory system (100) according to item 15, wherein an access from one of the plurality memory ports (115) is always prioritized when conflicting access occur at the same time, and / or wherein the plurality memory ports (115) are prioritized according to a predetermined order when conflicting access occur at the same time.

[0169] 18. The multiport memory system (100) according to any one of the preceding items, wherein the multiport memory is a multiport random-access memory (RAM), such as an SRAM, a DRAM, an SDRAM, an MRAM or an RRAM, or a multiport read-only memory (ROM).

[0170] 19. The multiport memory system (100) according to any one of the preceding items, comprising at least two memory ports (115), or at least three memory ports (115), or at least four memory ports (115), or at least six memory ports (115), or at least ten memory ports (115).

[0171] 20. The multiport memory system (100) according to any one of the preceding items, wherein the multiport memory system (100) is a two-port memory or a dual-port memory.

[0172] 21. The multiport memory system (100) according to any one of the preceding items, wherein each memory storage element (101) comprises: a storage part comprising a first transistor (106), a second transistor (107), a third transistor (108) and a fourth transistor (109) forming first and second cross-coupled inverters, wherein the first and second cross-coupled inverters define a first storage node (110) and an inverted first storage node (111); and an access part comprising at least two pairs of access transistors for reading and writing data from / to the first storage node (110) and the inverted first storage node (111), wherein a first wordline (103) and a first pair of complementary bitlines (102) are connected to a first pair of access transistors and a second wordline (103) and a second pair of complementary bitlines (102) are connected to a second pair of access transistor (112).

[0173] 22. The multiport memory system (100) according to any one of the preceding items, further comprising circuitry configured to generate a contention signal for an access from one or more memory ports (115), the contention signal comprising a predetermined delay indicating a contention window in which the access is considered for contention.

[0174] 23. The multiport memory system (100) according to any one of the preceding items, wherein the multiport memory system (100) is configured to prioritize accesses according to a predefined order if two or more accesses occur within a predefined time window.

[0175] 24. A method (200) of operating a multiport memory system (100) with built-in contention management, the method (200) comprising the steps of: providing (201) a multiport memory system (100) comprising a plurality of memory storage elements (101) and a plurality of memory ports (115) for accessing the plurality of memory storage elements (101), wherein each memory storage element (101) comprises access circuitry for each memory port (115) for reading and writing data from / to the memory storage element (101), wherein the access circuitry for each memory port (115) is connected to a wordline (103) and at least one bitline (102); determining (202) if two or more memory ports (115) request access to the same memory storage element(s) (101) by comparing addresses of the plurality of memory ports (115) of the multiport memory system (100); upon determining (202) that two or more memory ports (115) request access to the same memory storage element(s) (101), de-asserting (203) the wordlines (103) of all access circuitries of the memory storage element (101) except one wordline (103).

[0176] 25. A method (200) of operating a multiport memory system (100) according to item 23, wherein the multiport memory system (100) is a multi-port memory system according to any one of items 1 to 20.

Claims

Claims1 . A multiport memory system (100) with built-in contention management comprising: a plurality of memory storage elements (101); a plurality of memory ports (115) for accessing the plurality of memory storage elements (101) through wordlines (103) and bitlines (102) connected to the memory storage elements (101), each memory storage element (101) comprising access circuitry for each memory port (115) for reading and writing data from / to the memory storage element (101), wherein the access circuitry for each memory port (115) is connected to a wordline (103) and at least one bitline (102); contention management circuitry (104) configured to detect contention when two or more memory ports (115) request time-overlapping access to the same memory storage element (101) and de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except one wordline (103).

2. The multiport memory system (100) according to claim 1 , wherein at least one of the time-overlapping accesses is a write access, wherein the contention management circuitry (104) is further configured to determine that at least one of the time-overlapping accesses is a write access.

3. The multiport memory system (100) according to claim 2, wherein the contention management circuitry (104) is further configured to de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except the wordline (103) connected to the access circuitry associated with the memory port (115) requesting the last occurring write access.

4. The multiport memory system (100) according to claim 1 , wherein the contention management circuitry (104) is configured to detect contention when two or more memory ports (115) request time-overlapping access to the same memory storage element(s) and, upon determining (202) that all of the timeoverlapping accesses are read accesses, de-assert the wordlines (103) of all access circuitries of the memory storage element (101) except the wordline(103) connected to the access circuitry associated with the memory port (115) requesting the first occurring read access.

5. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) is configured to, upon determining (202) that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, forward or copy, directly or indirectly, write data from the last occurring write access to the memory port(s) requesting the read access(es).

6. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) is configured to, upon determining (202) that at least one of the time-overlapping accesses is a write access and at least one of the time-overlapping accesses is a read access, copy write data from the last occurring write access to a read buffer (120), from which it can be read by the memory port(s) (115) requesting the read access(es).

7. The multiport memory system (100) according to any one of the preceding claims, wherein at least two of the time-overlapping accesses are write accesses comprising a first write access from a first memory port and a second write access from a second memory port, the first access from the first memory port starting before the second access from the second memory port, wherein the contention management circuitry (104) is further configured to de-assert the wordline (103) of the access circuitry for the first memory port (115).

8. The multiport memory system (100) according to claim 4, wherein the contention management circuitry (104) is further configured to stop driving bitlines of the first write access from the first memory port when the second access form the second memory port is detected.

9. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) is configured to, upon determining (202) that all of the time-overlapping accesses are read accesses, forward or copy, directly or indirectly, read data from the firstoccurring read access to the memory port (s) (115) requesting the remaining read access(es).

10. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) is configured to, upon determining (202) that all of the time-overlapping accesses are read accesses, copy read data from the first occurring read access to a read buffer (120), from which it can be read by the memory port(s) (115) requesting the remaining read access(es).

11. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) system comprises comparison circuitry (114) comparing the addresses of the plurality of memory ports (115) to detect access to the same memory storage element(s) (101).

12. The multiport memory system (100) according to any one of the preceding claims, wherein the contention management circuitry (104) is configured to determine which of a plurality of conflicting accesses that occurs first, and / or to determine in which order a plurality of conflicting accesses occur.

13. The multiport memory system (100) according to any one of the preceding claims, wherein an access from one of the plurality memory ports (115) is always prioritized when conflicting access occur at the same time, and / or wherein the plurality memory ports (115) are prioritized according to a predetermined order when conflicting access occur at the same time.

14. The multiport memory system (100) according to any one of the preceding claims, further comprising circuitry configured to generate a contention signal for an access from one or more memory ports (115), the contention signal comprising a predetermined delay indicating a contention window in which the access is considered for contention.

15. The multiport memory system (100) according to any one of the preceding claims, wherein the multiport memory system (100) is configured to prioritize accesses according to a predefined order if two or more accesses occur within a predefined time window.

16. A method (200) of operating a multiport memory system (100) with built-in contention management, the method (200) comprising the steps of: providing (201) a multiport memory system (100) comprising a plurality of memory storage elements (101) and a plurality of memory ports (115) for accessing the plurality of memory storage elements (101), wherein each memory storage element (101) comprises access circuitry for each memory port (115) for reading and writing data from / to the memory storage element (101), wherein the access circuitry for each memory port (115) is connected to a wordline (103) and at least one bitline (102); determining (202) if two or more memory ports (115) request access to the same memory storage element(s) (101) by comparing addresses of the plurality of memory ports (115) of the multiport memory system (100); upon determining (202) that two or more memory ports (115) request access to the same memory storage element(s) (101), de-asserting (203) the wordlines (103) of all access circuitries of the memory storage element (101) except one wordline (103).

17. A method (200) of operating a multiport memory system (100) according to claim 14, wherein the multiport memory system (100) is a multi-port memory system according to any one of claims 1 to 15.

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