A superconducting vertical interconnect and a method of making thereof

Abstract

A structure comprising a preferably high-resistivity substrate comprising a superconducting vertical interconnect SVI (100) extending through the substrate (101) from a first side (101a) to a second side (101b) of the substrate (101), the second side (101b) being opposite to the first side (101a), said SVI (100) comprising: a first interconnect portion (103) extending from the first side (101a) into the substrate (101) without reaching the second side (101b) of the substrate (101), a plurality of second interconnect portions (104) extending from the second side (101b) to the first interconnect portion (103) thus joining with the first interconnect portion (103), a superconducting conformal coating (105) covering at least sidewalls (103a) of the first interconnect portion (103) and at least a portion of sidewalls (104a) of the plurality of second interconnect portions (104a), and a continuous superconducting path from the first side (101a) to the second side (101b) of the substrate (101), said path at least partially formed by the conformal coating (105). The disclosure further relates to a method of forming a superconducting vertical interconnect.

Description

[0001] A superconducting vertical interconnect and a method of making thereof

[0002] Technical field

[0003] The invention relates to superconducting through substrate vias (STSVs) or superconducting vertical interconnects (SVIs). The invention also concerns a structure comprising a qubit chip connected to the SVIs, and a method of forming the SVIs.

[0004] Background

[0005] A robust quantum computing system will require at least several hundred qubits within a unified system. Progress so far has been focused around 2D arrangements of qubits, yet accessing qubits in the interior regions of the 2D array necessitates an intricate layout of various coplanar waveguides (CPW) adding complexity to the design. Routing control lines thus requires 3D arrangements in large scale quantum processors (QPUs). With 3D design qubits and the ancillary CPW lines can be fabricated on different chips and later unified into a single structure through, for example, flip-chip bonding. The incorporation of STSV technology significantly advances 3D integration by offering an effective means of routing signals across chips.

[0006] Conventional TSVs are made by removing material in a substrate making a path from one side of the substrate to the other, coating the path with a conducting material, and subsequently filling the TSVs with a dielectric. Conventional TSVs, however tend to introduce signal loss and noise that are detrimental to the coherence of qubits. In addition, high frequency signals associated with qubits can experience attenuation and interference in traditional TSV structures. Moreover, the use of dielectrics creates losses at microwave frequencies, which may significantly limit the performance of high-fidelity qubits that have long coherence times and thus may be detrimental to quantum computing applications. Filling STSVs with superconducting material is one way to avoid lossy dielectrics. However, superconducting materials are expensive and of limited availability.

[0007] Alternatively, hollow STSVs have been demonstrated to be highly compatible with high-fidelity, high coherence qubits by circumventing the problem of lossy dielectrics. However, when performing additional processing on wafers containing STSVs, it is customary to close one end of the STSVs, enabling the use of tools equipped with vacuum-based handlers and facilitating efficient processing.

[0008] One way to close TSVs is by using membranes. However, when membranes are integrated within TSVs, they form a weak link in the structure that makes the wafers fragile and prone to defects and damages, especially during further processing of the wafers. This becomes especially important when working with STSVs for quantum computing applications, as broken membranes cause tremendous damage to the wafers in subsequent processing stages in addition to creating particles and debris that might cause short-circuit resonator lines and signal CPWs. To avoid membranes, conventional TSVs have so far been either filled with a filler material, such as parylene, or been subject to electroplating and chemical-mechanical polishing (CMP).

[0009] Summary

[0010] An object of the present invention is to provide an alternative and improved superconducting through silicon via (STSV) or superconducting vertical interconnect (SVI). In particular, the invention may increase mechanical robustness of the structure thus increasing chip yield. Moreover, the invention enables STSVs that are free of deposited amorphous dielectrics and have an ultra-low microwave loss at qubit frequencies while permitting the formation, growth and / or patterning of additional layers over the structure. The characterizing features of the structure comprising a substrate comprising a superconducting vertical interconnect according to the invention are given in claim 1. Another object of the invention is to provide an improved method of forming the SVI, the characterizing features of which are given in the other independent claim. Further benefits of the invention may be:

[0011] - compatibility with different superconducting layers used on the planar surfaces,

[0012] - compatibility with silicon processing methods, i.e., possible to produce the structure with silicon processing methods,

[0013] - scalability and possibility to execute the process on a wafer-scale as well as use it for wafer scale quantum circuits,

[0014] - high throughput of individual chips free from defects due to robustness of STSV design,

[0015] - design flexibility independent of resonators or any other structure fabrication,

[0016] - IC-clean and CMOS compatible process allowing various further processing options,

[0017] - improved performance of quantum components, and / or

[0018] - scalability of quantum devices.

[0019] According to a first aspect of the invention, a structure comprising a preferably high-resistivity substrate comprising a superconducting vertical interconnect (SVI) extending through the substrate from a first side to a second side of the substrate is provided where the second side is opposite to the first side. The SVI comprises:

[0020] - a first interconnect portion extending from the first side into the substrate without reaching the second side of the substrate,

[0021] - a plurality of second interconnect portions extending from the second side to the first interconnect portion thus joining with the first interconnect portion,

[0022] - a superconducting conformal coating covering at least sidewalls of the first interconnect portion and at least a portion of sidewalls of the plurality of second interconnect portions, and

[0023] - a continuous superconducting path from the first side to the second side of the substrate, said path at least partially formed by the superconducting conformal coating.

[0024] The superconducting conformal coating may further cover the first and / or second side of the substrate. The superconducting conformal coating on the first and / or second side of the substrate may be fully omitted or removed or patterned, such as etched, to cover only a portion of the first and / or second side of the substrate. The superconducting conformal coating may cover the exposed surfaces of the structure.

[0025] The superconducting conformal coating may be deposited by atomic layer deposition (ALD).

[0026] The superconducting conformal coating may be titanium nitride (TiN) or niobium nitride (NbN) or any other suitable superconducting material.

[0027] The SVI sidewalls and thus portions of the superconducting conformal coating on such sidewalls may be substantially perpendicular to the first side of the substrate. The first interconnect portion may further comprise a top surface at a plane between the first interconnect portion and the plurality of second interconnect portions, where said top surface may be covered by a superconducting conformal coating, which, together with the top surface may be substantially parallel to the first side of the substrate.

[0028] The structure may further comprise a superconducting cap layer on the second side of the substrate. The cap layer may be aligned to cover openings of the plurality of second interconnect portions. The cap layer may be aligned to the center of the plurality of second interconnect portions taken as a group.

[0029] The cap layer may be sputtered, evaporated, or deposited by ALD. The cap layer may be a conformal layer.

[0030] The cap layer may be made of titanium nitride (TiN) or niobium nitride (NbN) or any other suitable superconducting material.

[0031] The cap layer may have tapered sidewalls.

[0032] The structure comprising the cap may further comprise a superconducting conformally coated layer on the side of the cap layer being opposite to the side in contact with the substrate. The superconducting conformally coated layer may be the same, i.e., deposited at the same time, as the superconducting conformal coating discussed above. However, it may also be different, i.e. deposited separately and thus have the same or different material and layer thickness.

[0033] The thickness of the superconducting conformal coating may be arranged relative to the size of the first interconnect portion and / or the plurality of the second interconnect portions such that the first interconnect portion and the plurality of the second interconnect portions are hollow. Alternatively, the thickness of the superconducting conformal coating may be arranged relative to the size of the first interconnect portion and / or the plurality of the second interconnect portions such that the first interconnect portion is hollow and the plurality of the second interconnect portions are filled with the superconducting conformal coating.

[0034] The plurality of second interconnect portions may be arranged in a symmetric array or in a random distribution, wherein the symmetric array may have rotational, mirror or other type of symmetry. The projection of the array or the distribution on the first interconnect portion may be, though does not have to be, within the boundary of the first interconnect portion. Preferably the center of the array or distribution is aligned with the center of the first interconnect portion in a horizontal direction, i.e., so that a common vertical axis connects said centers.

[0035] The cross-sectional area of any one of the plurality of second interconnect portions may be at least 100 times smaller, preferably at least 2500 times smaller, than the cross-sectional area of the first interconnect portion. For example, if the first interconnect and the plurality of second interconnect portions have substantially circular cross sections, their diameter ratio is at least 10, preferably at least 50.

[0036] The largest width of the first interconnect portion, where width is parallel to the first side of the substrate, may be between 1 pm and 200 pm, preferably between 10 pm and 100 pm, for example, 60 pm. The first interconnect portion may, for example, have a substantially circular cross section, the width corresponding to the diameter of the first interconnect portion. As another example, the first interconnect portion may have a substantially race-track cross section the largest width correspond ing to the length of the major axis of the race-track shape.

[0037] The largest width, e.g., diameter, of the plurality of second interconnect portions, wherein width is parallel to the first side of the substrate, may be between 20 nm and 5 pm, preferably between 100 nm and 2 pm, for example, 1 pm.

[0038] The distance between two neighbouring second interconnect portions may be between two and ten times of the largest width of the plurality of second interconnect portions.

[0039] The length of the second interconnect portion may be between 100 nm and 100 pm. The length is defined to be perpendicular to the substrate’s first side.

[0040] The structure may further comprise:

[0041] - a qubit chip with at least one superconducting circuit,

[0042] - a superconducting ancillary circuit, such as comprising a coplanar waveguide, arranged on the substrate, and connected to the SVI, and

[0043] - a connector, such as an In bump, connecting the qubit chip, such as via at least one of the superconducting circuits of the qubit chip, with at least one SVI, such as via one of the superconducting ancillary circuits of the substrate.

[0044] According to a second aspect of the invention, a method of forming a superconducting vertical interconnect (SVI) extending through a substrate from a first side to a second side of the substrate is provided. The second side is opposite to the first side. The method comprises:

[0045] - obtaining the substrate,

[0046] - providing a first interconnect portion extending from the first side into the substrate,

[0047] - providing a plurality of second interconnect portions extending from the second side to the first interconnect portion, and

[0048] - forming a continuous superconducting path from the first side to the second side of the substrate, wherein forming comprises coating at least sidewalls of the first interconnect portion and at least a portion of sidewalls of the plurality of second interconnect portions with a conformal coating of a superconducting material.

[0049] The method step of providing of the first interconnect portion may comprise providing a mask, preferably a hard mask, on the first side of the substrate, and forming the first interconnect portion by deep reactive-ion etching (DRIE).

[0050] The method step of providing of the plurality of second interconnect portions may comprise:

[0051] - providing an etch stop layer, such as a thermally grown Silicon dioxide (SiO2) layer or aluminium oxide (AI2O3) layer deposited by ALD, on the first side of the substrate and the sidewalls of the first interconnect portion,

[0052] - providing a mask on the second side of the substrate, and

[0053] - forming the plurality of second interconnect portions by deep reactiveion etching until the etch stop layer is reached.

[0054] The method step of coating with the superconducting conformal coating may comprise removing any etch stop layer if present and providing the superconducting conformal coating using ALD.

[0055] The method may further comprise providing a superconducting cap layer on the second side of the substrate. Such cap layer may be provided before or after the deposition of the superconducting conformal coating. In cases where the second interconnect portions are hollow after the deposition of the superconducting conformal coating, the cap layer may be deposited to close openings of the plurality of second interconnect portions towards the second side of the substrate. The cap layer may be provided by sputtering, evaporation, or ALD.

[0056] The method may further comprise patterning the cap layer to define tapered sidewalls.

[0057] The superconducting conformal coating may be deposited to cover all exposed surfaces of the structure, such as the sidewalls and the top surface of the first and second interconnect portions respectively, the first side of the substrate, and either top of the superconducting cap layer if present or the second side of the substrate. The method may further comprise etching away whole or portions of the superconducting conformal coating on the first and / or second side of the substrate.

[0058] Brief description of the drawings

[0059] Embodiments of the invention are described below in more detail with reference to the accompanying drawings, in which:

[0060] Fig. 1 shows a schematic of a structure according to an embodiment of the invention, where Fig. 1 A shows a side cross-section view and Figs. 1 B-D show cross-sections at three different heights of Fig. 1A,

[0061] Fig. 2 shows a schematic of a structure comprising a cap layer according to an embodiment of the invention,

[0062] Fig. 3 shows a schematic of a structure comprising a cap layer according to an embodiment of the invention,

[0063] Fig. 4 shows a schematic of a structure according to an embodiment of the invention,

[0064] Fig. 5 shows a schematic of a structure according to an embodiment of the invention,

[0065] Fig. 6 shows a schematic of a structure comprising a qubit chip and a substrate comprising a superconductive vertical interconnect according to an embodiment of the invention,

[0066] Fig. 7 shows a schematic of a structure comprising a qubit chip and two substrates comprising a number of superconductive vertical interconnects according to an embodiment of the invention,

[0067] Fig. 8 shows a flowchart of the method according to the invention,

[0068] Fig. 9 shows a process flow and the various intermediate structures during the processing according to an embodiment of the invention, and

[0069] Fig. 10 shows a modified portion of a process flow and the various intermediate structures during the processing according to an embodiment of the invention. Detailed description

[0070] Fig. 1A shows a schematic side cross-section of a structure 100 according to an embodiment of the invention comprising a superconducting vertical interconnect (SVI) 102 extending through a substrate 101 from a first side 101 a to a second side 101 b of the substrate, where the first side is opposite to the second side. The substrate may be a silicon wafer. The substrate is preferably a high-resistivity substrate, such as having resistivity of at least 5000 Q cm, preferably at least 10000 Q-cm. The substrate may be doped or undoped.

[0071] Throughout this description, the horizontal direction is considered to be parallel to the first and second sides 101a, b of the substrate 101. Correspondingly, vertical direction is considered to be perpendicular to the said sides of the substrate. Fig. 1A illustrate horizontal direction as axis x and vertical direction as axis z. Length refers to the length along the vertical dimension, i.e., along z axis, whereas width is measured perpendicular to the length, not necessarily along just x axis, but parallel to the first and second sides of the substrate 101 . Whenever the shape’s cross-section perpendicular to vertical, z direction is circular, the width corresponds to the diameter.

[0072] The SVI 102 of Fig. 1A comprises a first interconnect portion 103 extending from the first side 101 a into the substrate 101 up to a set depth, such as to 90- 99%, preferably 94-98%, of the total thickness of the substrate 101 , without reaching the second side 101 b of the substrate 101.

[0073] The SVI further comprises a plurality of second interconnect portions 104 extending from the second side 101 b to, and thus joining with, the first interconnect portion 103. Each of the plurality of second interconnect portions 104 may be identical, although they do not have to be. The first interconnect portion may be etched up to a set depth into the substrate whereas the plurality of second interconnect portions may be etched until the top surface 103b of the first interconnect portion 103 is reached.

[0074] The SVI of Fig. 1 A further comprises a superconducting conformal coating 105 covering the preferably substantially vertical sidewalls 103a and preferably substantially horizontal top surface 103b of the first interconnect portion 103 and preferably substantially vertical sidewalls 104a and the openings 104b of the plurality of second interconnect portions 104. The superconducting conformal coating 105, interchangeably referred to as simply conformal coating 105, in Fig. 1 A forms a continuous superconducting path from the first side 101 a to the second side 101 b of the substrate 101. In Fig. 1A, the conformal coating 105 is further illustrated to coat the first side 101 a of the substrate, although it may be left uncoated or partially coated also, e.g., by removal of a part of the conformal coating. The continuous superconducting path may comprise other superconducting materials and thus may be formed partially by the conformal coating 105, for example, if a superconducting layer was deposited, such as sputtered or evaporated, on the second side 101 b of the substrate 101 after the plurality of second interconnect portions 104 have been etched away and thus openings 104b opened - a part of such deposited superconducting layer could enter the openings 104b and thus cover a portion of the sidewalls of the second interconnect portions 104, in which case if the conformal coating 105 is applied subsequently, the conformal coating 105 may cover only a portion of the sidewalls 104a.

[0075] Figs. 1 B-D illustrate cross sections of Fig. 1A at different heights as marked with roman numerals l-l, ll-ll, Ill-Ill and corresponding to the planes passing through the first side 101 a of the substrate, the top surface 103b of the first interconnect portion, and the second side 101 b of the substrate respectively. Figs. 1 B-D thus illustrate features present on said cross-section planes, Figs. 1 B and C focusing on the surfaces of the substrate 101 rather than those of the conformal coating 105. Fig. 1 B illustrates the first side 101 a of the substrate 101 , the portion of the conformal coating 105 on the sidewalls 103a of the first interconnect portion 103, and the void or hollow portion 103c of the first interconnect portion 103c. Fig. 1 C shows the boundaries of the sidewalls 103a of the first interconnect portion 103 as well as the sidewalls 104a of the second interconnect portions 104 and the top surface 103b area between said sidewall boundaries. Fig. 1 C further shows the conformal coating 105 deposited on the sidewalls 104a of the second interconnect portions as well as the void or hollow portion 104c of the plurality of second interconnect portions. The sidewalls 103a of the first interconnect portion 103 are shown as a dashed line in Fig. 1 C as there is not really any material boundary, the cross section comprising substrate 101 material on both sides of the dashed line, merely illustrating that that part of substrate 101 is referred to as the top surface 103b of the first interconnect portion. Fig. 1 D finally shows the top view of the Fig. 1 A structure, thus showing the openings 104b of the second interconnect portions being covered with the conformal coating 105.

[0076] The superconducting conformal coating 105 may be deposited by ALD. The superconducting conformal coating 105 may be any superconducting material, for example titanium nitride (TiN) or niobium nitride (NbN).

[0077] A conformal coating means that the coating uniformly covers the surface of an object, conforming to its contours and features, including edges, crevices, and irregular shapes. A conformal coating maintains a consistent thickness relative to the surface it covers. Hence, if the etched sidewalls 103a, 104a of the first and second interconnect portions are substantially vertical, then the conformal coating 105 deposited on such sidewalls will also be substantially vertical and if the top surface 103b of the second interconnect portion is substantially horizontal, i.e. substantially parallel to the first and second sides 101a,b of the substrate 101 , then the conformal coating 105 deposited therein will also be substantially parallel to said sides of the substrate.

[0078] As seen in Figs. 1 C, D, the plurality of second interconnect portions 104 may be arranged in a symmetric array with rotational symmetry. The plurality of second interconnect portions 104, however, may be arranged in any other symmetric array, such as with a mirror symmetry or others, or even be arranged in a random distribution. The plurality of second interconnect portions 104 may be arranged along a set of concentric shapes, such as concentric circles, ellipse, or racetrack shapes. Preferably, the plurality of second interconnect portions is arranged into an array, the projection of which on the first interconnection portion is within the boundary of the first interconnect portion, preferably wherein the centre of the array is aligned with the centre of the first interconnect portion in a horizontal direction, i.e., so that a common vertical axis connects said centres. An example of such arrangement is clearly illustrated in the cross-section of Fig. 1 C, where the plurality of second interconnect portions 104 are within the area defined by the sidewalls 104a of the first interconnect portion. Although Fig. 1 shows a cylindrical first interconnect portion 103, other shapes are possible, such as elliptical, oval, racetrack shaped, rectangular or other. Moreover, the first interconnect portion 103 may comprise multiple portions, such as a number of concentric cylinders or other shapes. The same applies to the plurality of second interconnect portions 104 where various shapes are possible, although a circular shape is preferrable for ease of manufacture.

[0079] The cross-sectional area of any one of the second interconnect portions may be at least 100 times smaller, preferably at least 2500 times smaller than the cross-sectional area of the first interconnect portion. We note that the figures are not up to scale for clarity of small features, however, in case of the examples where the first and the second interconnects have substantially circular cross sections, as illustrated in Fig. 1 , their diameter ratio is preferably at least 10, more preferably at least 50. In case of non-circular shapes, the largest width of the shape in a horizontal direction may be compared instead, such as, for example the major axis of an ellipse or a racetrack.

[0080] The length of the first interconnect portion is the thickness of the substrate 101 minus the length of the second interconnect portion, for example, if the thickness of the substrate 101 is 500 pm, the length of the first interconnect portion may be 475 pm. As an example, the length of the plurality of second interconnect portions may be between 100 nm and 100um, preferably around 10-50 pm, for example 25 pm.

[0081] The largest width of the first interconnect portion may be between 1 pm and 200 pm, preferably between 10 pm and 100 pm, for example 60 pm. In case of a racetrack cross section, width along the shortest axis may be 30 pm and along the longest axis may be 60 pm.

[0082] The largest width, such as the diameter, of the plurality of second interconnect portions 104 may be between 20 nm and 20 pm, preferably between 100 nm and 2 pm, for example, 1 pm. Aspect ratio of the largest width to the length of the second interconnect portions may be between 1 :5 and 1 :50, preferably between 1 :25 and 1 :30. The distance between two neighbouring second interconnect portions is preferably between 2-10 times of the largest width of the second interconnect portions. However, any distance and thus any density of the second interconnect portions may be possible as required by the design of the structure, as long as the fabrication process allows etching without causing any failure of the SVI sidewall, such as joining of the second interconnect portions.

[0083] Fig. 2 shows a structure 200, which is, although does not have to be, the same as that of Fig. 1 A with the addition of a superconducting cap layer 206 arranged on the second side 101 b of the substrate to cover the openings 104b of the plurality of second interconnect portions. The cap layer 206 is shown to be shaped to have tapered or trapezoidal sidewalls 206a, however, other shapes are also possible, such as any sidewalls achieved by regular deposition process without further patterning steps (for example, see 606, 706 in Figs. 6 and 7), or shaped with patterning steps. Tapered or sloping sidewalls may be beneficial for further deposition of continuous layers, such as continuous metal or resonator layers. The cap layer 206 may be made of any superconducting material, such as titanium nitride (TiN) or niobium nitride (NbN). The cap layer 206 may improve vacuum retention capability and thus increase reliability in further processing without introducing any defects or causing damage.

[0084] Fig. 2 shows an optional superconducting conformal layer 207 coated on the side of the cap layer 206 being opposite to the side in contact with the substrate 101. In other words, the cap layer 206 may be considered to comprise a first side in contact with the second side 101 b of the substrate and a second side opposite to the first side of the cap layer 206, the superconducting conformally coated layer 207 being thus deposited on the second side of the cap layer 206. The superconducting conformally coated layer 207 may be the same, i.e., deposited at the same time, as the superconducting conformal coating 105 discussed above. However, it may also be different, i.e. deposited separately and thus have the same or different material and layer thickness.

[0085] Fig. 3 shows a structure 300, which is, although does not have to be, essentially the same as that shown in Fig. 2, except that instead of the superconducting conformally coated layer 207 on the second side of the cap layer 206, now a layer 307 is deposited over the whole top side of the structure 300, including the second side 101 b of the substrate as well as the second side and sidewalls 206a of the cap layer 206. The layer 307 may be the same as the superconducting conformally coated layer 207 of Fig. 2, however, it may alternatively be a different layer, such as a resonator layer. The structure of Fig. 2 may in addition comprise a resonator layer, such as the layer 307 of Fig. 3 deposited on the second side 101 b of the substrate, the sidewalls of the cap layer 206 and the superconducting conformally coated layer 207.

[0086] Figs. 1-4 show structures where both the first and the plurality of the second interconnect portions 103, 104 are hollow and have, as illustrated, respective voids or hollow portions 103c, 104c. Such hollow portions may be beneficial in terms of quicker processing and material savings. The second interconnect portion, however, may be filled by the conformal coating 505, as shown in Fig. 5 structure 500, which may be beneficial to enable easier vacuum tool handling of the substrate without a need of special adjustments or additional layers, such as the cap layer 206 illustrated in Figs. 2, 3. The word filled above is intended to mean completely filled, without leaving a hollow space, however, not excluding the possibility of some voids or nanocavities due to nonuniformities in the dimensions of the second interconnect portions. The extent of the filling of the first and second interconnect portions may be controlled by selecting a thickness of the conformal coating 105. In particular, if the thickness of the conformal coating 105 is selected to be less than half the minimum width, or half the diameter in case of a circular cross section, of any of the second interconnect portions, both the first and the second interconnect portions will be hollow. The thickness of the conformal coating can be, however, chosen to be equal or larger than half the smallest width, or half the diameter in case of a circular cross section, of the second interconnect portions but smaller than half the smallest width, or diameter in case of a circular cross section, of the first interconnect portion, in which case, as shown in Fig. 5, the second interconnect portions are filled, and the first interconnect portion is hollow.

[0087] Appropriate thickness on the conformal coating 105 may be determined based on whether the second interconnect portions are to be filled as described above, as well as based on the critical current to be supported by the SVL The conformal coating 105 may have a thickness of 4 nm - 20 pm, preferably between 20 nm and 500 nm, for example, 200 nm. The total number of second interconnect portions per SVI, their shape and size, the thickness of the conformal coating and the choice of the material used for the conformal coating may all determine the value of the critical current allowed through the structure and through the SVI. Design of all such parameters thus may be based on the critical current required for specific applications. Critical current may further be modified with application of a magnetic field. A lower minimum critical current value may be sufficient when SVI is used for grounding as compared to when used as a signal SVI. A signal SVI may allow at least 10 pA critical current, preferably at least 100 pA.

[0088] The conformal coating 105 in Figs. 1-3 is shown to conformally cover also the opening 104b of the second interconnect portions. This may be achieved, for example, if a layer is deposited on the second side 101 b of the substrate prior to the deposition of the conformal coating 105, as will be described in more detail in connection to Fig. 9. The cap layer 206 shown in Figs. 2 and 3 may perform the function of such a layer, however, such layer is not necessary, and Fig. 4 illustrates a structure 400 according to an embodiment of the invention, where the superconducting conformal coating 405, which may otherwise be the same as that described earlier, is deposited on the structure when the SVI 102 is open to both the first and second side of the substrate 101 . As shown in Fig. 4, the plurality of second interconnect portions may then have a portion of the openings 104b open, i.e., not covered or filled by the conformal coating 405. Such openings may be closed, for example, as described above and shown in Fig. 5, by increasing the thickness of the conformal coating 405, 505, or by depositing a cap layer 206 as shown in Figs. 2 and 3.

[0089] The structure according to the invention may comprise more than one SVI, as for example shown in Figs. 6 and 7 in connection to a qubit chip, however, a substrate 101 may comprise one, two or any needed number of SVIs independently of the presence of a qubit chip or other features of Figs. 6 and 7. The substrate may comprise hundreds of SVIs.

[0090] The structure may comprise one or more qubit or one or more part of one or more qubit arranged on the substrate 101 . Fig. 6 illustrates a structure 600 according to an embodiment of the invention further comprising:

[0091] - a qubit chip 608 with a number of superconducting circuits 609, possibly including qubits, arranged to face the substrate containing the SVI 102,

[0092] - a number of superconducting ancillary circuits 611 , such as comprising a coplanar waveguide, arranged on the second side 101 b of the substrate 101 , facing the qubit chip 608, wherein at least some of the ancillary circuits 611 are connected to the conformal coating 105 of the SVI, optionally via a superconducting layer 606, and

[0093] - a connector 610, such as an In or other material bump, connecting the qubit chip 608, such as via at least one of the superconducting circuits 609 of the qubit chip 608, with at least one SVI 102, such as via one of the ancillary circuits 611 of the substrate 101 .

[0094] Fig. 7 illustrates another example of a structure 700 comprising:

[0095] - a qubit chip 608 with a number of superconducting circuits 609, possibly including qubits, arranged to face the substrate 101 containing the SVIs 102,

[0096] - a second substrate 701 which in turn comprises a second number of SVIs 702 extending through the second substrate from the first side to a second side of the second substrate 701 , the second side being opposite to the first side, wherein said SVI 702 may be same as described earlier,

[0097] - a number of superconducting ancillary circuits 611 , such as comprising a coplanar waveguide, arranged on the second side 101 b of the substrate 101 , facing away from the qubit chip 608, optionally connected to the conformal coating 105 of the SVI 102, optionally via a superconducting layer 606,

[0098] - a number of second superconducting ancillary circuits 711 arranged on the second side of the second substrate 701 , facing the second side of the substrate 101 and connected to the conformal coating 105 of the SVI 702 of the second structure, such as via a second superconducting layer 706,

[0099] - a connector 610, such as an In or other material bump, connecting qubit chip 608, such as via at least one of the superconducting circuits 609 of the qubit chip 608, with at least one SVI 102, such as via the conformal coating 105 of the SVI on the first side 101 a of the substrate, and

[0100] - a second connector 710 connecting at least one SV1 102, such as via at least one of the ancillary circuits 611 of the substrate 101 , with at least one SVI 702 of the second substrate 701 , such as via at least one of the second ancillary circuits 711 of the second substrate 701 . As shown in Fig. 7, the structure may further comprise a connector 710a connecting the SVIs 102, 702 directly via the superconducting layers 606, 706 of the SVIs 102, 702. It should be noted that in comparison to Fig. 6, in Fig. 7 the substrate 101 closest to the qubit chip 608 is flipped upside down. The second substrate 701 may, but does not have to, be same as the substrate 101 .

[0101] It should be further noted that Figs. 6 and 7 illustrate that not all parts of the ancillary circuits 611 , 711 are connected to an SVI. The representations in Figs. 6 and 7 show a “disconnected” cross-section to highlight that patterning was done on some sides of some substrates, e.g., in Fig. 6 on the second side of the substrate 101 , and in Fig. 7 on both sides of both substrates 101 , 701. It should be noted that such SVIs can be used for both ground stitching and for signal routing, where, e.g., in Fig. 6 the first side of the substrate 101 may be used as a ground, whereas the second side for signal routing. While Fig. 7 illustrates both sides of both substrates 101 , 701 being patterned and thus optimised for signal routing, other designs are also possible. In particular, design can be modified so that part of the SVIs are ground stitching and part are for signal routing.

[0102] In the era when QPUs are getting larger in lateral dimensions, structures with SVIs according to the invention may be used to improve QPU designs by providing vertical dimension, thereby increasing the density of qubits and superconducting junctions within the same lateral area. Such SVIs and design presented above allows the possibility to have a multi-chip (more than 2) bonded 3D structure with several interposer and / or qubit chips integrated into a unified system.

[0103] Figs. 6 and 7 described briefly above illustrate two examples of how the SVIs may be used in larger structures, such as in QPUs. Only core features are given of the examples as the skilled person would understand that many variations of the number as well arrangement of layers, circuits and connectors may be varied as needed in many ways. For example, the structure may comprise a plurality of qubit chips, where in some examples the additional qubit chips could be stacked on top of the qubit chip 608 or bonded on opposite sides of an SVI-containing substrate 101 , 701 . Alternatively, or in addition, the qubits or qubit chips could be located in place of the ancillary circuitry 611 , 711. If QPU design does not allow all the qubits to be placed on a single chip, a portion of the qubits may be placed on an SVI-containing substrate 101 , 701 or on multiple qubit chips which can then be stacked on top of each other and the whole stack may be bonded to the bottom most chip or substrate containing the other ancillary circuitry, such as the readout lines or flux lines. The SVIs in such case enable communications with qubits placed high up in the stack while bypassing any interference in or from any intermediate chips.

[0104] A method according to the invention is illustrated with a flowchart in Fig. 8 and an example method according to an embodiment of the invention is illustrated in more detail schematically via a processing flow showing intermediate structures in Fig. 9 as well as some alternative processing flow portions in Fig. 10.

[0105] As shown in Fig. 8, the method 800 according to the invention of forming a superconducting vertical interconnect (SVI) 102 extending through a substrate from a first side 101 a to a second side 101 b of the substrate 101 , the second side being opposite to the first side comprises:

[0106] - obtaining 801 the substrate 101 ,

[0107] - providing 802 a first interconnect portion 103 extending from the first side into the substrate,

[0108] - providing 803 a plurality of second interconnect portions 104 extending from the second side of the substrate to the first interconnect portion, and

[0109] - forming 804 a continuous superconducting path from the first side to the second side of the substrate, wherein forming comprises coating at least the sidewalls of the first interconnect portion and at least a portion of the sidewalls of the plurality of second interconnect portions with a conformal coating of a superconducting material.

[0110] The method as described above may have a specific order of steps, such as where the first interconnect portion 103 is provided before the plurality of second interconnect portions 104. The order of the steps may be in the order as listed above, however, a skilled person may be capable of adapting the required method steps in case of different order of steps. In particular, a first interconnect portion 103 may be provided 802 before or after the provision 803 of the plurality of second interconnect portions 104. The case where the first interconnect portion is provided 802 before the second interconnect portions is shown in Figs. 9 and 10 as discussed below. The alternative is discussed briefly afterwards.

[0111] The main steps 801 -804 of the method 800 are also indicated with arrows in Fig. 9. Some steps, such as steps 803-805 have been split into sub-steps marked as 803a, 803b, etc.

[0112] In one embodiment, as shown in Fig. 9, a substrate 101 with opposing first 101 a and second 101 b sides is first obtained in step 801 .

[0113] Provision 802 of the first interconnection portion 103 is illustrated in Fig. 9 as a step where a mask 910, preferably a hard mask, is provided on the first side 101a of the substrate and the first interconnect portion 103 is formed by etching away a part of the substrate 101 leaving a void 103c with a top surface 103b and sidewalls 103a. The etching may be performed by deep reactive-ion etching. The mask 910 may be made of various oxides, such as SiO2 or AI2O3. The mask may be deposited by plasma enhanced chemical vapor deposition (PECVD). Mask thickness may be 300 nm. Alternatively, a photoresist mask may be used without a hard mask.

[0114] After the provision 802 of the first interconnect portion 103, provision 803 of the plurality of second interconnect portions 104 comprises first a step 803a where the mask 910 is removed and an etch stop layer 911 is provided on the first side 101a of the substrate 101 and the side sidewalls 103a and the top surface 103b of the first interconnect portion. Next in step 803b, the plurality of second interconnect portions 104 are etched from the second side 101 b of the substrate until the etch stop layer 911 is reached. The etch stop layer 911 may be a thermal oxide layer, such as SiO2, or AI2O3 deposited by ALD. A thermal oxide layer may provide an added benefit of smoothening the surfaces of the first interconnect portion upon the removal of the thermal oxide layer. The thermal oxide layer may be deposited using a wet thermal oxidation process during which a thermal oxide layer is grown on both sides of the substrate 101 with a subsequent removal of the thermal oxide from the second side 101 b of the substrate, such as by a buffered oxide etcher solution. The etch stop layer may be several hundreds of nanometres thick. The etching step may include utilising at least one, preferably two, masks and deep reactive-ion etching.

[0115] After the provision 803 of the plurality of second interconnect portions, formation 804 of a continuous superconducting path from the first side 101 a of the substrate to the second side 101 b of the substrate may be split into two steps 804a and 804b. In first step 804a, a superconducting cap layer 916 is provided on the second side 101 b of the substrate, thus closing the openings 104b of the second interconnect portions 104. Thickness of the superconducting cap layer 916 may be 2 pm. The cap layer 916 is preferably provided by sputtering or evaporation. The cap layer 916 may be of any superconducting material, such as TiN or NbN.

[0116] In second step 804b, the etch stop layer 911 is removed and a superconducting conformal coating 105 is deposited on all exposed sides of the structure, such as onto the sidewalls 103a, 104a and the top surface 103b of the first and second interconnect portions respectively, the first side 101 a of the substrate 101 , and top of the superconducting cap layer 916. Masks or other covering means could be used to limit the deposition of the conformal coating to desired parts, such as to the sidewalls and the top surface of the first and second interconnect portions respectively. Alternatively, or in addition, some portions of conformal coating may be removed after the deposition. For example, the conformal coating 105 on the first and / or second side of the substrate could be omitted or patterned, such as by selective etching, to cover only a portion of the first side of the substrate as discussed in connection to Figs. 6 and 7. The superconducting conformal coating 105 may be deposited by ALD.

[0117] As discussed above and shown in the structure after step 804b, a superconducting conformal layer 917 may be deposited on top of the superconducting cap layer 916. The superconducting conformally coated layer may be the same, i.e., deposited at the same time, as the superconducting conformal coating 105 as discussed above. However, it may also be different, i.e. deposited separately and thus have the same or different material and layer thickness. The materials and properties of the conformal layer 917 may be the same as those of the conformal coating 105. The conformal coating 105 can thus be grown or deposited to cover all exposed surfaces of the structure. As shown in steps 805a, 805b, the method may further comprise patterning 805 of the cap layer 916 and optionally any superconducting conformal layer 917 on top of the cap layer 916. In particular, Fig. 9 illustrates patterning said layer to define tapered sidewalls 906. In step 805a, a tapered photoresist pattern is provided by lithographic patterning and resist reflow, after which, in step 805b, the cap layer 916 with its superconducting conformal layer 917 are patterned to have tapered sidewalls 906, such as through a combination of plasma and wet etching.

[0118] As discussed in connection to the SVI designs above, the superconducting cap layer 916 may be optional, i.e., omitted, or deposited after the deposition of the conformal coating 105, as also illustrated in Fig. 10. Fig. 10 illustrates an alternative flow process, where steps 801 to 803b may be the same as in Fig. 9 and are thus not repeated, and the flow process is shown starting from structure 900c, where step 804a is replaced by either 804c or 804e during which superconducting conformal coating 405, 505 is deposited at least on the SVI sidewalls. As shown in 804c and 804e, the conformal coating may be deposited also on the first side of the substrate. Although not shown in the figure 10, conformal coating may be deposited also on the second side of the substrate and such coating may be removed or kept depending on the application needs. The structures after steps 804c and 804e are shown without a conformal coating on the second side of the substrate, which may be achieved by either masking the second side before the conformal deposition or by depositing conformal coating on all exposed surfaces and etching away the conformal coating from the second side of the substrate after the deposition. In step 804c, the openings 104b of the second interconnect portions 104 are not closed and thus the shape of the deposited conformal coating 405 differs from that of coating 105 in Fig. 9 in that it does not fully cover the openings 104b, as illustrated also in Fig. 4, unless the thickness of the conformal coating 105 is such that it fills the second interconnect portions 104, as illustrated in Fig. 5 and as obtained after step 804e shown in Fig. 10 as coating 505. In either case, a cap layer 916 may be deposited after the deposition of the conformal coating 105, although it is illustrated only in the case of hollow second interconnect portions obtained in step 804c, as the cap serves the purpose of closing the openings 104b. The order of the steps 804a and 804b of Fig. 9 may thus be changed and / or step 804a could be omitted. Any further layer as described in steps 804b, 805a, and 805b earlier may be provided in the same manner in steps 804d, 805c, and 805d respectively in Fig. 10. Depositing the cap layer 916 after the deposition of the conformal coating 105 may be beneficial as a thinner cap layer 916 may be sufficient due to the reduced diameter of the openings 104b of the second interconnect portions. The cap layer 916 may be also omitted completely, however, in case of further processing, care must then be taken to arrange any vacuum handling system appropriately or use alternative means, such as static electricity, for securing the structure in place.

[0119] As discussed earlier, a first interconnect portion 103 may be provided 802 before or after the provision 803 of the plurality of second interconnect portions 104. The case where the first interconnect portion is provided 802 before the second interconnect portions was presented in connection to Figs. 9 and 10. Alternatively, the second interconnect portions may be etched first, such as by using one or more masks and RIE. After the etching, an etch stop layer may be deposited onto the walls of the second interconnect portions similar to the etch stop layer 911 of Fig. 9. However, such etch stop layer may also be omitted as the subsequent provision of the first interconnect portion may stop automatically, such as after reaching the second interconnect portion. Automatic stopping may be achieved, for example, by sensing of helium leakage once a path is opened between the first and second sides of the substrate. The automatic stopping may be executed once a predetermined helium flow threshold is reached. The provision, such as etching, of the first interconnect portion may continue beyond the sensing of helium leakage for a predetermined amount of time and optionally with adjusted etching parameters. Etching parameters may be adjusted to, for example, provide a reduced He flow once a first path is opened between the first and second sides of the substrate as detected by initial sensing of Helium flow. Optionally, a different etching technique or tool may be used.

[0120] The previously presented considerations concerning the various embodiments of the structure may be flexibly applied to the embodiments of the method mu- tatis mutandis, and vice versa, as being appreciated by a skilled person. While the exact steps of the method of obtaining each specific structure described earlier is not provided, based on the description of the structure and the steps of the method, a skilled person is expected to be able to interpolate the method steps required to achieve such structures. Moreover, it will be appreciated by a person skilled in the art that the invention is not limited to the embodiments described above but may vary within the scope of the appended claims.

Claims

Claims:

1. A structure (100, 200, 300, 400, 500, 600, 700, 900e-g) comprising a preferably high-resistivity substrate (101 ) comprising a superconducting vertical interconnect (SVI) (102) extending through the substrate from a first side (101 a) to a second side (101 b) of the substrate, the second side being opposite to the first side, said SVI comprising:- a first interconnect portion (103) extending from the first side into the substrate without reaching the second side of the substrate,- a plurality of second interconnect portions (104) extending from the second side to the first interconnect portion thus joining with the first interconnect portion,- a superconducting conformal coating (105, 405, 505) covering at least sidewalls (103a) of the first interconnect portion and at least a portion of sidewalls (104a) of the plurality of second interconnect portions, and- a continuous superconducting path from the first side to the second side of the substrate, said path at least partially formed by the superconducting conformal coating.

2. The structure according to claim 1 , wherein the superconducting conformal coating is deposited by atomic layer deposition (ALD), preferably wherein said coating is titanium nitride (TiN) or niobium nitride (NbN).

3. The structure according to claim 1 or 2, further comprising a superconducting cap layer (206, 606, 906, 916) on the second side of the substrate, preferably aligned to cover openings (104b) of the plurality of second interconnect portions.

4. The structure according to claim 3, wherein the cap layer has tapered sidewalls (206a).

5. The structure according to any one of claims 3-4, further comprising a superconducting conformally coated layer (207, 307, 907, 917) on the side of the cap layer being opposite to the side in contact with the substrate.

6. The structure according to any of the preceding claims, wherein the thickness of the superconducting conformal coating is arranged relative to the size of the first interconnect portion and / or the plurality of the second interconnect portions such that either:- the first interconnect portion and the plurality of the second interconnect portions are hollow, or- the first interconnect portion is hollow and the plurality of the second interconnect portions are filled with the superconducting conformal coating.

7. The structure according to any of the preceding claims, wherein the plurality of second interconnect portions is arranged in a symmetric array or in a random distribution, wherein- the symmetric array may have rotational, mirror or other type of symmetry, and- the projection of the array or distribution on the first interconnect portion is within the boundary (103a) of the first interconnect portion, preferably wherein the centre of the array is aligned with the centre of the first interconnect portion in a horizontal direction, i.e., so that a common vertical axis connects said centres.

8. The structure according to any of the preceding claims, wherein the cross-sectional area of any one of the plurality of second interconnect portions is at least 100 times smaller, preferably at least 2500 times smaller, than the cross-sectional area of the first interconnect portion, for example, if the first interconnect and the plurality of second interconnect portions have substantially circular cross sections, their diameter ratio is at least 10, preferably at least 50.

9. The structure according to any of the preceding claims, wherein the largest width, parallel to the first side of the substrate, e.g., diameter, of the plurality of second interconnect portions is between 20 nm and 5 pm, preferably between 100 nm and 2 pm, for example, 1 pm.

10. The structure according to any of the preceding claims, further comprising: a qubit chip (608) with at least one superconducting circuit (609),- a superconducting ancillary circuit (611 ), such as comprising a coplanar waveguide, arranged on the substrate (101 ) and connected to the SVI, and- a connector (610), such as an In bump, connecting the qubit chip, such as via at least one of the superconducting circuits of the qubit chip, with at least one SVI, such as via one of the superconducting ancillary circuits of the substrate.

11. A method (800) of forming a superconducting vertical interconnect (SVI) (102) extending through a substrate (101 ) from a first side (101 a) to a second side (101 b) of the substrate, the second side being opposite to the first side, the method comprising:- obtaining (801 ) the substrate,- providing (802) a first interconnect portion (103) extending from the first side into the substrate,- providing (803) a plurality of second interconnect portions (104) extending from the second side to the first interconnect portion, and- forming (804) a continuous superconducting path from the first side to the second side of the substrate, wherein forming comprises coating at least sidewalls (103a) of the first interconnect portion and at least a portion of sidewalls (104a) of the plurality of second interconnect portions with a conformal coating (105, 405, 505) of a superconducting material.

12. The method according to claim 11 , wherein the providing of the first interconnect portion comprises:- providing a mask (910) on the first side of the substrate, and- forming the first interconnect portion by deep reactive-ion etching.

13. The method according to claim 11 or 12, wherein the providing of the plurality of second interconnect portions comprises:- providing an etch stop layer (911 ), such as a thermal oxide layer or AI2O3 layer deposited by ALD, on the first side of the substrate and the sidewalls of the first interconnect portion,- providing a mask on the second side of the substrate, and- forming the plurality of second interconnect portions by deep reactiveion etching until the etch stop layer is reached.

14. The method according to any one of the claims 11-13, wherein the coating with the conformal coating comprises:- removing any etch stop layer if present, and - using atomic layer deposition (ALD) to provide the conformal coating.

15. The method according to any one of claims 11-14, further comprising providing a superconducting cap layer (916, 906) on the second side of the substrate, wherein said cap layer may be provided before or after the deposi- tion of the conformal coating.

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