Strain introduction method

Abstract

The strain introduction method according to the present invention is for introducing strain into the surface of silicon, and includes: a step for performing annealing on a substrate having a silicon oxide film layer formed on a (001) plane silicon substrate at a temperature of 1350°C or higher; and a step for cooling the substrate after annealing.

Description

Strain introduction method

[0001] The present invention relates to a strain introduction method for introducing strain into the surface of silicon by heat treatment.

[0002] Strain introduction technology is a technology that improves the mobility of electrons and holes and other physical properties by introducing strain, thereby increasing the performance of devices. This technology is mainly used to improve the performance of semiconductor integrated circuits. Meanwhile, application of strain introduction technology to silicon quantum bits is being considered.

[0003] In recent years, valley degeneracy of silicon has been recognized as a crucial problem in realizing spin qubit silicon quantum computers. Silicon quantum computers perform calculations using a pure spin two-level system, but the valley degeneracy remains in the quantum dots that form silicon quantum computers, making it impossible to perform correct quantum calculations with multiple qubits (see, for example, Non-Patent Document 1). Therefore, to realize a silicon quantum computer with quantum supremacy, it is necessary to completely resolve the valley degeneracy in each quantum dot.

[0004] One possible way to resolve valley degeneracy is to use external fields such as electric or magnetic fields. Since it is desirable for valley splitting to always be achieved in the operation of spin qubits, a structure that can consistently achieve valley splitting is optimal. When using electric or magnetic fields, in addition to the dot structure that forms the qubit in response to the application of the field and the gates that control their state, additional structures such as other electrodes or coils that control the valley splitting are required.

[0005] On the other hand, although the strain depends on the method of introduction, it is generally possible to consistently achieve valley splitting without introducing additional structures once strain is introduced. The magnitude of the valley splitting must be greater than the exchange interaction during quantum bit operation. This magnitude is generally on the order of several tens of μeV, and it is known that valley splitting due to strain can easily exceed this magnitude (see, for example, Non-Patent Document 2).

[0006] D. Buterakos and SD Sarma, “Spin-Valley Qubit Dynamics in Exchange-Coupled Silicon Quantum Dots”, PRX Quantum 2, 040358 (2021)J. Noborisaka, T. Hayashi, A. Fujiwara, K. Nishiguchi, “Valley splitting by extended zone effective mass approximation incorporating strain in silicon”, arxiv-2309.05219

[0007] There are two known methods for introducing strain into silicon. One method is called global strain, in which strain is introduced throughout the entire substrate by growing a germanium-containing alloy on a silicon substrate and then growing silicon again. The other method is called local strain, in which strain is introduced locally by depositing a material with strong residual stress (e.g., silicon nitride) above the channel during transistor fabrication and then removing the film except for the area where strain is to be introduced.

[0008] These methods are already being used in mass-produced products. Vapor phase growth is used to introduce strain in both methods. Vapor phase growth requires meeting many requirements, such as high vacuum, high-purity gases, the use of toxic gases, safety measures against toxic gases, and detoxification facilities, and the production of strained substrates is extremely costly.

[0009] As such, conventional strain-introducing techniques required costly vapor-phase growth techniques. Furthermore, realizing a silicon quantum computer required additional structures, such as electrodes and coils, to control valley splitting. These additional structures significantly complicate the elements that form the quantum bits, reducing yield and making large-scale implementation difficult, fundamentally complicating the realization of a silicon quantum computer.

[0010] The present invention has been made to solve these problems, and its object is to realize a method for introducing strain into a silicon surface at lower cost and more simply than conventional methods.

[0011] In order to solve the above-mentioned problems, the strain introduction method of the present invention is a strain introduction method for introducing strain into a silicon surface, and includes the steps of annealing a substrate having a silicon oxide film layer formed on a (001) silicon substrate at a temperature of 1350°C or higher, and cooling the substrate after the annealing.

[0012] According to the present invention, it is possible to realize a method for introducing strain into a silicon surface at lower cost and more simply than conventional methods.

[0013] FIG. 1A is a structural example of a silicon / silicon oxide substrate according to a first embodiment of the present invention. FIG. 1B is a structural example of a strain-introduced silicon / silicon oxide substrate according to the first embodiment of the present invention. FIG. 2A is a diagram showing the band dispersion relation of silicon according to the first embodiment of the present invention. FIG. 2B is a diagram showing the band dispersion relation of silicon according to the first embodiment of the present invention. FIG. 3 is a diagram showing an example of energy levels of a bulk and a quantum well according to the first embodiment of the present invention. FIG. 4A is a diagram showing the spatial distribution of the probability amplitude of an envelope function according to the first embodiment of the present invention. FIG. 4B is a diagram showing the probability amplitude of an envelope function in wavenumber space according to the first embodiment of the present invention. FIG. 5A is a diagram showing an example of a calculation of valley splitting according to the first embodiment of the present invention. FIG. 5B is a diagram showing an example of a calculation of valley splitting according to the first embodiment of the present invention. FIG. 6 is a diagram showing the total valley splitting according to the first embodiment of the present invention. FIG. 7 is a diagram showing an example of a configuration of an SOI substrate according to a third embodiment of the present invention. FIG. 8 is a diagram showing an example of a configuration of a thin-layer SOI substrate according to a sixth embodiment of the present invention. FIG. 9 is a diagram showing an example of a configuration of a double-gate MOSFET structure according to a seventh embodiment of the present invention. FIG. 10 is a diagram showing a configuration example of a double-gate MOSFET structure according to the seventh embodiment of the present invention.

[0014] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. The present invention can be implemented in various embodiments and is not limited to the embodiments described below.

[0015] <First embodiment> <Silicon / silicon oxide film substrate> Figure 1A shows an example of the structure of a silicon / silicon oxide film substrate in a first embodiment of the present invention. In the strain-introducing method of the present invention, strain is introduced into the silicon substrate 1 side of the interface between the silicon substrate 1 and the silicon oxide film 2. A silicon oxide film 2 is formed on a (001) silicon 1 that will serve as a substrate, to prepare a substrate as shown in Figure 1A.

[0016] Annealing refers to heat treatment of a substrate or the like in an annealing furnace set to a predetermined temperature. The melting point of silicon is generally around 1410°C, but silicon near the silicon oxide film 2 has a lower melting point due to its crystallinity, which differs from that of the bulk, and therefore begins to melt at 1350°C. Therefore, in this embodiment, annealing is performed at a temperature of 1350°C or higher.

[0017] After annealing the substrate at a temperature of 1350° C. or higher, cooling the substrate introduces a very large strain 10 into the silicon layer at the interface between the silicon substrate and the silicon oxide film 2, as shown in FIG. 1B. For example, when a (001) silicon substrate is used, a compressive strain of several percent is introduced in the <110> direction. The annealing time may be set appropriately depending on, for example, the size and structure of the substrate to be annealed. For example, annealing for 40 hours is considered, but is not limited to this.

[0018] <Band Dispersion Relation of Silicon> The band dispersion relation of silicon in the first embodiment of the present invention will be described with reference to Figures 2A and 2B. Figure 2A shows the band dispersion expanded to the second Brillouin zone up to point X. Figure 2B is an enlarged view of the band dispersion in the vicinity of point X.

[0019] Normally, when there is no shear strain, the degeneracy at the X point is not broken, as shown by the solid line in Figure 2B. On the other hand, when shear strain is introduced in the <110> direction, the band that forms the conduction band of silicon breaks the degeneracy near the X point, as shown by the dotted line in Figure 2B. The magnitude of the degeneracy splitting ΔE at the X point is expressed by the following equation (1).

[0020]

[0021] The degeneracy splitting of this X point is the valley separation ΔE ＶＳ When fabricating a silicon quantum dot structure to form a quantum bit, if a (001) surface substrate is used, the silicon quantum dot generally has the strongest confinement in the <001> direction because the gate is formed on the (001) surface.

[0022] <Bulk and quantum well energy levels> In this case, as shown in Figure 3, due to the anisotropy of the effective mass, the doubly degenerate valley with the heaviest effective mass in the <001> direction takes the ground energy, and the remaining four valleys perpendicular to the <001> direction form higher energy levels. This doubly degenerate state can be described as the product of the Bloch function and the quantum well envelope function in the <001> direction. The total wave function in the <001> direction can be expressed by the following equation (2).

[0023]

[0024] k ｔ is the wave number in the confinement plane direction (<100> or <010>), k ｚ is the wave number in the perpendicular direction (<001>), k ０ is the wave number (0.85 × 2π / a) that gives the minimum point of the valley ０ ), a ０ is the lattice constant of silicon.

[0025] In equation (2), the bottom of the conduction band, i.e., k ｔ = 0, k ｚ = ± k ０ Consider the state of k ｚ = ± k ０ The signs of represent the positive and negative valley states of the doubly degenerate valley. The total wave function in this case can be expressed by the following equation (3).

[0026]

[0027] <Probability Amplitude of Envelope Function> Fig. 4A is a diagram showing the spatial distribution of the probability amplitude of the envelope function in the first embodiment of the present invention. Fig. 4B is a diagram showing the probability amplitude of the envelope function in wave number space in the first embodiment of the present invention. The solid line indicates +k ０ Valley, dotted line is -k ０ represents the probability amplitude due to the valley of

[0028] In this embodiment, since a quantum well in the <001> direction is considered, the envelope function in the <001> direction in equation (3) forms a wave packet as shown in Fig. 4A. When this real space envelope function is Fourier transformed, it becomes a wave packet with wave numbers ±k ０ It can be seen that the Fourier coefficients in the high frequency range centered on have non-zero values. However, the amplitude of the high frequency Fourier coefficients increases in proportion to the strength of the real-space confinement.

[0029] As shown in FIG. 2A, the band minimum in the wavenumber space of the doubly degenerate valley in the <001> direction is k = |k ０ In the bulk state, the envelope function is a constant, and the Fourier transform of equation (3) is k ｚ = ± k ０ has a non-zero Fourier amplitude only at k ｚ = -k ０ , +k ０ The valleys of do not interfere in the bulk state and are in a doubly degenerate state.

[0030] On the other hand, in the quantum well structure, +k ０ , -k ０ The wave functions of the valleys of each have non-zero probability amplitudes in k-space depending on the strength of the confinement as described above. As the confinement becomes stronger, the wave functions of these valleys eventually overlap in wave number space. When overlap occurs in wave number space, k ｚ = -k ０ , +k ０ The valleys interfere and valley splitting is observed.

[0031] The magnitude of valley splitting in this case is given by the following equation (4) (see reference [FJ Ohkawa and Y. Uemura, “Theory of Valley Splitting in an N-Channel(100) Inversion Layer of Si”, J. Phys. Soc. Japan. 43, 907-917 (1977)]).

[0032]

[0033]

[0034] Gamma 15 , Γ １ ｕ The state of +k is the fundamental band that forms the bottom of the conduction band in a two-band k.p perturbation. The two bands are +k as shown in Figure 2A. ０ , -k ０ is a basis that forms bands corresponding to the valleys of

[0035] This band is ε at the Γ point. Γ The magnitude of this recoil is Γ 15 , Γ １ ｕ The conduction band from the Γ point to the X point is Γ when the two-band k.p perturbation is used. 15 , Γ １ ｕ It can be expressed as a linear sum of

[0036] +k ０ , -k ０ The valley state of is given by the linear sum of these bands, and in a <001> quantum well under strong confinement, these two valleys interfere. The magnitude of the interference is given by equation (6). The valley separation observed as a result of the interference is given by equation (5), which is equation (6) multiplied by the coupling strength of each band.

[0037] On the other hand, when the shear strain in the <110> direction is non-zero, the valley separation is given by the sum of the square roots of the valley separation through the X point and the valley separation at the Γ point, as shown in equation (4). Ｘ is given by the following equation (7).

[0038]

[0039] When the Brillouin zone is expanded and illustrated as shown in FIGS. 2A and 2B, the valley minimum on the second Brillouin zone side across point X is -k ０ It can be seen that this corresponds to the volleyball.

[0040] According to FIG. 2A, ±k ０ Wavenumber spatial distance Δk between valleys Ｘ is the Δk Γ This indicates that when the shear strain is non-zero, the valley separation at the X point may be significantly larger than that at the Γ point, since the magnitude of the shear strain deformation potential in the <110> direction is approximately 6 eV.

[0041] The key point of this embodiment is that a silicon substrate having a silicon oxide film formed at the interface of the silicon substrate where strain is to be introduced is subjected to high-temperature annealing treatment near the melting point of silicon, thereby enabling the introduction of a large compressive strain at the silicon / silicon oxide film interface.

[0042] Typically, strain is introduced by depositing a germanium film, which is an alloy with silicon, and then growing a strained silicon layer on top of that, or by leaving a silicon nitride film with residual stress on the silicon channel, which requires costly film deposition equipment.

[0043] In this embodiment, it is possible to introduce strain into a silicon layer by introducing a very simple heat treatment, namely, high-temperature annealing near the melting point of silicon. According to this embodiment, when a (001) silicon substrate is used, shear compressive strain in the <110> direction is introduced. Since the magnitude of the introduced strain is several percent, it is possible to separate the valley degeneracy to a magnitude of several tens of meV. This makes it possible to avoid the valley degeneracy problem, which is a fundamental issue in spin qubit silicon quantum computers.

[0044] <Use of SOI Substrate> The substrate to be subjected to high-temperature annealing may not be a silicon / silicon oxide substrate, but may be a substrate with an isolated silicon layer called SOI (Silicon On Insulator). Figure 7 is a diagram showing an example of the configuration of an SOI substrate in the third embodiment of the present invention.

[0045] When an SOI substrate is subjected to high-temperature annealing, it is possible for the interfaces between multiple silicon layers and silicon oxide layers to have strain. For example, in the configuration example of Figure 7, strain is introduced at both the interfaces between the silicon oxide layer 2 and the SOI layer 4 and between the silicon oxide layer 3 and the SOI layer 4, making it possible to realize a configuration in which valley degeneracy of the electronic state at both interfaces is eliminated.

[0046] <Calculation Example of Valley Separation> A calculation example of valley separation will be described with reference to Fig. 5A, Fig. 5B, and Fig. 6. Fig. 5A shows the valley separation ΔE due to the Γ point calculated using equations (5) and (6). Γ FIG. 5B shows the valley separation ΔE due to the X point calculated using equations (7) and (8). Ｘ 5A and 5B, the thickness of the SOI layer is 9 nm, and in FIG. 5B, a 5% shear strain in the <110> direction is introduced. In FIG. 5A and 5B, the horizontal axis represents the electric field strength in the <001> direction.

[0047] The total valley separation is given by the root of the sum of the squares of the valley separation due to the Γ point and the valley separation due to the X point, as shown in equation (4). Figure 6 shows the total valley separation ΔE for each <110> direction shear strain. ＶＳ The magnitude of the valley splitting is almost proportional to the electric field strength and is linear. This is due to the strong confinement caused by the electric field compressing the envelope function in the <001> direction.

[0048] Comparing Figures 5A and 5B, when the shear strain is finite, the valley separation ΔE Ｘ According to Figure 6, the magnitude of valley splitting increases almost linearly with increasing shear strain. As shown in Figure 6, when the shear strain is 5%, the magnitude of valley splitting reaches approximately 35 meV at an electric field strength of 50 MV / m in the <001> direction.

[0049] Second Embodiment Introduction of Inert Gas In the second embodiment, the substrate described in the first embodiment is subjected to a high-temperature annealing treatment in an inert gas atmosphere at 1350° C. or higher. The high-temperature annealing may be performed in a 100% oxygen atmosphere, but for the sake of oxidation speed, it may also be performed in an inert gas atmosphere in which approximately 0.5% oxygen has been introduced into an argon atmosphere.

[0050] However, 0.5% is not a required oxygen concentration. This 0.5% oxygen concentration is an example of a concentration that has been proven to prevent deterioration of the morphology at the silicon / silicon oxide interface. The inert gas is not limited to argon; any gas that is inert to silicon and silicon oxide at the temperature during high-temperature annealing can be used. For example, helium or nitrogen can also be used. Furthermore, annealing can be performed in an atmosphere of these inert gases or a mixture of inert gases that does not contain oxygen.

[0051] Third Embodiment Use of SIMOX In the third embodiment, a SIMOX (Separation by implanted oxygen) substrate, which is a type of SOI substrate, is used as the substrate for high-temperature annealing. It has been confirmed that a huge valley splitting of approximately 30 meV occurs in a SIMOX substrate (see K. Takashina, Y. Ono, A. Fujiwara, Y. Takahashi, and Y. Hirayama, "Valley Polarization in Si (100) at Zero Magnetic Field," Phys. Rev. Lett. 96, 236801 (2006)).

[0052] <Fourth embodiment> <Use of UNIBOND> In the fourth embodiment, UNIBOND, which is a type of SOI substrate, is used as the substrate for high-temperature annealing. As with SIMOX, UNIBOND can also be used for high-temperature annealing to introduce strain into the SOI / BOX layer interface.

[0053] Fifth Embodiment Use of Thin-Layer SOI Substrate In the fifth embodiment, a thin-layer SOI substrate is used as the SOI substrate. In this case, as shown in Fig. 8, it is possible to control the coupling of electrons in the electron reservoir 20 and the electron reservoir 30 formed at the silicon / silicon oxide film interface above and below the thin-layer SOI 4 by the electric field applied to the front gate 40 and the back gate 50. For the purpose of coupling of electrons in the electron reservoir 20 and the electron reservoir 30, the thickness of the thin-layer SOI 4 should be equal to or less than a thickness at which the overlap integral of the real-space wave function is non-zero.

[0054] <Sixth Embodiment> <Use of MOSFET> As a sixth embodiment, a double-gate MOSFET (metal oxide semiconductor field effect transistor) as shown in Fig. 9 may be used. In this structure, n-type silicon contacts 60 are formed on the silicon oxide films (2, 3) above and below the strained SOI layer 4, forming gates that are electrically connected to the SOI channel. This makes it possible to control valley splitting at the upper and lower silicon / silicon oxide film interfaces with the electric field of each gate.

[0055] By using the upper and lower gate electric fields, it is also possible to couple or separate the electronic states at the upper and lower interfaces of the SOI layer 4. Furthermore, as shown in Fig. 10, by stacking the structure of Fig. 9 via an insulating film 5, it is also possible to form a multi-layer SOI layer 4 in which valley separation can be controlled. By adjusting the size and arrangement of the upper and lower gates, it is also possible to form multiple quantum dots in the SOI layer 4 by electric field induction.

[0056] <Seventh embodiment> <Use of a substrate with a plane of other index> As a seventh embodiment, silicon with a plane of other index may be used. When silicon with a plane of other index is used, the direction of the introduced strain changes, and it is expected that the mobility of electrons or holes will change significantly.

[0057] Eighth Embodiment Adjustment of the Amount of Strain by Temperature Profile As an eighth embodiment, the temperature profile during high-temperature annealing may be adjusted to adjust the amount of strain introduced at the silicon / silicon oxide film interface. Specifically, the amount of strain can be adjusted by the rate at which the temperature is lowered during cooling after high-temperature annealing. When rapid cooling is performed, very large strain remains at the silicon / silicon oxide film interface. On the other hand, when slow cooling is performed, it is expected that the strain will be smaller. The degree of rapid cooling can be adjusted within a range that does not damage the substrate.

[0058] <Effects of the Embodiments of the Present Invention> According to the strain introduction method of the embodiments of the present invention, strain is introduced only by heat treatment, making it possible to realize a strain introduction method that does not require costly film formation equipment, etc. By performing the heat treatment of this embodiment on a silicon substrate with a (001) plane, it is possible to introduce shear compressive strain of up to several percent in the <110> direction. This significantly reduces the manufacturing cost of semiconductor integrated circuits and makes it possible to easily eliminate valley degeneracy, which is a problem in realizing spin qubit silicon quantum computers.

[0059] Although the present invention has been described above with reference to the embodiments, the present invention is not limited to the above-described embodiments. Various modifications that can be understood by those skilled in the art can be made to the configuration of the present invention within the scope of the present invention.

[0060] Some or all of the above-described embodiments can be described as, but are not limited to, the following supplementary notes.

[0061] [Supplementary Note 1] A strain introduction method for introducing strain into a silicon surface, comprising the steps of annealing a substrate having a silicon oxide film layer formed on a (001) silicon substrate at a temperature of 1350°C or higher, and cooling the substrate after the annealing. [Supplementary Note 2] A strain introduction method for introducing strain into a silicon surface, comprising the steps of annealing an SOI substrate at a temperature of 1350°C or higher, and cooling the substrate after the annealing. [Supplementary Note 3] The strain introduction method according to Supplementary Note 1 or Supplementary Note 2, wherein the annealing is performed in an atmosphere of a gas that is inert to the SOI substrate, the silicon substrate, and the silicon oxide film layer. [Supplementary Note 4] The strain introduction method according to any one of Supplementary Notes 1 to 3, wherein the amount of strain is adjusted by the rate of temperature decrease during cooling in the step of cooling the substrate.

[0062] 1... silicon substrate, 2, 3... silicon oxide film, 4... SOI layer, 5... insulating film, 10... strain, 20, 30... electron reservoir, 40... front gate, 50... back gate, 60... n-type silicon contact (gate).

Claims

1. A method for introducing strain into a silicon surface, comprising the steps of annealing a (001) silicon substrate having a silicon oxide film layer formed on it at a temperature of 1350°C or higher, and cooling the substrate after the annealing.

2. A strain introduction method for introducing strain into a silicon surface, comprising the steps of annealing an SOI substrate at a temperature of 1350°C or higher, and cooling the substrate after the annealing.

3. The strain introducing method according to claim 1, wherein the annealing is performed in an atmosphere of a gas that is inert to the silicon substrate and the silicon oxide film layer.

4. The strain introduction method according to claim 1, wherein the amount of strain is adjusted by the rate at which the temperature is decreased during cooling of the substrate.

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