Decoding device

Abstract

This decoding device is used for coherent digital signal processing, and comprises: a distributor for respectively distributing decoding metrics to each of first through d-th (d being an integer 2 or higher) lanes, such metrics obtained by demodulating received data in which communication channel noise occurring on a communication channel has been added to transmitted data transmitted from a transmission device on the basis of probability distribution information about the communication channel noise as well as a received signal; a first likelihood calculation unit that is provided on the first through (d-1)-th lanes and uses the decoding metrics distributed by the distributor to calculate a first log-likelihood ratio for each of the first through (d-1)-th lanes; a decoding unit for using soft decision decoding to perform error correction decoding on the first log-likelihood ratios, using SISO decoding typified by each of the iterative processes in Pyndiah-Chase decoding to calculate likelihoods from error correction decoding results, and feeding same back to the first likelihood calculation unit; and a second likelihood calculation unit that is provided on the d-th lane and makes a hard decision about results obtained when a predetermined number of processes were performed at the first likelihood calculation unit.　

Description

Decryption device

[0001] The present invention relates to a decoding device.

[0002] In optical transmission, the trade-off between power consumption and decoding performance is important for forward error correction (FEC). Optical transmission networks for data centers use short-length linear codes and low-computational-load soft-decision decoding methods, such as Chase 2 decoding. On the other hand, low-computational-load decoding methods are limited to short-length linear codes because the decoding load increases exponentially as the code length increases. Therefore, the decoding performance is limited by the code length.

[0003] In response to this, a configuration using CP-MLC (Channel-polarized multilevel coding) has been proposed in recent years (see, for example, Non-Patent Document 1). The CP-MLC method can improve the decoding performance limit for low-overhead, short-code-length linear codes.

[0004] T. Kakizaki et al., “Improved Performance-complexity Trade-offs for Soft-decision Decoding by Channel-polarized Multilevel Coding”, ECOC2023.

[0005] However, when the overhead is high, the CP-MLC method has a problem in that the decoding performance is limited by the error floor.

[0006] In view of the above circumstances, an object of the present invention is to provide a technique that can reduce the error floor and improve decoding performance more than ever before.

[0007] One aspect of the present invention is a decoding device used in coherent digital signal processing, comprising: a distributor that distributes, to each of a first lane to a dth (d is an integer greater than or equal to 2) lanes, a decoding metric obtained by demodulating received data to which channel noise has been added and transmitted from a transmitting device, based on probability distribution information of channel noise generated in the communication channel and the received signal; a first likelihood calculation unit that is provided on the first lane to the (d-1)th lane and that calculates a first log-likelihood ratio for each of the first lane to the (d-1)th lane using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using soft-decision decoding on the first log-likelihood ratio calculated for each of the first lane to the (d-1)th lane by the first likelihood calculation unit and feeds back the error correction decoding result to the first likelihood calculation unit; and a second likelihood calculation unit that is provided on the dth lane and that makes a hard decision on the result of a predetermined number of processes performed in the first likelihood calculation unit.

[0008] According to the present invention, it is possible to reduce the error floor and improve the decoding performance more than ever before.

[0009] 1 is a block diagram showing an example of the configuration of a transmitting device in an embodiment; 2 is a block diagram showing an example of the configuration of a receiving device in an embodiment; 3 is a diagram showing an example of the configuration of an encoding circuit in an embodiment when d = 3; 4 is a diagram showing the correspondence between a factor graph representation of a decoding circuit in an embodiment and variables described in the embodiment; and 5 is a diagram showing the results of a comparison experiment to evaluate the decoding performance between a conventional configuration and the configuration of an embodiment.

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] 1 is a block diagram showing an example of the configuration of a transmitting device 1 according to an embodiment. The transmitting device 1 is part of a digital coherent communication system and is a transmitting device used to transmit data to be transmitted (hereinafter referred to as "transmission data"). The transmitting device 1 transmits the transmission data to a receiving device connected via a communication path. The communication path is assumed to be, for example, an AWGN (Additive White Gaussian Noise) communication path.

[0012] The transmitting device 1 includes an encoding circuit 10, a symbol mapper 11, and a transmitting unit 12. The encoding circuit 10 includes an HD-FEC (Hard-Decision FEC) encoding unit 110, a 1:d converter 120, an SD-FEC (Soft-Decision FEC) encoding unit 130, a bit conversion circuit 140, and a d:1 converter 150.

[0013] Data to be transmitted is input to the HD-FEC encoding unit 110. The HD-FEC encoding unit 110 encodes the input data to be transmitted using HD-FEC technology. The data to be transmitted obtained by encoding is referred to as data z. The HD-FEC encoding unit 110 outputs data z to the 1:d converter 120.

[0014] The 1:d converter 120 divides the data z output from the HD-FEC encoding unit 110 into a predetermined division number d (d is an integer equal to or greater than 2). As a result, the data z is divided into d pieces. Hereinafter, the divided data z will be referred to as divided data z （１）´ , z （２）´ ,…, z （ｄ） The 1:d converter 120 converts the divided data z （１）´ , z （２）´ ,…, z （ｄ） are output to the first lane to the dth lane, respectively.

[0015] The 1:d converter 120 may include a bit interleaver for bit interleaving. However, the total bit length of the (d-1) lanes from the first lane to the (d-1)th lane is nR ＳＤ (d-1) / d, n represents an arbitrary constant, and R ＳＤ denotes the rate of the SD-FEC code.

[0016] The SD-FEC encoding unit 130 is provided on the first lane to the (d-1)th lane, and encodes the divided data z （１）´ , z （２）´ ,…, z （ｄ－１）´ The SD-FEC encoding unit 130 encodes the divided data z （１）, z （２） ,…, z （ｄ－１） The SD-FEC encoding unit 130 may have a bit interleaver for bit interleaving. The SD-FEC encoding unit 130 obtains the obtained divided data z （１） , z （２） ,…, z （ｄ－１） to the bit conversion circuit 140. In this way, the SD-FEC encoding unit 130 converts the divided data z （ｄ） is not encoded using error correction codes.

[0017] The bit conversion circuit 140 is a conversion circuit that converts a bit sequence into another bit sequence using exclusive OR. Specifically, the bit conversion circuit 140 converts the divided data z （ｄ） For example, the bit conversion circuit 140 converts the divided data z output from the SD-FEC encoding unit 130 to the first lane into （１） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） Similarly, the bit conversion circuit 140 performs an exclusive OR on the divided data z output from the SD-FEC encoding unit 130 to the second lane. （２） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） The exclusive OR is taken with

[0018] The bit conversion circuit 140 performs the above-described process on the divided data z output to each lane from the first lane to the (d-1)th lane. （１） , z （２） ,…, z （ｄ－１） The bit conversion circuit 140 converts the divided data z （１） , z （２） ,…, z （ｄ－１） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） The bit conversion circuit 140 outputs the result of the exclusive OR operation with the input divided data z （ｄ）is output to the d:1 converter 150 as is.

[0019] The d:1 converter 150 converts the divided data z transmitted in the first to d-th lanes into （１） , z （２） ,…, z （ｄ） The d:1 converter 150 converts the 1-lane series data into 1-lane series data by parallel-to-serial conversion. The d:1 converter 150 outputs the 1-lane series data to the symbol mapper 11.

[0020] The symbol mapper 11 generates transmission data by, for example, assigning symbols to the one-lane series of data output from the d:1 converter 150 using Gray labeling. The symbol mapper 11 outputs the generated transmission data to the transmitter 12.

[0021] The transmitter 12 transmits the transmission data generated by the symbol mapper 11 .

[0022] 2 is a block diagram showing an example of the configuration of a receiving device 2 according to an embodiment. The receiving device 2 is a transmitting device used in a digital coherent communication system. The receiving device 2 receives transmission data transmitted from a transmitting device 1 connected via a communication path.

[0023] The receiving device 2 includes a receiving unit 20 , a symbol demapper 21 , and a decoding circuit 22 .

[0024] The receiving unit 20 receives the transmission data transmitted from the transmitting device 1 via a communication path.

[0025] The symbol demapper 21 demodulates the transmission data received by the receiver 20 based on the channel information and the received signal using a demodulation method corresponding to the modulation method, and obtains a decoding metric. The decoding metric is, for example, a log-likelihood ratio (LLR). The channel information represents the probability distribution of noise occurrence on the channel. The channel information can be measured using a spectrum analyzer or the like. It is assumed that the channel information is measured in advance and stored in the SD likelihood calculation unit 230, which will be described later.

[0026] The decoding circuit 22 decodes the transmitted data based on the decoding metric obtained by the symbol demapper 21. The decoding circuit 22 is one aspect of a decoding device. The decoding circuit 22 is composed of a distributor 220, an SD likelihood calculation unit 230, an SD-FEC decoding unit 240, an HD likelihood calculation unit 250, a d:1 converter 260, and an HD-FEC decoding unit 270.

[0027] The distributor 220 receives the value demapped by the symbol demapper 21. The value demapped by the symbol demapper 21 is the received signal L:=(L （１） , L （２） ,…, L （ｉ） ) where L （ｉ） Let L be the LLR corresponding to the bit of lane i (i is an integer between 1 and d). The distributor 220 shares the received signal L among the first lane to the d-th lane. Specifically, the distributor 220 copies the same symbol to all lanes from the first lane to the d-th lane and shares it.

[0028] SD likelihood calculation unit 230 is provided on the first lane to the (d-1)th lane, and calculates a log-likelihood ratio for each of the first lane to the (d-1)th lane based on a value (e.g., received signal L) shared by each of the first lane to the (d-1)th lane by distributor 220. SD likelihood calculation unit 230 outputs the log-likelihood ratio calculated for each of the first lane to the (d-1)th lane from each of the first lane to the (d-1)th lane to SD-FEC decoding unit 240.

[0029] Furthermore, the SD likelihood calculation unit 230 receives the decoding results as feedback from the SD-FEC decoding unit 240. The SD likelihood calculation unit 230 uses the fed-back values ​​to again calculate the log-likelihood ratios for each of the first lane to the (d-1)th lane. The SD likelihood calculation unit 230 outputs the log-likelihood ratios calculated for each of the first lane to the (d-1)th lane to the SD-FEC decoding unit 240 from each of the first lane to the (d-1)th lane. The SD likelihood calculation unit 230 repeats the above process t times (1≦t≦T) times, where T is an integer greater than or equal to 1. The SD likelihood calculation unit 230 outputs the result of repeating the above process t times (the tth decoding result) to the HD likelihood calculation unit 250.

[0030] The SD-FEC decoder 240 performs error correction decoding using the log-likelihood ratios for each of the first lane to the (d-1)th lane calculated by the SD likelihood calculator 230. Here, the SD-FEC decoder 240 performs soft-input / soft-output decoding (hereinafter referred to as "SISO decoding"), which is typified by each iterative process of Pyndiah-Chase decoding. SISO in SISO decoding is an abbreviation for Soft Input Soft Output. Specific processing will be described later. The SD-FEC decoder 240 feeds back the decoding results for each of the first lane to the (d-1)th lane to the SD likelihood calculator 230. The SD-FEC decoder 240 repeats the above processing t times.

[0031] HD likelihood calculation unit 250 is provided on the d-th lane, and receives as input the decoded results for each of lanes 1 to (d−1) that are output from SD likelihood calculation unit 230 and the value distributed to the d-th lane by divider 220. HD likelihood calculation unit 250 makes a hard decision using the input decoded results for each of lanes 1 to (d−1) and the value distributed to the d-th lane by divider 220. HD likelihood calculation unit 250 outputs the hard decision result to d:1 converter 260.

[0032] The d:1 converter 260 converts the values ​​transmitted in each of the first to dth lanes into one lane of data by performing parallel-to-serial conversion.

[0033] The HD-FEC decoder 270 decodes the one-lane series of data output from the d:1 converter 260 using a decoding technique corresponding to the encoding performed by the HD-FEC encoder 110 .

[0034] Here, we will explain the specific flow of processing in the decoding circuit 22. In explaining the flow of processing in the decoding circuit 22, equation (1) will be defined below.

[0035]

[0036] The SD likelihood calculation unit 230 calculates the log likelihood ratio λ for i=1 to (d−1). （ｉ） ｔ is calculated based on the following formula (2).

[0037]

[0038] The SD-FEC decoder 240 corresponding to each i calculates the log-likelihood ratio λ （ｉ） ｔ is used as an input, and the extrinsic information L is calculated in the same manner as in the equations (18) and (19) in Reference 1 below. （ｉ） ｔ，ｅｘｔ By calculating the log-likelihood ratio L （ｉ） ｔ，ｅｘｔ is calculated based on the following formula (3): where α in formula (3) is 0≦α≦1. Here, the extrinsic information L （ｉ） is called extrinsic information or extrinsic LLR.

[0039] (Reference 1: Ramesh Mahendra Pyndiah, “Near-Optimum Decoding of Product Codes: Block Turbo Codes”, IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 46, NO. 8, AUGUST 1998.)

[0040]

[0041] Then, the SD-FEC decoder 240 calculates the log-likelihood ratio L （ｄ,ｉ） ｔ＋１ is calculated based on the following formula (4).

[0042]

[0043] L （ｄ,ｉ） ｔ is the unreliable LLR λ of lane i （ｉ） ｔ The log-likelihood ratio of the lane d with improved reliability at iteration t for calculating L is called the corrected LLR here. Note that the initial value for t=1 is （ｄ） Just use

[0044] The SD likelihood calculation unit 230 and the SD-FEC decoding unit 240 repeat the above process t times. Here, if the encoding circuit 10 performs the bit interleaving described in paragraph 0016, the decoding circuit 22 performs deinterleaving. The SD likelihood calculation unit 230 outputs the result of repeating the above process t times (the tth decoding result) to the HD likelihood calculation unit 250. The SD-FEC decoding unit 240 outputs the result of repeating the above process t times (the tth decoding result) to the d:1 converter 260.

[0045] The HD likelihood calculation unit 250 performs hard decision on the decoded results for each of the input lanes, from the first lane to the (d−1)th lane. The decoded results for each of the first lane to the (d−1)th lane are expressed by the following equation (5).

[0046]

[0047] The HD likelihood calculation unit 250 outputs the hard decision result to the d:1 converter 260 .

[0048] As described above, the decoding circuit 22 calculates the log-likelihood ratio of the next stage of each iteration using extrinsic information that is the output of SISO decoding (Reference 1), typified by each iteration of Pyndiah-Chase decoding used in turbo product codes, and calculates the LLR corresponding to the bit conversion circuit 140 using belief propagation as shown in the following Reference 2. Here, the extrinsic information may be subjected to hard decision, and +1 or −1 may be used instead of the LLR.

[0049] (Reference 2: Bo Yuan and Keshab K. Parhi, “Early Stopping Criteria for Energy-Efficient Low-Latency Belief-Propagation Polar Code Decoders”, IEEE TRANSACTIONS ON SIGNAL PROCESSING, VOL. 62, NO. 24, DECEMBER.)

[0050] (Factor Graph Representation) Next, the algorithm of the present invention will be described using a factor graph representation with reference to Figs. 3 and 4. Here, the case of three lanes (d = 3) will be described. Fig. 3 is a diagram showing an example of the configuration of the encoding circuit 10 in an embodiment when d = 3. Fig. 4 is a diagram showing the correspondence between the factor graph representation of the decoding circuit 22 in the embodiment and the variables described in the above embodiment.

[0051] 3, when the encoding circuit 10 has three lanes (d=3), an SD-FEC encoding unit 130 is provided on the first lane and the second lane. The SD-FEC encoding unit 130 encodes the divided data z output to the first lane and the second lane. （１）´ , z （２）´ The SD-FEC encoding unit 130 encodes the divided data z （１） , z （２） The SD-FEC encoding unit 130 obtains the divided data z output to the third lane. （３） is not encoded using error correction codes.

[0052] The bit conversion circuit 140 converts the divided data z （１） and the divided data z output from the 1:d converter 120 to the third lane. （３） Similarly, the bit conversion circuit 140 performs an exclusive OR on the divided data z output from the SD-FEC encoding unit 130 to the second lane. （２） and the divided data z output from the 1:d converter 120 to the third lane. （３） The bit conversion circuit 140 converts the divided data z （１） , z （２） and the divided data z output from the 1:d converter 120 to the third lane. （３） The bit conversion circuit 140 outputs the result of the exclusive OR operation with the input divided data z （３）The d:1 converter 150 outputs the divided data z transmitted through the first to third lanes as they are to the d:1 converter 150. （１） , z （２） , z （３） is converted into one lane of sequence data by parallel-to-serial conversion. The above is the flow of processing by the encoding circuit 10 when d=3.

[0053] "BCH" in Fig. 4 corresponds to the SD-FEC decoder 240. When the decoding circuit 22 has three lanes (d=3), the SD-FEC decoder 240 is provided on the first and second lanes. Note that δ() in Fig. 4 is a function that returns 1 if the logical expression in the () is true, and 0 if it is false.

[0054] (Effects of the Embodiments) Next, the results of a comparison experiment to evaluate the decoding performance between a conventional configuration and the configuration of the above-described embodiment will be described using Fig. 5. Fig. 5 shows the results of an evaluation of the BER characteristics of a configuration of the embodiment having the same overhead and a conventional BCH code (Chase decoding: number of test patterns = 2048). The horizontal axis in Fig. 5 represents the signal-to-noise ratio (Eb / N0) per information bit, and the vertical axis represents the BER. Eb is the energy per bit, and N0 is the noise spectral density.

[0055] The conditions for the evaluation experiment are as follows: (Conventional configuration) Element code: (127,113)-BCH code Overhead: 12.38% Number of test patterns (number of TPs): 2048 (Configuration of the embodiment) Element code: (127,106)-BCH code Overhead: 12.38% Number of test patterns (number of TPs): 512 The number of repetitions (number of repetitions) was set to T=10, and in the embodiment (d=3), element code 1 was set to -BCH code. Note that the evaluation experiment shown here did not perform the above-mentioned bit interleaving (described in paragraphs 0016 and 0044, for example).

[0056] In Figure 5, line L1 represents the results obtained with the configuration of the embodiment, and line L2 represents the results obtained with the conventional configuration. As shown in Figure 5, it can be confirmed that the decoding characteristics are excellent at a BER of about 2.4E-4. This indicates that when connected to an HDD, it is possible to construct a code with better decoding characteristics than the conventional method, depending on the HDD threshold.

[0057] The receiving device 2 configured as described above includes a distributor 220 that distributes the decoding metrics obtained by demodulating the transmission data transmitted from the transmitting device 1 based on information about noise generated in the communication path and the received signal to each of the first to d-th lanes; an SD likelihood calculation unit 230 that is provided on the first to (d-1)-th lanes and calculates a log-likelihood ratio for each of the first to (d-1)-th lanes using the decoding metrics distributed by distributor 220; an SD-FEC decoding unit 240 that performs error correction decoding using soft-decision decoding on the log-likelihood ratios calculated by the SD likelihood calculation unit 230 for each of the first to (d-1)-th lanes and feeds back the error correction decoding results to the SD likelihood calculation unit 230; and an HD likelihood calculation unit 250 that is provided on the d-th lane and makes a hard decision on the results of a predetermined number of processes performed in the SD likelihood calculation unit 230.

[0058] As a result, the theoretical limit of the conventional code length is extended, as in the conventional configuration (e.g., Non-Patent Document 1), and the decoding performance is improved. While an error floor occurs due to the error rate of bits that do not undergo SD-FEC decoding, it is possible to improve the decoding performance in the medium BER region.

[0059] (Modification 1) In the transmitting device 1, if the BER (Bit Error Rate) after SD-FEC decoding is below a threshold, the transmitting device 1 does not need to include the HD-FEC encoding unit 110.

[0060] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0061] Some of the functional units (e.g., encoding circuit 10) of the transmitting device 1 and some of the functional units (e.g., decoding circuit 22) of the receiving device 2 in the above-described embodiment may be implemented by a computer. In this case, a program for implementing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Note that the term "computer system" here includes hardware such as an OS (Operating System) and peripheral devices.

[0062] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, optical magnetic disks, ROMs (Read Only Memory), and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Furthermore, "computer-readable recording media" may also include devices that dynamically store programs for a short period of time, such as communication lines used when transmitting programs over networks like the Internet or communication lines like telephone lines, or devices that store programs for a fixed period of time, such as volatile memory within the computer systems that serve as servers or clients. Furthermore, the programs may be designed to realize some of the aforementioned functions, or may be capable of realizing the aforementioned functions in combination with programs already stored in the computer system, or may be realized using programmable logic devices such as FPGAs (Field Programmable Gate Arrays).

[0063] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0064] The present invention is applicable to communication systems that use encoders and decoders.

[0065] REFERENCE SIGNS LIST 1... transmitting device, 2... receiving device, 10... encoding circuit, 11... symbol mapper, 12... transmitting unit, 20... receiving unit, 21... symbol demapper, 22... decoding circuit, 110... HD-FEC encoding unit, 120... 1:d converter, 130... SD-FEC encoding unit, 140... bit conversion circuit, 150... d:1 converter, 220... distributor, 230... SD likelihood calculation unit, 240... SD-FEC decoding unit, 250... HD likelihood calculation unit, 260... d:1 converter, 270... HD-FEC decoding unit

Claims

1. A decoding device used in coherent digital signal processing, comprising: a distributor that distributes, to each of a first lane through a dth (d is an integer of 2 or greater) lane, a decoding metric obtained by demodulating received data to which channel noise has been added and transmitted from a transmitting device, based on probability distribution information of channel noise generated in the communication channel and the received signal; a first likelihood calculation unit that is provided on the first lane through the (d-1)th lane and that calculates a first log-likelihood ratio for each of the first lane through the (d-1)th lane using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using soft-decision decoding on the first log-likelihood ratio calculated for each of the first lane through the (d-1)th lane by the first likelihood calculation unit, and feeds back the error correction decoding result to the first likelihood calculation unit; and a second likelihood calculation unit that is provided on the dth lane and that makes a hard decision on the result of a predetermined number of processes performed in the first likelihood calculation unit.

2. The decoding device according to claim 1, wherein the decoding unit calculates the soft-decision decoding result to be fed back to the first likelihood calculation unit based on extrinsic information, which is output information of SISO (Soft Input Soft Output) decoding, typified by each iteration of Pyndiah-Chase decoding, and the decoding metric, and calculates an updated log-likelihood ratio as input information.

3. The decoding device according to claim 2, wherein the transmitting device uses belief propagation to calculate the log-likelihood ratio corresponding to the process of converting a bit sequence from the first lane to the (d-1)th lane using exclusive OR to another bit sequence, or performs hard decision on extrinsic information and uses +1 or -1 instead of the log-likelihood ratio.

4. The decoding device according to any one of claims 1 to 3, wherein, when bit interleaving is performed in the transmitting device, the decoding unit performs deinterleaving.

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