Semiconductor device and power conversion device

Abstract

The purpose of the present disclosure is to suppress diffusion of Si from an SiO2 film to a gallium oxide layer in a gallium oxide semiconductor device. A semiconductor device (101) is provided with a gallium oxide layer (20) and an insulating film formed on the gallium oxide layer (20). The insulating film includes a first gate insulating film (51) being a first insulating film not containing silicon as a material thereof, a second gate insulating film (52) being a second insulating film having silicon dioxide, and an interlayer insulating film (7) being a third insulating film. The first gate insulating film (51) is provided between the second gate insulating film (52) and the gallium oxide layer (20). The interlayer insulating film (7) is provided on the side of the second gate insulating film (52) opposite from the first gate insulating film (51).

Description

Semiconductor device and power conversion device

[0001] The present disclosure relates to a gallium oxide layer and a SiO ２ and an insulating film mainly containing

[0002] In a semiconductor device, various insulating films such as a gate insulating film, an interlayer insulating film, and a passivation film are provided on a semiconductor layer. ２ ) or SiO ２ Materials containing mainly SiO 2 have a large band gap and a large dielectric breakdown field, and are therefore widely used as insulating films in semiconductor devices. For example, Patent Document 1 discloses a material comprising an n-type semiconductor layer and a SiO 2 film covering a part of the upper surface of the n-type semiconductor layer. ２ and an insulating film made of the material.

[0003] Japanese Patent Application Laid-Open No. 2023-37564

[0004] However, according to the study by the inventors of the present disclosure, gallium oxide (Ga ２ O ３ ) as an insulating film on a semiconductor layer made of SiO ２ When a film having Ga is formed, Ga ２ O ３ / SiO ２ At the interface, silicon (Si) is ２ O ３ Diffuses into Ga ２ O ３ It has been found that there is a problem in that the donor concentration on the surface changes, causing fluctuations in the electrical characteristics of the semiconductor device.

[0005] The present disclosure has been made to solve the above-mentioned problems, and provides a gallium oxide semiconductor device in which SiO ２ The purpose of this invention is to suppress the diffusion of Si from the film having the above structure into the gallium oxide layer.

[0006] The semiconductor device of the present disclosure includes a gallium oxide layer and an insulating film formed above the gallium oxide layer. The insulating film includes a first insulating film that does not contain silicon, a second insulating film that contains silicon dioxide, and a third insulating film that is thicker than the second insulating film. The first insulating film is provided between the second insulating film and the gallium oxide layer, and the third insulating film is provided on the second insulating film opposite to the first insulating film.

[0007] The semiconductor device of the present disclosure is made of SiO ２ Since the lower insulating film containing no Si is provided between the upper insulating film having the above-mentioned formula (I) and the gallium oxide layer, the diffusion of Si from the upper insulating film to the gallium oxide layer is suppressed, thereby enabling the electrical characteristics of the semiconductor device to be maintained stable while providing high insulating performance due to the upper insulating film.

[0008] 1 is a cross-sectional view showing a configuration of an active region of a semiconductor device according to a first embodiment. ２ , Al ２ O ３ , and Ga ２ O ３ Fig. 1 is a diagram showing an energy band of a semiconductor device according to a first embodiment; Fig. 2 is a cross-sectional view showing a configuration of a termination region of a semiconductor device according to a first embodiment; Fig. 3 is a cross-sectional view showing another configuration of a termination region of a semiconductor device according to a second embodiment; Fig. 4 is a block diagram showing a configuration of a power conversion system according to a third embodiment;

[0009] In the following description, n-type and p-type refer to the conductivity types of semiconductors. In this disclosure, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may also be p-type and the second conductivity type as n-type. n+ type means a higher impurity concentration than n-type, and n- type means a lower impurity concentration than n-type. p+ type means a higher impurity concentration than p-type, and p- type means a lower impurity concentration than p-type. Furthermore, the impurity concentration of each region is defined by the peak concentration. In other words, a region with a high (or low) impurity concentration means a region with a high (or low) peak impurity concentration.

[0010] The drawings are schematic illustrations, and the relative sizes and positions of images shown in different drawings are not necessarily accurately depicted and may be changed as appropriate. In the following description, similar components are denoted by the same reference numerals, and their names and functions are also the same. Therefore, detailed descriptions thereof may be omitted.

[0011] In the following description, terms that indicate specific positions and directions, such as "top," "bottom," "side," "front," and "back," may be used. However, these terms are used for convenience to facilitate understanding of the contents of the embodiments, and do not relate to the directions in which the embodiments are actually implemented.

[0012] <A. First Embodiment> <A-1. Active Region> Figure 1 is a cross-sectional view showing the configuration of an active region of a semiconductor device 101 according to a first embodiment. The semiconductor device 101 is a vertical planar MOSFET. As shown in Figure 1, the semiconductor device 101 is configured to include, in its active region, a gallium oxide layer 20, a gate insulating film 5, a gate electrode 6, an interlayer insulating film 7, a source electrode 8, and a drain electrode 9. Here, a transistor is described as an example of the semiconductor device 101, but the semiconductor device 101 may be another device such as a diode.

[0013] The gallium oxide layer 20 has a first main surface S1 and a second main surface S2. The gallium oxide layer 20 is made of gallium oxide (Ga ２ O ３), but may contain impurities such as In or Al. The gallium oxide layer 20 includes an n+-type first gallium oxide layer 1, an n--type second gallium oxide layer 2, a p-type well layer 3, and an n+-type source region 4. The second gallium oxide layer 2 is provided on the first main surface S1 side of the first gallium oxide layer 1. The lower surface of the first gallium oxide layer 1 corresponds to the second main surface S2, and a drain electrode 9 is provided on the second main surface S2. Here, for example, a gallium oxide single crystal substrate can be used for the first gallium oxide layer 1. However, in cases where the semiconductor device 101 is manufactured using a so-called backside grinding or heterosubstrate peeling process, the gallium oxide layer 20 may not include the first gallium oxide layer 1.

[0014] A p-type well layer 3 is formed in a portion of the surface layer of the second gallium oxide layer 2 on the first main surface S1 side. The well layer 3 is not limited to a p-type layer, and may be a layer to which an element such as nitrogen is added to form a slightly deep or deep acceptor level. An n+ type source region 4 is formed in the surface layer of the well layer 3 on the first main surface S1 side. The surface layer of the well layer 3 between the source region 4 and the second gallium oxide layer 2 serves as a channel region. A gate insulating film 5 is formed on the first main surface in contact with the second gallium oxide layer 2, the channel region, and some of the source regions 4 between adjacent well layers 3.

[0015] The gate insulating film 5 has a two-layer structure consisting of a first gate insulating film 51 in contact with the gallium oxide layer 20 and a second gate insulating film 52 on the first gate insulating film 51. The first gate insulating film 51 is made of a material that does not contain Si, such as aluminum oxide (Al ２ O ３ The second gate insulating film 52 is made of, for example, SiO ２ The second gate insulating film 52 is made of only SiO ２ It is not composed only of other insulating materials and SiO ２ It may also consist of

[0016] A gate electrode 6 is formed on the gate insulating film 5. An interlayer insulating film 7 is formed on the gate electrode 6. A source electrode 8 is formed on the interlayer insulating film 7. The gate electrode 6 and the source electrode 8 are insulated from each other by the interlayer insulating film 7. The interlayer insulating film 7 is thicker than the second gate insulating film 52 or the gate insulating film 5. The interlayer insulating film 7 is in contact with the gate insulating film 5 at both ends of the gate electrode 6. The interlayer insulating film 7 may or may not contain Si.

[0017] In the semiconductor device 101, the second gate insulating film 52 is made of SiO ２ The first gate insulating film 51 is an insulating film that does not contain Si and is provided between the second insulating film and the gallium oxide layer, and is also referred to as the first insulating film. The interlayer insulating film 7 is an insulating film provided on the opposite side of the second insulating film from the first insulating film and is also referred to as the third insulating film.

[0018] The source electrode 8 is in contact with the source region 4 in a portion of the first main surface S1 where the gate insulating film 5 is not formed.

[0019] The semiconductor device 101 includes a gallium oxide layer 20 and a SiO ２ The first gate insulating film 51, which does not contain Si, is inserted between the second gate insulating film 52, which is made of Si. This suppresses the diffusion of Si from the second gate insulating film 52 into the gallium oxide layer 20. As a result, the donor concentration of the gallium oxide layer 20 is stabilized, and the conductivity is stabilized.

[0020] The material of the first gate insulating film 51 does not need to contain Si in order to suppress the diffusion of Si, but it is desirable that the material further satisfy the following conditions. ２ O ３ or HfO ２ However, the insulating film may be an insulating film made of three or more elements and satisfy the following conditions.

[0021] FIG. 2 shows the SiO 2 used for the second gate insulating film 52. ２ As an example, Al used for the first gate insulating film 51 ２ O ３and β-Ga used for the gallium oxide layer 20 as an example. ２ O ３ The energy bands are shown.

[0022] (1) The band gap of the material of the first gate insulating film 51 is Eg_1, Ga ２ O ３ The band gap of (Eg_Ga ２ O ３ )=4.6eV, SiO ２ The band gap of (Eg_SiO ２ ) = 8.7 eV, (Eg_SiO ２ )>(Eg_1)>(Eg_Ga ２ O ３ ) is desirable. Materials that satisfy this condition include Al, which has a band gap of 6.8 eV. ２ O ３ , hafnium oxide (HfO) with a band gap of about 6 eV ２ ), or ZrO with a band gap of 5.5 eV ２ etc.

[0023] (2) The conduction band minimum of the material of the first gate insulating film 51 and Ga ２ O ３ The absolute value of the energy difference between the conduction band minimum of SiO ２ and the conduction band edge of Ga ２ O ３ The absolute value of the energy difference between the conduction band minimum and the ２ ), then (ΔEc_SiO ２ )>(ΔEc_1)>0. ２ O ３ , HfO ２ , ZrO ２ This condition is also met if

[0024] (3) The upper edge of the valence band of the material of the first gate insulating film 51 and Ga ２ O ３ The absolute value of the energy difference between the top of the valence band of SiO is (ΔEv_1), ２ The upper edge of the valence band of Ga ２ O ３The absolute value of the energy difference between the top of the valence band and ｉ O ２ ), then (ΔEv_SiO ２ )>(ΔEv_1)>0. ２ O ３ This condition is also satisfied when the conditions (1), (2), and (3) are satisfied, and therefore the band gap changes stepwise from the gallium oxide layer 20 to the first gate insulating film 51 and further to the second gate insulating film 52, thereby preventing electrons or holes from being trapped in the first gate insulating film 51 or at the interface.

[0025] (4) The thickness of the first gate insulating film 51 is (t_1), and the thickness of the SiO 2 film used for the second gate insulating film 52 is (t_2). ２ The thickness of (t_SiO ２ ), then (t_SiO ２ )>(t_1). The thicker the first gate insulating film 51, the more effective it is in suppressing the diffusion of Si. However, since there is an upper limit to the thickness of the gate insulating film 5 in terms of design, the thicker the first gate insulating film 51, the thinner the second gate insulating film 52 may become. ２ This condition is obtained from the viewpoint of ensuring the thickness.

[0026] <A-2. Termination Region> Figure 3 is a cross-sectional view showing the configuration of the termination region of semiconductor device 101 according to the first embodiment. In Figure 3, A indicates a chip edge. As shown in Figure 3, semiconductor device 101 includes, in the termination region, second gallium oxide layer 2, well layer 3, termination well layer 11, first termination insulating film 21, second termination insulating film 22, interlayer insulating film 23, surface protective film 24, and source electrode 8. Note that Figure 3 does not illustrate drain electrode 9, first gallium oxide layer 1, and various electric field relaxation structures.

[0027] The termination well layer 11 is a p-type semiconductor layer made of an oxide semiconductor or a high-resistance layer formed by nitrogen ion implantation or the like in a surface layer portion on the first main surface S1 side of the second gallium oxide layer 2, and is adjacent to the well layer 3. The well layer 3 is also a p-type semiconductor layer made of an oxide semiconductor or a high-resistance layer formed by nitrogen ion implantation or the like in a surface layer portion on the first main surface S1 side of the second gallium oxide layer 2. The depths or impurity concentrations of the well layer 3 and the termination well layer 11 may be different or the same.

[0028] A first termination insulating film 21 is formed on termination well layer 11. A second termination insulating film 22 is formed on first termination insulating film 21. An interlayer insulating film 23 is formed on second termination insulating film 22. A source electrode 8 is formed on well layer 3. A surface protective film 24 is formed on second gallium oxide layer 2, covering first termination insulating film 21, second termination insulating film 22, and interlayer insulating film 23.

[0029] The first termination insulating film 21, the second termination insulating film 22, and the interlayer insulating film 23 may be formed in the same process as the first gate insulating film 51, the second gate insulating film 52, and the interlayer insulating film 7, respectively, and may be made of the same material as these. ２ and first termination insulating film 21 does not contain Si.

[0030] 3, the first termination insulating film 21 can suppress the diffusion of Si from the second termination insulating film 22 into the well layer 3 or the termination well layer 11. As a result, the electric field in the gallium oxide layer can be stabilized, and the electrical characteristics can be maintained stable. In particular, fluctuations in the electrical characteristics or a decrease in breakdown voltage of the semiconductor device due to the impurity type or amount of impurities in the p-type semiconductor in the termination region can be suppressed.

[0031] 3 has been described with reference to the case where a termination well layer 11 is formed on the surface of the second gallium oxide layer 2. However, as shown in FIG. 4 , instead of the termination well layer 11, a hetero material layer 12 made of a material different from gallium oxide may be formed on the first main surface S1 of the second gallium oxide layer 2. In this case, a first termination insulating film 21 is formed on the hetero material layer 12, and a second termination insulating film 22 is formed on the first termination insulating film 21. The hetero material layer 12 is, for example, a p-type semiconductor layer, and may be made of NiO, Cu, or the like. ２ 4, first termination insulating film 21 and second termination insulating film 22 are also formed on second gallium oxide layer 20, but they may be formed only on hetero material layer 12.

[0032] 3 and 4 , first termination insulating film 21 and second termination insulating film 22 are not formed to the chip edges. In this case, there is a risk of Si diffusing from second termination insulating film 22 to second gallium oxide layer 2 through regions of first main surface S1 where first termination insulating film 21 is not formed. To prevent this, first termination insulating film 21 and second termination insulating film 22 may be formed to the chip edges. Furthermore, first termination insulating film 21 and second termination insulating film 22 may be formed to regions outside various electric field relaxation structures (not shown) that do not overlap with the dicing lines of the chip.

[0033] <A-3. Effects> As described above, the semiconductor device 101 according to the first embodiment includes the gallium oxide layer 20 and the gate insulating film 5 formed on the gallium oxide layer 20. The gate insulating film 5 includes a first gate insulating film 51 that does not contain silicon as a material, a second gate insulating film 52 that contains silicon dioxide, and an interlayer insulating film 7. The first gate insulating film 51 is provided between the second gate insulating film 52 and the gallium oxide layer 20. The interlayer insulating film 7 is provided on the side of the second gate insulating film 52 opposite to the first gate insulating film 51. With this configuration, the second gate insulating film 52 or the SiO ２ When the interlayer insulating film 7 has the above structure, the diffusion of Si from the interlayer insulating film 7 to the gallium oxide layer 20 is suppressed. As a result, the donor concentration of the gallium oxide layer 20 is stabilized, and the electrical characteristics of the semiconductor device are stabilized.

[0034] <B. Second Embodiment> <B-1. Active Region> Figure 5 is a cross-sectional view showing the configuration of an active region of a semiconductor device 102 according to a second embodiment. The semiconductor device 102 is a vertical trench MOSFET. As shown in Figure 5, a trench 10 is formed in the gallium oxide layer 20, extending from the first main surface S1 through the source region 4 and the well layer 3 to reach the second gallium oxide layer 2. A gate insulating film 5 is formed on the side and bottom surfaces of the trench 10, and a gate electrode 6 is buried in the trench 10 with the gate insulating film 5 interposed therebetween.

[0035] The gate insulating film 5 has a two-layer structure of a first gate insulating film 51 and a second gate insulating film 52. The second gate insulating film 52 is formed in contact with the gate electrode 6, and the first gate insulating film 51 is formed between the second gate insulating film 52 and the gallium oxide layer 20.

[0036] An interlayer insulating film 7 is formed on the gate electrode 6. The interlayer insulating film 7 insulates the gate electrode 6 from the source electrode 8. The interlayer insulating film 7 contacts the second gate insulating film 52 on both sides of the trench 10. The remaining configuration of the active region of the semiconductor device 102 is similar to the configuration of the active region of the semiconductor device 101 described in the first embodiment.

[0037] <B-2. Termination Region> The configuration of the termination region of semiconductor device 102 may be similar to the configuration of the termination region of semiconductor device 101 shown in Figures 3 and 4. Alternatively, a trench reaching second gallium oxide layer 2 may be formed in the termination region, with hetero material layer 12 formed in the trench. In other words, as long as the formation of first termination insulating film 21 and second termination insulating film 22 suppresses Si diffusion and stabilizes the function of the termination region, the termination region of semiconductor device 102 is not limited to a specific structure.

[0038] <B-3. Effects> In the semiconductor device 102, the first gate insulating film 51 is provided on the bottom and sidewalls of the trench 10 formed in the gallium oxide layer 20. The second gate insulating film 52 is provided on the bottom and sidewalls of the trench 10 via the first gate insulating film 51. The semiconductor device 102 includes a gate electrode 6 embedded in the trench 10 via the first gate insulating film 51 and the second gate insulating film 52. In the semiconductor device 102, the third insulating film is an interlayer insulating film 7. In the above configuration, as in the semiconductor device 101 according to the first embodiment, the first gate insulating film 51 suppresses the diffusion of Si from the second gate insulating film 52 into the gallium oxide layer 20. As a result, the donor concentration of the gallium oxide layer 20 is stabilized, the electric field of the gallium oxide layer is stabilized, and the electrical characteristics of the semiconductor device are stabilized. In the trench type, the gate insulating film 5 contacts two surfaces, the side surface and the bottom surface, of the trench 10, and therefore it is not easy to select a plane orientation of the gallium oxide layer 20 so as to reduce the influence of Si diffusion on both surfaces. Therefore, it can be said that the configuration of the present disclosure, in which the first gate insulating film 51 suppresses the diffusion of Si into the gallium oxide layer 20, is particularly effective in the trench type.

[0039] <C. Third Embodiment> In this embodiment, the semiconductor devices 101 and 102 according to the above-described first and second embodiments are applied to a power conversion device. Although the application of the semiconductor devices 101 and 102 according to the first and second embodiments is not limited to a specific power conversion device, a case in which the semiconductor devices 101 and 102 according to the first and second embodiments are applied to a three-phase inverter will be described below as the third embodiment.

[0040] FIG. 6 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to this embodiment is applied.

[0041] The power conversion system shown in Fig. 6 is composed of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various components, such as a DC system, a solar cell, or a storage battery, or it may be composed of a rectifier circuit or an AC / DC converter connected to an AC system. The power supply 100 may also be composed of a DC / DC converter that converts DC power output from a DC system into a predetermined power.

[0042] The power conversion device 200 is a three-phase inverter connected between the power source 100 and the load 300, and converts DC power supplied from the power source 100 into AC power and supplies the AC power to the load 300. As shown in Fig. 6 , the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals that drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202.

[0043] The load 300 is a three-phase electric motor driven by AC power supplied from the power conversion device 200. The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical devices, and is used as an electric motor for, for example, a hybrid vehicle, an electric vehicle, a railroad car, an elevator, or an air conditioning device.

[0044] The power conversion device 200 will be described in detail below. The main conversion circuit 201 includes switching elements and freewheel diodes (not shown). The switching elements convert DC power supplied from the power supply 100 into AC power, which is supplied to the load 300. The main conversion circuit 201 can have a variety of specific circuit configurations. The main conversion circuit 201 according to this embodiment is a two-level, three-phase full-bridge circuit, which can be configured with six switching elements and six freewheel diodes connected in anti-parallel to each switching element. The semiconductor devices 101 and 102 according to the first and second embodiments are applied to at least one of the switching elements and freewheel diodes of the main conversion circuit 201. Two of the six switching elements are connected in series to form upper and lower arms, which constitute each phase (U phase, V phase, and W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0045] The drive circuit 202 generates drive signals for driving the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, in accordance with control signals from a control circuit 203 (described later), the drive circuit 202 outputs to the control electrodes of each switching element a drive signal that turns the switching element on and a drive signal that turns the switching element off. When maintaining a switching element in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element, and when maintaining a switching element in the off state, the drive signal is a voltage signal (off signal) that is equal to or lower than the threshold voltage of the switching element.

[0046] The control circuit 203 controls the switching elements of the main conversion circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main conversion circuit 201 should be in the on state based on the power to be supplied to the load 300. For example, the main conversion circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an on signal is output to the switching element that should be in the on state at each point in time, and an off signal is output to the switching element that should be in the off state at each point in time. In accordance with this control signal, the drive circuit 202 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element.

[0047] In the power conversion device according to the present embodiment, the semiconductor devices 101 and 102 according to the first and second embodiments are used as switching elements in the main conversion circuit 201, and therefore the reliability of the power conversion device can be improved.

[0048] In the present embodiment, an example has been described in which the semiconductor devices 101 and 102 according to the first and second embodiments are applied to a two-level three-phase inverter. However, the application of the semiconductor devices 101 and 102 according to the first and second embodiments is not limited to this, and they can be applied to various power conversion devices. In the present embodiment, a two-level power conversion device is described, but a three-level or multi-level power conversion device may also be applied. In addition, when power is supplied to a single-phase load, the semiconductor devices 101 and 102 according to the first and second embodiments may also be applied to a single-phase inverter. Furthermore, when power is supplied to a DC load or the like, the semiconductor devices 101 and 102 according to the first and second embodiments can also be applied to a DC / DC converter or an AC / DC converter.

[0049] Furthermore, the power conversion device to which the semiconductor devices 101 and 102 according to the first and second embodiments are applied is not limited to the case where the load described above is an electric motor, but can also be used, for example, as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0050] Note that the second termination insulating film 22 and the second gate insulating film 52 according to the first and second embodiments contain Si. Therefore, Si may diffuse into the vicinity of the exterior of each film, for example, the first termination insulating film 21 or the first gate insulating film 51, to form the first termination insulating film 21 or the first gate insulating film 51 containing Si. If we refer to this insulating film containing Si as a Si-containing insulating film, the Si-containing insulating film may be interposed between the first termination insulating film 21 and the second termination insulating film 22, or between the first gate insulating film 51 and the second gate insulating film 52, for example. The Si-containing insulating film may have a composition containing Si or an oxygen-rich composition based on the composition of the first termination insulating film 21 or the first gate insulating film 51, for example. Thus, strictly speaking, the gate insulating film 5 or the termination insulating film can be said to have at least a three-layer structure, but this is omitted from the above description. It is also conceivable that Si may diffuse and reach the interface of the gallium oxide layer 20, that is, that Si may be present throughout the entire area or almost the entire area of ​​the first termination insulating film 21 or the first gate insulating film 51. In this case, the gate insulating film 5 or the termination insulating film may be said to have at least a two-layer structure, or partially a three-layer structure.

[0051] Furthermore, first termination insulating film 21 and first gate insulating film 51 according to the first and second embodiments can also be said to be layers that stop or suppress the diffusion of Si, and preferably have a trap structure that easily traps Si. The trap structure may have, for example, a molecular structure such as a defect that easily forms a bond, such as a covalent bond, with Si over a partial or entire region, as long as it has some function of stopping or suppressing the diffusion of Si.

[0052] Although the preferred embodiments have been described above in detail, the present disclosure is not limited to the above embodiments, and various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims. Furthermore, the present disclosure can be applied not only to power semiconductor devices but also to high-frequency semiconductor devices.

[0053] 1 First gallium oxide layer, 2 Second gallium oxide layer, 3 Well layer, 4 Source region, 5 Gate insulating film, 6 Gate electrode, 7, 23 Interlayer insulating film, 8 Source electrode, 9 Drain electrode, 10 Trench, 11 Termination well layer, 12 Hetero material layer, 20 Gallium oxide layer, 21 First termination insulating film, 22 Second termination insulating film, 24 Surface protective film, 51 First gate insulating film, 52 Second gate insulating film, 100 Power supply, 101, 102 Semiconductor device, 200 Power conversion device, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load, S1 First main surface, S2 Second main surface.

Claims

1. A semiconductor device comprising: a gallium oxide layer; and an insulating film formed above the gallium oxide layer, the insulating film having a first insulating film that does not contain silicon as a material, a second insulating film that contains silicon dioxide, and a third insulating film that is thicker than the second insulating film, wherein the first insulating film is provided between the second insulating film and the gallium oxide layer, and the third insulating film is provided on the second insulating film opposite to the first insulating film.

2. The semiconductor device according to claim 1, wherein the band gap of the material constituting said first insulating film is larger than the band gap of a gallium oxide semiconductor and smaller than the band gap of silicon dioxide.

3. The semiconductor device according to claim 1 or 2, wherein the thickness of said first insulating film is smaller than the thickness of said second insulating film.

4. A semiconductor device according to any one of claims 1 to 3, wherein the absolute value of the energy difference between the conduction band minimum of the material constituting the first insulating film and the conduction band minimum of the gallium oxide semiconductor is smaller than the absolute value of the energy difference between the conduction band minimum of silicon dioxide and the conduction band minimum of the gallium oxide semiconductor, and is greater than 0.

5. A semiconductor device according to any one of claims 1 to 4, wherein the absolute value of the energy difference between the top of the valence band of the material constituting the first insulating film and the top of the valence band of the gallium oxide semiconductor is smaller than the absolute value of the energy difference between the top of the valence band of silicon dioxide and the top of the valence band of the gallium oxide semiconductor, and is greater than 0.

6. The semiconductor device according to any one of claims 1 to 5, wherein the first insulating film is provided on the bottom and sidewalls of a trench formed in the gallium oxide layer, the second insulating film is provided on the bottom and sidewalls of the trench via the first insulating film, the third insulating film is an interlayer insulating film formed on the gate electrode, and the semiconductor device further comprises a gate electrode embedded in the trench via the first insulating film and the second insulating film.

7. A semiconductor device according to any one of claims 1 to 6, which is divided into an active region and a termination region surrounding the active region in a plan view, and further comprises a heterogeneous semiconductor layer made of a semiconductor different from the gallium oxide and provided on the gallium oxide layer in the termination region, wherein the first insulating film is provided on the heterogeneous semiconductor layer, and the second insulating film is provided on the heterogeneous semiconductor layer via the first insulating film.

8. A semiconductor device according to any one of claims 1 to 6, wherein, in a plan view, the semiconductor device is divided into an active region and a termination region surrounding the active region, the first insulating film is provided on the gallium oxide layer in the termination region, and the second insulating film is provided on the gallium oxide layer via the first insulating film.

9. The semiconductor device according to claim 8, further comprising a high-resistance layer or a p-type semiconductor layer having an acceptor level in the termination region, and the first insulating film is provided on the high-resistance layer or the p-type semiconductor layer.

10. A power conversion device comprising the semiconductor device according to any one of claims 1 to 9, a main conversion circuit that converts input power and outputs it, and a control circuit that outputs a control signal to the main conversion circuit to control the main conversion circuit.

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