High frequency circuit

Abstract

A high frequency circuit (1) is provided with an antenna connection terminal (101), a filter (31) connected to the antenna connection terminal (101), a signal processing circuit (51), a signal processing circuit (52) having lower power consumption than the signal processing circuit (51), and a switch circuit (41) including a common terminal (410) connected to the filter (31), a selection terminal (411) connected to the signal processing circuit (51), and a selection terminal (412) connected to the signal processing circuit (52).

Description

High-frequency circuits

[0001] The present invention relates to a high-frequency circuit.

[0002] The 3GPP (registered trademark) (3rd Generation Partnership Project) is considering support for Low-Power Wake-up Signals (LPWUS), which can contribute to reducing power consumption of communication devices. Patent Document 1 discloses a wireless communication device equipped with a WUR (Wake-up Receiver).

[0003] Special table 2020-507977 publication

[0004] However, in the above-described conventional technology, the size of the communication device may increase in order to support LPWUS.

[0005] Therefore, the present invention provides a high-frequency circuit that can contribute to the miniaturization of communication devices compatible with LPWUS.

[0006] A high-frequency circuit according to one aspect of the present invention includes a first antenna connection terminal, a first filter connected to the first antenna connection terminal, a first signal processing circuit, a second signal processing circuit that consumes less power than the first signal processing circuit, and a first switch circuit including a first common terminal connected to the first filter, a first selection terminal connected to the first signal processing circuit, and a second selection terminal connected to the second signal processing circuit.

[0007] The present invention can contribute to the miniaturization of communication devices compatible with LPWUS.

[0008] Fig. 1 is a circuit configuration diagram of a communication device according to a first embodiment. Fig. 2 is a circuit configuration diagram of a first signal processing circuit according to the first embodiment. Fig. 3 is a circuit configuration diagram of a second signal processing circuit according to the first embodiment. Fig. 4 is a diagram showing a first mode of a high-frequency circuit according to the first embodiment. Fig. 5 is a diagram showing a second mode of a high-frequency circuit according to the first embodiment. Fig. 6 is a circuit configuration diagram of a communication device according to a second embodiment. Fig. 7 is a circuit configuration diagram of a communication device according to a third embodiment.

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the embodiments described below are all comprehensive or specific examples. The numerical values, shapes, materials, components, arrangements and connection forms of the components shown in the following embodiments are merely examples and are not intended to limit the present invention.

[0010] It should be noted that the drawings are schematic diagrams in which emphasis, omission, or adjustment of proportions has been appropriately made to illustrate the present invention, and are not necessarily strictly illustrated, and may differ from the actual shapes, positional relationships, and proportions. In the drawings, the same reference numerals are used to denote substantially the same components, and redundant explanations may be omitted or simplified.

[0011] In the following description, "connected" includes not only direct connection by connection terminals and / or wiring conductors, but also electrical connection via other circuit elements. "Connected between A and B" means connected to both A and B between A and B, and arranged in series on the path connecting A and B. "C is connected between A and B" means one end of C is connected to A and the other end of C is connected to B, and C is arranged in series on the path connecting A and B. "Path connecting A and B" means a path made up of conductors electrically connecting A to B.

[0012] "Terminal" means a point where a conductor within an element terminates. Note that terminal is understood to mean any point on the conductor between elements or the entire conductor, not just a single point, provided the impedance of the conductor between elements is sufficiently low.

[0013] "On state" means a state in which power consumption is higher than the sleep state and the off state. "Sleep state" means a state in which power consumption is lower than the on state but higher than the off state. "Off state" means a state in which power consumption is lower than the sleep state and the on state.

[0014] Terms indicating the relationship between elements, such as "parallel" and "perpendicular," terms indicating the shape of elements, such as "straight line," and numerical ranges do not only express strict meanings, but also include substantially equivalent ranges, for example, including an error of about several percent.

[0015] (First Embodiment) A first embodiment will be described.

[0016] [1.1. Configuration of communication device 4] First, the configuration of the communication device 4 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a diagram showing the configuration of the communication device 4 according to this embodiment.

[0017] 1 is an exemplary configuration, and communication device 4 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of communication device 4 provided below should not be construed as limiting.

[0018] The communication device 4 can be used to provide wireless connectivity. For example, the communication device 4 can be implemented in a UE in a cellular network (also called a mobile network), such as a mobile phone, a smartphone, a tablet computer, or a wearable device. In another example, the communication device 4 can be implemented to provide wireless connectivity to Internet of Things (IoT) sensor devices, medical / healthcare devices, cars, unmanned aerial vehicles (UAVs) (also known as drones), and automated guided vehicles (AGVs). In yet another example, the communication device 4 can be implemented to provide wireless connectivity in a wireless access point or wireless hotspot.

[0019] The communication device 4 includes a high-frequency circuit 1, an antenna 2a, and a BBIC (Baseband Integrated Circuit) 3.

[0020] The high frequency circuit 1 can transmit high frequency signals between the antenna 2a and the BBIC 3. The circuit configuration of the high frequency circuit 1 will be described later.

[0021] The antenna 2a is connected to the high-frequency circuit 1. The antenna 2a can receive a high-frequency signal from the high-frequency circuit 1 and transmit it to the outside of the communication device 4. Furthermore, the antenna 2a can receive a high-frequency signal from the outside of the communication device 4 and supply it to the high-frequency circuit 1. Note that the antenna 2a does not have to be included in the communication device 4. Furthermore, the communication device 4 may further include one or more antennas in addition to the antenna 2a.

[0022] The BBIC 3 is a baseband signal processing circuit that processes signals using a frequency band lower than the high-frequency signals transmitted by the high-frequency circuit 1. The signals processed by the BBIC 3 include, for example, image signals for image display and / or audio signals for calls via a speaker.

[0023] [1.2. Circuit Configuration of High-Frequency Circuit 1] Next, the circuit configuration of the high-frequency circuit 1 according to this embodiment will be described with reference to Fig. 1. Note that Fig. 1 is an exemplary circuit configuration, and the high-frequency circuit 1 can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1 provided below should not be interpreted in a limiting manner.

[0024] The high-frequency circuit 1 includes a power amplifier 10, a low-noise amplifier 20, filters 31 and 32, switch circuits 41 and 42, signal processing circuits 51 and 52, an antenna connection terminal 101, an input terminal 110, and output terminals 121 and 122.

[0025] The antenna connection terminal 101 is an example of a first antenna connection terminal, and is an external connection terminal of the high-frequency circuit 1. The antenna connection terminal 101 is a terminal for supplying a high-frequency signal to the antenna 2a and a terminal for receiving a high-frequency signal from the antenna 2a. The antenna connection terminal 101 is connected to the antenna 2a outside the high-frequency circuit 1, and is connected to the switch circuit 42 inside the high-frequency circuit 1.

[0026] The input terminal 110 is an external connection terminal of the high-frequency circuit 1, and is a terminal for receiving a baseband signal from the BBIC 3. The input terminal 110 is connected to the BBIC 3 outside the high-frequency circuit 1, and is connected to the signal processing circuit 51 inside the high-frequency circuit 1.

[0027] The output terminals 121 and 122 are external connection terminals of the high frequency circuit 1 and are terminals for supplying baseband signals to the BBIC 3. The output terminals 121 and 122 are connected to the BBIC 3 outside the high frequency circuit 1 and are connected to the signal processing circuits 51 and 52 inside the high frequency circuit 1, respectively.

[0028] The power amplifier 10 is connected between the signal processing circuit 51 and the switch circuit 42. Specifically, the input terminal of the power amplifier 10 is connected to the signal processing circuit 51, and the output terminal of the power amplifier 10 is connected to a selection terminal 421 of the switch circuit 42. The power amplifier 10 can amplify high-frequency signals using power supplied from a power supply (not shown).

[0029] The power amplifier 10 may be configured with a heterojunction bipolar transistor (HBT) and may be manufactured using a semiconductor material. Examples of the semiconductor material include silicon germanium (SiGe) and gallium arsenide (GaAs). The amplifying transistors of the power amplifier 10 are not limited to HBTs. For example, the power amplifier 10 may be configured with a high electron mobility transistor (HEMT) or a metal-semiconductor field effect transistor (MESFET). In this case, gallium nitride (GaN) or silicon carbide (SiC) may be used as the semiconductor material. Furthermore, some or all of the amplifying transistors of the power amplifier 10 may be configured with a complementary metal oxide semiconductor (CMOS) or may be manufactured using a silicon-on-insulator (SOI) process. In this case, single crystal silicon (Si) may be used as the semiconductor material.

[0030] The low-noise amplifier 20 is connected between the filter 31 and the switch circuit 41. Specifically, the input terminal of the low-noise amplifier 20 is connected to the filter 31, and the output terminal of the low-noise amplifier 20 is connected to a common terminal 410 of the switch circuit 41.

[0031] The low-noise amplifier 20 can be configured with a field-effect transistor (FET) and can be manufactured using a semiconductor material. Examples of the semiconductor material that can be used include silicon single crystal (Si), gallium nitride (GaN), and silicon carbide (SiC). The amplifying transistor of the low-noise amplifier 20 is not limited to a FET. For example, the low-noise amplifier 20 may be configured with a bipolar transistor.

[0032] The filter 31 is an example of a first filter, and is connected to the antenna connection terminal 101. Specifically, one end of the filter 31 is connected to the antenna connection terminal 101 via the switch circuit 42, and the other end of the filter 31 is connected to the input terminal of the low-noise amplifier 20.

[0033] The filter 32 is an example of a second filter, and is connected between the switch circuit 41 and the signal processing circuit 51. Specifically, one end of the filter 32 is connected to the selection terminal 411 of the switch circuit 41, and the other end of the filter 32 is connected to the signal processing circuit 51. The filter 32 is an optional component, and does not necessarily have to be included in the high-frequency circuit 1. The filter 32 may also be a variable filter whose pass characteristics are variable.

[0034] The filters 31 and / or 32 may be any of a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, an LC filter, and a dielectric filter, or any combination thereof.

[0035] The switch circuit 41 is an example of a first switch circuit and includes a common terminal 410 and selection terminals 411 and 412. The common terminal 410 is an example of a first common terminal and is connected to the filter 31 via the low-noise amplifier 20. The selection terminal 411 is an example of a first selection terminal and is connected to the signal processing circuit 51 via the filter 32. The selection terminal 412 is an example of a second selection terminal and is connected to the signal processing circuit 52. In this connection configuration, the switch circuit 41 can selectively connect the common terminal 410 to the selection terminals 411 and 412 based on, for example, a control signal from the signal processing circuits 51 and / or 52. The switch circuit 41 is configured, for example, as an SPDT (Single-Pole Double-Throw) type switch circuit.

[0036] The switch circuit 42 is an example of a second switch circuit and includes a common terminal 420 and selection terminals 421 and 422. The common terminal 420 is an example of a second common terminal and is connected to the antenna connection terminal 101. The selection terminal 421 is an example of a third selection terminal and is connected to the power amplifier 10. The selection terminal 422 is an example of a fourth selection terminal and is connected to the filter 31. In this connection configuration, the switch circuit 42 can selectively connect the common terminal 420 to the selection terminals 421 and 422 based on, for example, a control signal from the signal processing circuits 51 and / or 52. The switch circuit 42 is configured as, for example, an SPDT type switch circuit.

[0037] The signal processing circuit 51 is an example of a first signal processing circuit, and is connected between the power amplifier 10 and the input terminal 110, and between the filter 32 and the output terminal 121. The signal processing circuit 51 is configured to process a data signal (e.g., an LTE signal or a 5G NR signal). Specifically, the signal processing circuit 51 can upconvert a baseband transmission signal supplied from the BBIC 3 into a high-frequency transmission signal and supply it to the power amplifier 10, and can downconvert a high-frequency reception signal into a baseband reception signal and supply it to the BBIC 3. The circuit configuration of the signal processing circuit 51 will be described later using FIG. 2 .

[0038] The signal processing circuit 52 is an example of a second signal processing circuit, and is connected between the switch circuit 41 and the output terminal 122. The signal processing circuit 52 is configured to process a wake-up signal (e.g., LPWUS). The circuit configuration of the signal processing circuit 52 will be described later with reference to FIG. 3.

[0039] The signal processing circuit 52 consumes less power than the signal processing circuit 51. Specifically, the power consumption of the signal processing circuit 52 when set to the on state is lower than the power consumption of the signal processing circuit 51 when set to the on state. The power consumption of the signal processing circuit can be determined by measuring the power supplied to the power supply terminal of the signal processing circuit using an ammeter or a power analyzer. If it is difficult to measure the power supplied to the power supply terminal of the signal processing circuit, the power supplied from a power supply (not shown) to the power supply terminal of the high-frequency circuit may be measured.

[0040] The signal processing circuits 51 and / or 52 may have a control unit that controls the switches, amplifiers, etc. of the high-frequency circuit 1. Note that part or all of the functions of the signal processing circuits 51 and / or 52 as the control unit may be included outside the signal processing circuits 51 and / or 52, and may be included in the BBIC 3, for example.

[0041] [1.3. Circuit Configuration of Signal Processing Circuit 51] Next, the circuit configuration of the signal processing circuit 51 will be described with reference to Fig. 2. Fig. 2 is a circuit configuration diagram of the signal processing circuit 51 according to this embodiment.

[0042] 2 is an exemplary circuit configuration, and the signal processing circuit 51 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of the signal processing circuit 51 provided below should not be construed as limiting.

[0043] The signal processing circuit 51 includes a transmission signal processing circuit 51T and a reception signal processing circuit 51R. The transmission signal processing circuit 51T includes a quadrature modulator 511, a local oscillator LO1, amplifiers A1 and A2, low-pass filters F1 and F2, and digital-to-analog converters (DACs) DA1 and DA2.

[0044] The digital-to-analog converters DA1 and DA2 are connected between the input terminal 110 and the low-pass filters F1 and F2. The digital-to-analog converters DA1 and DA2 can convert two digital signals (an in-pulse (I) signal and a quadrature-phase (Q) signal)) supplied from the BBIC 3 into two baseband signals (an I signal and a Q signal), respectively.

[0045] The low-pass filter F1 is connected between the digital-to-analog converter DA1 and the amplifier A1. The low-pass filter F2 is connected between the digital-to-analog converter DA2 and the amplifier A2. The low-pass filters F1 and F2 can filter the two baseband signals supplied from the digital-to-analog converters DA1 and DA2, respectively.

[0046] The amplifier A1 is connected between the low-pass filter F1 and the mixer M1. The amplifier A2 is connected between the low-pass filter F2 and the mixer M2. The amplifiers A1 and A2 can amplify the two baseband signals supplied from the low-pass filters F1 and F2, respectively.

[0047] The local oscillator LO1 is connected to the quadrature modulator 511. The local oscillator LO1 can generate a local oscillation signal and supply it to the quadrature modulator 511.

[0048] The quadrature modulator 511 is connected to the local oscillator LO1 and the amplifiers A1 and A2. The quadrature modulator 511 can convert the two baseband signals amplified by the amplifiers A1 and A2 into two high-frequency signals (I signal and Q signal) based on the local oscillation signal generated by the local oscillator LO1. Furthermore, the quadrature modulator 511 can combine the two high-frequency signals. The quadrature modulator 511 includes a mixer M1 connected to the amplifier A1 and a mixer M2 connected to the amplifier A2.

[0049] The reception signal processing circuit 51R includes a quadrature demodulator 512, a local oscillator LO2, amplifiers A3 and A4, low-pass filters F3 and F4, and analog-to-digital converters (ADCs) AD1 and AD2.

[0050] The local oscillator LO2 is connected to the quadrature demodulator 512. The local oscillator LO2 can generate a local oscillation signal and supply it to the quadrature demodulator 512.

[0051] The quadrature demodulator 512 is connected to a local oscillator LO2 and low-pass filters F3 and F4. The quadrature demodulator 512 can convert a high-frequency signal into two baseband signals (I signal and Q signal) based on the local oscillation signal generated by the local oscillator LO2. The quadrature demodulator 512 includes a mixer M3 connected to the low-pass filter F3 and a mixer M4 connected to the low-pass filter F4.

[0052] The low-pass filter F3 is connected between the mixer M3 and the amplifier A3. The low-pass filter F4 is connected between the mixer M4 and the amplifier A4. The low-pass filters F3 and F4 can filter the two baseband signals supplied from the quadrature demodulator 512, respectively.

[0053] The amplifier A3 is connected between the low-pass filter F3 and the analog-to-digital converter AD1. The amplifier A4 is connected between the low-pass filter F4 and the analog-to-digital converter AD2. The amplifiers A3 and A4 can amplify the two baseband signals supplied from the low-pass filters F3 and F4, respectively.

[0054] The analog-to-digital converters AD1 and AD2 are connected between the amplifiers A3 and A4 and the output terminal 121. The analog-to-digital converters AD1 and AD2 can convert the two baseband signals amplified by the amplifiers A3 and A4 into two digital signals, respectively.

[0055] 2, the signal processing circuit 51 is a direct conversion transceiver, but is not limited to this. For example, the signal processing circuit 51 may be a superheterodyne transceiver. In this case, the signal processing circuit 51 may include a filter for an intermediate frequency.

[0056] [1.4. Circuit Configuration of Signal Processing Circuit 52] Next, the circuit configuration of the signal processing circuit 52 will be described with reference to Fig. 3. Fig. 3 is a circuit configuration diagram of the signal processing circuit 52 according to this embodiment.

[0057] 3 is an exemplary circuit configuration, and signal processing circuit 52 may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of signal processing circuit 52 provided below should not be construed as limiting.

[0058] The signal processing circuit 52 includes an envelope detector 521, an amplifier A5, a low-pass filter F5, and an analog-to-digital converter (ADC) AD3.

[0059] The envelope detector 521 can detect the envelope of the high-frequency signal that has passed through the filter 31 and been amplified by the low-noise amplifier 20. The envelope detector 521 includes a diode D1, a capacitor C1, and a resistor R1. The diode D1 is connected between the input and output terminals of the envelope detector 521. The capacitor C1 is connected in parallel with the resistor R1 between the path between the output terminal of the diode D1 and the output terminal of the envelope detector 521 and ground. The resistor R1 is connected in parallel with the capacitor C1 between the path between the output terminal of the diode D1 and the output terminal of the envelope detector 521 and ground.

[0060] The circuit configuration of envelope detector 521 shown in FIG. 3 is an example of the simplest one, and the present invention is not limited to this circuit configuration.

[0061] The amplifier A5 is connected between the envelope detector 521 and the low-pass filter F5. The amplifier A5 can amplify the envelope signal (baseband signal) supplied from the envelope detector 521.

[0062] A low-pass filter F5 is connected between the amplifier A5 and the analog-to-digital converter AD3, and is capable of filtering the envelope signal amplified by the amplifier A5.

[0063] The analog-to-digital converter AD3 is connected to the low-pass filter F5, and can convert the envelope signal that has passed through the low-pass filter F5 into a digital signal.

[0064] [1.5. Multiple Modes] Next, multiple modes of the high-frequency circuit 1 configured as above will be described.

[0065] [1.5.1. First Mode] First, the first mode included in the multiple modes will be described with reference to Fig. 4. Fig. 4 is a diagram showing the first mode of the high-frequency circuit 1 according to this embodiment. In the following figures, dashed arrows indicate the path of the high-frequency signal.

[0066] The first mode is a mode in which LTE signals or 5G NR signals are processed using the signal processing circuit 51, and is a high-power mode that consumes more power than the second mode described below.

[0067] In the first mode, the signal processing circuit 51 is set to an ON state, and the signal processing circuit 52 is set to an OFF state. The switch circuit 41 connects the common terminal 410 to the selection terminal 411. The switch circuit 42 connects the common terminal 420 to the selection terminal 422.

[0068] As a result, the LTE signal or 5G NR signal is transmitted from the antenna 2a to the BBIC 3 via the antenna connection terminal 101, the switch circuit 42, the filter 31, the low noise amplifier 20, the switch circuit 41, the filter 32, the signal processing circuit 51, and the output terminal 121.

[0069] In the first mode, the signal processing circuit 52 does not have to be set to the off state, but may be set to the sleep state or the on state.

[0070] [1.5.2. Second Mode] Next, the second mode included in the multiple modes will be described with reference to Fig. 5. Fig. 5 is a diagram showing the second mode of the high-frequency circuit 1 according to this embodiment.

[0071] The second mode is a mode in which the signal processing circuit 52 processes a wake-up signal (for example, LPWUS), and is a low-power mode in which power consumption is lower than in the first mode.

[0072] In the second mode, the signal processing circuit 51 is set to an off state or a sleep state, and the signal processing circuit 52 is set to an on state. The switch circuit 41 connects the common terminal 410 to the selection terminal 412. The switch circuit 42 connects the common terminal 420 to the selection terminal 422.

[0073] As a result, the wake-up signal is transmitted from the antenna 2 a to the BBIC 3 via the antenna connection terminal 101 , the switch circuit 42 , the filter 31 , the low-noise amplifier 20 , the switch circuit 41 , the signal processing circuit 52 , and the output terminal 122 .

[0074] When a predetermined condition (such as communication volume, time, or load) is satisfied in the first mode, the radio frequency circuit 1 switches from the first mode to the second mode. Also, when a wake-up signal is received in the second mode, the radio frequency circuit 1 switches from the second mode to the first mode.

[0075] The multiple modes of the high-frequency circuit 1 may include other modes in addition to the first and second modes. For example, the other modes may be modes in which an LTE signal or a 5G NR signal is transmitted using the signal processing circuit 51.

[0076] [1.6. Summary] As described above, the high-frequency circuit 1 according to this embodiment includes the antenna connection terminal 101, the filter 31 connected to the antenna connection terminal 101, the signal processing circuit 51, the signal processing circuit 52 that consumes less power than the signal processing circuit 51, and the switch circuit 41 that includes the common terminal 410 connected to the filter 31, the selection terminal 411 connected to the signal processing circuit 51, and the selection terminal 412 connected to the signal processing circuit 52.

[0077] This allows the switch circuit 41 to switch the connection of the filter 31 between the signal processing circuits 51 and 52. Therefore, the data signal can be processed by the high-power signal processing circuit 51, and the LPWUS can be processed by the low-power signal processing circuit 52, thereby reducing the power consumption of the high-frequency circuit 1. Furthermore, the filter 31 can be shared for filtering the data signal and the LPWUS, reducing the number of filters and contributing to the miniaturization of the communication device 4. In other words, this can contribute to the miniaturization of the communication device 4 that supports LPWUS.

[0078] Furthermore, for example, the high-frequency circuit 1 according to this embodiment may further include a low-noise amplifier 20 connected between the filter 31 and the common terminal 410 .

[0079] According to this, the switch circuit 41 can switch the connection of the low-noise amplifier 20 between the signal processing circuits 51 and 52. Therefore, the low-noise amplifier 20 can be used in common for amplifying the data signal and the LPWUS, which reduces the number of low-noise amplifiers and contributes to miniaturization of the communication device 4.

[0080] Furthermore, for example, the high-frequency circuit 1 according to this embodiment may further include a filter 32 connected between the selection terminal 411 and the signal processing circuit 51 .

[0081] This allows the data signal to be filtered by the filter 32 in addition to the filter 31, thereby improving the reception sensitivity.

[0082] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the filter 32 may be a variable filter.

[0083] This allows the pass characteristics of the filter 32 to be changed, thereby further improving the reception sensitivity.

[0084] Also, for example, in the high-frequency circuit 1 according to this embodiment, the signal processing circuit 51 may be configured to process an LTE signal or a 5G NR signal, and the signal processing circuit 52 may be configured to process a wake-up signal.

[0085] This allows LTE signals or 5G NR signals to be processed by a high-power signal processing circuit 51, and LPWUS to be processed by a low-power signal processing circuit 52, thereby reducing the power consumption of the high-frequency circuit 1.

[0086] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the signal processing circuit 51 may include a quadrature demodulator 512 and a local oscillator LO2.

[0087] This allows the quadrature demodulator 512 and local oscillator LO2 to process LTE signals or 5G NR signals.

[0088] Furthermore, for example, in the high-frequency circuit 1 according to this embodiment, the signal processing circuit 52 may include an envelope detector 521 .

[0089] This allows the envelope detector 521 to process LPWUS at low power.

[0090] For example, the high-frequency circuit 1 according to this embodiment may further include a power amplifier 10 connected to the signal processing circuit 51, and a switch circuit 42 including a common terminal 420 connected to the antenna connection terminal 101, a selection terminal 421 connected to the power amplifier 10, and a selection terminal 422 connected to the filter 31.

[0091] This allows the high frequency circuit 1 to handle not only reception but also transmission of high frequency signals.

[0092] Also, for example, in the high-frequency circuit 1 according to this embodiment, in a first mode in which an LTE signal or a 5G NR signal is processed using the signal processing circuit 51, the switch circuit 41 may connect the common terminal 410 to the selection terminal 411, and the signal processing circuit 51 may be set to an on state; in a second mode in which a wake-up signal is processed using the signal processing circuit 52, the switch circuit 41 may connect the common terminal 410 to the selection terminal 412, the signal processing circuit 51 may be set to an off state or a sleep state, and the signal processing circuit 52 may be set to an on state.

[0093] This allows the wake-up signal to be processed in the second mode after the high-power-consumption signal processing circuit 51 is set to the off state or sleep state, thereby reducing the power consumption of the high-frequency circuit 1.

[0094] (Embodiment 2) Next, embodiment 2 will be described. This embodiment differs from embodiment 1 above mainly in that the high-frequency circuit includes two low-noise amplifiers. The following describes this embodiment with reference to the drawings, focusing on the differences from embodiment 1 above.

[0095] The communication device 4A according to this embodiment is similar to the communication device 4 except that it includes a high-frequency circuit 1A instead of the high-frequency circuit 1, and therefore a description of its circuit configuration will be omitted.

[0096] [2.1. Circuit Configuration of High-Frequency Circuit 1A] The configuration of the high-frequency circuit 1A according to this embodiment will be described with reference to Fig. 6. Fig. 6 is a configuration diagram of a communication device 4A according to this embodiment.

[0097] 6 is an exemplary configuration, and the high-frequency circuit 1A can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1A provided below should not be construed as limiting.

[0098] The high-frequency circuit 1A includes a power amplifier 10, low-noise amplifiers 21 and 22, filters 31 and 32, switch circuits 41 and 42, signal processing circuits 51 and 52, an antenna connection terminal 101, an input terminal 110, and output terminals 121 and 122.

[0099] The low-noise amplifier 21 is an example of a first low-noise amplifier, and is connected between the switch circuit 41 and the filter 32. Specifically, the input terminal of the low-noise amplifier 21 is connected to the selection terminal 411 of the switch circuit 41, and the output terminal of the low-noise amplifier 21 is connected to the signal processing circuit 51 via the filter 32.

[0100] The low-noise amplifier 22 is an example of a second low-noise amplifier, and is connected between the switch circuit 41 and the signal processing circuit 52. Specifically, the input terminal of the low-noise amplifier 22 is connected to the selection terminal 412 of the switch circuit 41, and the output terminal of the low-noise amplifier 22 is connected to the signal processing circuit 52.

[0101] The low-noise amplifiers 21 and 22 may be configured with FETs and may be manufactured using semiconductor materials. Examples of the semiconductor materials that may be used include silicon single crystal (Si), gallium nitride (GaN), and silicon carbide (SiC). The amplifying transistors of the low-noise amplifiers 21 and 22 are not limited to FETs. For example, some or all of the low-noise amplifiers 21 and 22 may be configured with bipolar transistors.

[0102] [2.2. Summary] As described above, the high-frequency circuit 1A according to the present embodiment may further include the low-noise amplifier 21 connected between the selection terminal 411 and the signal processing circuit 51, and the low-noise amplifier 22 connected between the selection terminal 412 and the signal processing circuit 52.

[0103] According to this, the signal processing circuits 51 and 52 are connected to the low noise amplifiers 21 and 22, respectively. Therefore, it is possible to use the low noise amplifiers 21 and 22 that are suitable for amplifying the data signal processed by the signal processing circuit 51 and the LPWUS processed by the signal processing circuit 52, respectively, and it is possible to reduce the noise figure (NF).

[0104] Furthermore, for example, the high-frequency circuit 1A according to this embodiment may further include a filter 32 connected between the low-noise amplifier 21 and the signal processing circuit 51.

[0105] This allows the data signal to be filtered by the filter 32 in addition to the filter 31, thereby improving the reception sensitivity.

[0106] Furthermore, for example, in the high-frequency circuit 1A according to this embodiment, the filter 32 may be a variable filter.

[0107] This allows the pass characteristics of the filter 32 to be changed, thereby further improving the reception sensitivity.

[0108] (Embodiment 3) Next, embodiment 3 will be described. In this embodiment, the main difference is that two reception paths for LTE signals or 5G NR signals are included in the communication device. Hereinafter, this embodiment will be described with reference to the drawings, focusing on the differences from embodiment 1 above.

[0109] [3.1. Circuit Configuration of Communication Device 4B] The circuit configuration of the communication device 4B will be described with reference to Fig. 7. Fig. 7 is a circuit configuration diagram of the communication device 4B according to this embodiment.

[0110] 7 is an exemplary configuration, and communication device 4B may be implemented using any of a wide variety of circuit implementations and circuit technologies, and therefore the description of communication device 4B provided below should not be construed as limiting.

[0111] The communication device 4B includes a high-frequency circuit 1B, antennas 2a and 2b, and a BBIC (Baseband Integrated Circuit) 3.

[0112] The antenna 2b is connected to the high-frequency circuit 1B. The antenna 2b can receive a high-frequency signal from the high-frequency circuit 1B and transmit it to the outside of the communication device 4B. Furthermore, the antenna 2b can receive a high-frequency signal from the outside of the communication device 4B and supply it to the high-frequency circuit 1B. The antenna 2b does not have to be included in the communication device 4B. Furthermore, the communication device 4B may include one or more antennas in addition to the antenna 2b.

[0113] [3.2. Circuit Configuration of High-Frequency Circuit 1B] Next, the circuit configuration of the high-frequency circuit 1B according to this embodiment will be described with reference to FIG. 7. Note that FIG. 7 is an exemplary circuit configuration, and the high-frequency circuit 1B can be implemented using any of a wide variety of circuit implementations and circuit technologies. Therefore, the description of the high-frequency circuit 1B provided below should not be interpreted as limiting.

[0114] The high-frequency circuit 1B includes a power amplifier 10, low-noise amplifiers 20 and 23, filters 31, 32, 33 and 34, switch circuits 41, 42 and 43, signal processing circuits 51, 52 and 53, antenna connection terminals 101 and 102, an input terminal 110, and output terminals 121, 122 and 123.

[0115] The antenna connection terminal 102 is an example of a second antenna connection terminal, an external connection terminal of the high-frequency circuit 1B, and a terminal for receiving a high-frequency signal from the antenna 2b. The antenna connection terminal 102 is connected to the antenna 2b outside the high-frequency circuit 1B, and is connected to the filter 33 inside the high-frequency circuit 1B.

[0116] The output terminal 123 is an external connection terminal of the high-frequency circuit 1B, and is a terminal for supplying a baseband signal to the BBIC 3. The output terminal 123 is connected to the BBIC 3 outside the high-frequency circuit 1B, and is connected to the signal processing circuit 53 inside the high-frequency circuit 1B.

[0117] The low-noise amplifier 23 is connected between the filter 33 and the switch circuit 43. Specifically, the input terminal of the low-noise amplifier 23 is connected to the filter 33, and the output terminal of the low-noise amplifier 23 is connected to a common terminal 430 of the switch circuit 43.

[0118] The low-noise amplifier 23 may be configured with a FET and may be manufactured using a semiconductor material. Examples of the semiconductor material that may be used include silicon single crystal (Si), gallium nitride (GaN), and silicon carbide (SiC). The amplifying transistor of the low-noise amplifier 23 is not limited to a FET. For example, the low-noise amplifier 23 may be configured with a bipolar transistor.

[0119] The filter 33 is an example of a third filter, and is connected between the antenna connection terminal 102 and the low-noise amplifier 23. Specifically, one end of the filter 33 is connected to the antenna connection terminal 102, and the other end of the filter 33 is connected to the input terminal of the low-noise amplifier 23.

[0120] The filter 34 is connected between the switch circuit 43 and the signal processing circuit 53. Specifically, one end of the filter 34 is connected to the selection terminal 431 of the switch circuit 43, and the other end of the filter 34 is connected to the signal processing circuit 53. The filter 34 is an optional component and does not need to be included in the high-frequency circuit 1B. The filter 34 may also be a variable filter whose pass characteristics are variable.

[0121] The filters 33 and / or 34 may be any of a SAW filter, a BAW filter, an LC filter, and a dielectric filter, or any combination thereof.

[0122] The switch circuit 43 is an example of a third switch circuit and includes a common terminal 430 and selection terminals 431 and 432. The common terminal 430 is an example of a third common terminal and is connected to the filter 33 via the low-noise amplifier 23. The selection terminal 431 is an example of a fifth selection terminal and is connected to the signal processing circuit 53 via the filter 34. The selection terminal 432 is an example of a sixth selection terminal and is connected to the signal processing circuit 52. In this connection configuration, the switch circuit 43 can selectively connect the common terminal 430 to the selection terminals 431 and 432 based on, for example, control signals from the signal processing circuits 52 and / or 53. The switch circuit 43 is, for example, an SPDT type switch circuit.

[0123] The signal processing circuit 53 is an example of a third signal processing circuit, and is connected between the filter 34 and the output terminal 123. The signal processing circuit 53 is configured to process a data signal (e.g., an LTE signal or a 5G NR signal). Specifically, the signal processing circuit 53 can down-convert a high-frequency reception signal to a baseband reception signal and supply the baseband reception signal to the BBIC 3. The circuit configuration of the signal processing circuit 53 is the same as that of the signal processing circuit 51 in FIG. 2 with the transmission signal processing circuit 51T removed, and therefore will not be illustrated or described again.

[0124] The signal processing circuit 53 may be integrated with the signal processing circuit 51 .

[0125] [3.3. Summary] As described above, the high-frequency circuit 1B according to the present embodiment may further include the antenna connection terminal 102, the filter 33 connected to the antenna connection terminal 102, the signal processing circuit 53 that consumes more power than the signal processing circuit 52, and the switch circuit 43 that includes the common terminal 430 connected to the filter 33, the selection terminal 431 connected to the signal processing circuit 53, and the selection terminal 432 connected to the signal processing circuit 52.

[0126] This allows the signal processing circuit 52 to be shared between the receiving path connected to the antenna connection terminal 101 and the receiving path connected to the antenna connection terminal 102, which contributes to the miniaturization of the communication device 4B.

[0127] (Other Embodiments) While the high-frequency circuit according to the present invention has been described above based on the embodiments, the high-frequency circuit according to the present invention is not limited to the above embodiments. The present invention also includes other embodiments realized by combining any of the components in the above embodiments, modifications obtained by applying various modifications to the above embodiments that would occur to those skilled in the art without departing from the spirit of the present invention, and various devices incorporating the above-mentioned high-frequency circuit.

[0128] For example, in the circuit configuration of the high-frequency circuit according to each of the above embodiments, other circuit elements, wiring, etc. may be inserted between the paths connecting the circuit elements and signal paths disclosed in the drawings. For example, an impedance matching circuit may be connected between the filter 31 and the switch circuit 42 and / or between the filter 31 and the low-noise amplifier 20. Furthermore, for example, a coupler may be connected between the switch circuit 42 and the antenna connection terminal 101.

[0129] The high-frequency circuits according to the above embodiments may not include a transmission path. In this case, the high-frequency circuits according to the above embodiments may not include the power amplifier 10, the switch circuit 42, and the input terminal 110, and the signal processing circuit 51 may not include the transmission signal processing circuit 51T.

[0130] The features of the high-frequency circuits described based on the above embodiments will be described below.

[0131] <1> A radio frequency circuit comprising: a first antenna connection terminal; a first filter connected to the first antenna connection terminal; a first signal processing circuit; a second signal processing circuit that consumes less power than the first signal processing circuit; and a first switch circuit including a first common terminal connected to the first filter, a first selection terminal connected to the first signal processing circuit, and a second selection terminal connected to the second signal processing circuit.

[0132] <2> The high-frequency circuit according to <1>, further comprising a low-noise amplifier connected between the first filter and the first common terminal.

[0133] <3> The high-frequency circuit according to <2>, further comprising a second filter connected between the first selection terminal and the first signal processing circuit.

[0134] <4> The high-frequency circuit according to <3>, wherein the second filter is a variable filter.

[0135] <5> The high-frequency circuit according to <1>, further comprising: a first low-noise amplifier connected between the first selection terminal and the first signal processing circuit; and a second low-noise amplifier connected between the second selection terminal and the second signal processing circuit.

[0136] <6> The high-frequency circuit according to <5>, further comprising a second filter connected between the first low-noise amplifier and the first signal processing circuit.

[0137] <7> The high-frequency circuit according to <6>, wherein the second filter is a variable filter.

[0138] <8> The radio frequency circuit according to any one of <1> to <7>, wherein the first signal processing circuit is configured to process an LTE (Long Term Evolution) signal or a 5GNR (5th Generation New Radio) signal, and the second signal processing circuit is configured to process a wake-up signal.

[0139] <9> The high-frequency circuit according to any one of <1> to <8>, wherein the first signal processing circuit includes a quadrature demodulator and a local oscillator.

[0140] <10> The high-frequency circuit according to any one of <1> to <9>, wherein the second signal processing circuit includes an envelope detector.

[0141] <11> The radio frequency circuit according to any one of <1> to <10>, further comprising: a power amplifier connected to the first signal processing circuit; and a second switch circuit including a second common terminal connected to the first antenna connection terminal, a third selection terminal connected to the power amplifier, and a fourth selection terminal connected to the first filter.

[0142] <12> The radio frequency circuit according to any one of <1> to <11>, wherein in a first mode in which an LTE signal or a 5G NR signal is processed using the first signal processing circuit, the first switch circuit connects the first common terminal to the first selection terminal, and the first signal processing circuit is set to an on state; and in a second mode in which a wake-up signal is processed using the second signal processing circuit, the first switch circuit connects the first common terminal to the second selection terminal, and the first signal processing circuit is set to an off state or a sleep state, and the second signal processing circuit is set to an on state.

[0143] <13> The radio frequency circuit according to any one of <1> to <12>, further comprising: a second antenna connection terminal; a third filter connected to the second antenna connection terminal; a third signal processing circuit having higher power consumption than the second signal processing circuit; and a third switch circuit including a third common terminal connected to the third filter, a fifth selection terminal connected to the third signal processing circuit, and a sixth selection terminal connected to the second signal processing circuit.

[0144] The present invention can be widely used as a high-frequency circuit disposed in the front end of communication devices such as mobile phones.

[0145] REFERENCE SIGNS LIST 1, 1A, 1B High frequency circuit 2a, 2b Antenna 3 BBIC 4, 4A, 4B Communication device 10 Power amplifier 20, 21, 22, 23 Low noise amplifier 31, 32, 33, 34 Filter 41, 42, 43 Switch circuit 51, 52, 53 Signal processing circuit 51R Receiving signal processing circuit 51T Transmitting signal processing circuit 101, 102 Antenna connection terminal 110 Input terminal 121, 122, 123 Output terminal 511 Quadrature modulator 512 Quadrature demodulator 521 Envelope detector A1, A2, A3, A4, A5 Amplifier AD1, AD2, AD3 Analog-to-digital converter C1 Capacitor D1 Diode DA1, DA2 Digital-to-analog converter F1, F2, F3, F4, F5 Low-pass filter LO1, LO2 Local oscillator M1, M2, M3, M4 Mixer R1 Resistor

Claims

1. A radio frequency circuit comprising: a first antenna connection terminal; a first filter connected to the first antenna connection terminal; a first signal processing circuit; a second signal processing circuit that consumes less power than the first signal processing circuit; and a first switch circuit including a first common terminal connected to the first filter, a first selection terminal connected to the first signal processing circuit, and a second selection terminal connected to the second signal processing circuit.

2. The high-frequency circuit according to claim 1, further comprising a low-noise amplifier connected between said first filter and said first common terminal.

3. The high frequency circuit according to claim 2, further comprising a second filter connected between the first selection terminal and the first signal processing circuit.

4. The high-frequency circuit according to claim 3, wherein the second filter is a variable filter.

5. The high-frequency circuit according to claim 1, further comprising: a first low-noise amplifier connected between the first selection terminal and the first signal processing circuit; and a second low-noise amplifier connected between the second selection terminal and the second signal processing circuit.

6. The high-frequency circuit according to claim 5, further comprising a second filter connected between the first low-noise amplifier and the first signal processing circuit.

7. The high-frequency circuit according to claim 6, wherein the second filter is a variable filter.

8. The radio frequency circuit according to any one of claims 1 to 7, wherein the first signal processing circuit is configured to process an LTE (Long Term Evolution) signal or a 5GNR (5th Generation New Radio) signal, and the second signal processing circuit is configured to process a wake-up signal.

9. The high frequency circuit according to any one of claims 1 to 8, wherein the first signal processing circuit includes a quadrature demodulator and a local oscillator.

10. The high frequency circuit according to any one of claims 1 to 9, wherein the second signal processing circuit includes an envelope detector.

11. The radio frequency circuit according to any one of claims 1 to 10, further comprising: a power amplifier connected to the first signal processing circuit; and a second switch circuit including a second common terminal connected to the first antenna connection terminal, a third selection terminal connected to the power amplifier, and a fourth selection terminal connected to the first filter.

12. The radio frequency circuit according to any one of claims 1 to 11, wherein in a first mode in which an LTE signal or a 5G NR signal is processed using the first signal processing circuit, the first switch circuit connects the first common terminal to the first selection terminal, and the first signal processing circuit is set to an on state; and in a second mode in which a wake-up signal is processed using the second signal processing circuit, the first switch circuit connects the first common terminal to the second selection terminal, the first signal processing circuit is set to an off state or a sleep state, and the second signal processing circuit is set to an on state.

13. The radio frequency circuit according to any one of claims 1 to 12, further comprising: a second antenna connection terminal; a third filter connected to the second antenna connection terminal; a third signal processing circuit consuming more power than the second signal processing circuit; and a third switch circuit including a third common terminal connected to the third filter, a fifth selection terminal connected to the third signal processing circuit, and a sixth selection terminal connected to the second signal processing circuit.

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