Electronic component

Abstract

An electronic component 1 comprises: an active element 10 and a passive element 20 which are disposed so as to correspond to a plurality of channels and which constitute a voltage regulator; a load 30 which is supplied with DC voltage that has been adjusted by a voltage regulator and which includes a semiconductor element; and a wiring board 40 which is electrically connected to the active element 10, the passive element 20, and the load 30. The active element 10 of the voltage regulator includes a switching element. The passive element 20 of the voltage regulator includes a plurality of capacitor elements 80. The plurality of capacitor elements 80 that are disposed in the channels constitute a capacitor array 50 in which the capacitor elements 80 are arranged so as to each have a vertical orientation with respect to the mounting surface of the wiring board 40 with external electrodes (81, 82) disposed opposite from each other. The capacitor array 50 has a plurality of through-conductors 90 that penetrate the capacitor array 50 so as to have a vertical orientation with respect to the mounting surface of the wiring board 40. When viewed from the mounting surface of the wiring board 40, at least a portion of the capacitor array 50 is disposed so as to coincide with the load 30. In a plan view of the capacitor array 50, a through-conductor 90 is disposed so as to coincide with the centroid of the triangle that is formed by three capacitor elements 80 of the plurality of capacitor elements 80 which are in close proximity to the through-conductor 90.

Description

Electronic Components

[0001] The present invention relates to electronic components.

[0002] Semiconductor devices having voltage control devices are used in electronic devices such as mobile phones and smartphones. In recent years, electronic devices have become smaller and thinner, which has led to a corresponding demand for smaller semiconductor devices. Furthermore, multi-channel DC-DC converter ICs or PMICs equipped with low power consumption functions are used in the power supply circuits of highly functional mobile terminals such as smartphones. These ICs are becoming increasingly capable of high-speed operation and low power consumption due to low voltages and large currents.

[0003] There is a demand for higher capacitance density in voltage smoothing capacitors and capacitors for decoupling purposes, such as noise suppression and high-frequency short-circuiting for each channel. Furthermore, as the connection distance from the capacitor to the load increases, losses due to equivalent series inductance (ESL) and equivalent series resistance (ESR) increase due to the inductive and resistive components of the wiring. Therefore, it is desirable to place capacitors close to the load. For these reasons, there is a need for capacitor-embedded boards that can be placed near the load, with vertically embedded capacitors to increase capacitance density and numerous current paths (through holes) to supply large currents to the load and reduce ESL.

[0004] To meet these demands, a structure in which a capacitor element is embedded in a substrate and a through hole is formed in the vicinity thereof is an effective means for solving these problems.

[0005] Patent Document 1 describes that chip capacitors are embedded in a core substrate, and that through holes are formed around the periphery of an area where a plurality of chip capacitors are arranged.

[0006] Japanese Patent Application Laid-Open No. 2002-171072

[0007] In Patent Document 1, through holes connected to a power supply circuit or a ground circuit are arranged around the periphery of an area where multiple chip capacitors are arranged. However, with the arrangement described in Patent Document 1, the distance between the capacitor and the power supply line is still far, and the wiring length is long, which affects the impedance due to the wiring.

[0008] Therefore, there was a demand for a configuration in which capacitor elements are arranged vertically within a substrate, and penetrating conductors such as through holes are arranged adjacent to the capacitor elements, thereby increasing the mounting density of the capacitor elements from the perspective of increasing the capacitance of the capacitor, shortening the distance between the penetrating conductors and the capacitor elements, and increasing the density of the number of penetrating conductors.

[0009] The present invention has been made to solve the above problems, and aims to provide an electronic component in which a capacitor element and a through conductor are adjacent to each other, thereby increasing the density of both the capacitor and the through conductor.

[0010] The electronic component of the present invention is an electronic component comprising: active and passive elements that are arranged to correspond to a plurality of channels and that constitute a voltage regulator; a load that includes a semiconductor element and is supplied with a DC voltage regulated by the voltage regulator; and a wiring board that is electrically connected to the active elements, the passive elements, and the load; wherein the active elements that constitute the voltage regulator include switching elements, and the passive elements that constitute the voltage regulator include a plurality of capacitor elements, and the plurality of capacitor elements arranged in the channels constitute a capacitor array in which the capacitor elements are arranged with their external electrodes facing each other vertically with respect to the mounting surface of the wiring board, and the capacitor array has a plurality of through conductors that pass through the capacitor array vertically with respect to the mounting surface of the wiring board, and at least a portion of the capacitor array is arranged in a position that overlaps the load when viewed from the mounting surface of the wiring board, and the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements of the plurality of capacitor elements in a planar view of the capacitor array.

[0011] According to the present invention, it is possible to provide an electronic component having a configuration in which the capacitor element and the through conductor are adjacent to each other, and the density of both the capacitor and the through conductor is high.

[0012] FIG. 1 is a cross-sectional view schematically illustrating an example of an electronic component according to an embodiment of the present invention. FIG. 2 is a plan view of the electronic component illustrated in FIG. 1 as viewed from one mounting surface of a wiring board. FIG. 3 is a plan view illustrating an arrangement of capacitor elements and through conductors constituting a capacitor array. FIG. 4 is a circuit configuration diagram of the electronic component illustrated in FIGS. 1 and 2. FIG. 5 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 6 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 7 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 8 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 9 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 10 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 11 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 12 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 13 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 14 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. FIG. 15 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 16 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 17 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 18 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 19 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 20 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 21 is a process diagram illustrating an example of a method for manufacturing a wiring board including a capacitor array. Fig. 22 is a plan view schematically showing another example of a capacitor array.

[0013] The electronic component of the present invention will be described below. However, the present invention is not limited to the following configuration, and can be appropriately modified and applied within the scope of the present invention. Note that a combination of two or more of the individual desirable configurations described below also constitutes the present invention.

[0014] Fig. 1 is a cross-sectional view schematically showing an example of an electronic component according to an embodiment of the present invention. Fig. 2 is a plan view of the electronic component shown in Fig. 1 as seen from one mounting surface of a wiring board. Fig. 3 is a plan view showing the arrangement of capacitor elements and through conductors that constitute a capacitor array. Fig. 4 is a circuit configuration diagram of the electronic component shown in Figs. 1 and 2. Fig. 2 shows an example in which the number of channels is two, but the number of channels may be three or more.

[0015] The electronic component 1 shown in FIGS. 1 and 2 includes an active element 10 and a passive element 20 that constitute a voltage regulator, a load 30 to which a DC voltage regulated by the voltage regulator is supplied, and a wiring board 40 that is electrically connected to the active element 10, the passive element 20, and the load 30. The load 30 includes a semiconductor element. Examples of the load 30 include semiconductor integrated circuits (ICs) such as logic circuits or memory circuits. In the example shown in FIG. 1, the load 30 is disposed on one mounting surface of the wiring board 40.

[0016] The active elements 10 and the passive elements 20 are arranged for each channel. The first channel CH1 constitutes a single-phase power supply with one power supply circuit, and the second channel CH2 constitutes a multi-phase power supply with multiple power supply circuits connected in parallel. In the second channel CH2, an example of a multi-phase power supply with three power supply circuits connected in parallel is shown, but the number of power supply circuits connected in parallel is not particularly limited.

[0017] Both the first channel CH1 and the second channel CH2 may constitute a single-phase power supply. Alternatively, both the first channel CH1 and the second channel CH2 may constitute a multi-phase power supply. In this case, the number of power supply circuits connected in parallel may be the same or different.

[0018] The active element 10 constituting the voltage regulator includes switching elements SW1, SW2, SW3, and SW4. Of these, switching element SW1 is arranged in a first channel CH1, and switching elements SW2, SW3, and SW4 are arranged in a second channel CH2.

[0019] In the example shown in Figures 1 and 2, the switching element SW1 arranged in the first channel CH1 and the switching elements SW2, SW3, and SW4 arranged in the second channel CH2 are arranged on one mounting surface of the wiring board 40.

[0020] A circuit layer 45 including lands for mounting components such as switching elements SW1, SW2, SW3, and SW4, inductors L1, L2, L3, and L4, and load 30, as well as wiring for connecting these components, is formed on one mounting surface of wiring board 40. Wiring board 40 is electrically connected to active element 10, passive element 20, and load 30 via circuit layer 45.

[0021] Although not shown, in addition to the active element 10, the passive element 20, and the load 30, electronic devices such as a choke inductor, a diode element for surge protection, and a resistor element for voltage division may be arranged on the mounting surface of the wiring board 40.

[0022] The passive element 20 constituting the voltage regulator includes output capacitors C1 and C2, of which the output capacitor C1 is arranged in the first channel CH1 and the output capacitor C2 is arranged in the second channel CH2.

[0023] The passive element 20 constituting the voltage regulator further includes inductors L1, L2, L3, and L4, of which the inductor L1 is arranged in the first channel CH1, and the inductors L2, L3, and L4 are arranged in the second channel CH2.

[0024] It should be noted that the passive element 20 constituting the voltage regulator is only required to include at least the output capacitors C1 and C2, and does not necessarily have to include the inductors L1, L2, L3, and L4.

[0025] The output capacitors C1 and C2 are examples of capacitors for stably driving the power supply and are output capacitors for smoothing the output voltage. As shown in Figure 2, the output capacitor C1 arranged in the first channel CH1 and the output capacitor C2 arranged in the second channel CH2 are each configured as a capacitor array 50 in which capacitor elements 80 housed on a wiring board are arranged.

[0026] When viewed from the mounting surface of the wiring board, the capacitor array 50 is disposed at a position where at least a portion of the capacitor array 50 overlaps with the load. In Fig. 2, the position of the load is indicated by a dotted rectangle L, and the capacitor array 50 overlaps with this rectangle L.

[0027] A multilayer ceramic capacitor (MLCC) can be used as the capacitor element 80. The multilayer ceramic capacitor is a chip component having a rectangular parallelepiped elongated shape, and is arranged so that its longitudinal direction faces vertically relative to the mounting surface of the wiring board. The multilayer ceramic capacitor has a first external electrode and a second external electrode that face each other in the longitudinal direction.

[0028] In FIG. 2, the size of the first capacitor array 51, which is the capacitor array that constitutes the output capacitor C1, may be the same as or different from the size of the second capacitor array 52, which is the capacitor array that constitutes the output capacitor C2.

[0029] A first connection terminal 61 is connected to one external electrode (first external electrode 81 of the MLCC) of each capacitor element 80 constituting the capacitor array 50, and a second connection terminal 62 is connected to the other external electrode (second external electrode 82 of the MLCC) of the capacitor element 80. The capacitor array 50 also has a plurality of through conductors 90 that pass through the capacitor array 50 in a vertical direction relative to the mounting surface of the wiring board 40. A third connection terminal 63 is connected to one end of each through conductor 90, and a fourth connection terminal 64 is connected to the other end of each through conductor 90.

[0030] Examples of the through conductors 90 include plated through holes or metal pins. The plated through holes are formed on at least the inner wall surfaces of through holes that penetrate from the top surface to the bottom surface in the thickness direction of the capacitor array. The inner wall surfaces of the through holes are metallized with a low-resistance metal such as Cu, Au, or Ag. For ease of processing, plated through holes metallized by, for example, electroless Cu plating or electrolytic Cu plating can be used. Note that the plated through holes are not limited to those in which only the inner wall surfaces of the through holes are metallized, but may also be filled with metal or a composite material of metal and resin.

[0031] The metal pins may be Cu pins. When the metal pins are Cu pins, the electronic component can handle a larger current. When the metal pins are Cu pins, the heat dissipation effect is also greater.

[0032] The through conductor may be connected to ground, or may be a through conductor for an I / O line.

[0033] In Figure 1, only one representative set of through conductors 90 and capacitor elements 80 that form the first capacitor array 51 that constitutes the output capacitor C1 is shown on the left side, and only one representative set of through conductors 90 and capacitor elements 80 that form the second capacitor array 52 that constitutes the output capacitor C2 is shown on the right side, but because a capacitor array is made up of multiple capacitor elements and multiple through conductors, there are many more capacitor elements and through conductors in the actual cross section of the electronic component.

[0034] FIG. 2 shows the configuration of the capacitor array, with a plurality of capacitor elements 80 constituting a first capacitor array 51 shown on the left side and a plurality of capacitor elements 80 constituting a second capacitor array 52 shown on the right side.

[0035] In the electronic component of the present invention, the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements among the plurality of capacitor elements in a plan view of the capacitor array. This will be described with reference to FIG.

[0036] Fig. 3 shows an enlarged view of the area indicated by area A in Fig. 2. Each capacitor element 80 constituting the capacitor array 50 is housed in a cavity 70. The capacitor element 80 housed in the cavity 70 is an MLCC, and its first external electrode 81 is visible in the plan view. Fig. 3 shows a configuration in which one capacitor element is housed in one circular cavity.

[0037] In the electronic component of the present invention, in a plan view of the capacitor array, the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements among the plurality of capacitor elements. This will be explained. In FIG. 3 , three adjacent capacitor elements are designated as capacitor elements 80a, 80b, and 80c, and a triangle is drawn with the center (center of gravity) of each capacitor element as a vertex. The through conductor 90 overlaps the center of gravity G of the triangle. The center of gravity of the triangle and the center (center of gravity) of the through conductor may coincide, or a portion close to the periphery of the through conductor may overlap the center of gravity of the triangle. Furthermore, it is preferable that the triangle formed by the three adjacent capacitor elements is an equilateral triangle.

[0038] When the positional relationship between the capacitor element and the through conductor is as described above, the capacitor element and the through conductor are adjacent to each other, and the capacitors and the through conductors are densely arranged, so that the density of both the capacitors and the through conductors can be increased.

[0039] In the electronic component of the present invention, since the capacitors and through conductors are densely arranged, the through conductors are generally arranged so as to overlap the center of gravity of the triangle formed by three adjacent capacitor elements, but among the multiple through conductors, there may be through conductors that do not overlap the center of gravity of the triangle formed by three adjacent capacitor elements. It is preferable that the proportion of such through conductors is 5% or less in a plan view of the capacitor array.

[0040] By increasing the number of through conductors, the parasitic inductance in the capacitor array can be reduced, and the impedance on the high frequency side can be reduced. Furthermore, by arranging a large number of through conductors while increasing the capacitance density, it becomes possible to input large amounts of power. Furthermore, since the through conductors also function as heat transfer paths, providing a large number of through conductors can improve heat dissipation from electronic components. Furthermore, ESL can be reduced.

[0041] Furthermore, in the electronic component of the present invention, an arrangement in which the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements is repeated, and it is preferable that six through conductors are arranged around one capacitor element located other than the outer edge of the capacitor array.

[0042] 3, when focusing on capacitor element 80a, six through conductors 90a, 90b, 90c, 90d, 90e, and 90f are arranged around capacitor element 80a. When focusing on other capacitor elements (80b, 80c, etc.), six through conductors are also arranged around the capacitor element.

[0043] This arrangement can be said to be the closest arrangement in which the capacitor elements and the through conductors are arranged at equal intervals, and thus the density of the capacitor elements and the through conductors can be increased. Increasing the density of the capacitor elements increases the capacitance density, thereby lowering the impedance. Furthermore, surrounding one capacitor element with six through conductors prevents the generation of abnormal signals due to electrical inductive coupling between adjacent capacitor elements and reduces ESL. As a result, signal quality is improved, preventing malfunction of electronic components. Furthermore, the driving voltage can be lowered, enabling reduced power consumption.

[0044] Furthermore, it is preferable that the positions of the through conductors arranged opposite one capacitor element are equidistant from the capacitor element. In Fig. 3, the positional relationships of the through conductors 90a and 90d, 90b and 90e, and 90c and 90f are such that the through conductors are arranged opposite the capacitor element 80a. When the capacitor element and the through conductors are in such a positional relationship, the magnetic fields are canceled out, thereby reducing the loop impedance connecting the capacitor, load, and through conductor.

[0045] Furthermore, in the electronic component of the present invention, in a plan view of the capacitor array, the shortest distance P between adjacent capacitor elements is preferably shorter than the diagonal length W at the end face of the capacitor element. In Fig. 3, the shortest distance between adjacent capacitor elements is indicated by a double-headed arrow P, and the diagonal length at the end face of the capacitor element is indicated by a double-headed arrow W. It is preferable that the distance P is smaller than the diagonal length W.

[0046] Furthermore, the ratio of the diagonal length W at the end face of the capacitor element to the shortest distance P between adjacent capacitor elements is preferably (W / P)=0.5 or more, and more preferably (W / P)=less than 1.0.

[0047] If the distance P or the diagonal length W varies depending on the location where the lengths are measured, the following can be done. In a planar view of an area containing 10 or more capacitor elements, the distance between one capacitor element included in the area and the closest capacitor element is defined as P. The average value of the distances P for each capacitor element is then calculated and defined as the shortest distance P between adjacent capacitor elements. Furthermore, in a planar view of an area containing 10 or more capacitor elements, the average value of the diagonal lengths W at the end faces of each capacitor element included in the area is calculated and defined as the diagonal length W at the end faces of the capacitor elements. The distance P and diagonal length W calculated in this way can then be compared.

[0048] Furthermore, in the electronic component of the present invention, in a plan view of the capacitor array, the ratio of the center-to-center distance Q of adjacent capacitor elements to the shortest distance P between adjacent capacitor elements is preferably (Q / P) equal to or greater than 3 and is preferably equal to or less than 100. In Fig. 3, the center-to-center distance of adjacent capacitor elements is indicated by a double-headed arrow Q.

[0049] When determining the ratio Q / P, the two adjacent capacitor elements between which the shortest distance P of interest is measured are determined, and the ratio Q / P can be determined using the center-to-center distance Q between the two capacitor elements.

[0050] Furthermore, in the electronic component of the present invention, each capacitor element is housed in a circular cavity, and in a plan view of the capacitor array, the shortest distance N between adjacent cavities is preferably equal to or less than the diameter R of the cavity circle. In Fig. 3, the shortest distance between adjacent cavities is indicated by a double-headed arrow N, and the diameter of the cavity circle is indicated by a double-headed arrow R. It is preferable that the distance N is less than or equal to the diameter R.

[0051] Furthermore, it is preferable that the shortest distance N between adjacent cavities satisfies 0≦N≦R.

[0052] If the distance N or the diameter R varies depending on the location where the length is measured, the following can be done. In a plan view of an area containing 10 or more circular cavities that house capacitor elements, the distance between one cavity included in the area and the cavity located closest to it is defined as N. The average value of the distances N for each cavity is then calculated and defined as the shortest distance N between adjacent cavities. Furthermore, in a plan view of an area containing 10 or more circular cavities that house capacitor elements, the average value of the diameters R of the circles of the cavities included in the area is calculated and defined as the diameter R of the circles of the cavities. The distance N and diameter R calculated in this way can then be compared.

[0053] In the electronic component of the present invention, each capacitor element is housed in a circular cavity, and in a plan view of the capacitor array, the through conductor has a circular top view shape, and the diameter of the top view shape of the through conductor is preferably shorter than the diameter of the circle of the cavity. In Fig. 3, the diameter of the top view shape of the through conductor is indicated by a double-headed arrow S, and the diameter of the circle of the cavity is indicated by a double-headed arrow R. It is preferable that the diameter S is smaller than the diameter R.

[0054] The diameter of the circular cavity is usually just large enough to fit the capacitor element in. By making the diameter of the through conductor shorter than the diameter of the cavity, when the capacitor element is inserted into the cavity, it is possible to prevent the capacitor element from being inserted into the through hole that will become the through conductor by mistake.

[0055] In a planar view of an area containing 10 or more circular cavities and through conductors that house capacitor elements, the average diameter R of each cavity included in the area and the average diameter S of the through conductors are calculated, and the diameter R and the diameter S are compared.

[0056] Furthermore, the diameter of the through conductor in top view is preferably 150 μm or less. When the diameter of the through conductor in top view is in this range, the capacitor elements can be arranged at higher density.

[0057] Furthermore, in a plan view of the capacitor array, the area of ​​the through conductor is preferably smaller than the area of ​​the capacitor element adjacent to the through conductor. This configuration makes it easier to maximize the density of the capacitors and the through conductors while reducing the impedance. In a plan view of an area including 10 or more capacitor elements and through conductors, the average area of ​​each capacitor element and the average area of ​​the through conductors included in the area can be calculated, and the two areas can be compared.

[0058] 3 shows a configuration in which one capacitor element is accommodated in one circular cavity, but a plurality of capacitor elements may be accommodated in one cavity. A plurality of capacitor elements may be arranged in one large cavity, and a plurality of through conductors may be arranged in a predetermined arrangement relative to the capacitor elements.

[0059] An example of a method for manufacturing a wiring substrate including a capacitor array will be described below. Figures 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are process diagrams illustrating an example of a method for manufacturing a wiring substrate including a capacitor array.

[0060] Through the steps up to this point, a capacitor-embedded substrate that will become part of the wiring board is obtained. The capacitor-embedded substrate is a substrate that has a capacitor element and a through conductor inside.

[0061] A core substrate 100 is prepared as shown in Fig. 5, and through holes that become cavities 70 are formed in the core substrate as shown in Fig. 6. The through holes are arranged so that a large number of cavities are lined up in a predetermined array in plan view, as shown in Fig. 3.

[0062] 7, core substrate 100 is attached to adhesive sheet 110, and capacitor element 80 is placed in cavity 70. Capacitor element 80 is placed vertically in cavity 70. A thermally foamed sheet can be used as adhesive sheet 110.

[0063] As shown in FIG. 8 , the cavity 70 is sealed with a sealant 120, and the upper surface (first surface 101) of the core substrate 100 is also covered with the sealant 120. The sealant 120 can be provided in the cavity 70 and on the first surface 101 of the core substrate 100 by vacuum lamination. The sealant 120 is then heated to a temperature of, for example, 180°C. The sealant 120 is then heated to a temperature above the peeling temperature (for example, 200°C) of the adhesive sheet 110, which is a thermal foaming sheet, to lose its adhesive force, and the adhesive sheet 110 is then peeled off. Next, the lower surface (second surface 102) of the core substrate 100 is also covered with the sealant 120. The sealant 120 can be provided on the second surface 102 of the core substrate 100 by vacuum lamination. The sealant 120 is then heated to a temperature of, for example, 180°C.

[0064] 9, a metal layer 130 is provided on the sealing material 120 on each of the first surface 101 side and the second surface 102 side of the core substrate 100. The metal layer can be formed by copper foil attachment, plating, or the like.

[0065] As shown in Fig. 10, through holes 140 for forming the through conductors are formed. The through holes 140 are positioned so that the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements in a plan view. Furthermore, it is preferable that the through holes 140 are positioned so that six through conductors are arranged around one capacitor element, as shown in Fig. 3.

[0066] 11 , a through-hole plating layer 150 is formed in the through hole 140. The through-hole plating layer becomes the through conductor 90. At this time, a plating layer is also formed on the surface of the metal layer 130 on the sealing material 120, and is connected to the through-hole plating layer 150.

[0067] As shown in FIG. 12, the through-hole 140 having the through-hole plating layer 150 formed on the inner wall is filled with a filling resin 160.

[0068] 13, via holes 170 are formed by a laser in the sealing material 120 on each of the first surface 101 side and the second surface 102 side of the core substrate 100. The via holes 170 are formed at positions where the first external electrode 81 and the second external electrode 82 of the capacitor element 80 are exposed from the via holes 170. For example, a CO ２ A laser can be used. It is preferable to remove the metal layer 130 and the plating layer at the position where the via hole 170 is to be formed by etching before drilling with the laser.

[0069] As shown in Fig. 14, a conductor layer 180 is provided on the via hole 170 and the plating layer on the first surface 101 side and the second surface 102 side of the core substrate 100. Furthermore, as shown in Fig. 15, the conductor layer is etched to provide a first connection terminal 61 electrically connected to the first external electrode 81 of the capacitor element 80 and a second connection terminal 62 electrically connected to the second external electrode 82 of the capacitor element 80. Furthermore, etching is performed to form a third connection terminal 63 and a fourth connection terminal 64 connected to the through-hole plating layer 150. The conductor layer 180 can be formed by a method such as printing a conductive paste or metal plating.

[0070] Furthermore, after the formation of the first connection terminal, the second connection terminal, the third connection terminal, and the fourth connection terminal, another conductor wiring and an insulating layer may be laminated to provide a build-up layer (rewiring layer). The build-up layer may be formed, for example, by plating (e.g., a semi-additive process). Through the above steps, a capacitor element-embedded substrate 200 including a capacitor array, which will become part of the wiring substrate, is obtained.

[0071] 16, 17, 18, 19, 20, and 21 are process diagrams illustrating an example of a method for manufacturing a wiring board including a capacitor array. A wiring board including a capacitor element built-in substrate including a capacitor array is obtained through the following process.

[0072] As shown in Figure 16, a core substrate 300 having a cavity 340 is prepared, and a capacitor element built-in substrate 200 processed to a desired size is fixed on an adhesive sheet 310, thereby placing the capacitor element built-in substrate 200 in the cavity 340.

[0073] As shown in FIG. 17, the cavity 340 is sealed with a sealing material 320 from the first connection terminal 61 side of the capacitor-embedded substrate 200 , and the surface of the capacitor-embedded substrate 200 on the first connection terminal 61 side is covered with the sealing material 320 .

[0074] As shown in FIG. 18, the adhesive sheet 310 is peeled off from the capacitor-embedded substrate 200 .

[0075] 19 , resin sealing is performed using the sealing material 320 from the second connection terminal 62 side of the capacitor element built-in substrate 200, and the surface of the capacitor element built-in substrate 200 on the second connection terminal 62 side is covered with the sealing material 320. In this way, the capacitor element built-in substrate 200 is built into the core substrate 300.

[0076] As shown in FIG. 20, via holes 370 are formed in the sealing material 320 to expose the first connection terminal 61, the second connection terminal 62, the third connection terminal 63 and the fourth connection terminal 64.

[0077] 21 , a plating process is performed to provide a conductor layer inside the via hole 370 and on the sealing material, and the conductor layer is etched to provide extraction electrodes 391, 392, 393, and 394 that extract the first connection terminal 61, the second connection terminal 62, the third connection terminal 63, and the fourth connection terminal 64 to the outside. The conductor layers can be formed by methods such as printing a conductive paste or metal plating. By performing the steps up to this point, the wiring board 40 is manufactured.

[0078] Then, components such as active elements including switching elements and loads including semiconductor elements are placed on the wiring board so that at least a portion of the capacitor array overlaps with the load when viewed from the mounting surface of the wiring board. Through these steps, the electronic component of the present invention is obtained.

[0079] 3 has been described as an example of an embodiment in which the triangle formed by three adjacent capacitor elements is an equilateral triangle, but the arrangement of the capacitor elements in the electronic component of the present invention is not limited to an equilateral triangle. Fig. 22 is a plan view schematically showing another example of a capacitor array. In Fig. 22, three adjacent capacitor elements are capacitor elements 80a, 80b, and 80c, and a triangle T is formed with the centers (centers of gravity) of the respective capacitor elements as vertices. Ａ Draw the triangle T Ａ The through conductor 90 overlaps the center of gravity G of the capacitor elements 80a, 80b, and 80c. Ａ is not an equilateral triangle. Furthermore, a triangle T Ｂ Draw the triangle T B The through conductor 90 is arranged to overlap the center of gravity G of the triangle T. Ａ and triangle T Ｂ 22 is a form in which the capacitor array shown in FIG. 22 is arranged so that a parallelogram formed by four adjacent capacitor elements is repeated.

[0080] In the electronic component of the present invention, the orientation of the sides of the quadrangle in the top view of the capacitor elements may or may not be the same. Fig. 22 shows an example in which the orientation of the sides of the quadrangle in the top view of the capacitor elements is not the same for each capacitor element. Fig. 3 shows an example in which the orientation of the sides of the quadrangle in the top view of the capacitor elements is the same for each capacitor element.

[0081] The present specification discloses the following:

[0082] <1> An electronic component comprising: active elements and passive elements that constitute a voltage regulator, the active elements and passive elements being arranged corresponding to a plurality of channels; a load that is supplied with a DC voltage regulated by the voltage regulator and includes a semiconductor element; and a wiring board that is electrically connected to the active elements, the passive elements, and the load, wherein the active elements that constitute the voltage regulator include a switching element, and the passive elements that constitute the voltage regulator include a plurality of capacitor elements, the plurality of capacitor elements arranged in the channels constitute a capacitor array in which the capacitor elements are arranged with their external electrodes facing each other in a vertical direction with respect to a mounting surface of the wiring board, the capacitor array has a plurality of through conductors that pass through the capacitor array in a vertical direction with respect to the mounting surface of the wiring board, and at least a portion of the capacitor array is arranged at a position that overlaps with the load when viewed from the mounting surface of the wiring board, and the through conductors are arranged to overlap with the center of gravity of a triangle formed by three adjacent capacitor elements of the plurality of capacitor elements in a plan view of the capacitor array.

[0083] <2> The electronic component according to <1>, wherein the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements among the plurality of capacitor elements, and six through conductors are arranged around one capacitor element located other than the outer edge of the capacitor array.

[0084] <3> The electronic component according to <1> or <2>, wherein the through conductor is a plated through hole.

[0085] <4> The electronic component according to <1> or <2>, wherein the through conductor is a metal pin.

[0086] <5> The electronic component according to any one of <1> to <4>, wherein, in a plan view of the capacitor array, a shortest distance P between adjacent capacitor elements is shorter than a diagonal length W of an end face of the capacitor element.

[0087] <6> The electronic component according to <5>, wherein a ratio of the rectangular wire length W to the shortest distance P is (W / P)=0.5 or more and less than 1.0.

[0088] <7> The electronic component according to any one of <1> to <6>, wherein, in a plan view of the capacitor array, a ratio of a center-to-center distance Q between adjacent capacitor elements to a shortest distance P between adjacent capacitor elements is (Q / P) = 3 or more and 100 or less.

[0089] <8> The electronic component according to any one of <1> to <7>, wherein each capacitor element is housed in a circular cavity, and in a plan view of the capacitor array, a shortest distance N between adjacent cavities is equal to or less than a diameter R of the circle of the cavity.

[0090] <9> The electronic component according to <8>, wherein the relationship between the shortest distance N and the diameter R satisfies 0≦N≦R.

[0091] <10> The electronic component according to any one of <1> to <9>, wherein, in a plan view of the capacitor array, the area of ​​the through conductor is smaller than the area of ​​the capacitor element adjacent to the through conductor.

[0092] REFERENCE SIGNS LIST 1 Electronic component 10 Active element 20 Passive element 30 Load 40 Wiring board 45 Circuit layer 50 Capacitor array 51 First capacitor array 52 Second capacitor array 61 First connection terminal 62 Second connection terminal 63 Third connection terminal 64 Fourth connection terminal 70 Cavity 80, 80a, 80b, 80c, 80d Capacitor element 81 First external electrode 82 Second external electrode 90, 90a, 90b, 90c, 90d, 90e, 90f Through conductor 100 Core substrate 101 First surface of core substrate 102 Second surface of core substrate 110 Adhesive sheet 120 Sealant 130 Metal layer 140 Through hole 150 Through-hole plating layer 160 Filling resin 170 Via hole 180 Conductor layer 200: Capacitor element built-in substrate 300: Core substrate 310: Adhesive sheet 320: Sealing material 340: Cavity 370: Via hole 391, 392, 393, 394: Lead electrode

Claims

1. An electronic component comprising: active elements and passive elements that constitute a voltage regulator, arranged to correspond to a plurality of channels; a load that includes a semiconductor element and is supplied with a DC voltage regulated by the voltage regulator; and a wiring board that is electrically connected to the active elements, the passive elements, and the load, wherein the active elements that constitute the voltage regulator include switching elements, and the passive elements that constitute the voltage regulator include a plurality of capacitor elements, and the plurality of capacitor elements arranged in the channels constitute a capacitor array in which the capacitor elements are arranged with their external electrodes facing each other vertically with respect to the mounting surface of the wiring board, and the capacitor array has a plurality of through conductors that pass through the capacitor array vertically with respect to the mounting surface of the wiring board, and at least a portion of the capacitor array is arranged in a position that overlaps the load when viewed from the mounting surface of the wiring board, and the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements of the plurality of capacitor elements in a plan view of the capacitor array.

2. The electronic component according to claim 1, wherein the through conductors are arranged so as to overlap the center of gravity of a triangle formed by three adjacent capacitor elements among the plurality of capacitor elements, and six through conductors are arranged around one capacitor element located other than on the outer edge of the capacitor array.

3. An electronic component according to claim 1 or 2, wherein the through conductor is a plated through hole.

4. An electronic component according to claim 1 or 2, wherein the through conductor is a metal pin.

5. The electronic component according to any one of claims 1 to 4, wherein, in a plan view of the capacitor array, the shortest distance P between adjacent capacitor elements is shorter than the diagonal length W of the end faces of the capacitor elements.

6. The electronic component according to claim 5, wherein the ratio of the rectangular wire length W to the shortest distance P is (W / P)=0.5 or more and less than 1.

0.

7. The electronic component according to any one of claims 1 to 6, wherein, in a plan view of the capacitor array, the ratio of the center-to-center distance Q of adjacent capacitor elements to the shortest distance P between adjacent capacitor elements is (Q / P) = 3 or more and 100 or less.

8. An electronic component according to any one of claims 1 to 7, wherein each capacitor element is housed in a circular cavity, and the shortest distance N between adjacent cavities in a plan view of the capacitor array is equal to or less than the diameter R of the circle of the cavity.

9. The electronic component according to claim 8, wherein the relationship between the shortest distance N and the diameter R satisfies 0≦N≦R.

10. The electronic component according to any one of claims 1 to 9, wherein, in a plan view of the capacitor array, the area of ​​the through conductor is smaller than the area of ​​the capacitor element adjacent to the through conductor.

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