Imaging device

Abstract

[Problem] To prevent the occurrence of image quality degradation of a captured image due to an offset error, and to reduce circuit area and power consumption. [Solution] An imaging device comprises: a pixel that has a photoelectric conversion element for accumulating a charge corresponding to an amount of incident light and that generates a pixel signal corresponding to the charge; a signal line that transmits the pixel signal; a sample-and-hold circuit that continuously performs a sample operation and a hold operation of the pixel signal on the signal line in accordance with the cycle in which the pixel signal on the signal line switches; and an analog-to-digital converter that converts the pixel signal held in the sample-and-hold circuit into a digital pixel signal.

Description

Imaging device

[0001] An embodiment of the present invention relates to an imaging device.

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors (hereinafter also referred to as CIS) have become widespread. These sensors perform analog-to-digital (AD) conversion of pixel signals by using a comparator to compare an analog pixel signal with a linearly changing reference signal and counting the time until the reference signal intersects with the pixel signal.

[0003] Recently, CIS with a high dynamic range (HDR) function that captures images by switching between multiple sensitivities by providing multiple photodiodes in the pixel array section or by providing a capacitor for storing electric charge has been attracting attention.

[0004] To capture images by switching between multiple sensitivities, multiple AD conversions are required, which must be performed after ensuring a settling time until the voltage of the floating diffusion region stabilizes, making it difficult to achieve HDR functionality at a high frame rate.

[0005] Therefore, a technique has been proposed in which pixel signal sampling and AD conversion are performed in parallel at a plurality of sensitivities (see Patent Document 1).

[0006] In Patent Document 1, in order to widen the dynamic range, a large-capacity capacitor is provided in the pixel array section, so that electric charges overflowing from the photodiode at times of high illuminance can be stored in the capacitor.

[0007] International Publication No. 2022 / 172714A1

[0008] In the imaging device described in Patent Document 1, a plurality of pixel signals captured at a plurality of sensitivities are output sequentially to vertical signal lines and AD converted. Since the process of outputting a plurality of pixel signals sequentially to vertical signal lines must be performed within one horizontal line period, Patent Document 1 aims to shorten one horizontal line period by providing a plurality of sample-and-hold circuits between the pixel columns and the vertical signal lines and performing sampling and holding operations of the plurality of pixel signals in parallel.

[0009] However, the switches and capacitors provided in each of the multiple sample-and-hold circuits vary in electrical characteristics due to manufacturing variations, etc., which causes offset errors in the output voltage of each sample-and-hold circuit. In particular, when the signal level and reset level of a pixel signal are sampled and held using separate sample-and-hold circuits, the offset errors described above occur, and even if CDS (Correlated Double Sampling) processing is performed, the kTC noise cannot be canceled out, which may result in a deterioration in the image quality of the captured image.

[0010] Furthermore, providing a plurality of sample-and-hold circuits for each vertical signal line increases the circuit area, making it impossible to miniaturize the chip of the imaging device and increasing power consumption.

[0011] Therefore, the present disclosure provides an imaging device that can prevent degradation of image quality of a captured image due to the offset error described above, and can reduce circuit area and power consumption.

[0012] In order to solve the above problems, according to the present disclosure, there is provided an imaging device comprising: a pixel having a photoelectric conversion element that accumulates an electric charge according to the amount of incident light, and that generates a pixel signal according to the electric charge; a signal line that transmits the pixel signal; a sample-and-hold circuit that continuously performs a sampling operation and a holding operation of the pixel signal on the signal line in accordance with a cycle at which the pixel signal on the signal line switches; and an analog-to-digital converter that converts the pixel signal held by the sample-and-hold circuit into a digital pixel signal.

[0013] The sample and hold circuit may alternately switch between the sampling operation and the holding operation every time the pixel signal on the signal line switches.

[0014] The sample and hold circuit may perform the sampling operation after a settling operation of the pixel signal on the signal line is completed, and may perform the holding operation in parallel with the settling operation.

[0015] The analog-to-digital converter may have a comparator that compares the pixel signal held by the sample-and-hold circuit with a reference signal, and the sample-and-hold circuit may perform the holding operation in accordance with a period during which the reference signal changes over time.

[0016] The sample and hold circuit may include: a sample and hold capacitor that accumulates charge corresponding to the pixel signal on the signal line; a first switching circuit connected between the signal line and a first end of the sample and hold capacitor; a second switching circuit connected between the first end of the sample and hold capacitor and an output node of the sample and hold circuit; a third switching circuit connected between a second end of the sample and hold capacitor and an output node of the sample and hold circuit; and a transistor that outputs a signal corresponding to a voltage level of the second end from the output node.

[0017] The sample and hold circuit may perform the sample operation by turning on the first switching circuit to electrically connect the signal line and the first terminal, turning on the third switching circuit to electrically connect the second terminal and the output node, turning off the second switching circuit to electrically disconnect the first terminal and the output node, turning off the first switching circuit to electrically disconnect the signal line and the first terminal, turning off the third switching circuit to electrically disconnect the second terminal and the output node, and turning on the second switching circuit to electrically connect the first terminal and the output node.

[0018] The image sensor may include a pixel array section having a plurality of the pixels arranged in a first direction and a second direction that intersect with each other, and a plurality of the signal lines that are arranged in the first direction and transmit two or more of the pixel signals generated by two or more of the pixels arranged in the second direction, and the sample-and-hold circuit and the analog-to-digital converter may be provided for each of the plurality of signal lines.

[0019] Each of the plurality of pixels may output a plurality of pixel signals having different sensitivities at different times, and the sample and hold circuit may alternately switch between sampling and holding the plurality of pixel signals for each of the plurality of sensitivities.

[0020] The sample and hold circuit may alternately switch between sampling and holding the signal levels and reset levels of the plurality of pixel signals for each of a plurality of sensitivities.

[0021] The sample and hold capacitance may have at least a first capacitor and a second capacitor; the first switching circuit may have: a first switch connected between the signal line and a first end of the first capacitor; and a second switch connected between the signal line and a first end of the second capacitor; the second switching circuit may have: a third switch connected between the first end of the first capacitor and the output node; and a fourth switch connected between the first end of the second capacitor and the output node; and the third switching circuit may have a fifth switch connected between the second end of the first capacitor and the output node, and between the second end of the second capacitor and the output node.

[0022] The second capacitor may be used to sample and hold a pixel signal for a sensitivity that requires time for settling on the signal line, among the plurality of sensitivities.

[0023] The plurality of sensitivities may include an ultra-low sensitivity, a low sensitivity, a medium sensitivity, and a high sensitivity, and the second capacitor may be used to sample and hold a reset level of a low-sensitivity pixel signal.

[0024] The sample-and-hold circuit may turn on the second switch and the fifth switch and turn off the fourth switch to sample the pixel signal on the signal line by the second capacitor, then turn off the second switch, the fourth switch, and the fifth switch to put the second capacitor into a high impedance state, and then turn off the second switch and the fifth switch and turn on the fourth switch, thereby holding the pixel signal sampled by the second capacitor.

[0025] The period during which the second capacitor is in the high impedance state may depend on the time required for the pixel signal on the signal line to settle.

[0026] During the period in which the second capacitor is in a high impedance state, the sample operation using the first capacitor, in which the first switch and the fifth switch are turned on and the third switch is turned off, and the hold operation using the first capacitor, in which the first switch and the fifth switch are turned off and the third switch is turned on may be performed alternately.

[0027] The sample and hold circuit alternatively switches between a first mode and a second mode to sample and hold the pixel signal on the signal line; in the first mode, the first to fifth switches are switched to alternately perform the sample operation and the hold operation using the first capacitor, and the second capacitor is set to a high impedance state; and in the second mode, the sample operation using the first capacitor by turning on the first switch and the fifth switch and turning off the third switch and the hold operation using the first capacitor by turning off the first switch and the fifth switch and turning on the third switch may be alternately performed, in parallel with the sample operation using the second capacitor by turning on the second switch and the fifth switch and turning off the fourth switch, and the hold operation using the second capacitor by turning off the second switch and the fifth switch and turning on the fourth switch.

[0028] The sample-and-hold circuit may include an interference countermeasure circuit to prevent the gate voltage of the transistor from fluctuating due to the second capacitor being in a high impedance state.

[0029] The interference countermeasure circuit has: a sixth switch connected between the second end of the first capacitor and the gate of the transistor; and a seventh switch connected between the second end of the second capacitor and the gate of the transistor; and when the first capacitor is not in a high impedance state and the second capacitor is in a high impedance state, the sample and hold circuit may turn on the sixth switch to electrically connect the second end of the first capacitor and the gate of the transistor, and turn off the seventh switch to cut off the connection between the second end of the second capacitor and the gate of the transistor.

[0030] The interference countermeasure circuit may have an eighth switch connected between a first end of the first capacitor and a first end of the second capacitor, and when the second capacitor is set to a high impedance state, the sample-and-hold circuit may turn on the eighth switch in synchronization with the timing at which the pixel signal on the signal line is sampled by the first capacitor, thereby short-circuiting the first end of the first capacitor and the first end of the second capacitor.

[0031] The sample and hold circuit has: a ninth switch that switches whether to short-circuit the first end and the second end of the first capacitor; and a tenth switch that switches whether to short-circuit the first end and the second end of the second capacitor; and when the second capacitor is set to a high impedance state, the sample and hold circuit may keep the ninth switch always in an off state and the tenth switch always in an on state while the first capacitor is alternately performing the sampling operation and the holding operation.

[0032] 1 is a block diagram showing a schematic configuration of an image pickup device according to a first embodiment of the present disclosure. FIG. 1 is a conceptual diagram showing an example of an image pickup device in which a semiconductor chip corresponding to a pixel array unit and a semiconductor chip corresponding to a processing circuit are stacked. FIG. 2 is a circuit diagram showing the basic configuration of a high dynamic range pixel. FIG. 3 is a timing chart of each drive signal at the start of pixel exposure. FIG. 4 is a diagram showing the S / N ratio of a pixel signal obtained by combining four pixel signals captured at four sensitivities. FIG. 5 is a timing chart when reading out a pixel signal from a pixel. FIG. 6 is a circuit diagram of a main part of an image pickup device according to a first embodiment. FIG. 7 is a circuit diagram of an SH circuit according to the first embodiment. FIG. 8 is a timing diagram of sample operations and hold operations performed by the SH circuit. FIG. 9 is a circuit diagram of a main part of an image pickup device according to a comparative example. FIG. 10 is a circuit diagram of a sample and hold unit of an image pickup device according to a comparative example. FIG. 11 is a timing diagram of sample operations and hold operations of a sample and hold unit according to a comparative example. FIG. 12 is a diagram explaining a settling operation of a pixel signal on a vertical signal line. FIG. 13 is a timing diagram of sample operations and hold operations in a comparative example. FIG. 14 is a voltage waveform diagram of a vertical signal line during a sample operation. FIG. 15 is a voltage waveform diagram of a reference signal input to a comparator in an ADC. FIG. 16 is a diagram showing the shortest sample period and hold period. 19A and 19B are timing diagrams showing sample and hold periods of the image pickup device 1 according to the first embodiment.

[0033] FIG. 23B is a diagram showing the states of switches in the SH circuit during sample and hold operations.

[0034] FIG. 23B is a timing diagram showing pixel signals on vertical signal lines, pixel signals to be AD converted, pixel signals to be sampled and held by the first SH circuit, and pixel signals to be sampled and held by the second SH circuit in a comparative example.

[0035] FIG. 23C is a timing diagram showing pixel signals on vertical signal lines, pixel signals to be AD converted, and pixel signals to be sampled and held by the SH circuit in the first embodiment.

[0036] FIG. 23D is a timing diagram of the image pickup device according to the comparative example shown in FIG. 10.

[0037] FIG. 23E is a circuit diagram of a sample and hold unit included in an image pickup device according to a second embodiment.

[0038] FIG. 23F is a timing diagram of the SH circuit in the sample and hold unit according to the second embodiment shown in FIG. 19, when first to third SH circuits are provided in the sample and hold unit according to a comparative example.

[0039] FIG. 23G is a timing diagram of an SH circuit in which interference countermeasures have been implemented.

[0039] FIG. 23H is a timing diagram of an SH circuit according to a first modified example of FIG. Fig. 26 is a timing chart of the SH circuit of Fig. 25. Fig. 27 is a circuit diagram of the SH circuit according to the second modified example of Fig. 23B.Fig. 28 is a timing chart of the SH circuit in Fig. 27. Fig. 29 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig. 30 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0033] Hereinafter, an embodiment of an imaging device will be described with reference to the drawings. The following description will focus on the main components of the imaging device, but the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0034] 1 is a block diagram showing a schematic configuration of an image pickup device 1 according to a first embodiment of the present disclosure. The image pickup device 1 includes a pixel array unit 101, a timing control circuit 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0035] The pixel array unit 101 has unit pixels (hereinafter simply referred to as pixels) arranged in a matrix, each of which includes a photoelectric conversion element that photoelectrically converts incident light into an electric charge (pixel signal) corresponding to the amount of light. In this specification, the row direction may be referred to as a first direction, and the column direction may be referred to as a second direction. The pixel array unit 101 has a plurality of pixel rows arranged in the column direction, each of which includes a plurality of pixels aligned in the row direction. In this specification, these pixel rows may be referred to as pixel groups.

[0036] The specific circuit configuration of the pixel will be described later. Furthermore, in the pixel array unit 101, pixel drive lines 109 are wired for each row of the matrix-like pixel arrangement along the left-right direction of the drawing (the pixel arrangement direction / horizontal direction of the pixel rows), and vertical signal lines VSL are wired for each column along the up-down direction of the drawing (the pixel arrangement direction / vertical direction of the pixel columns). One end of each pixel drive line 109 is connected to an output terminal of the vertical scanning circuit 103 corresponding to each row. Although FIG. 1 shows one pixel drive line 109 for each pixel row, two or more pixel drive lines 109 may be provided for each pixel row.

[0037] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. The timing control circuit 102 controls the driving of the vertical scanning circuit 103, the DAC 104, the multiple ADCs 105, the horizontal transfer scanning circuit 106, etc., based on the various timing signals generated by the timing generator in response to externally applied control signals, etc.

[0038] The vertical scanning circuit 103 is made up of a shift register, an address decoder, etc. Although the specific configuration is not shown here, the vertical scanning circuit 103 includes a read scanning system and a sweep scanning system.

[0039] The readout scanning system sequentially selects and scans the unit pixels from which signals are read out, row by row. Meanwhile, the sweep scanning system performs sweep scanning on the readout row being read out by the readout scanning system, sweeping out (resetting) unnecessary charges from the photoelectric conversion elements of the unit pixels of that readout row, prior to the readout scanning by the readout scanning system by the shutter speed. This sweeping out (resetting) of unnecessary charges by the sweep scanning system results in a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge in the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge). The signal read out by the readout operation by the readout scanning system corresponds to the amount of light incident since the previous readout operation or electronic shutter operation. The period from the readout timing of the previous readout operation or the sweeping timing of the electronic shutter operation to the readout timing of the current readout operation is the photoelectric charge accumulation time (exposure time) in the unit pixel.

[0040] Pixel signals (analog signals) output from each unit pixel of a pixel row selected and scanned by the vertical scanning circuit 103 are supplied to a plurality of ADCs 105 via a plurality of vertical signal lines VSL corresponding to each column.

[0041] The DAC 104 generates a reference signal RAMP, which is a linearly changing ramp waveform signal, and supplies the reference signal RAMP to a plurality of ADCs 105. The DAC 104 is commonly connected to a plurality of comparators 121 via wiring for the reference signal RAMP, and supplies the same reference signal RAMP to the plurality of comparators 121. The reference signal line that transmits the reference signal RAMP transmits the reference signal RAMP to the plurality of comparators 121.

[0042] Each of the plurality of ADCs 105 includes a comparator 121, a counter 122, and a plurality of latch circuits 123. The plurality of ADCs 105 converts pixel signals (analog signals) from the pixel array unit 101 into digital signals.

[0043] The comparator 121, the counter 122, and the latch circuit 123 are provided corresponding to the pixel columns of the pixel array unit 101, and constitute the ADC 105a. The ADC 105a is provided for each pixel column in the column direction.

[0044] The comparator 121 compares the voltage of the signal obtained by adding the pixel signal output from each pixel and the reference signal RAMP via a capacitor with a predetermined reference voltage, and supplies an output signal indicating the comparison result to the counter 122.

[0045] The counter 122 counts the time until the voltage magnitude relationship between the pixel signal and the reference signal RAMP is inverted based on the output signal of the comparator 121. In this way, the analog pixel signal is converted into a digital pixel signal represented by a count value. The counter 122 supplies the count value to the latch circuit 123.

[0046] The latch circuit 123 holds the count value supplied from the counter 122. The latch circuit 123 also performs CDS (Correlated Double Sampling) by calculating the difference between the data signal count value corresponding to the pixel signal at the signal level and the reset signal count value corresponding to the pixel signal at the reset level. Note that the CDS processing may be performed by the signal processing circuit 108 at a subsequent stage.

[0047] The horizontal transfer scanning circuit 106 is configured with a shift register, an address decoder, etc., and sequentially selects and scans circuit portions corresponding to pixel columns of the plurality of ADCs 105. By the selective scanning by this horizontal transfer scanning circuit 106, the digital pixel signals held in the latch circuits 123 are sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0048] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch circuit 123 and supplies the amplified signal to the signal processing circuit 108 .

[0049] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signals supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 corrects vertical line defects and point defects, clamps the signal, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a downstream device.

[0050] 1 may be configured as a single semiconductor chip as a whole, or may be configured as multiple semiconductor chips. When the imaging device 1 is configured as multiple semiconductor chips, the pixel array unit 101 and other processing circuits may be formed as separate semiconductor chips, and these two semiconductor chips may be stacked.

[0051] 2 is a conceptual diagram showing an example of an imaging device 1 in which a semiconductor chip 511 corresponding to the pixel array unit 101 and a semiconductor chip 512 corresponding to a processing circuit are stacked. As shown in Fig. 2, the imaging device 1 is composed of two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0052] The semiconductor chip 511 has a pixel array unit 101 formed on a semiconductor substrate. The semiconductor chip 512 has a plurality of ADCs 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 includes a timing control circuit 102, a vertical scanning circuit 103, a DAC 104, a horizontal transfer scanning circuit 106, etc. The peripheral circuit 517 includes a signal processing circuit 108, etc.

[0053] Each pixel of the pixel array unit 101 in the semiconductor chip 511 and elements such as the ADCs (105, 516, 517) of the semiconductor chip 512 are electrically connected using, for example, through electrodes such as TSVs (Through Silicon Vias) provided in via regions 513 and 514. The multiple ADCs 105 can transmit and receive signals to and from the pixel array unit 101 via the TSVs. Furthermore, the semiconductor chips 511 and 512 may be bonded together so that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are in contact with each other (Cu-Cu bonding). Furthermore, although not shown, the pixel array unit 101 and some of the ADCs (105, 516, 517) may be configured as one semiconductor chip 511, and the remaining components may be configured as another semiconductor chip 512.

[0054] 1 outputs a pixel signal of high dynamic range (hereinafter also referred to as HDR). Before describing the specific configuration of a pixel according to the first embodiment, the basic configuration of a pixel of high dynamic range will be described.

[0055] (Basic Configuration of a High Dynamic Range Pixel) FIG. 3 is a circuit diagram showing the basic configuration of a high dynamic range pixel. The pixel PX in FIG. 3 is configured to include a first photoelectric conversion unit PD11a, a second photoelectric conversion unit PD11b, first to fourth transfer gate units T12a to T12d, a reset transistor T13, a charge accumulation unit C14, a first floating diffusion region (floating diffusion, first floating diffusion region) FD15a, a second floating diffusion region (floating diffusion, second floating diffusion region) FD15b, an amplifier transistor T16, and a selection transistor T17. In this specification, the transistors in the pixel PX are sometimes collectively referred to as pixel transistors. Each pixel transistor in the pixel PX is an N-type MOS transistor that turns on when a high-level drive signal is input to its gate. In this specification, the signal level of the drive signal that turns on each pixel transistor is referred to as an active state.

[0056] 3 are arranged in a plurality of rows and columns, and each row of pixels arranged in the row direction is provided with a pixel drive line 109 shown in Fig. 1. Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical scanning circuit 103 shown in Fig. 1 via a plurality of drive lines to be input to the gates of the pixel transistors in the pixel PX.

[0057] The first photoelectric conversion unit PD11a is made up of, for example, a PN junction photodiode. The first photoelectric conversion unit PD11a generates and accumulates electric charges according to the amount of light received. The second photoelectric conversion unit PD11b is made up of, for example, a PN junction photodiode, similar to the first photoelectric conversion unit PD11a. The second photoelectric conversion unit PD11b generates and accumulates electric charges according to the amount of light received.

[0058] Comparing the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b, the first photoelectric conversion unit PD11a has a larger light-receiving surface area and higher sensitivity than the second photoelectric conversion unit PD11b. Note that the relationship in size between the light-receiving surface areas of the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b is arbitrary.

[0059] The first transfer gate unit T12a is connected between the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a. A drive signal TGL is applied to the gate electrode of the first transfer gate unit T12a. When the drive signal TGL becomes active, the first transfer gate unit T12a becomes conductive, and the charges stored in the first photoelectric conversion unit PD11a are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a.

[0060] The second transfer gate unit T12b is connected between the charge storage unit C14 and the second floating diffusion region FD15b. A drive signal FCG is applied to the gate electrode of the second transfer gate unit T12b. When the drive signal FCG becomes active, the second transfer gate unit T12b becomes conductive, and the potentials of the charge storage unit C14 and the second floating diffusion region FD15b are coupled.

[0061] The conversion efficiency switching transistor (third transfer gate portion, first transistor) T12c is connected between the first floating diffusion region FD15a and the second floating diffusion region FD15b. A drive signal FDG is applied to the gate electrode of the conversion efficiency switching transistor T12c. When the drive signal FDG becomes active, the conversion efficiency switching transistor T12c becomes conductive, and the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0062] The fourth transfer gate unit T12d is connected between the second photoelectric conversion unit PD11b and the charge accumulation unit C14. A drive signal TGS is applied to the gate electrode of the fourth transfer gate unit T12d. When the drive signal TGS becomes active, the fourth transfer gate unit T12d becomes conductive, and the charges accumulated in the second photoelectric conversion unit PD11b are transferred to the charge accumulation unit C14 via the fourth transfer gate unit T12d.

[0063] Furthermore, the potential below the gate electrode of the fourth transfer gate unit T12d is slightly deeper, and an overflow path is formed that transfers charge that exceeds the saturated charge amount of the second photoelectric conversion unit PD11b and overflows from the second photoelectric conversion unit PD11b to the charge accumulation unit C14. Note that, hereinafter, the overflow path formed below the gate electrode of the fourth transfer gate unit T12d will be simply referred to as the overflow path of the fourth transfer gate unit T12d.

[0064] The reset transistor T13 is connected between a power supply (hereinafter, the power supply may also be referred to as VDD) that supplies a power supply voltage VDD and the second floating diffusion region FD15b. A drive signal RST is applied to the gate electrode of the reset transistor T13. When the drive signal RST is activated, the reset transistor T13 is turned on. As a result, for example, the potential region formed by the coupling of the first floating diffusion region FD15a and the second floating diffusion region FD15b, or the potential region formed by the coupling of the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b, is reset to the level of the power supply voltage VDD.

[0065] The charge storage unit C14 has, for example, a capacitor, and the counter electrode of the charge storage unit C14 is connected to the power supply VDD. The charge storage unit C14 stores the charge transferred from the second photoelectric conversion unit PD11b. The capacitor constituting the charge storage unit C14 is, for example, a lateral overflow integration capacitor (LOFIC). The charge storage unit C14 can hold the charge that overflows from the second photoelectric conversion unit PD11b under high illuminance conditions. By increasing the capacity of the charge storage unit C14, the charge that overflows from the second photoelectric conversion unit PD11b can be held to generate a pixel signal, thereby preventing overexposure under high illuminance conditions and expanding the dynamic range.

[0066] The first floating diffusion region FD15a and the second floating diffusion region FD15b convert the charges of the first or second photoelectric conversion unit PD11a or PD11b into a voltage signal and output the converted signal. By electrically connecting or disconnecting the first floating diffusion region FD15a and the second floating diffusion region FD15b, the capacitance of the entire floating diffusion region of the pixel PX can be switched. By switching the capacitance of the floating diffusion region of the pixel PX, the pixel PX can output a pixel signal with a plurality of charge-voltage conversion efficiencies.

[0067] The amplifier transistor T16 has a gate electrode connected to the first floating diffusion region FD15a and a drain electrode connected to the power supply VDD, and serves as an input part of a readout circuit that reads out the charge held in the first floating diffusion region FD15a, a so-called source follower circuit. That is, the amplifier transistor T16 has a source electrode connected to the vertical signal line VSL via the selection transistor T17, and thereby forms a source follower circuit together with a constant current source CS18 connected to one end of the vertical signal line VSL.

[0068] The selection transistor T17 is connected between the source electrode of the amplification transistor T16 and the vertical signal line VSL. A drive signal SEL is applied to the gate electrode of the selection transistor T17. When the drive signal SEL is activated, the selection transistor T17 is rendered conductive, and the pixel PX in FIG. 3 is rendered selected. As a result, the pixel signal output from the amplification transistor T16 is output to the vertical signal line VSL via the selection transistor T17.

[0069] In the following, when each drive signal is in an active state, it is referred to as the drive signal being turned on, and when each drive signal is in an inactive state, it is referred to as the drive signal being turned off. In the following, when each gate unit or each transistor is in a conductive state, it is referred to as the gate unit or each transistor being turned on, and when each gate unit or each transistor is in a non-conductive state, it is referred to as the gate unit or each transistor being turned off.

[0070] In this embodiment, the pixel PX shown in Fig. 3 switches between multiple sensitivities to generate multiple pixel signals divided into signal levels and reset levels. Although the type of sensitivity is not important, the following mainly describes an example in which the pixel PX switches between four sensitivities. Hereinafter, the four sensitivities will be referred to as ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity.

[0071] More specifically, the signal level of the ultra-low sensitivity pixel signal is called SH2DOL, and the reset level of the ultra-low sensitivity pixel signal is called NH2DOL. SH2DOL and NH2DOL use the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, the first floating diffusion region FD15a, and the second floating diffusion region FD15b shown in FIG. 3 .

[0072] Hereinafter, the signal level of the high-sensitivity pixel signal will be referred to as SH1, and the reset level of the high-sensitivity pixel signal will be referred to as NH1. SH1 and NH1 use the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the first floating diffusion region FD15a in FIG. 3 .

[0073] Hereinafter, the signal level of the medium-sensitivity pixel signal will be referred to as SH2, and the reset level of the medium-sensitivity pixel signal will be referred to as NH2. SH2 and NH2 use the first photoelectric conversion unit PD11a, first transfer gate unit T12a, first floating diffusion region FD15a, and second floating diffusion region FD15b shown in FIG.

[0074] Hereinafter, the signal level of the low-sensitivity pixel signal will be referred to as SL, and the signal level of the low-sensitivity pixel signal will be referred to as NL. SL and NL use the second photoelectric conversion unit PD11b, the second transfer gate unit T12b, the third transfer gate unit T12c, the fourth transfer gate unit (second transistor) T12d, and the charge accumulation unit C14 in FIG. 3 .

[0075] (Example of operation at the start of exposure of pixel PX in FIG. 3) FIG. 4 is a timing chart of each drive signal at the start of exposure of pixel PX. FIG. 4 shows a timing chart of the horizontal synchronization signal XHS and drive signals SEL, RST, FDG, TGL, TGS, and FCG. Hereinafter, an example of operation at the start of exposure of pixel PX in FIG. 3 will be described with reference to FIG. 4. FIG. 4 shows a timing chart for one horizontal line period. The multiple pixel rows included in the pixel array unit 101 are driven for each pixel row or for multiple pixel rows in accordance with the timing chart of FIG. 4.

[0076] First, at time t1, the horizontal synchronization signal XHS is input, and the exposure process of the pixel PX in FIG. 3 begins.

[0077] Next, at time t2, the drive signals RST and FDG are turned on, and the reset transistor T13 and the conversion efficiency switching transistor (third transfer gate unit) T12c are turned on, thereby coupling the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the coupled potential region is reset to the level of the power supply voltage VDD.

[0078] Next, at time t3, the drive signal TGL is turned on, turning on the first transfer gate unit T12a, which transfers the charge stored in the first photoelectric conversion unit PD11a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled via the first transfer gate unit T12a, resetting the first photoelectric conversion unit PD11a.

[0079] Next, at time t4, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, which starts the accumulation of charges in the first photoelectric conversion unit PD11a and starts the exposure period.

[0080] Next, at time t5, the drive signals TGS and FCG are turned on, turning on the fourth transfer gate unit T12d and the second transfer gate unit T12b. This couples the potentials of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. Furthermore, the charge stored in the second photoelectric conversion unit PD11b is transferred via the fourth transfer gate unit T12d to the coupled potential region of the first floating diffusion region FD15a and the second floating diffusion region FD15b, resetting the second photoelectric conversion unit PD11b and the charge storage unit C14.

[0081] Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off. This causes charge accumulation in the second photoelectric conversion unit PD11b to begin. In this way, the exposure period of the pixel PX begins at time t4, and charge accumulation is performed using only the first photoelectric conversion unit PD11a during the period from time t4 to t6. After time t6, charge accumulation is performed using both the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b.

[0082] Next, at time t7, the drive signal FCG is turned off and the second transfer gate unit T12b is turned off, causing the charge accumulation unit C14 to start accumulating the charge that overflows from the second photoelectric conversion unit PD11b and is transferred via the overflow path of the fourth transfer gate unit T12d.

[0083] Next, at time t8, the drive signals RST and FDG are turned off, and the reset transistor T13 and the conversion efficiency switching transistor T12c are turned off. At time t9, the horizontal synchronization signal XHS is input, and the next horizontal line period begins.

[0084] During the period from time t1 to time t9, the drive signal SEL is at a low level and the selection transistor T17 is in an off state, so that pixel signals are not read out to the vertical signal line VSL.

[0085] (Combining Multiple Pixel Signals Corresponding to Multiple Sensitivities) The imaging device 1 according to this embodiment can switch between four sensitivities, and combines and outputs four pixel signals that are exposed and read out at the four sensitivities. A portion of the circuitry of the pixel PX is used for each sensitivity.

[0086] FIG. 5 is a diagram showing the S / N ratio of a pixel signal obtained by combining four pixel signals captured at four sensitivities. The horizontal axis of FIG. 5 represents illuminance, and the vertical axis represents the S / N ratio. FIG. 5 shows a waveform obtained by combining waveforms of four S / N ratios corresponding to the four sensitivities. Specifically, FIG. 5 includes a waveform w1 of an ultra-low sensitivity pixel signal (NH2DOL-SH2DOL), a waveform w2 of a low sensitivity pixel signal (NL-SL), a waveform w3 of a medium sensitivity pixel signal (NH2-SH2), and a waveform w4 of a high sensitivity pixel signal (NH1-SH1).

[0087] The ultra-low sensitivity pixel signal (NH2DOL-SH2DOL) is generated using the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the conversion efficiency switching transistor T12c in the pixel PX.

[0088] The low-sensitivity pixel signal (NL-SL) is generated using the second photoelectric conversion unit PD11b, the second transfer gate unit T12b, the fourth transfer gate unit T12d, and the charge accumulation unit C14 in the pixel PX.

[0089] The medium-sensitivity pixel signal (NH2-SH2) is generated using the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the conversion efficiency switching transistor T12c in the pixel PX.

[0090] The medium-sensitivity pixel signal (NL-SL) and the ultra-low-sensitivity pixel signal (NH2DOL-SH2DOL) are generated using the same circuit, but the ultra-low-sensitivity pixel signal (NH2DOL-SH2DOL) has a shorter exposure time than the medium-sensitivity pixel signal (NL-SL), so even when exposed to high-intensity light, charges corresponding to the amount of incident light can be correctly accumulated in the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0091] The high-sensitivity pixel signal (NH1-SH1) is generated using the first photoelectric conversion unit PD11a and the first transfer gate unit T12a.

[0092] (Example of operation when reading out pixel PX in FIG. 3) FIG. 6 is a timing chart when reading out pixel signals from pixel PX. FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and vertical signal line VSL. Hereinafter, an example of operation when reading out pixel signals from pixel PX in FIG. 3 will be described with reference to the timing chart of FIG. 6. The pixel signals of each pixel PX included in the pixel array unit 101 are read out to the vertical signal line VSL for each pixel row or for each set of multiple pixel rows, in accordance with the timing chart of FIG. 4.

[0093] The pixel PX in the Nth row connected to the vertical signal line VSL in Figure 3 outputs pixel signals to the vertical signal line VSL in the order of, for example, an ultra-low sensitivity reset level NH2DOL, an ultra-low sensitivity signal level SH2DOL, a medium sensitivity reset level NH2, a high sensitivity reset level NH1, a high sensitivity signal level SH1, a medium sensitivity signal level SH2, a low sensitivity signal level SL, and a low sensitivity reset level NL.

[0094] First, at time t11, the horizontal synchronization signal XHS is input, and the readout period of the pixel PX in FIG. 3 begins.

[0095] Next, at time t12, the drive signals SEL, RST, and FDG are turned on, turning on the selection transistor T17, the reset transistor T13, and the conversion efficiency switching transistor T12c. This selects the pixel PX in FIG. 3. Furthermore, the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, and the coupled potential region is reset to the level of the power supply voltage VDD.

[0096] Next, at time t13, the drive signal RST is turned off, turning off the reset transistor T13. This stops the discharge of charges from the first floating diffusion region FD15a and the second floating diffusion region FD15b to the power supply voltage VDD node, and the first photoelectric conversion unit PD11a starts exposure, causing charges due to photoelectric conversion to be accumulated in the first photoelectric conversion unit PD11a. At time t13, the first transfer gate unit T12a is in the off state, so the accumulated charges in the first photoelectric conversion unit PD11a are not transferred to the first floating diffusion region FD15a.

[0097] Next, at time ta between time t13 and time t14, a pixel signal NH2DOL corresponding to the potential of the coupled first floating diffusion region FD15a and second floating diffusion region FD15b is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NH2DOL is a signal obtained by detecting the reset levels of the floating diffusion regions FD15a and FD15b in FIG. 3 using the coupled potential region of the first floating diffusion region FD15a and second floating diffusion region FD15b, and is a reset level with ultra-low sensitivity.

[0098] Next, at time t14, the first transfer gate unit T12a is turned on, and the accumulated charge in the first photoelectric conversion unit PD11a is transferred to the first floating diffusion region FD15a. The first photoelectric conversion unit PD11a accumulates charge for a short period of time, from time t13 to t14, and the accumulated charge for that short period of time is transferred to the first floating diffusion region FD15a at time t14. Because the charge accumulation time of the first photoelectric conversion unit PD11a is limited, the accumulated charge in the first photoelectric conversion unit PD11a does not overflow, even under high illuminance conditions.

[0099] Next, at time t15, the first transfer gate unit T12a is turned off. At time tb between times t15 and t16, a pixel signal SH2DOL corresponding to the charges transferred to the first floating diffusion region FD15a is output to the vertical signal line VSL. This pixel signal SH2DOL has an ultra-low sensitivity signal level for reading out the amount of light during the short exposure period from time t13 to t14.

[0100] 6 shows the voltage level of the vertical signal line VSL under high illuminance (solid line) and the voltage level of the vertical signal line VSL under low illuminance (dashed line). As shown in the figure, the higher the illuminance, the lower the voltage level of the vertical signal line VSL. In FIG. 6, the time when the voltage level of the vertical signal line VSL becomes stable is designated as t16.

[0101] Next, at time t17, the drive signal RST goes high, turning on the reset transistor T13. At this point, the selection transistor T17 and the conversion efficiency switching transistor T12c are in the on state. As a result, the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, and the charge in the coupled potential region is discharged to the power supply voltage VDD node via the reset transistor T13.

[0102] At time t18, the drive signal RST goes low, turning off the reset transistor T13.

[0103] At time tc between times t18 and t19, a pixel signal NH2 corresponding to the potential of the combined potential region is output to the vertical signal line VSL. This pixel signal NH2 is at the reset level for medium sensitivity. As shown in FIGS. 3 and 5, the pixel signals for ultra-low sensitivity and medium sensitivity are read out using the same circuit portion within the pixel PX.

[0104] Next, at time t19, the drive signal FDG is turned off, and the conversion efficiency switching transistor T12c is turned off, thereby dissolving the potential coupling between the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0105] Next, at time td between time t19 and time t20, a pixel signal NH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NH1 is a signal obtained by detecting the reset states of the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a shown in FIG. 3 using the first floating diffusion region FD15a, and is a high-sensitivity reset level. As shown in FIGS. 3 and 5, the high-sensitivity reset level NH1 is detected without using the second floating diffusion region FD15b.

[0106] Next, at time t20, the drive signal TGL is turned on, turning on the first transfer gate unit T12a. As a result, the charges generated and accumulated in the first photoelectric conversion unit PD11a during the exposure period are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a. At time t20, readout of pixel signals begins, and the exposure period of the first photoelectric conversion unit PD11a ends.

[0107] Next, at time t21, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the first floating diffusion region FD15a.

[0108] Next, at time te between times t21 and t22, a pixel signal SH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SH1 is a signal based on the potential of the first floating diffusion region FD15a at the time when the charges generated by the first photoelectric conversion unit PD11a during the exposure period from times t18 to t20 are accumulated in the first floating diffusion region FD15a. The pixel signal SH1 has a high-sensitivity signal level.

[0109] Next, at time t22, the drive signals FDG and TGL are turned on, and the conversion efficiency switching transistor T12c and the first transfer gate unit T12a are turned on, thereby coupling the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the charge that remains in the first photoelectric conversion unit PD11a and was not transferred between time t20 and time t21 is transferred via the first transfer gate unit T12a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0110] When the pixel signal SH1 is read out at time te, the capacity for charge-to-voltage conversion is small compared to the amount of charge to be handled, so there is no problem even if charge remains in the first photoelectric conversion unit PD11a. The charge remaining in the first photoelectric conversion unit PD11a can be transferred when the pixel signal SH2 is read out, and the charge in the first photoelectric conversion unit PD11a is not damaged.

[0111] Next, at time t23, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0112] Next, at time tf between times t23 and t24, a pixel signal SH2 based on the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SH2 is a signal corresponding to the charges generated by the first photoelectric conversion unit PD11a during the exposure period from times t18 to t42, which are accumulated in the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled. Therefore, the capacitance for charge-to-voltage conversion when the pixel signal SH2 is read out is the combined capacitance of the first floating diffusion region FD15a and the second floating diffusion region FD15b, which is larger than the capacitance when the high-sensitivity data signal SH1 is read out at time tc. The pixel signal SH2 has a medium-sensitivity signal level.

[0113] Next, at time t24, the drive signal RST is turned on, turning on the reset transistor T13, thereby resetting the potential region formed by the coupling of the first floating diffusion region FD15a and the second floating diffusion region FD15b to the level of the power supply voltage VDD.

[0114] Next, at time t25, the selection transistor T17 is turned off, and the pixel PX in Fig. 3 is put into a non-selected state. Subsequently, at time t26, the reset transistor T13 is turned off.

[0115] Next, at time t27, the drive signals SEL, TGS, and FCG are turned on, turning on the selection transistor T17, the fourth transfer gate unit T12d, and the second transfer gate unit T12b. This causes the pixel PX in FIG. 3 to be selected again. Furthermore, the potentials of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled, and the charge stored in the second photoelectric conversion unit PD11b is transferred to the coupled potential region. As a result, the charge stored in the second photoelectric conversion unit PD11b and the charge storage unit C14 during the exposure period is stored in the coupled potential region.

[0116] Next, at time t28, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off, thereby stopping the transfer of charges from the second photoelectric conversion unit PD11b.

[0117] Next, at time tg between times t28 and t29, a pixel signal SL based on the potential of the potential region where the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SL is a signal based on the potential of the potential region where the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled when the charge generated by the second photoelectric conversion unit PD11b and accumulated in the second photoelectric conversion unit PD11b and the charge accumulation unit C14 is accumulated in the coupled potential region. Therefore, the capacitance for charge-to-voltage conversion when the pixel signal SL is read out is the combined capacitance of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. This capacitance is larger than when pixel signal SH1 is read out at time tc and when pixel signal SH2 is read out at time td. Pixel signal SL has a low-sensitivity signal level. As shown in FIGS. 3 and 5, the low-sensitivity signal level SL is detected using the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b.

[0118] Next, at time t29, the drive signal RST is turned on, turning on the reset transistor T13, thereby resetting the potential region formed by the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b.

[0119] Next, at time t30, the drive signals SEL and FCG are turned off, and the selection transistor T17 and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential of the charge storage unit C14 is separated from the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0120] Next, at time t31, the drive signal RST is turned off, and the reset transistor T13 is turned off.

[0121] Next, at time t32, the drive signals SEL and FCG are turned on, turning on the selection transistor T17 and the second transfer gate unit T12b. This causes the pixel PX in FIG. 3 to be selected again. Furthermore, the potential of the charge storage unit C14 is coupled to the potential of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0122] Next, at time th between times t32 and t33, a pixel signal NL based on the potential of the potential region to which the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NL is a signal based on the potential of the reset state of the potential region to which the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled. The pixel signal NL is at a low-sensitivity reset level.

[0123] Next, at time t33, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor T17, the conversion efficiency switching transistor T12c, and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential coupling between the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b is released.

[0124] Next, at time t34, the horizontal synchronization signal XHS is input, and the readout period of the pixel signal from pixel PX in FIG. 3 ends.

[0125] As described above, each pixel PX outputs a plurality of pixel signals with different sensitivities to a vertical signal line at different times. The plurality of pixel signals with different sensitivities include, for example, an ultra-low sensitivity signal level, an ultra-low sensitivity reset level, a low sensitivity signal level, a low sensitivity reset level, a medium sensitivity signal level, a medium sensitivity reset level, a high sensitivity signal level, and a high sensitivity reset level. It is not easy to output these pixel signals from the pixel PX to the vertical signal line in one horizontal line period.

[0126] By providing multiple sample-and-hold circuits and performing sample and hold operations in parallel, it is possible to shorten one horizontal line period, but as described above, variations in the electrical characteristics of the switches and capacitors of each sample-and-hold circuit cause offset errors in the output voltages of the multiple sample-and-hold circuits. Therefore, in the imaging device 1 according to the first embodiment, only one sample-and-hold circuit performs sample and hold operations for pixel signals with multiple sensitivities. In this embodiment, the duration of the sample operation and the hold operation are shortened to prevent one horizontal line period from becoming longer.

[0127] 7 is a circuit diagram of the main components of the image pickup device 1 according to the first embodiment. The image pickup device 1 according to the first embodiment includes a sample-and-hold unit 125 disposed between each vertical signal line VSL and the ADC 105. The sample-and-hold unit 125 includes one SH circuit SHC1. This SH circuit samples and holds pixel signals of a plurality of sensitivities in turn.

[0128] 7 shows a circuit configuration of a VSL boost circuit 12 connected to one vertical signal line VSL, an SH circuit SHC1 in a sample-and-hold unit 125, and an ADC 105. A plurality of vertical signal lines VSL are arranged in the pixel array unit 101, and are arranged in a first direction (row direction) X and extend in a second direction (column direction) Y. A sample-and-hold unit 125 and an ADC 105 are provided for each of the plurality of vertical signal lines VSL.

[0129] (VSL Boost Circuit 12) The VSL boost circuit 12 includes n-type transistors Tn6 to Tn8, a capacitor C15, and a constant current source CS15. The gate of the transistor Tn8 is connected to the vertical signal line VSL. The drain of the transistor Tn8 is connected to the power supply VDD, and its source is connected to the constant current source CS15. As a result, the transistor Tn8 and the constant current source CS15 function as a source follower, and the gain thereof is smaller than "1."

[0130] One end of the capacitor C15 is connected to the gate of the transistor Tn8 via the transistor Tn6. The other end of the capacitor C15 is connected to the source of the transistor Tn8. As a result, the source of the transistor Tn6 sees a signal of the same polarity obtained by dividing the pixel signal of the vertical signal line VSL by the gain of the transistor Tn6, and the source of the transistor Tn8 sees a signal obtained by multiplying the fluctuation of the pixel signal of the vertical signal line VSL by the gain of the source follower. As a result, across the capacitor C15, it appears as if a gain of the same polarity that is larger than that of the source of the transistor Tn6 is being applied to the source of the transistor Tn8. As a result, the VSL boost circuit 12 operates as a negative capacitance circuit.

[0131] The transistor Tn7 is connected between one end of the capacitor C15 and the ground GND. The transistor Tn6 is connected between one end of the capacitor C15 and the vertical signal line VSL. The transistor Tn7 functions as a constant current source for the vertical signal line VSL.

[0132] Parasitic capacitance occurs in the vertical signal line VSL. Assume that a voltage of +Vs is applied to the parasitic capacitance of the vertical signal line VSL. In this case, if the gain of the transistor Tn8 functioning as a source follower and the constant current source CS15 in the negative capacitance circuit 310 is set to "0.9" and the source-to-drain gain of the transistor Tn6 is set to "10," then 0.1×Vs is applied to the terminal of the capacitor C15 on the vertical signal line VSL side, and 0.9×Vs is applied to the terminal on the opposite side. Therefore, when the potential (0.9×Vs) on the opposite side to the vertical signal line VSL is used as a reference, a voltage of -0.8×Vs is applied to the capacitor C15. As a result, +Vs is applied to the parasitic capacitance of the vertical signal line VSL, and -0.8×Vs is applied to the capacitor C15, resulting in a lower wiring capacitance of the vertical signal line VSL compared to when the negative capacitance circuit 310 is not present.

[0133] As described above, by providing the VSL boost circuit 12, the wiring capacitance of the vertical signal line VSL can be reduced, the potential of the vertical signal line VSL can be quickly stabilized, and the settling time can be shortened.

[0134] In addition, the VSL boost circuit 12 of the present disclosure uses a transistor Tn8 that functions as a source follower and a constant current source CS15, but other configurations that can perform non-inverting amplification may be used as long as the influence of the parasitic capacitance of the vertical signal line VSL can be sufficiently reduced.

[0135] (Sample and Hold Circuit (SH Circuit)) As described above, a sample and hold unit 125 is provided between each vertical signal line VSL and the ADC 105. The sample and hold unit 125 has one SH circuit SHC1. The SH circuit SHC1 samples and holds multiple pixel signals on the vertical signal line VSL corresponding to multiple sensitivities in turn. More specifically, the SH circuit SHC1 continuously performs a sample operation and a hold operation on the pixel signal on the vertical signal line VSL in accordance with the cycle at which the pixel signal on the vertical signal line VSL switches. The SH circuit SHC1 alternately switches between the sample operation and the hold operation every time the pixel signal on the vertical signal line VSL switches. The SH circuit SHC1 performs a sample operation after the settling operation of the pixel signal on the vertical signal line VSL is completed. The SH circuit SHC1 performs a hold operation in parallel with the settling operation of the vertical signal line VSL.

[0136] The SH circuit has a capacitor (sample and hold capacitance) Cp1, a transistor Tr1, switches (first to third switching circuits) SW1 to SW3, and a constant current source CS1.

[0137] One end of the capacitor Cp1 is connected to the vertical signal line VSL via the switch SW1, and can store a charge corresponding to a pixel signal, and the other end of the capacitor Cp1 is connected to the gate of the transistor Tr1.

[0138] The capacitor Cp1 accumulates electric charges corresponding to pixel signals on the vertical signal lines, and may be referred to as a sample-and-hold capacitor in this specification.

[0139] The drain of transistor Tr1 is connected to a constant current source CS1, and its source is connected to ground (reference voltage source) GND. The constant current source CS1 is connected between the power supply VDD and the drain of transistor Tr1, and passes a constant current through the drain of transistor Tr1. Transistor Tr1 passes a current between its drain and source that corresponds to the potential of its gate. As a result, the drain of transistor Tr1 has a potential that corresponds to the potential of the gate of transistor Tr1. The drain voltage of transistor Tr1 is output as an output signal from SH circuit SHC1.

[0140] The switch SW1 is connected between the capacitor Cp1 and the vertical signal line VSL, the switch SW2 is connected between the drain of the transistor Tr1 and one end of the capacitor Cp1, and the switch SW3 is connected between the drain of the transistor Tr1 and the other end of the capacitor Cp1.

[0141] When the SH circuit SHC1 samples the pixel signal on the vertical signal line VSL to the capacitor Cp1, the switches SW1 and SW3 are turned on (conductive). At this time, the switch SW2 is turned off (non-conductive). As a result, the pixel signal is transmitted to one end of the capacitor Cp1, and the capacitor node opposite the gate of the transistor Tr1 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switches SW1 and SW3 are turned off and the switch SW2 is turned on. As a result, the pixel signal stored in the capacitor Cp1 is held. At this time, the transistor Tr1 is turned on (analog state) in accordance with the pixel signal, and the drain of the transistor Tr1 is maintained at a potential corresponding to the pixel signal. Therefore, the SH circuit SHC1 outputs a hold signal corresponding to the pixel signal from the drain of the transistor Tr1.

[0142] In this way, capacitor Cp1 performs a sample operation by turning on switch SW1 to electrically connect the signal line and the first terminal, turning on switch SW3 to electrically connect the second terminal and the output node, turning off switch SW2 to electrically disconnect the first terminal and the output node, turning off switch SW1 to electrically disconnect the signal line and the first terminal, turning off switch SW3 to electrically disconnect the second terminal and the output node, and turning on switch SW2 to electrically connect the first terminal and the output node.

[0143] The SH circuit SHC1 samples and holds a plurality of pixel signals corresponding to a plurality of sensitivities in turn. The number and type of switchable sensitivities are not important, but in this embodiment, as described with reference to FIG. 5 , an example will be described in which the SH circuit SHC1 samples and holds four pixel signals in turn: ultra-low sensitivity, high sensitivity, medium sensitivity, and low sensitivity. The SH circuit SHC1 alternately switches between sampling and holding the signal levels and reset levels of a plurality of pixel signals on the corresponding vertical signal line VSL for each of the four sensitivities.

[0144] (ADC 105) The ADC 105 performs AD conversion on pixel signals read out from the high dynamic range pixels PX shown in Fig. 3. The ADC 105 converts the pixel signals held by the sample and hold unit 125 into digital pixel signals. More specifically, the ADC 105 performs AD conversion on each pixel PX in the order of an ultra-low sensitivity reset level NH2DOL, an ultra-low sensitivity signal level SH2DOL, a high sensitivity reset level NH1, a high sensitivity signal level SH1, a medium sensitivity reset level NH2, a medium sensitivity signal level SH2, a low sensitivity signal level SL, and a low sensitivity reset level NL.

[0145] The ADC 105 includes a comparator 121 and a counter 122 .

[0146] (Configuration and Function of Comparator 121) The comparator 121 includes an input comparison circuit 121a and an output circuit 121b.

[0147] The input comparison circuit 121a includes p-type transistors Tp1 and Tp2, n-type transistors Tn1 to Tn3, capacitors Cvsl, Cref, C16 to C18, an AZ switch SWAZ, and switches SW15 to SW17.

[0148] One end of the capacitors Cvsl and Cref is connected to the output of the sample-and-hold unit 125 and the reference signal RAMP, respectively. The other ends of the capacitors Cvsl and Cref are commonly connected to the gate of the transistor Tp1.

[0149] The transistors Tn1, Tp1, and Tn2 are connected in series in this order between a power supply VDD and a ground GND.

[0150] The drain of the transistor Tn1 is connected to the power supply VDD, and the source of the transistor Tn1 is connected to the source of the transistor Tp1. The gate of the transistor Tn1 is connected to a switch SW15 and a capacitor C16. The transistor Tn1 functions as an LDO (Low Dropout) linear regulator.

[0151] As described above, the gate of transistor Tp1 is commonly connected to the other ends of capacitors Cvsl and Cref. The source of transistor Tp1 is connected to the source of transistor Tn1, and the drain of transistor Tp1 is connected to the drain of transistor Tn2 and the gate of transistor Tp2. When the sum of the output signal of sample-and-hold unit 125 and reference signal RAMP from DAC 104 exceeds a threshold voltage, transistor Tp1 changes from a conductive state to a non-conductive state, inverting the voltage level of the gate of transistor Tp2 from high to low. In other words, transistor Tp1 functions as an amplifier that amplifies and detects the level of the output signal of sample-and-hold unit 125.

[0152] The gate of transistor Tp2 is connected to the drain of transistor Tp1. The source of transistor Tp2 is connected to the source of transistor Tn1 in common with the source of transistor Tp1. The drain of transistor Tp2 is connected to the drain of transistor Tn3. When transistor Tp1 changes from a conductive state to a non-conductive state, transistor Tp2 conversely changes from a non-conductive state to a conductive state, inverting the drain voltage of transistor Tp2 from low level to high level.

[0153] The transistor Tn2 is connected between the drain of the transistor Tp1 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp1. The transistor Tn3 is connected between the drain of the transistor Tp2 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp2.

[0154] The AZ switch SWAZ is connected between the gate of the transistor Tp1 and the gate of the transistor Tp2, and performs an auto-zero operation by equalizing the potential between the gate and drain of the transistor Tp1 before the output signal of the sample-and-hold unit 125 is detected.

[0155] The output circuit 121b includes p-type transistors Tp3 and Tp4 and n-type transistors Tn4 and Tn5. The transistor Tp3 is connected between the power supply VDD and the output terminal OUT of the comparator 121. The transistor Tn5 is connected between the source of the transistor Tn4 and ground GND. The gates of the transistors Tp3 and Tn5 are connected in common. The transistors Tp3 and Tn5 serve to fix the output OUT to a high level outside of the count period. The transistors Tp4 and Tn4 are connected in series between the power supply VDD and the drain of the transistor Tn5. The node between the transistors Tp4 and Tn4 forms the output terminal OUT. The gates of the transistors Tp4 and Tn4 are connected in common to the output of the input comparison circuit 121a (the drain of the transistor Tp2). The transistors Tp4 and Tn4 function as an inverter circuit.

[0156] When the drain voltage of the transistor Tp2 is inverted from low to high, the output terminal OUT of the comparator 121 is inverted from high to low by the transistors Tp4 and Tn4. The inversion of the voltage level of the output terminal OUT is used to stop the operation of the counter 122, thereby enabling AD conversion.

[0157] FIG. 8 is a circuit diagram of the SH circuit SHC1 according to the first embodiment, and FIG. 9 is a timing diagram of the sample operation and hold operation performed by the SH circuit SHC1. The SH circuit SHC1 according to this embodiment is characterized by shortening the sample operation period and the hold operation period. The SH circuit SHC1 performs a hold operation for a pixel signal of a certain sensitivity immediately after the sample operation period for that sensitivity ends. Furthermore, after the hold operation period ends, the SH circuit SHC1 successively performs a sample operation and a hold operation for a pixel signal of the next sensitivity. In this way, the SH circuit SHC1 successively performs sample operations and hold operations for multiple pixel signals corresponding to multiple sensitivities in turn. During the hold operation period, the ADC 105 AD converts the pixel signals held by the SH circuit SHC1. In this way, during the hold operation period, the hold operation for the sampled pixel signal and AD conversion of the held pixel signal are performed.

[0158] As shown in Fig. 9, during sample operation, switches SW1 and SW3 are turned on and switch SW2 is turned off. During hold operation, switches SW1 and SW3 are turned off and switch SW2 is turned on. In Fig. 9, the period during which switches SW1 and SW3 are high and the period during which switch SW2 is off are slightly offset, but the offset in the timing at which switches SW1 to SW3 are turned on or off is not essential for understanding the circuit operation, and the timing diagram in Fig. 9 is merely an example.

[0159] FIG. 10 is a circuit diagram of the main components of an image pickup device 100 according to a comparative example. In FIG. 10, components common to those in FIG. 7 are assigned the same reference numerals, and the following description will focus on the differences. The image pickup device 100 according to the comparative example has a sample-and-hold unit 125 and a multiplexer between the vertical signal line VSL and the ADC 105. The sample-and-hold unit 125 has two SH circuits SHC1 and SHC2. Hereinafter, the two SH circuits will be referred to as the first SH circuit SHC1 and the second SH circuit SHC2.

[0160] The first SH circuit SHC1 and the second SH circuit SHC2 both have the same circuit configuration as the SH circuit SHC1 in Fig. 7. Fig. 10 shows an example in which the first SH circuit SHC1 has a capacitor Cp1, a transistor Tr1, switches SW1 to SW3, and a constant current source CS1, and the second SH circuit SHC2 has a capacitor Cp2, a transistor Tr2, switches SW4 to SW6, and a constant current source CS2.

[0161] The first SH circuit SHC1 and the second SH circuit SHC2 sample and hold pixel signals of different sensitivities. For example, the first SH circuit SHC1 samples and holds two pixel signals of medium sensitivity and low sensitivity, and the second SH circuit SHC2 samples and holds two pixel signals of high sensitivity and very low sensitivity. The first SH circuit SHC1 and the second SH circuit SHC2 can sample and hold pixel signals of different sensitivities in parallel.

[0162] The multiplexer MUX selects one of the two hold signals sampled and held by the first and second SH circuits SHC1, SHC2 and the pixel signal on the vertical signal line VSL, and supplies the selected signal to the ADC 105. The multiplexer MUX is connected to two lines connected to the output nodes of the first and second SH circuits SHC1, SHC2, and a bypass line BPL that transmits the pixel signal on the vertical signal line VSL.

[0163] For example, while one of the first and second SH circuits SHC1, SHC2 is waiting for the discharge of the pixel's charge storage unit C14 to finish, the multiplexer MUX selects in turn the hold signal of the other SH circuit and the pixel signal on the signal line, and then selects the reset level of the pixel signal sampled and held by one of the SH circuits after the charge storage unit C14 has discharged. Fig. 11 is a circuit diagram of the sample and hold unit 125 of the imaging device 100 according to a comparative example. The sample and hold unit 125 according to the comparative example has a first SH circuit SHC1 and a second SH circuit SHC2.

[0164] 12 is a timing diagram of the sample operation and hold operation of the sample and hold unit 125 according to a comparative example. From time t1 to t2 in FIG. 12, the first SH circuit SHC1 performs the sample operation while the second SH circuit SHC2 performs the hold operation. In the first SH circuit SHC1 that performs the sample operation, switches SW1 and SW3 are turned on and switch SW2 is turned off. In the second SH circuit SHC2 that performs the hold operation, switches SW4 and SW6 are turned off and switch SW5 is turned on.

[0165] From time t2 to t3, the first SH circuit SHC1 performs a hold operation while the second SH circuit SHC2 performs a sample operation. From time t3 to t4, similar to times t1 to t2, the first SH circuit SHC1 performs a sample operation while the second SH circuit SHC2 performs a hold operation.

[0166] In this way, while the first SH circuit SHC1 alternately performs the sample operation and the hold operation, the second SH circuit SHC2 alternately performs the hold operation and the sample operation. Also, during the hold operation, the ADC 105 at the subsequent stage of the sample-and-hold unit 125 performs AD conversion of the hold signal. That is, during the hold operation, the hold operation and the AD conversion operation are performed.

[0167] The periods of the sample operation and the hold operation are different between the first embodiment shown in Fig. 9 and the comparative example shown in Fig. 12. In the first embodiment, the periods of the sample operation and the hold operation are both shortened, so that both the sample operation and the hold operation can be performed during the period in which the comparative example performs the sample operation.

[0168] The pixel signal sampling operation must be performed after the pixel signal on the vertical signal line VSL has settled. FIG. 13 is a diagram illustrating the settling operation of the pixel signal on the vertical signal line VSL. FIG. 13 shows an example in which a pixel signal is output from a specific pixel connected to the vertical signal line VSL. When the selection transistor T17 in the pixel is turned on, a pixel signal corresponding to the charge in the floating diffusion region of the pixel is output to the vertical signal line VSL. A load resistor Rvsl and a load capacitor Cvsl are connected to the vertical signal line VSL, and it takes a certain amount of time for charge corresponding to the voltage level of the pixel signal to be accumulated in the load capacitor Cvsl. While charge is being accumulated in the load capacitor Cvsl, the voltage level of the vertical signal line VSL changes. When charge accumulation in the load capacitor Cvsl is completed, the vertical signal line VSL reaches a voltage level corresponding to the pixel signal. In this specification, the time required for the vertical signal line VSL to reach a voltage level corresponding to the pixel signal is referred to as the settling time, and the operation until the vertical signal line VSL reaches a voltage level corresponding to the pixel signal is referred to as the settling operation. During the settling operation and the sampling operation, as indicated by the arrow y1 in FIG. 13, a current flows from the pixel through the vertical signal line VSL to the first SH circuit SHC1.

[0169] 13 shows an example in which the second SH circuit SHC2 performs a hold operation and an AD conversion operation in parallel with the first SH circuit SHC1 performing a sample operation. When the second SH circuit SHC2 performs a hold operation and an AD conversion operation, a current flows from the second SH circuit SHC2 to the comparator 121 in the ADC 105, as shown by the arrow y2 in FIG.

[0170] 14A is a timing diagram of the sample operation and the hold operation in a comparative example, FIG. 14B is a voltage waveform diagram of the vertical signal line VSL during the sample operation, and FIG. 14C is a voltage waveform diagram of the reference signal RAMP input to the comparator 121 in the ADC 105.

[0171] When the pixel signal on the vertical signal line VSL is switched, the voltage level of the vertical signal line VSL changes abruptly, then gradually changes, and eventually reaches a constant level, as shown in Fig. 14B. The SH circuit SHC1 only needs to perform a sampling operation when the voltage level of the vertical signal line VSL has reached a constant level, and does not need to perform a sampling operation during a settling operation.

[0172] Furthermore, the comparator 121 in the ADC 105 compares the held pixel signal with a reference signal RAMP. The reference signal RAMP has a period during which its voltage level changes, as shown in Fig. 14C. The SH circuit SHC1 only needs to perform a hold operation during this period; it does not need to perform a hold operation during a period during which the voltage level of the reference signal RAMP does not change.

[0173] 15A is a diagram showing the shortest sample period and hold period. As shown in FIG. 15A, the sample period can be set to a period after the voltage level of the vertical signal line VSL has stabilized, and can be significantly shorter than the sample period of FIG. 14A (the period including the dashed line period of FIG. 15A). The hold period can be set to a period during which the voltage level of the reference signal RAMP changes, and can be shorter than the hold period of FIG. 14B (the period including the dashed line period of FIG. 15B).

[0174] 15B is a diagram showing a sample period and a hold period of the imaging device 1 according to the first embodiment. In the first embodiment, the sample period in FIG. 15A is shifted, and a sample period is provided at the beginning of a unit period, and the hold period in FIG. 15A is provided immediately thereafter. The unit period is a sample-and-hold period, and this period includes a sample period in which a sample operation is performed and a hold period in which a hold operation is performed.

[0175] In the first embodiment, as shown in Figure 15B, a sample period is provided when the voltage level of the vertical signal line VSL has stabilized, during which pixel signals are sampled, and a hold period is provided immediately after the sample period to hold the sampled pixel signals. The hold period can be shortened by inputting a reference signal RAMP in accordance with the hold period. Thereafter, sample periods and hold periods are provided alternately, allowing multiple pixel signals corresponding to multiple sensitivities to be read out in one horizontal line period.

[0176] FIG. 16 is a diagram showing the states of the switches SW1 to SW3 of the SH circuit during the sample operation and the hold operation.

[0177] Time t11 is a hold period. During the hold period, switches SW1 and SW3 are turned off and switch SW2 is turned on. During the hold period, a pixel signal of the next sensitivity is output to vertical signal line VSL, and a settling operation is performed to charge and discharge the load capacitance connected to vertical signal line VSL.

[0178] Time t12 is the sample period. During the sample period, the switches SW1 and SW3 are turned on and the switch SW2 is turned off. This causes a sample operation to be performed, charging and discharging the capacitor (sample capacitance) Cp1 in the SH circuit.

[0179] Time t13 is a hold period. As at time t11, switches SW1 and SW3 are turned off, and switch SW2 is turned on. This performs a hold operation to hold the pixel signal sampled in capacitor Cp1, and the held pixel signal is immediately AD-converted by ADC 105. Furthermore, in parallel with this operation, as at time t11, a settling operation is performed to charge and discharge the load capacitance of vertical signal line VSL in accordance with the pixel signal of the next sensitivity.

[0180] As described above, the imaging device 1 according to the first embodiment reads out a plurality of pixel signals corresponding to a plurality of sensitivities. These pixel signals are read out sequentially during one horizontal line period.

[0181] 17A is a timing diagram showing pixel signals on the vertical signal line VSL, pixel signals to be AD converted, pixel signals to be sampled and held by the first SH circuit SHC1, and pixel signals to be sampled and held by the second SH circuit SHC2 in a comparative example. FIG. 17B is a timing diagram showing pixel signals on the vertical signal line VSL, pixel signals to be AD converted, and pixel signals to be sampled and held by the SH circuit SHC1 in the first embodiment.

[0182] 17A and 17B show an example in which pixels in an Nth pixel row (hereinafter referred to as the Nth row) sequentially output to the corresponding vertical signal line VSL a reset level NH2DOL of an ultra-low-sensitivity pixel signal, a signal level SH2DOL of an ultra-low-sensitivity pixel signal, a reset level NH2 of a medium-sensitivity pixel signal, a reset level NH1 of a high-sensitivity pixel signal, a signal level SH1 of a high-sensitivity pixel signal, a signal level SH2 of a medium-sensitivity pixel signal, a signal level SL of a low-sensitivity pixel signal, and a reset level NL of a low-sensitivity pixel signal, and then pixels in the (N+1)th row output a reset level NH2DOL of an ultra-low-sensitivity pixel signal. The ADC 105 performs AD conversion on the pixel signal with a delay of one cycle from the pixel signal on the vertical signal line VSL.

[0183] The first SH circuit SHC1 according to the comparative example samples the reset level NH2DOL of the ultra-low sensitivity pixel signal of the Nth row from time t21 to t22 in FIG. 17A and holds this reset level NH2DOL from time t22 to t23. Next, it samples the reset level NH2 of the medium sensitivity pixel signal of the Nth row from time t23 to t24 and holds this reset level NH2 from time t24 to t25. Next, it samples the signal level SH1 of the high sensitivity pixel signal of the Nth row from time t25 to t26 and holds this signal level SH1 from time t26 to t27. Next, it samples the signal level SL of the low sensitivity pixel signal of the Nth row from time t27 to t28 and holds this signal level SL from time t28 to t29. Next, it samples the reset level NL of the ultra-low sensitivity pixel signal of the (N+1)th row from time t9 to t30.

[0184] The second SH circuit SHC2 according to one comparative example holds the reset level NL of the low-sensitivity pixel signal of the (N-1)th row from time t21 to t22 in FIG. 17A , samples the signal level SH2DOL of the ultra-low-sensitivity pixel signal of the Nth row from time t22 to t23, and holds this signal level SH2DOL from time t23 to t24. Subsequently, it samples the reset level NH1 of the high-sensitivity pixel signal from time t24 to t25 and holds this reset level NH1 from time t25 to t26. Subsequently, it samples the signal level SH2 of the medium-sensitivity pixel signal from time t26 to t27 and holds this signal level SH2 from time t27 to t28. Subsequently, it samples the reset level NL of the low-sensitivity pixel signal from time t28 to t29 and holds this reset level NL from time t29 to t30.

[0185] When the timing of AD conversion of pixel signals is the same in the first embodiment and the comparative example, the timing of outputting each pixel signal to the vertical signal line VSL is delayed by the sample period in the first embodiment compared to the comparative example. In Fig. 17B, the sample period ST is (ST = t21a - t21).

[0186] The SH circuit SHC1 according to the first embodiment samples the low-sensitivity reset level NL of the pixel signal of the (N-1)th row from time t21 to t21a in FIG. 17B and holds this reset level NL from time t21a to t22. Subsequently, it samples the ultra-low-sensitivity reset level NH2DOL of the pixel signal of the Nth row from time t22 to t22a and holds this reset level NH2DOL from time t22a to t23. Subsequently, it samples the ultra-low-sensitivity signal level SH2DOL of the Nth row from time t23 to t23a and holds this signal level SH2DOL from time t23a to t24. Subsequently, it samples the reset level NH2 of the medium-sensitivity pixel signal of the Nth row from time t24 to t24a and holds this reset level NH2 from time t24a to t25. Next, the reset level NH1 of the high-sensitivity pixel signal of the Nth row is sampled from time t25 to t25a, and this reset level NH1 is held from time t25a to t26. Next, the signal level SH1 of the high-sensitivity pixel signal of the Nth row is sampled from time t26 to t26a, and this signal level SH1 is held from time t26a to t27. Next, the signal level SH2 of the medium-sensitivity pixel signal of the Nth row is sampled from time t27 to t27a, and this signal level SH2 is held from time t27a to t28. Next, the signal level SL of the low-sensitivity pixel signal of the Nth row is sampled from time t28 to t28a, and this signal level SL is held from time t28a to t29. Subsequently, the reset level NH of the low-sensitivity pixel signals in the Nth row is sampled from time t29 to t29a, and this reset level NH is held from time t29a to t30.

[0187] In this way, in the first embodiment, the SH circuit SHC1 successively performs a sample operation and a hold operation in accordance with the cycle in which the pixel signals on the vertical signal line VSL are switched. As a result, when a plurality of pixel signals corresponding to a plurality of sensitivities are output to the vertical signal line VSL in sequence, the plurality of pixel signals can be AD converted without providing a plurality of SH circuits SHC1, HC2 and without lengthening one horizontal line period.

[0188] If the timing of AD conversion were the same as in the comparative example, the timing of outputting the pixel signal from the pixel to the vertical signal line VSL would need to be delayed by the sample period, but the sample hold period in the first embodiment does not affect the length of one horizontal line period, so there is no risk of the frame rate slowing down.

[0189] Second Embodiment In order to prevent overexposure even when high-intensity light such as sunlight is incident, it is desirable to increase the capacitance of the charge storage section C14 in the pixel shown in Fig. 3 as much as possible. However, if the capacitance of the charge storage section C14 is increased, there is a risk that it will take a long time to discharge the accumulated charge in the charge storage section C14 when reading out the reset level of the pixel signal at low sensitivity.

[0190] Fig. 18 is a timing diagram of the image pickup device 100 according to the comparative example shown in Fig. 10. This timing diagram assumes that it takes time for the charge storage section C14 of the pixel to discharge.

[0191] The pixel PX outputs a pixel signal of an ultra-low sensitivity reset level NH2DOL to the vertical signal line VSL from time t41 to t42. The third SH circuit SHC3 samples this reset level NH2DOL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t41 to t42. The first SH circuit SHC1 holds the low-sensitivity reset level NL of the (N-2)th row from time t41 to t42, and the ADC 10515 performs AD conversion of the held reset level NL.

[0192] The pixel PX outputs a pixel signal of an ultra-low sensitivity signal level SH2DOL to the vertical signal line VSL from time t42 to t43. The first SH circuit SHC1 samples this signal level SH2DOL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t42 to t43. The third SH circuit SHC3 and the ADC 105 hold and AD convert the ultra-low sensitivity reset level NH2DOL sampled by the third SH circuit SHC3 from time t41 to t42 from time t42 to t43. The signal processing circuit 108 outputs the difference (NL-SL) between the ultra-low sensitivity reset level and the signal level of the (N-2)th row from time t42 to t43.

[0193] The pixel PX outputs a pixel signal of the medium-sensitivity reset level NH2 to the vertical signal line VSL from time t43 to t44. The third SH circuit SHC3 samples this reset level NH2. The second SH circuit SHC2 and the ADC 105 do not perform the sample operation or the hold operation from time t43 to t44. The first SH circuit SHC1 and the ADC 105 hold and AD convert the ultra-low sensitivity signal level SH2DOL sampled by the first SH circuit SHC1 from time t42 to t43 from time t43 to t44. The signal processing circuit 108 outputs the difference (NL-SL) between the ultra-low sensitivity reset level and the signal level of the (N-2)th row from time t43 to t44, following on from times t42 to t43.

[0194] The pixel PX outputs a pixel signal of the high-sensitivity reset level NH1 to the vertical signal line VSL from time t44 to t45. The first to third SH circuits SHC1 to SHC3 and the ADC 105 do not perform sample and hold operations from time t44 to t45. The multiplexer MUX selects the high-sensitivity reset level NH1 on the vertical signal line VSL from time t44 to t45. The signal processing circuit 108 outputs the difference (NH2DOL-SH2DOL) between the ultra-low-sensitivity reset level and the signal level of the Nth row from time t44 to t45.

[0195] The pixel PX outputs a pixel signal of the high-sensitivity signal level SH1 to the vertical signal line VSL from time t45 to t46. The first to third SH circuits SHC1 to SHC3 and the ADC 105 do not perform sample and hold operations from time t45 to t46. The multiplexer MUX selects the high-sensitivity signal level SH1 on the vertical signal line VSL from time t45 to t46. The signal processing circuit 108 outputs the difference between the ultra-low-sensitivity reset level and the signal level (NH2DOL-SH2DOL) from time t45 to t46, following on from time t44 to t45.

[0196] The pixel PX outputs a pixel signal of a medium-sensitivity signal level SH2 to the vertical signal line VSL from time t46 to t47. The first SH circuit SHC1 samples this signal level SH2. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t46 to t47. From time t46 to t47, the ADC 105 holds and AD-converts the medium-sensitivity reset level NH2 sampled by the third SH circuit SHC3 from time t43 to t44. From time t46 to t47, the signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and the signal level of the Nth row.

[0197] The pixel PX outputs a pixel signal of a low-sensitivity signal level SL to the vertical signal line VSL from time t47 to t48. The third SH circuit SHC3 samples this signal level SL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t47 to t48. The first SH circuit SHC1 and the ADC 105 hold and AD convert the medium-sensitivity signal level SH2 sampled by the first SH circuit SHC1 from time t46 to t47 from time t47 to t48. The signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and the signal level of the Nth row from time t47 to t48, following on from time t46 to t47.

[0198] Between times t48 and t49, the ADC 105 holds and AD-converts the low-sensitivity signal level SL sampled by the second SH circuit SHC2 between times t47 and t48. This process is performed between times t16 and t17 in FIG. 8. The first SH circuit SHC1 maintains the sampling operation of the low-sensitivity reset level NL until the discharge of the charge storage unit C14 is completed.

[0199] During the period from time t49 to t50, the pixel signals of the adjacent (N+1)th row are not read out, and the first SH circuit SHC1 waits until the discharge of the charge storage unit C14 is completed. At time t50, the first SH circuit SHC1 completes the sampling operation of the low-sensitivity reset level NL.

[0200] Between times t50 and t51, the first SH circuit SHC1 and the ADC 105 hold and AD convert the low-sensitivity reset level NL sampled by the first SH circuit SHC1 between times t49 and t50. Between times t48 and t50, the signal processing circuit 108 outputs the difference (NH2-SH2) between the medium-sensitivity reset level and the signal level. Thereafter, between times t51 and t52, the signal processing circuit 108 outputs the difference (NL-SL) between the low-sensitivity reset level and the signal level.

[0201] In this way, in the imaging device 100 according to the comparative example, if it takes a long time to read out pixel signals of some sensitivities, the time required for one horizontal line period to read out pixel signals of all sensitivities becomes longer, and the frame rate decreases.

[0202] One way to shorten the time required to read out a plurality of pixel signals corresponding to a plurality of pixels is to further increase the number of SH circuits provided in the sample and hold unit 125 of FIG. 10, provide a dedicated SH circuit for sampling and holding the reset level of low-sensitivity pixel signals, and have another SH circuit sample and hold the next pixel row while this SH circuit is waiting to perform a sampling operation.

[0203] However, the electrical characteristics of the switches and capacitors provided in each SH circuit do not necessarily match due to manufacturing variations, etc. Therefore, the more SH circuits there are in the sample-and-hold unit 125, the greater the variations in the output voltage of the sample-and-hold unit 125 become.

[0204] FIG. 19 is a circuit diagram of a sample-and-hold unit 125 included in an imaging device according to the second embodiment. As shown in FIG. 19, the sample-and-hold unit 125 according to the second embodiment includes one SH circuit SHC1a. The SH circuit SHC1a in FIG. 19 includes switches SW1 to SW3, capacitor Cp1, transistor Tr1, and current source CS1 in the SH circuit SHC1 of FIG. 7, as well as switches SW11 and SW12 and a capacitor Cp11. Capacitor Cp11 is used, for example, to sample and hold pixel signals for sensitivities that require time for settling on the vertical signal line VSL among multiple sensitivities. For example, if the multiple sensitivities include ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity, capacitor Cp11 is used to sample and hold the reset level of a low-sensitivity pixel signal. As will be described later, capacitor Cp11 may also be used for purposes other than those described above. In this specification, the switch (first switch) SW1 and the switch (second switch) SW11 may be referred to as a first switching circuit, and the switch (third switch) SW3 and the switch (fourth switch) SW12 may be referred to as a second switching circuit.

[0205] The switch SW11 and the capacitor Cp11 are connected in series between the vertical signal line VSL and the gate of the transistor Tr1. The switch SW12 is connected between the connection node between the switch SW11 and the capacitor Cp11 and the drain of the transistor Tr1. By individually controlling the switches SW1 to SW3, SW11, and SW12, the capacitors Cp1 and Cp11 can be used to sample and hold pixel signals with different sensitivities.

[0206] FIG. 20 is a timing diagram of a comparative example in which the sample-and-hold unit 125 is provided with first to third SH circuits SHC1 to SHC3, and of the SH circuit SHC1a of the sample-and-hold unit 125 according to the second embodiment shown in FIG.

[0207] In one comparative example, the first and second SH circuits SHC1 and SHC2 alternate between sample and hold operations during each sample and hold period. That is, while the first SH circuit SHC1 in one comparative example is performing a sample operation, the second SH circuit SHC2 is performing a hold operation, and while the second SH circuit SHC2 in one comparative example is performing a hold operation, the first SH circuit SHC1 is performing a sample operation. In one comparative example, the third SH circuit SHC3 is performing a sample and hold operation of the reset level of a low-sensitivity pixel signal. After performing a sample and hold operation of the reset level of a low-sensitivity pixel signal, the third SH circuit SHC3 in one comparative example waits until the discharge of the charge storage unit C14 of the pixel is completed, and continues the hold state until the discharge of the charge storage unit C14 is completed. Because the third SH circuit SHC3 continues to hold the voltage at the time of sampling, kTC noise is not added.

[0208] On the other hand, the SH circuit SHC1a in the second embodiment uses capacitor Cp1 to continuously perform sample and hold operations within a unit period, similar to the SH circuit SHC1 in the first embodiment. Furthermore, the SH circuit SHC1a in the second embodiment uses capacitor Cp11 to sample and hold the reset level of a low-sensitivity pixel signal. After performing the sample operation of this reset level, the SH circuit SHC1a in the second embodiment places capacitor Cp11 in the SH circuit SHC1a in a high-impedance state. After discharging of the pixel's charge storage section C14 is completed, the SH circuit SHC1a performs a hold operation using capacitor Cp11. The output voltage of the SH circuit SHC1a is not the same during the sample operation and the hold operation. For this reason, kTC noise is added to the output voltage of the SH circuit SHC1a. However, because optical shot noise becomes a dominant term compared to kTC noise at high illuminance, the addition of kTC noise is not a practical problem when used at high illuminance, i.e., at low sensitivity.

[0209] The period during which the SH circuit SHC1a in the second embodiment puts the capacitor Cp11 into a high-impedance state depends on the time required for the pixel signal on the vertical signal line VSL to settle. During the period during which the capacitor Cp11 is put into a high-impedance state, the SH circuit SHC1a alternately performs a sample operation using the capacitor Cp1, which turns on the switches SW1 and SW5 and turns off the switch SW3, and a hold operation using the capacitor Cp1, which turns off the switches SW1 and SW5 and turns on the switch SW3.

[0210] In this way, in the second embodiment, two capacitors Cp1 and Cp11 are provided in the sample-and-hold unit 125, and each capacitor can be arbitrarily switched between performing a sample operation, performing a hold operation, or entering a high impedance state. Therefore, even if it takes a long time for the charge storage unit C14 of a pixel to discharge, by operating the capacitors Cp1 and Cp11 separately, it is possible to read out a plurality of pixel signals corresponding to a plurality of sensitivities without lengthening one horizontal line period.

[0211] Third Embodiment The capacitor Cp11 in the SH circuit according to the second embodiment is not only used for the sampling operation and reset operation of low-sensitivity pixel signals, but can also be charged and discharged in synchronization with the capacitor Cp1.

[0212] The imaging device 1 according to the third embodiment has the same configuration as the imaging device 1 according to the second embodiment. Specifically, like the imaging device 1 according to the second embodiment, the imaging device 1 according to the third embodiment has an SH circuit SHC1a having the circuit configuration shown in FIG.

[0213] The SH circuit SHC1a according to the third embodiment can switch between normal operation and low-noise operation by turning on / off the switches SW1 to SW3, SW11, and SW12 in Fig. 19. In this specification, the normal operation may be referred to as the first mode, and the low-noise operation may be referred to as the second mode.

[0214] Fig. 21 is a timing diagram during normal operation, and Fig. 22 is a timing diagram during low-noise operation. During normal operation in Fig. 21, the SH circuit SHC1a alternately repeats a sample operation using capacitor Cp1 that turns on switches SW1 and SW3 and turns off switch SW2, and a hold operation using capacitor Cp1 that turns off switches SW1 and SW3 and turns on switch SW2. In parallel with this, during normal operation, switches SW11 and SW12 are turned off to put capacitor Cp11 into a high-impedance state.

[0215] In this way, during normal operation, the capacitor Cp11 is always in a high impedance state, and the sample operation and the hold operation are performed alternately using the capacitor Cp1, so during normal operation, the same sample and hold operation as the SH circuit SHC1 according to the first embodiment is performed.

[0216] In the low-noise operation of FIG. 22, a sample operation using capacitors Cp1 and Cp11 that turns on switches SW1, SW3, and SW11 and turns off switches SW2 and SW12, and a hold operation using capacitors Cp1 and Cp11 that turns off switches SW1, SW3, and SW11 and turns on switches SW2 and SW12 are performed alternately.

[0217] This allows the capacitors Cp1 and Cp11 to be charged and discharged in synchronization during low-noise operation, thereby increasing the total amount of charge to be sampled and held and reducing kTC noise.

[0218] During normal operation, the capacitor Cp11 is in a high impedance state, and therefore there is a risk that the output voltage of the SH circuit SHC1a may fluctuate due to interference from this capacitor Cp11.

[0219] 23A is a diagram showing how the voltage at the output node of the SH circuit SHC1a fluctuates due to the capacitor Cp11 being in a high-impedance state. During both a sample operation in which the switches SW1 and SW3 connected to the capacitor Cp1 are turned on and the switch SW2 is turned off, and during a hold operation in which the switches SW1 and SW3 are turned off and the switch SW2 is turned on, the voltage across the capacitor Cp11 is unstable, so the output node of the SH circuit SHC1a may fluctuate.

[0220] Fig. 23B is a circuit diagram of an SH circuit SHC1a to which interference countermeasures have been implemented. The SH circuit SHC1a of Fig. 23B has a configuration in which a switch (sixth switch) SW13 and a switch (seventh switch) SW14 are added to the SH circuit SHC1a of Fig. 23A. The switch SW13 is connected between the capacitor Cp1 and the gate of the transistor Tr1. The switch SW14 is connected between the capacitor Cp11 and the gate of the transistor Tr1. In this specification, the switches SW13 and SW14 may be referred to as an interference countermeasure circuit.

[0221] The timing diagram of Figure 23A is similar to Figure 21. Figure 24 is a timing diagram of Figure 23B. While the sampling operation and holding operation are being performed using capacitor Cp1, switch SW13 is on. On the other hand, switch SW14 is always off. This prevents capacitor Cp11, which is in a high impedance state, from interfering with the output node of the SH circuit.

[0222] The circuit configuration for preventing interference of the capacitor Cp11 is not limited to that shown in FIG. 23B, and various modifications are possible.

[0223] Fig. 25 is a circuit diagram of an SH circuit SHC1b according to the first modification of Fig. 23B. The SH circuit SHC1b of Fig. 25 includes a switch (eighth switch) SW15 in addition to the SH circuit of Fig. 23B. The switch SW15 is connected between the connection node between the switch SW1 and the capacitor Cp1 and the connection node between the switch SW11 and the capacitor Cp11.

[0224] Figure 26 is a timing diagram of the SH circuit SHC1b in Figure 25. During the sample period of capacitor Cp1, when switches SW1 and SW3 are on and switch SW2 is off, switch SW15 is turned on. This allows sampling to be performed using both capacitors Cp1 and Cp11. Thereafter, during the hold period of capacitor Cp1, when switches SW1 and SW3 are off and switch SW2 is on, switch SW15 is turned off.

[0225] In this way, the SH circuit SHC1b according to the first modification performs a sampling operation using the capacitors Cp1 and Cp11, and therefore the total amount of charge that can be stored can be increased, and kTC noise can be reduced.

[0226] Fig. 27 is a circuit diagram of an SH circuit SHC1c according to the second modification of Fig. 23B, and Fig. 28 is a timing diagram of the SH circuit SHC1c of Fig. 27. In addition to the SH circuit SHC1b of Fig. 23B, the SH circuit SHC1c of Fig. 27 includes a switch (ninth switch) SW16 and a switch (tenth switch) SW17. The switch SW16 is always off, so both ends of the capacitor Cp1 are never short-circuited. The switch SW17 switches whether or not both ends of the capacitor Cp11 are short-circuited.

[0227] 28, switch SW17 is always on, while switch SW16 is always off. As a result, both ends of capacitor Cp11 are always shorted, and both ends of capacitor Cp1 are never shorted. Therefore, capacitor Cp1 can alternately perform sample and hold operations, and during the hold period of capacitor Cp1, the output node of the SH circuit SHC1c is not affected by capacitor Cp11, which is in a high impedance state.

[0228] As described above, in the third embodiment, the sample-and-hold unit 125 alternately switches between normal operation and low-noise operation to sample and hold pixel signals on the signal lines, and during normal operation, the first through fifth switches SW5 are switched to alternately perform a sample operation and a hold operation using the capacitor Cp1, and the capacitor Cp11 is set to a high-impedance state. During low-noise operation, a sample operation using the capacitor Cp1 that turns on the switches SW1 and SW5 and turns off the switch SW3 and a hold operation using the capacitor Cp1 that turns off the switches SW1 and SW5 and turns on the switch SW3 are alternately performed, while a sample operation using the capacitor Cp11 that turns on the switches SW2 and SW5 and turns off the switch SW4 and a hold operation using the capacitor Cp11 that turns off the switches SW2 and SW5 and turns on the switch SW4 are alternately performed.

[0229] According to the third embodiment, by charging and discharging the capacitors Cp1 and Cp11 in synchronization during low-noise operation, the total amount of charge during sample-and-hold can be increased, thereby reducing kTC noise. Also, by connecting a new switch to the capacitor Cp11, which is in a high-impedance state during normal operation, it is possible to prevent the capacitor Cp11 in the high-impedance state from interfering with the output node of the SH circuit.

[0230] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0231] FIG. 29 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0232] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 29, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0233] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0234] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0235] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0236] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0237] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0238] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0239] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0240] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0241] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 29, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0242] FIG. 30 is a diagram showing an example of the installation position of the imaging unit 12031.

[0243] In FIG. 30, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0244] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0245] 30 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0246] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0247] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0248] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0249] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0250] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the components described above. Specifically, the imaging device 1 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0251] The present technology can be configured as follows. (1) An imaging device comprising: a pixel having a photoelectric conversion element that accumulates a charge corresponding to the amount of incident light, and that generates a pixel signal corresponding to the charge; a signal line that transmits the pixel signal; a sample and hold circuit that continuously performs a sample operation and a hold operation of the pixel signal on the signal line in accordance with a period in which the pixel signal on the signal line switches; and an analog-to-digital converter that converts the pixel signal held by the sample and hold circuit into a digital pixel signal. (2) The imaging device described in (1), in which the sample and hold circuit alternately switches between the sample operation and the hold operation each time the pixel signal on the signal line switches. (3) The imaging device described in (1) or (2), in which the sample and hold circuit performs the sample operation after a settling operation of the pixel signal on the signal line has finished, and performs the hold operation in parallel with the settling operation. (4) The imaging device according to (3), wherein the analog-to-digital converter has a comparator that compares the pixel signal held by the sample and hold circuit with a reference signal, and the sample and hold circuit performs the holding operation in accordance with a period during which the reference signal changes over time. (5) The imaging device according to any one of (1) to (4), wherein the sample and hold circuit has: a sample and hold capacitor that accumulates a charge corresponding to the pixel signal on the signal line, a first switching circuit connected between the signal line and a first end of the sample and hold capacitor, a second switching circuit connected between the first end of the sample and hold capacitor and an output node of the sample and hold circuit, a third switching circuit connected between a second end of the sample and hold capacitor and an output node of the sample and hold circuit, and a transistor that outputs a signal corresponding to a voltage level of the second end from the output node.(6) The imaging device according to (5), wherein the sample and hold circuit performs the sample operation by turning on the first switching circuit to electrically connect the signal line and the first end, turning on the third switching circuit to electrically connect the second end and the output node, turning off the second switching circuit to electrically disconnect the first end and the output node, turning off the first switching circuit to electrically disconnect the signal line and the first end, turning off the third switching circuit to electrically disconnect the second end and the output node, and turning on the second switching circuit to electrically connect the first end and the output node. (7) The imaging device according to (5) or (6), comprising: a pixel array unit having a plurality of the pixels arranged in a first direction and a second direction intersecting each other; and a plurality of the signal lines arranged in the first direction and transmitting two or more pixel signals generated by two or more of the pixels arranged in the second direction, wherein the sample and hold circuit and the analog-to-digital converter are provided for each of the plurality of signal lines. (8) The imaging device according to (7), wherein each of the plurality of pixels outputs a plurality of the pixel signals having different sensitivities at different times, and the sample-and-hold circuit alternately switches between a sampling operation and a holding operation of the plurality of pixel signals for each of the plurality of sensitivities. (9) The imaging device according to (8), wherein the sample-and-hold circuit alternately switches between a sampling operation and a holding operation of signal levels and reset levels of the plurality of pixel signals for each of the plurality of sensitivities.(10) The imaging device according to (9), wherein the sample and hold capacitance has at least a first capacitor and a second capacitor, the first switching circuit has a first switch connected between the signal line and a first end of the first capacitor, and a second switch connected between the signal line and a first end of the second capacitor, the second switching circuit has a third switch connected between the first end of the first capacitor and the output node, and a fourth switch connected between the first end of the second capacitor and the output node, and the third switching circuit has a fifth switch connected between a second end of the first capacitor and the output node and between the second end of the second capacitor and the output node. (11) The imaging device according to (10), wherein the second capacitor is used to sample and hold a pixel signal for a sensitivity that requires time for settling on the signal line among the plurality of sensitivities. (12) The imaging device according to (11), wherein the plurality of sensitivities include ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity, and the second capacitor is used to sample and hold a reset level of a low-sensitivity pixel signal. (13) The imaging device according to any one of (10) to (12), wherein the sample-and-hold circuit turns on the second switch and the fifth switch and turns off the fourth switch to sample the pixel signal on the signal line by the second capacitor, then turns off the second switch, the fourth switch, and the fifth switch to put the second capacitor into a high-impedance state, and then turns off the second switch and the fifth switch and turns on the fourth switch, thereby holding the pixel signal sampled by the second capacitor. (14) The imaging device according to (13), wherein a period during which the second capacitor is put into a high-impedance state depends on a time required for settling of the pixel signal on the signal line.(15) The imaging device described in (13) or (14), wherein during a period in which the second capacitor is in a high impedance state, the sampling operation using the first capacitor, which turns on the first switch and the fifth switch and turns off the third switch, and the holding operation using the first capacitor, which turns off the first switch and the fifth switch and turns on the third switch, are alternately performed. (16) The imaging device described in any one of (13) to (15), wherein the sample and hold circuit alternatively switches between a first mode and a second mode to sample and hold the pixel signal on the signal line, and in the first mode, the sample operation and the hold operation are alternately performed using the first capacitor by switching the first to fifth switches, and the second capacitor is set to a high impedance state, and in the second mode, the sample operation using the first capacitor by turning on the first switch and the fifth switch and turning off the third switch and the hold operation using the first capacitor by turning off the first switch and the fifth switch and turning on the third switch are alternately performed, in parallel with the sample operation using the second capacitor by turning on the second switch and the fifth switch and turning off the fourth switch and the hold operation using the second capacitor by turning off the second switch and the fifth switch and turning on the fourth switch are alternately performed. (17) The imaging device according to any one of (13) to (15), wherein the sample-and-hold circuit includes an interference countermeasure circuit to prevent the gate voltage of the transistor from fluctuating due to the second capacitor being in a high-impedance state.(18) The imaging device according to (17), wherein the interference countermeasure circuit includes: a sixth switch connected between the second end of the first capacitor and the gate of the transistor; and a seventh switch connected between the second end of the second capacitor and the gate of the transistor, and when the first capacitor is not in a high impedance state and the second capacitor is in a high impedance state, the sample and hold circuit turns on the sixth switch to electrically connect the second end of the first capacitor to the gate of the transistor and turns off the seventh switch to cut off the connection between the second end of the second capacitor and the gate of the transistor. (19) The imaging device according to (17), wherein the interference countermeasure circuit includes an eighth switch connected between the first end of the first capacitor and the first end of the second capacitor, and when the second capacitor is put into a high impedance state, the sample and hold circuit turns on the eighth switch to short-circuit the first end of the first capacitor and the first end of the second capacitor in synchronization with sampling the pixel signal on the signal line by the first capacitor. (20) The imaging device described in (17), wherein the sample and hold circuit has: a ninth switch that switches whether or not the first and second ends of the first capacitor are short-circuited; and a tenth switch that switches whether or not the first and second ends of the second capacitor are short-circuited; and when the second capacitor is put into a high impedance state, the sample and hold circuit keeps the ninth switch always in an off state and the tenth switch always in an on state while the first capacitor is alternately performing the sample operation and the hold operation.

[0252] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0253] 1 Imaging device, 12 VSL boost circuit, 100 Imaging device, 101 Pixel array section, 102 Timing control circuit, 103 Vertical scanning circuit, 104 Charge storage section, 106 Horizontal transfer scanning circuit, 107 Amplifier circuit, 108 Signal processing circuit, 109 Pixel drive line, 111 Horizontal transfer line, 121 Comparator, 121a Input comparison circuit, 121b Output circuit, 122 Counter, 123 Latch circuit, 125 Sample and hold section, 310 Negative capacitance circuit, 511 Semiconductor chip, 512 Semiconductor chip, 513 Via area, 514 Via area, 516 Logic circuit, 517 Peripheral circuit

Claims

1. An imaging device comprising: pixels each having a photoelectric conversion element that accumulates an electric charge according to the amount of incident light, and that generate a pixel signal according to the electric charge; a signal line that transmits the pixel signal; a sample-and-hold circuit that continuously samples and holds the pixel signal on the signal line in accordance with the cycle at which the pixel signal on the signal line switches; and an analog-to-digital converter that converts the pixel signal held by the sample-and-hold circuit into a digital pixel signal.

2. The imaging device according to claim 1, wherein the sample and hold circuit alternately switches between the sample operation and the hold operation every time the pixel signal on the signal line switches.

3. The imaging device according to claim 1, wherein the sample and hold circuit performs the sampling operation after a settling operation of the pixel signal on the signal line has finished, and performs the holding operation in parallel with the settling operation.

4. The imaging device according to claim 3, wherein the analog-to-digital converter has a comparator that compares the pixel signal held by the sample-and-hold circuit with a reference signal, and the sample-and-hold circuit performs the holding operation in accordance with a period during which the reference signal changes over time.

5. The imaging device of claim 1, wherein the sample and hold circuit comprises: a sample and hold capacitor that accumulates charge corresponding to the pixel signal on the signal line; a first switching circuit connected between the signal line and a first end of the sample and hold capacitor; a second switching circuit connected between the first end of the sample and hold capacitor and an output node of the sample and hold circuit; a third switching circuit connected between a second end of the sample and hold capacitor and an output node of the sample and hold circuit; and a transistor that outputs a signal corresponding to the voltage level of the second end from the output node.

6. The imaging device according to claim 5, wherein the sample and hold circuit performs the sample operation by turning on the first switching circuit to electrically connect the signal line and the first terminal, turning on the third switching circuit to electrically connect the second terminal and the output node, turning off the second switching circuit to electrically disconnect the first terminal and the output node, turning off the first switching circuit to electrically disconnect the signal line and the first terminal, turning off the third switching circuit to electrically disconnect the second terminal and the output node, and turning on the second switching circuit to electrically connect the first terminal and the output node.

7. An imaging device according to claim 5, comprising: a pixel array section having a plurality of the pixels arranged in a first direction and a second direction that intersect with each other; and a plurality of the signal lines that are arranged in the first direction and transmit a plurality of the pixel signals generated by two or more of the pixels arranged in the second direction, wherein the sample-and-hold circuit and the analog-to-digital converter are provided for each of the plurality of signal lines.

8. The imaging device according to claim 7, wherein each of the plurality of pixels outputs a plurality of pixel signals having different sensitivities at different times, and the sample-and-hold circuit alternately switches between sampling and holding the plurality of pixel signals for each of the plurality of sensitivities.

9. The imaging device according to claim 8, wherein the sample-and-hold circuit alternately switches between sampling and holding the signal levels and reset levels of the plurality of pixel signals for each of a plurality of sensitivities.

10. The imaging device of claim 9, wherein the sample and hold capacitance has at least a first capacitor and a second capacitor; the first switching circuit has a first switch connected between the signal line and a first end of the first capacitor, and a second switch connected between the signal line and a first end of the second capacitor; the second switching circuit has a third switch connected between the first end of the first capacitor and the output node, and a fourth switch connected between the first end of the second capacitor and the output node; and the third switching circuit has a fifth switch connected between the second end of the first capacitor and the output node, and between the second end of the second capacitor and the output node.

11. The imaging device according to claim 10, wherein the second capacitor is used to sample and hold pixel signals for a sensitivity that requires time for settling on the signal line, among the plurality of sensitivities.

12. The imaging device according to claim 11, wherein the plurality of sensitivities include an ultra-low sensitivity, a low sensitivity, a medium sensitivity, and a high sensitivity, and the second capacitor is used to sample and hold a reset level of a low-sensitivity pixel signal.

13. The imaging device according to claim 10, wherein the sample-and-hold circuit turns on the second switch and the fifth switch and turns off the fourth switch to sample the pixel signal on the signal line using the second capacitor, then turns off the second switch, the fourth switch, and the fifth switch to put the second capacitor into a high impedance state, and then turns off the second switch and the fifth switch and turns on the fourth switch, thereby holding the pixel signal sampled by the second capacitor.

14. The imaging device according to claim 13, wherein the period during which the second capacitor is in a high impedance state depends on the time required for the pixel signal on the signal line to settle.

15. The imaging device according to claim 13, wherein, during a period in which the second capacitor is in a high impedance state, the sample operation using the first capacitor, in which the first switch and the fifth switch are turned on and the third switch is turned off, and the hold operation using the first capacitor, in which the first switch and the fifth switch are turned off and the third switch is turned on, are alternately performed.

16. The imaging device according to claim 13, wherein the sample and hold circuit alternately switches between a first mode and a second mode to sample and hold the pixel signal on the signal line, and in the first mode, the first to fifth switches are switched to alternately perform the sample operation and the hold operation using the first capacitor, and the second capacitor is set to a high impedance state, and in the second mode, the sample operation using the first capacitor by turning on the first switch and the fifth switch and turning off the third switch and the hold operation using the first capacitor by turning off the first switch and the fifth switch and turning on the third switch are alternately performed, while the sample operation using the second capacitor by turning on the second switch and the fifth switch and turning off the fourth switch and the hold operation using the second capacitor by turning off the second switch and the fifth switch and turning on the fourth switch are alternately performed.

17. The imaging device according to claim 13, wherein the sample-and-hold circuit includes an anti-interference circuit to prevent the gate voltage of the transistor from fluctuating due to the second capacitor being in a high-impedance state.

18. The imaging device of claim 17, wherein the interference countermeasure circuit has a sixth switch connected between the second end of the first capacitor and the gate of the transistor, and a seventh switch connected between the second end of the second capacitor and the gate of the transistor, and when the first capacitor is not in a high impedance state and the second capacitor is in a high impedance state, the sample and hold circuit turns on the sixth switch to electrically connect the second end of the first capacitor to the gate of the transistor, and turns off the seventh switch to cut off the connection between the second end of the second capacitor and the gate of the transistor.

19. The imaging device described in claim 17, wherein the interference countermeasure circuit has an eighth switch connected between the first end of the first capacitor and the first end of the second capacitor, and the sample-and-hold circuit, when putting the second capacitor into a high-impedance state, turns on the eighth switch in accordance with the timing at which the pixel signal on the signal line is sampled by the first capacitor, thereby short-circuiting the first end of the first capacitor and the first end of the second capacitor.

20. The imaging device of claim 17, wherein the sample-and-hold circuit has a ninth switch that switches whether the first and second ends of the first capacitor are short-circuited, and a tenth switch that switches whether the first and second ends of the second capacitor are short-circuited, and when the second capacitor is set to a high impedance state, the sample-and-hold circuit keeps the ninth switch always in an off state and the tenth switch always in an on state while the first capacitor is alternately performing the sampling operation and the holding operation.

Images