Imaging device

Abstract

[Problem] To make it possible to read a plurality of pixel signals corresponding to a plurality of sensitivities without lengthening a horizontal line period. [Solution] An imaging device comprising: pixels that each have a photoelectric conversion element for accumulating charge corresponding to the amount of incident light and generate a pixel signal corresponding to the charge; signal lines for transmitting the pixel signals; an analog-digital converter for converting the pixel signals on the signal lines into digital pixel signals; three or more sample-and-hold circuits for sampling and holding the pixel signals on the signal lines; and a selection circuit for selecting any one of the three or more held signals held by the sample-and-hold circuits and the pixel signals on the signal lines, and supplying the signal to the analog-digital converter.

Description

Imaging device

[0001] An embodiment of the present invention relates to an imaging device.

[0002] CMOS (Complementary Metal Oxide Semiconductor) image sensors (hereinafter also referred to as CIS) have become widespread. These sensors perform analog-to-digital (AD) conversion of pixel signals by using a comparator to compare an analog pixel signal with a linearly changing reference signal and counting the time until the reference signal intersects with the pixel signal.

[0003] Recently, CIS with HDR (High Dynamic Range) functionality, which captures images by switching between multiple sensitivities by providing multiple photodiodes or charge storage capacitors in each pixel of the pixel array, has been attracting attention.

[0004] To capture images by switching between multiple sensitivities, multiple AD conversions are required, which must be performed after ensuring a settling time until the voltage of the floating diffusion region stabilizes, making it difficult to achieve HDR functionality at a high frame rate.

[0005] Therefore, a technique has been proposed in which pixel signal sampling and AD conversion are performed in parallel at a plurality of sensitivities (see Patent Document 1).

[0006] In Patent Document 1, in order to widen the dynamic range, a large-capacity capacitor is provided in each pixel of the pixel array section, so that electric charges overflowing from the photodiode at times of high illuminance can be stored in the capacitor.

[0007] International Publication No. 2022 / 172714A1

[0008] However, if a large-capacity capacitor is provided for each pixel in the pixel array section, it takes time for the capacitor to discharge, and therefore, when maintaining the reset level of the pixel signal, it is necessary to wait until the capacitor has completely discharged, which lengthens the horizontal line period and results in a lower frame rate.

[0009] Therefore, the present disclosure provides an imaging device that can read out multiple pixel signals corresponding to multiple sensitivities without lengthening the period of one horizontal line, even when a large-capacity capacitor is provided in each pixel of the pixel array section.

[0010] In order to solve the above problem, according to one embodiment of the present invention, there is provided an imaging device comprising: a pixel having a photoelectric conversion element that accumulates an electric charge according to the amount of incident light, and that generates a pixel signal according to the electric charge; a signal line that transmits the pixel signal; an analog-to-digital converter that converts the pixel signal on the signal line into a digital pixel signal; three or more sample-and-hold circuits that sample and hold the pixel signal on the signal line; and a selection circuit that selects one of the three or more hold signals held by the three or more sample-and-hold circuits and the pixel signal on the signal line, and supplies the selected signal to the analog-to-digital converter.

[0011] The pixel array unit may include a pixel array section having a plurality of pixels arranged in a first direction and a second direction that intersect with each other; and a plurality of signal lines that are arranged in the first direction and transmit pixel signals generated by two or more of the pixels arranged in the second direction, wherein the three or more sample-and-hold circuits, the selection circuit, and the analog-to-digital converter are provided for each of the signal lines.

[0012] Of the three or more sample and hold circuits provided for each of the plurality of signal lines, a sample and hold circuit that samples and holds the pixel signal that takes time to stabilize may sample and hold the pixel signal after a waiting period until the pixel signal stabilizes, and other sample and hold circuits may sample and hold the pixel signals generated by other pixels during the waiting period.

[0013] Each of the plurality of pixels may output a plurality of pixel signals having different sensitivities at different times, and the three or more sample-and-hold circuits and the analog-to-digital converter may perform a sampling operation, a holding operation, and an analog-to-digital conversion operation of the plurality of pixel signals having different sensitivities in parallel.

[0014] Each of the plurality of pixels may switch the sensitivity of the corresponding pixel between four or more levels, and may divide the pixel signal into a signal level and a reset level for each sensitivity and output the divided signal level and reset level with a time lag, and the three or more sample-and-hold circuits provided for each of the plurality of signal lines may sample and hold the signal level and reset level of the pixel signal with a time lag for each sensitivity.

[0015] The signal level and the reset level of the pixel signals of the same sensitivity may be sampled and held by the same sample and hold circuit.

[0016] The pixel array unit has a plurality of pixel groups arranged in the second direction, each of which includes two or more of the pixels arranged in the first direction, and sample and hold circuits other than some of the three or more sample and hold circuits may sample and hold pixel signals output to the signal line from a pixel group other than any of the pixel groups during a period when the some of the sample and hold circuits are waiting to sample the pixel signal in any of the pixel groups.

[0017] The pixel has a charge accumulation section that stores accumulated charge in the photoelectric conversion element, and the some of the sample and hold circuits wait until discharge of the charge accumulation section of the pixel to be read out of one of the pixel groups is completed, and then sample and hold the pixel signal, and the sample and hold circuits other than the some of the sample and hold circuits among the three or more sample and hold circuits may sample and hold the pixel signal output to the signal line from a pixel group different from one of the pixel groups during a discharge period of the charge accumulation section.

[0018] The any one of the pixel groups and the different pixel group may be a first pixel group and a second pixel group adjacent to each other in the second direction.

[0019] One of the three or more sample and hold circuits may sample and hold a pixel signal output to the signal line from the first pixel group including the pixel having the charge storage section whose discharge has finished, and the other sample and hold circuits of the three or more sample and hold circuits may sample and hold a pixel signal output to the signal line from the second pixel group during the discharge period of the charge storage section.

[0020] One of the three or more sample and hold circuits may sample and hold a reset level of the pixel signal after the charge storage section is discharged, after a sample and hold circuit other than the one sample and hold circuit samples and holds a pixel signal output from the second pixel group to the signal line and the analog-to-digital converter converts it into a digital pixel signal.

[0021] The selection circuit may select in turn the hold signals of the sample and hold circuits other than the one sample and hold circuit among the three or more sample and hold circuits and the pixel signal on the signal line during a period in which the one sample and hold circuit is waiting until the discharge of the charge accumulation unit is completed, and then select a reset level of the pixel signal after the discharge of the charge accumulation unit that has been sampled and held by the one sample and hold circuit.

[0022] The pixel may include a plurality of the photoelectric conversion elements each having a different light receiving area, and the charge storage section may hold charges photoelectrically converted by at least some of the plurality of photoelectric conversion elements.

[0023] The pixel may have a first photoelectric conversion element, a first floating diffusion region, a second floating diffusion region, a second photoelectric conversion element, a first transistor that switches whether or not to transfer at least a portion of the charge photoelectrically converted and accumulated in the first photoelectric conversion element and the charge held in the first floating diffusion region to the second floating diffusion region, and a second transistor that discharges the charge held in the charge accumulation portion, and the charge accumulation portion may hold the charge photoelectrically converted in the second photoelectric conversion element.

[0024] The image sensor may further include a signal processing circuit that generates, for each of four or more sensitivities based on the digital pixel signal, a differential signal between a reset level and a signal level of the digital pixel signal, and a delay circuit that aligns the timing of the differential signals so that the differential signals corresponding to the four or more sensitivities are output at the same timing.

[0025] The delay circuit may align the timing of the plurality of differential signals to match the timing at which one of the three or more sample-and-hold circuits holds a pixel signal output to the signal line from a pixel group having the charge storage section that has finished discharging.

[0026] Each of the plurality of pixels may generate four pixel signals having four different sensitivities, each divided into a signal level and a reset level.

[0027] The four sensitivities may be ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity, and during a standby period in which any of the three or more sample-and-hold circuits samples and holds a reset level of the pixel signal of the ultra-low sensitivity, at least one other sample-and-hold circuit may sample and hold the pixel signals of the low sensitivity, the medium sensitivity, and the high sensitivity in another pixel group arranged in the second direction.

[0028] The selection circuit may select one of the three hold signals sampled and held by the three sample and hold circuits and the pixel signal on the signal line and supply the selected signal to the analog-to-digital converter; of the three sample and hold circuits, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals within one horizontal line period; the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the reset level of the low-sensitivity pixel signal in a horizontal line period following the one horizontal line period; and the remaining sample and hold circuits may sample and hold the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals in the next horizontal line period.

[0029] The selection circuit may select one of the four hold signals sampled and held by the four sample and hold circuits and the pixel signal on the signal line and supply the selected signal to the analog-to-digital converter; of the four sample and hold circuits, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals within one horizontal line period; the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the reset level of the low-sensitivity pixel signal within two horizontal line periods following the one horizontal line period; and the remaining sample and hold circuits may sample and hold the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals of two pixel groups adjacent in the second direction during the next two horizontal line periods.

[0030] 12. A block diagram showing a schematic configuration of an imaging device according to a first embodiment of the present disclosure. A conceptual diagram showing an example of an imaging device in which a semiconductor chip of a pixel array section and a semiconductor chip of a processing circuit are stacked. A circuit diagram showing the basic configuration of a high dynamic range pixel. A timing chart of each drive signal at the start of exposure of a pixel. A diagram showing the S / N ratio of a pixel signal obtained by combining four pixel signals captured at four sensitivities. A timing chart when reading out a pixel signal from a pixel. A circuit diagram of a main part of an imaging device according to a first embodiment. A timing chart of an imaging device according to the first embodiment. A circuit diagram of a main part of an imaging device according to a comparative example. A timing chart of an imaging device according to a comparative example. A circuit diagram of a main part of an imaging device according to a second embodiment. A circuit diagram of a main part of an imaging device according to a modified example of the second embodiment. A voltage waveform diagram of an output node of the input comparison circuit of FIG. 12. A circuit diagram of a main part of an imaging device according to a third embodiment. A timing chart of an imaging device according to the third embodiment. A diagram showing an example of a delay circuit provided in a signal processing circuit. A block diagram showing an example of a schematic configuration of a vehicle control system. An explanatory diagram showing an example of the installation positions of an outside information detection unit and an imaging unit.

[0031] Hereinafter, an embodiment of an imaging device will be described with reference to the drawings. The following description will focus on the main components of the imaging device, but the imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0032] 1 is a block diagram showing a schematic configuration of an image pickup device 1 according to a first embodiment of the present disclosure. The image pickup device 1 includes a pixel array unit 101, a timing control circuit 102, a vertical scanning circuit 103, a DAC (digital-to-analog converter) 104, an ADC (analog-to-digital converter) 105, a horizontal transfer scanning circuit 106, an amplifier circuit 107, and a signal processing circuit 108.

[0033] The pixel array unit 101 has unit pixels (hereinafter simply referred to as pixels) arranged in a matrix, each of which includes a photoelectric conversion element that photoelectrically converts incident light into an electric charge (pixel signal) corresponding to the amount of light. In this specification, the row direction may be referred to as a first direction, and the column direction may be referred to as a second direction. The pixel array unit 101 has a plurality of pixel rows arranged in the column direction, each of which includes a plurality of pixels aligned in the row direction. In this specification, these pixel rows may be referred to as pixel groups.

[0034] The specific circuit configuration of the pixel will be described later. Furthermore, in the pixel array unit 101, pixel drive lines 109 are wired for each row of the matrix-like pixel arrangement along the left-right direction of the drawing (the pixel arrangement direction / horizontal direction of the pixel rows), and vertical signal lines VSL are wired for each column along the up-down direction of the drawing (the pixel arrangement direction / vertical direction of the pixel columns). One end of each pixel drive line 109 is connected to an output terminal of the vertical scanning circuit 103 corresponding to each row. Although FIG. 1 shows one pixel drive line 109 for each pixel row, two or more pixel drive lines 109 may be provided for each pixel row.

[0035] The timing control circuit 102 includes a timing generator (not shown) that generates various timing signals. The timing control circuit 102 controls the driving of the vertical scanning circuit 103, the DAC 104, the multiple ADCs 105, the horizontal transfer scanning circuit 106, etc., based on the various timing signals generated by the timing generator in response to externally applied control signals, etc.

[0036] The vertical scanning circuit 103 is made up of a shift register, an address decoder, etc. Although the specific configuration is not shown here, the vertical scanning circuit 103 includes a read scanning system and a sweep scanning system.

[0037] The readout scanning system sequentially selects and scans the unit pixels from which signals are read out, row by row. Meanwhile, the sweep scanning system performs sweep scanning on the readout row being read out by the readout scanning system, sweeping out (resetting) unnecessary charges from the photoelectric conversion elements of the unit pixels of that readout row, prior to the readout scanning by the readout scanning system by the shutter speed. This sweeping out (resetting) of unnecessary charges by the sweep scanning system results in a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the photoelectric charge in the photoelectric conversion element and starting a new exposure (starting the accumulation of photoelectric charge). The signal read out by the readout operation by the readout scanning system corresponds to the amount of light incident since the previous readout operation or electronic shutter operation. The period from the readout timing of the previous readout operation or the sweeping timing of the electronic shutter operation to the readout timing of the current readout operation is the photoelectric charge accumulation time (exposure time) in the unit pixel.

[0038] Pixel signals (analog signals) output from each unit pixel of a pixel row selected and scanned by the vertical scanning circuit 103 are supplied to a plurality of ADCs 105 via a plurality of vertical signal lines VSL corresponding to each column.

[0039] The DAC 104 generates a reference signal RAMP, which is a linearly changing ramp waveform signal, and supplies the reference signal RAMP to the plurality of ADCs 105. The DAC 104 is commonly connected to the plurality of comparators 121 via a reference signal line RAMP, and supplies the same reference signal RAMP to the plurality of comparators 121. The reference signal line RAMP transmits the reference signal RAMP to the plurality of comparators 121.

[0040] Each of the plurality of ADCs 105 includes a comparator 121, a counter 122, and a plurality of latch circuits 123. The plurality of ADCs 105 converts pixel signals (analog signals) from the pixel array unit 101 into digital signals.

[0041] The comparator 121, the counter 122, and the latch circuit 123 are provided corresponding to the pixel columns of the pixel array unit 101, and constitute the ADC 105a. The ADC 105a is provided for each pixel column in the column direction.

[0042] The comparator 121 compares the voltage of the signal obtained by adding the pixel signal output from each pixel and the reference signal RAMP via a capacitor with a predetermined reference voltage, and supplies an output signal indicating the comparison result to the counter 122.

[0043] The counter 122 counts the time until the voltage magnitude relationship between the pixel signal and the reference signal RAMP is inverted based on the output signal of the comparator 121. In this way, the analog pixel signal is converted into a digital pixel signal represented by a count value. The counter 122 supplies the count value to the latch circuit 123.

[0044] The latch circuit 123 holds the count value supplied from the counter 122. The latch circuit 123 also performs CDS (Correlated Double Sampling) by calculating the difference between the data signal count value corresponding to the pixel signal at the signal level and the reset signal count value corresponding to the pixel signal at the reset level.

[0045] The horizontal transfer scanning circuit 106 is configured with a shift register, an address decoder, etc., and sequentially selects and scans circuit portions corresponding to pixel columns of the plurality of ADCs 105. By the selective scanning by this horizontal transfer scanning circuit 106, the digital pixel signals held in the latch circuits 123 are sequentially transferred to the amplifier circuit 107 via the horizontal transfer line 111.

[0046] The amplifier circuit 107 amplifies the digital pixel signal supplied from the latch circuit 123 and supplies the amplified signal to the signal processing circuit 108 .

[0047] The signal processing circuit 108 performs predetermined signal processing on the digital pixel signals supplied from the amplifier circuit 107 to generate two-dimensional image data. For example, the signal processing circuit 108 corrects vertical line defects and point defects, clamps the signal, and performs digital signal processing such as parallel-serial conversion, compression, encoding, addition, averaging, and intermittent operation. The signal processing circuit 108 outputs the generated image data to a downstream device.

[0048] 1 may be configured as a single semiconductor chip as a whole, or may be configured as multiple semiconductor chips. When the imaging device 1 is configured as multiple semiconductor chips, the pixel array unit 101 and other processing circuits may be formed as separate semiconductor chips 511 and 512, and the semiconductor chips 511 and 512 may be stacked.

[0049] 2 is a conceptual diagram showing an example of an imaging device 1 in which a semiconductor chip 511 of a pixel array unit 101 and a semiconductor chip 512 of a processing circuit are stacked. As shown in Fig. 2, the imaging device 1 is configured with two stacked semiconductor chips 511 and 512. Note that the number of stacked semiconductor chips may be three or more.

[0050] The semiconductor chip 511 includes a pixel array unit 101 formed on a semiconductor substrate. The semiconductor chip 512 includes a plurality of ADCs 105, a logic circuit 516, and a peripheral circuit 517 formed on another semiconductor substrate. The logic circuit 516 includes a timing control circuit 102, a vertical scanning circuit 103, a DAC 104, a horizontal transfer scanning circuit 106, etc. The peripheral circuit 517 includes a signal processing circuit 108, etc.

[0051] Each pixel of the pixel array section 101 of the semiconductor chip 511 and elements such as the ADCs (105, 516, 517) of the semiconductor chip 512 may be electrically connected using, for example, through electrodes such as TSVs (Through Silicon Vias) provided in via regions 513 and 514. The multiple ADCs 105 can transmit and receive signals to and from the pixel array section 101 via the TSVs. Furthermore, the semiconductor chips 511 and 512 may be bonded together so that the wiring of the semiconductor chip 511 and the wiring of the semiconductor chip 512 are in contact with each other (Cu-Cu bonding). Furthermore, although not shown, the pixel array section 101 and some of the ADCs (105, 516, 517) may be configured as one semiconductor chip 511, and the remaining components may be configured as another semiconductor chip 512.

[0052] 1 outputs a pixel signal of high dynamic range (hereinafter also referred to as HDR). Before describing the specific configuration of a pixel according to the first embodiment, the basic configuration of a high dynamic range pixel will be described.

[0053] (Basic Configuration of a High Dynamic Range Pixel) FIG. 3 is a circuit diagram showing the basic configuration of a high dynamic range pixel. The pixel PX in FIG. 3 is configured to include a first photoelectric conversion unit PD11a, a second photoelectric conversion unit PD11b, first to fourth transfer gate units T12a to T12d, a reset transistor T13, a charge accumulation unit C14, a first floating diffusion region (floating diffusion, first floating diffusion region) FD15a, a second floating diffusion region (floating diffusion, second floating diffusion region) FD15b, an amplifier transistor T16, and a selection transistor T17. In this specification, the transistors in the pixel PX are sometimes collectively referred to as pixel transistors. Each pixel transistor in the pixel PX is an N-type MOS transistor that turns on when a high-level drive signal is input to its gate. In this specification, the signal level of the drive signal that turns on each pixel transistor is referred to as an active state.

[0054] 3 are arranged in a plurality of rows and columns, and each row of pixels arranged in the row direction is provided with a pixel drive line 109 shown in Fig. 1. Various drive signals TGL, FCG, FDG, TGS, RST, and SEL are supplied from the vertical scanning circuit 103 shown in Fig. 1 via a plurality of drive lines to be input to the gates of the pixel transistors in the pixel PX.

[0055] The first photoelectric conversion unit PD11a is made up of, for example, a PN junction photodiode. The first photoelectric conversion unit PD11a generates and accumulates electric charges according to the amount of light received. The second photoelectric conversion unit PD11b is made up of, for example, a PN junction photodiode, similar to the first photoelectric conversion unit PD11a. The second photoelectric conversion unit PD11b generates and accumulates electric charges according to the amount of light received.

[0056] Comparing the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b, the first photoelectric conversion unit PD11a has a larger light-receiving surface area and higher sensitivity than the second photoelectric conversion unit PD11b. Note that the relationship in size between the light-receiving surface areas of the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b is arbitrary.

[0057] The first transfer gate unit T12a is connected between the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a. A drive signal TGL is applied to the gate electrode of the first transfer gate unit T12a. When the drive signal TGL becomes active, the first transfer gate unit T12a becomes conductive, and the charges stored in the first photoelectric conversion unit PD11a are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a.

[0058] The second transfer gate unit T12b is connected between the charge storage unit C14 and the second floating diffusion region FD15b. A drive signal FCG is applied to the gate electrode of the second transfer gate unit T12b. When the drive signal FCG becomes active, the second transfer gate unit T12b becomes conductive, and the potentials of the charge storage unit C14 and the second floating diffusion region FD15b are coupled.

[0059] The conversion efficiency switching transistor (first transistor) T12c is connected between the first floating diffusion region FD15a and the second floating diffusion region FD15b. A drive signal FDG is applied to the gate electrode of the conversion efficiency switching transistor T12c. When the drive signal FDG becomes active, the conversion efficiency switching transistor T12c becomes conductive, and the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0060] The fourth transfer gate unit T12d is connected between the second photoelectric conversion unit PD11b and the charge accumulation unit C14. A drive signal TGS is applied to the gate electrode of the fourth transfer gate unit T12d. When the drive signal TGS becomes active, the fourth transfer gate unit T12d becomes conductive, and the charges accumulated in the second photoelectric conversion unit PD11b are transferred to the charge accumulation unit C14 via the fourth transfer gate unit T12d.

[0061] Furthermore, the potential below the gate electrode of the fourth transfer gate unit T12d is slightly deeper, and an overflow path is formed that transfers charge that exceeds the saturated charge amount of the second photoelectric conversion unit PD11b and overflows from the second photoelectric conversion unit PD11b to the charge accumulation unit C14. Note that, hereinafter, the overflow path formed below the gate electrode of the fourth transfer gate unit T12d will be simply referred to as the overflow path of the fourth transfer gate unit T12d.

[0062] The reset transistor T13 is connected between a power supply (hereinafter, the power supply may also be referred to as VDD) that supplies a power supply voltage VDD and the second floating diffusion region FD15b. A drive signal RST is applied to the gate electrode of the reset transistor T13. When the drive signal RST is activated, the reset transistor T13 is turned on. As a result, for example, the potential region formed by the coupling of the first floating diffusion region FD15a and the second floating diffusion region FD15b, or the potential region formed by the coupling of the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b, is reset to the level of the power supply voltage VDD.

[0063] The charge storage unit C14 includes, for example, a capacitor, and the counter electrode of the charge storage unit C14 is connected to the power supply voltage VDD node. The charge storage unit C14 stores the charge transferred from the second photoelectric conversion unit PD11b. The capacitor constituting the charge storage unit C14 is, for example, a lateral overflow integration capacitor (LOFIC). The charge storage unit C14 can hold the charge that overflows from the second photoelectric conversion unit PD11b under high illuminance conditions. By increasing the capacity of the charge storage unit C14, the charge that overflows from the second photoelectric conversion unit PD11b can be held to generate a pixel signal, thereby preventing overexposure under high illuminance conditions and expanding the dynamic range.

[0064] The first floating diffusion region FD15a and the second floating diffusion region FD15b convert the charges of the first or second photoelectric conversion unit PD11a or PD11b into a voltage signal and output the converted signal. By electrically connecting or disconnecting the first floating diffusion region FD15a and the second floating diffusion region FD15b, the capacitance of the entire floating diffusion region of the pixel PX can be switched. By switching the capacitance of the floating diffusion region of the pixel PX, the pixel PX can output a pixel signal with a plurality of charge-voltage conversion efficiencies.

[0065] The amplifier transistor T16 has a gate electrode connected to the first floating diffusion region FD15a and a drain electrode connected to the power supply voltage VDD node, and serves as an input part of a readout circuit that reads out the charges held in the first floating diffusion region FD15a, a so-called source follower circuit. That is, the amplifier transistor T16 has a source electrode connected to the vertical signal line VSL via the selection transistor T17, and thereby forms a source follower circuit together with a constant current source CS18 connected to one end of the vertical signal line VSL.

[0066] The selection transistor T17 is connected between the source electrode of the amplification transistor T16 and the vertical signal line VSL. A drive signal SEL is applied to the gate electrode of the selection transistor T17. When the drive signal SEL is activated, the selection transistor T17 is rendered conductive, and the pixel PX in FIG. 3 is rendered selected. As a result, the pixel signal output from the amplification transistor T16 is output to the vertical signal line VSL via the selection transistor T17.

[0067] In the following, when each drive signal is in an active state, it is referred to as the drive signal being turned on, and when each drive signal is in an inactive state, it is referred to as the drive signal being turned off. In the following, when each gate unit or each transistor is in a conductive state, it is referred to as the gate unit or each transistor being turned on, and when each gate unit or each transistor is in a non-conductive state, it is referred to as the gate unit or each transistor being turned off.

[0068] In this embodiment, the pixel PX shown in Fig. 3 switches between multiple sensitivities to generate multiple pixel signals divided into signal levels and reset levels. Although the type of sensitivity is not important, the following mainly describes an example in which the pixel PX switches between four sensitivities. Hereinafter, the four sensitivities will be referred to as ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity.

[0069] More specifically, the signal level of the ultra-low sensitivity pixel signal is called SH2DOL, and the reset level of the ultra-low sensitivity pixel signal is called NH2DOL. SH2DOL and NH2DOL use the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, the first floating diffusion region FD15a, and the second floating diffusion region FD15b shown in FIG. 3 .

[0070] Hereinafter, the signal level of the high-sensitivity pixel signal will be referred to as SH1, and the reset level of the high-sensitivity pixel signal will be referred to as NH1. SH1 and NH1 use the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the first floating diffusion region FD15a in FIG. 3 .

[0071] Hereinafter, the signal level of the medium-sensitivity pixel signal will be referred to as SH2, and the reset level of the medium-sensitivity pixel signal will be referred to as NH2. SH2 and NH2 use the first photoelectric conversion unit PD11a, first transfer gate unit T12a, first floating diffusion region FD15a, and second floating diffusion region FD15b shown in FIG.

[0072] Hereinafter, the signal level of the low-sensitivity pixel signal will be referred to as SL, and the signal level of the low-sensitivity pixel signal will be referred to as NL. SL and NL use the second photoelectric conversion unit PD11b, the second transfer gate unit T12b, the third transfer gate unit T12c, the fourth transfer gate unit (second transistor) T12d, and the charge accumulation unit C14 in FIG. 3 .

[0073] (Example of operation at the start of exposure of pixel PX in FIG. 3) FIG. 4 is a timing chart of each drive signal at the start of exposure of pixel PX. FIG. 4 shows a timing chart of the horizontal synchronization signal XHS and drive signals SEL, RST, FDG, TGL, TGS, and FCG. Hereinafter, an example of operation at the start of exposure of pixel PX in FIG. 3 will be described with reference to FIG. 4. FIG. 4 shows a timing chart for one horizontal line period. The multiple pixel rows included in the pixel array unit 101 are driven for each pixel row or for multiple pixel rows in accordance with the timing chart of FIG. 4.

[0074] First, at time t1, the horizontal synchronization signal XHS is input, and the exposure process of the pixel PX in FIG. 3 begins.

[0075] Next, at time t2, the drive signals RST and FDG are turned on, and the reset transistor T13 and the conversion efficiency switching transistor T12c are turned on, thereby coupling the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the coupled potential region is reset to the level of the power supply voltage VDD.

[0076] Next, at time t3, the drive signal TGL is turned on, turning on the first transfer gate unit T12a, which transfers the charge stored in the first photoelectric conversion unit PD11a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled via the first transfer gate unit T12a, resetting the first photoelectric conversion unit PD11a.

[0077] Next, at time t4, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, which starts the accumulation of charges in the first photoelectric conversion unit PD11a and starts the exposure period.

[0078] Next, at time t5, the drive signals TGS and FCG are turned on, turning on the fourth transfer gate unit T12d and the second transfer gate unit T12b. This couples the potentials of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. Furthermore, the charge stored in the second photoelectric conversion unit PD11b is transferred via the fourth transfer gate unit T12d to the coupled potential region of the first floating diffusion region FD15a and the second floating diffusion region FD15b, resetting the second photoelectric conversion unit PD11b and the charge storage unit C14.

[0079] Next, at time t6, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off. This causes charge accumulation in the second photoelectric conversion unit PD11b to begin. In this way, the exposure period of the pixel PX begins at time t4, and charge accumulation is performed using only the first photoelectric conversion unit PD11a during the period from time t4 to t6. After time t6, charge accumulation is performed using both the first photoelectric conversion unit PD11a and the second photoelectric conversion unit PD11b.

[0080] Next, at time t7, the drive signal FCG is turned off and the second transfer gate unit T12b is turned off, causing the charge accumulation unit C14 to start accumulating the charge that overflows from the second photoelectric conversion unit PD11b and is transferred via the overflow path of the fourth transfer gate unit T12d.

[0081] Next, at time t8, the drive signals RST and FDG are turned off, and the reset transistor T13 and the conversion efficiency switching transistor T12c are turned off. At time t9, the horizontal synchronization signal XHS is input, and the next horizontal line period begins.

[0082] During the period from time t1 to time t9, the drive signal SEL is at a low level and the selection transistor T17 is in an off state, so that pixel signals are not read out to the vertical signal line VSL.

[0083] (Combining Multiple Pixel Signals of Multiple Sensitivities) The imaging device 1 according to this embodiment can switch between four sensitivities, and combines and outputs four pixel signals that are exposed and read out at the four sensitivities. A portion of the circuitry of the pixel PX is used for each sensitivity.

[0084] FIG. 5 is a diagram showing the S / N ratio of a pixel signal obtained by combining four pixel signals captured at four sensitivities. The horizontal axis of FIG. 5 represents illuminance, and the vertical axis represents the S / N ratio. FIG. 5 shows a waveform obtained by combining waveforms of four S / N ratios corresponding to the four sensitivities. Specifically, FIG. 5 includes a waveform w1 of an ultra-low sensitivity pixel signal (NH2DOL-SH2DOL), a waveform w2 of a low sensitivity pixel signal (NL-SL), a waveform w3 of a medium sensitivity pixel signal (NH2-SH2), and a waveform w4 of a high sensitivity pixel signal (NH1-SH1).

[0085] The ultra-low sensitivity pixel signal (NH2DOL-SH2DOL) is generated using the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the conversion efficiency switching transistor T12c in the pixel PX.

[0086] The low-sensitivity pixel signal (NL-SL) is generated using the second photoelectric conversion unit PD11b, the second transfer gate unit T12b, the fourth transfer gate unit T12d, and the charge accumulation unit C14 in the pixel PX.

[0087] The medium-sensitivity pixel signal (NH2-SH2) is generated using the first photoelectric conversion unit PD11a, the first transfer gate unit T12a, and the conversion efficiency switching transistor T12c in the pixel PX.

[0088] The medium-sensitivity pixel signal (NL-SL) and the ultra-low-sensitivity pixel signal (NH2DOL-SH2DOL) are generated using the same circuit, but the ultra-low-sensitivity pixel signal (NH2DOL-SH2DOL) has a shorter exposure time than the medium-sensitivity pixel signal (NL-SL), so even when exposed to high-intensity light, charges corresponding to the amount of incident light can be correctly accumulated in the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0089] The high-sensitivity pixel signal (NH1-SH1) is generated using the first photoelectric conversion unit PD11a and the first transfer gate unit T12a.

[0090] (Example of operation when reading out pixel PX in FIG. 3) FIG. 6 is a timing chart when reading out pixel signals from pixel PX. FIG. 6 shows a timing chart of the horizontal synchronization signal XHS, drive signals SEL, RST, FDG, TGL, TGS, FCG, and vertical signal line VSL. Hereinafter, an example of operation when reading out pixel signals from pixel PX in FIG. 3 will be described with reference to the timing chart of FIG. 6. The pixel signals of each pixel PX included in the pixel array unit 101 are read out to the vertical signal line VSL for each pixel row or for each set of multiple pixel rows, in accordance with the timing chart of FIG. 4.

[0091] First, at time t11, the horizontal synchronization signal XHS is input, and the readout period of the pixel PX in FIG. 3 begins.

[0092] Next, at time t12, the drive signals SEL, RST, and FDG are turned on, turning on the selection transistor T17, the reset transistor T13, and the conversion efficiency switching transistor T12c. This selects the pixel PX in FIG. 3. Furthermore, the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, and the coupled potential region is reset to the level of the power supply voltage VDD.

[0093] Next, at time t13, the drive signal RST is turned off, turning off the reset transistor T13. This stops the discharge of charges from the first floating diffusion region FD15a and the second floating diffusion region FD15b to the power supply voltage VDD node, and the first photoelectric conversion unit PD11a starts exposure, causing charges due to photoelectric conversion to be accumulated in the first photoelectric conversion unit PD11a. At time t13, the first transfer gate unit T12a is in the off state, so the accumulated charges in the first photoelectric conversion unit PD11a are not transferred to the first floating diffusion region FD15a.

[0094] Next, at time ta between time t13 and time t14, a pixel signal NH2DOL corresponding to the potential of the coupled first floating diffusion region FD15a and second floating diffusion region FD15b is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NH2DOL is a signal obtained by detecting the reset levels of the floating diffusion regions FD15a and FD15b in FIG. 3 using the coupled potential region of the first floating diffusion region FD15a and second floating diffusion region FD15b, and is a reset level with ultra-low sensitivity.

[0095] Next, at time t14, the first transfer gate unit T12a is turned on, and the accumulated charge in the first photoelectric conversion unit PD11a is transferred to the first floating diffusion region FD15a. The first photoelectric conversion unit PD11a accumulates charge for a short period of time, from time t13 to t14, and the accumulated charge for that short period of time is transferred to the first floating diffusion region FD15a at time t14. Because the charge accumulation time of the first photoelectric conversion unit PD11a is limited, the accumulated charge in the first photoelectric conversion unit PD11a does not overflow, even under high illuminance conditions.

[0096] Next, at time t15, the first transfer gate unit T12a is turned off. At time tb between times t15 and t16, a pixel signal SH2DOL corresponding to the charges transferred to the first floating diffusion region FD15a is output to the vertical signal line VSL. This pixel signal SH2DOL has an ultra-low sensitivity signal level for reading out the amount of light during the short exposure period from time t13 to t14.

[0097] 6 shows the voltage level of the vertical signal line VSL under high illuminance (solid line) and the voltage level of the vertical signal line VSL under low illuminance (dashed line). As shown in the figure, the higher the illuminance, the lower the voltage level of the vertical signal line VSL. In FIG. 6, the time when the voltage level of the vertical signal line VSL becomes stable is designated as t16.

[0098] Next, at time t17, the drive signal RST goes high, turning on the reset transistor T13. At this point, the selection transistor T17 and the conversion efficiency switching transistor T12c are in the on state. As a result, the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled, and the charge in the coupled potential region is discharged to the power supply voltage VDD node via the reset transistor T13.

[0099] At time t18, the drive signal RST goes low, turning off the reset transistor T13.

[0100] At time tc between times t18 and t19, a pixel signal NH2 corresponding to the potential of the combined potential region is output to the vertical signal line VSL. This pixel signal NH2 is at the reset level for medium sensitivity. As shown in FIGS. 3 and 5, the pixel signals for ultra-low sensitivity and medium sensitivity are read out using the same circuit portion within the pixel PX.

[0101] Next, at time t19, the drive signal FDG is turned off, and the conversion efficiency switching transistor T12c is turned off, thereby dissolving the potential coupling between the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0102] Next, at time td between time t19 and time t20, a pixel signal NH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NH1 is a signal obtained by detecting the reset states of the first photoelectric conversion unit PD11a and the first floating diffusion region FD15a shown in FIG. 3 using the first floating diffusion region FD15a, and is a high-sensitivity reset level. As shown in FIGS. 3 and 5, the high-sensitivity reset level NH1 is detected without using the second floating diffusion region FD15b.

[0103] Next, at time t20, the drive signal TGL is turned on, turning on the first transfer gate unit T12a. As a result, the charges generated and accumulated in the first photoelectric conversion unit PD11a during the exposure period are transferred to the first floating diffusion region FD15a via the first transfer gate unit T12a. At time t20, readout of pixel signals begins, and the exposure period of the first photoelectric conversion unit PD11a ends.

[0104] Next, at time t21, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the first floating diffusion region FD15a.

[0105] Next, at time te between times t21 and t22, a pixel signal SH1 based on the potential of the first floating diffusion region FD15a is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SH1 is a signal based on the potential of the first floating diffusion region FD15a at the time when the charges generated by the first photoelectric conversion unit PD11a during the exposure period from times t18 to t20 are accumulated in the first floating diffusion region FD15a. The pixel signal SH1 has a high-sensitivity signal level.

[0106] Next, at time t22, the drive signals FDG and TGL are turned on, and the conversion efficiency switching transistor T12c and the first transfer gate unit T12a are turned on, thereby coupling the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b, and the charge that remains in the first photoelectric conversion unit PD11a and was not transferred between time t20 and time t21 is transferred via the first transfer gate unit T12a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0107] When the pixel signal SH1 is read out at time te, the capacity for charge-to-voltage conversion is small compared to the amount of charge to be handled, so there is no problem even if charge remains in the first photoelectric conversion unit PD11a. The charge remaining in the first photoelectric conversion unit PD11a can be transferred when the pixel signal SH2 is read out, and the charge in the first photoelectric conversion unit PD11a is not damaged.

[0108] Next, at time t23, the drive signal TGL is turned off, and the first transfer gate unit T12a is turned off, thereby stopping the transfer of charges from the first photoelectric conversion unit PD11a to the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled.

[0109] Next, at time tf between times t23 and t24, a pixel signal SH2 based on the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SH2 is a signal corresponding to the charges generated by the first photoelectric conversion unit PD11a during the exposure period from times t18 to t42, which are accumulated in the potential region where the first floating diffusion region FD15a and the second floating diffusion region FD15b are coupled. Therefore, the capacitance for charge-to-voltage conversion when the pixel signal SH2 is read out is the combined capacitance of the first floating diffusion region FD15a and the second floating diffusion region FD15b, which is larger than the capacitance when the high-sensitivity data signal SH1 is read out at time tc. The pixel signal SH2 has a medium-sensitivity signal level.

[0110] Next, at time t24, the drive signal RST is turned on, turning on the reset transistor T13, thereby resetting the potential region formed by the coupling of the first floating diffusion region FD15a and the second floating diffusion region FD15b to the level of the power supply voltage VDD.

[0111] Next, at time t25, the selection transistor T17 is turned off, and the pixel PX in Fig. 3 is put into a non-selected state. Subsequently, at time t26, the reset transistor T13 is turned off.

[0112] Next, at time t27, the drive signals SEL, TGS, and FCG are turned on, turning on the selection transistor T17, the fourth transfer gate unit T12d, and the second transfer gate unit T12b. This causes the pixel PX in FIG. 3 to be selected again. Furthermore, the potentials of the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled, and the charge stored in the second photoelectric conversion unit PD11b is transferred to the coupled potential region. As a result, the charge stored in the second photoelectric conversion unit PD11b and the charge storage unit C14 during the exposure period is stored in the coupled potential region.

[0113] Next, at time t28, the drive signal TGS is turned off, and the fourth transfer gate unit T12d is turned off, thereby stopping the transfer of charges from the second photoelectric conversion unit PD11b.

[0114] Next, at time tg between times t28 and t29, a pixel signal SL based on the potential of the potential region where the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. The pixel signal SL is a signal based on the potential of the potential region where the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled when the charge generated by the second photoelectric conversion unit PD11b and accumulated in the second photoelectric conversion unit PD11b and the charge accumulation unit C14 is accumulated in the coupled potential region. Therefore, the capacitance for charge-to-voltage conversion when the pixel signal SL is read out is the combined capacitance of the charge accumulation unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b. This capacitance is larger than when pixel signal SH1 is read out at time tc and when pixel signal SH2 is read out at time td. Pixel signal SL has a low-sensitivity signal level. As shown in FIGS. 3 and 5, the low-sensitivity signal level SL is detected using the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b.

[0115] Next, at time t29, the drive signal RST is turned on, turning on the reset transistor T13, thereby resetting the potential region formed by the charge storage portion C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b.

[0116] Next, at time t30, the drive signals SEL and FCG are turned off, and the selection transistor T17 and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential of the charge storage unit C14 is separated from the potentials of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0117] Next, at time t31, the drive signal RST is turned off, and the reset transistor T13 is turned off.

[0118] Next, at time t32, the drive signals SEL and FCG are turned on, turning on the selection transistor T17 and the second transfer gate unit T12b. This causes the pixel PX in FIG. 3 to be selected again. Furthermore, the potential of the charge storage unit C14 is coupled to the potential of the first floating diffusion region FD15a and the second floating diffusion region FD15b.

[0119] Next, at time th between times t32 and t33, a pixel signal NL based on the potential of the potential region to which the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled is output to the vertical signal line VSL via the amplification transistor T16 and the selection transistor T17. This pixel signal NL is a signal based on the potential of the reset state of the potential region to which the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b are coupled. The pixel signal NL is at a low-sensitivity reset level.

[0120] Next, at time t33, the drive signals SEL, FDG, and FCG are turned off, and the selection transistor T17, the conversion efficiency switching transistor T12c, and the second transfer gate unit T12b are turned off. This causes the pixel PX in FIG. 3 to enter a non-selected state. Furthermore, the potential coupling between the charge storage unit C14, the first floating diffusion region FD15a, and the second floating diffusion region FD15b is released.

[0121] Next, at time t34, the horizontal synchronization signal XHS is input, and the readout period of the pixel signal from pixel PX in FIG. 3 ends.

[0122] As described above, each pixel PX outputs a plurality of pixel signals with different sensitivities to a vertical signal line at different times. The plurality of pixel signals with different sensitivities include, for example, an ultra-low sensitivity signal level, an ultra-low sensitivity reset level, a low sensitivity signal level, a low sensitivity reset level, a medium sensitivity signal level, a medium sensitivity reset level, a high sensitivity signal level, and a high sensitivity reset level. It is not easy to output these pixel signals from the pixel PX to the vertical signal line in one horizontal line period.

[0123] Therefore, the imaging device 1 according to the first embodiment is provided with three or more sample-and-hold circuits (hereinafter referred to as SH circuits) and a multiplexer (selection circuit) for each vertical signal line. The multiplexer selects one of the three or more hold signals held by the three or more SH circuits or the pixel signal on the signal line, and supplies the selected signal to an analog-to-digital converter (hereinafter referred to as ADC: Analog Digital Converter). The ADC performs AD conversion on the pixel signal to generate a digital pixel signal.

[0124] 7 is a circuit diagram of the main components of the image pickup device 1 according to the first embodiment. The image pickup device 1 according to the first embodiment includes a sample-and-hold unit 125 arranged between each vertical signal line VSL and the ADC 105. The sample-and-hold unit 125 includes three or more SH circuits SHC1 to SHC3 and a selection circuit (multiplexer) MUX. An example in which the sample-and-hold unit 125 according to the first embodiment includes three SH circuits SHC1 to SHC3 will be described below.

[0125] FIG. 7 shows a circuit configuration of the VSL boost circuit 12 connected to one vertical signal line VSL, three SH circuits SHC1 to SHC3 and a multiplexer MUX in the sample-and-hold unit 125, and the ADC 105.

[0126] (VSL Boost Circuit 12) The VSL boost circuit 12 includes n-type transistors Tn6 to Tn8, a capacitor C15, and a constant current source CS15. The gate of the transistor Tn8 is connected to the vertical signal line VSL. The drain of the transistor Tn8 is connected to the power supply voltage VDD node, and its source is connected to the constant current source CS15. As a result, the transistor Tn8 and the constant current source CS15 function as a source follower, and the gain thereof is smaller than "1."

[0127] One end of the capacitor C15 is connected to the gate of the transistor Tn8 via the transistor Tn6. The other end of the capacitor C15 is connected to the source of the transistor Tn8. As a result, the source of the transistor Tn6 sees a signal of the same polarity obtained by dividing the pixel signal of the vertical signal line VSL by the gain of the transistor Tn6, and the source of the transistor Tn8 sees a signal obtained by multiplying the fluctuation of the pixel signal of the vertical signal line VSL by the gain of the source follower. As a result, across the capacitor C15, it appears as if a gain of the same polarity that is larger than that of the source of the transistor Tn6 is being applied to the source of the transistor Tn8. As a result, the VSL boost circuit 12 operates as a negative capacitance circuit.

[0128] The transistor Tn7 is connected between one end of the capacitor C15 and the ground GND. The transistor Tn6 is connected between one end of the capacitor C15 and the vertical signal line VSL. The transistor Tn7 functions as a constant current source for the vertical signal line VSL.

[0129] Parasitic capacitance occurs in the vertical signal line VSL. Assume that a voltage of +Vs is applied to the parasitic capacitance of the vertical signal line VSL. In this case, if the gain of the transistor Tn8 functioning as a source follower and the constant current source CS15 in the negative capacitance circuit 310 is set to "0.9" and the source-to-drain gain of the transistor Tn6 is set to "10," then 0.1×Vs is applied to the terminal of the capacitor C15 on the vertical signal line VSL side, and 0.9×Vs is applied to the terminal on the opposite side. Therefore, when the potential (0.9×Vs) on the opposite side to the vertical signal line VSL is used as a reference, a voltage of -0.8×Vs is applied to the capacitor C15. As a result, +Vs is applied to the parasitic capacitance of the vertical signal line VSL, and -0.8×Vs is applied to the capacitor C15, resulting in a lower wiring capacitance of the vertical signal line VSL compared to when the negative capacitance circuit 310 is not present.

[0130] As described above, by providing the VSL boost circuit 12, the wiring capacitance of the vertical signal line VSL can be reduced, the potential of the vertical signal line VSL can be quickly stabilized, and the settling time can be shortened.

[0131] In addition, the VSL boost circuit 12 of the present disclosure uses a transistor Tn8 that functions as a source follower and a constant current source CS15, but other configurations that can perform non-inverting amplification may be used as long as the influence of the parasitic capacitance of the vertical signal line VSL can be sufficiently reduced.

[0132] (Sample and Hold Circuit (SH Circuit)) As described above, a sample and hold unit 125 is provided between each vertical signal line VSL and the ADC 105. The sample and hold unit 125 has three SH circuits SHC1 to SHC3 and a multiplexer MUX. The SH circuits SHC1 to SHC3 sample and hold pixel signals on the vertical signal line VSL.

[0133] Of the SH circuits SHC1 to SHC3, the SH circuit that samples and holds a pixel signal that takes time to stabilize samples and holds the pixel signal after a standby period until the pixel signal stabilizes, while the other SH circuits sample and hold pixel signals generated by other pixels during the standby period. The standby period until the pixel signal stabilizes is, for example, the period until the discharge of the charge storage unit C14 of pixel PX is completed.

[0134] Each of the pixels PX outputs a plurality of pixel signals having different sensitivities to the vertical signal line VSL at different times. The SH circuits SHC1 to SHC3 and the ADC 105 perform a sampling operation, a holding operation, and an analog-to-digital conversion operation of the plurality of pixel signals having different sensitivities in parallel.

[0135] Each of the plurality of pixels PX switches the sensitivity of the corresponding pixel PX between four or more levels, and divides the pixel signal into a signal level and a reset level for each sensitivity and outputs them to the vertical signal line VSL with a time lag. SH circuits SHC1 to SHC3 provided for each of the plurality of vertical signal lines VSL sample and hold the signal level and reset level of the pixel signal for each sensitivity with a time lag. For example, the signal level and reset level of pixel signals of the same sensitivity are sampled and held by the same SH circuit.

[0136] Among the SH circuits SHC1 to SHC3, the SH circuits other than some of the SH circuits sample and hold pixel signals output to signal lines from pixel rows other than the some of the pixel rows during a period when the some of the SH circuits are waiting to sample pixel signals in the pixel rows.

[0137] For example, some of the SH circuits SHC1 to SHC3 wait until the discharge of the charge storage unit of the pixel to be read out in one of the pixel groups is completed, and then sample and hold the pixel signal. In this case, the SH circuits SHC1 to SHC3, excluding some of the SH circuits, sample and hold the pixel signal output to the vertical signal line VSL from a pixel group other than one of the pixel groups, during the discharge period of the charge storage unit C14.

[0138] For example, one of the SH circuits SHC1 to SHC3 samples and holds pixel signals output to the vertical signal line VSL from a first pixel row including pixels having charge storage units C14 that have finished discharging. In this case, the SH circuits other than one SH circuit sample and hold pixel signals output to the vertical signal line VSL from a second pixel row during the discharging period of the charge storage units C14. For example, the first pixel row and the second pixel row are adjacent pixel rows in the column direction.

[0139] For example, one of the SH circuits SHC1 to SHC3 samples and holds the pixel signal output from the second pixel row to the vertical signal line VSL by an SH circuit other than one SH circuit, and after the ADC 105 converts it into a digital pixel signal, it samples and holds the reset level of the pixel signal after the charge storage unit C14 is discharged.

[0140] The multiplexer MUX selects one of the three hold signals sampled and held by the three SH circuits SHC1 to SHC3 and the pixel signal on the vertical signal line VSL, and supplies the selected signal to the ADC 105. Hereinafter, the three SH circuits will be referred to as the first to third SH circuits SHC1 to SHC3. A bypass line BPL that transmits the pixel signal on the vertical signal line VSL is connected to the multiplexer MUX.

[0141] For example, during the period when one SH circuit is waiting until the discharge of the charge storage unit C14 is completed, the multiplexer MUX selects in turn the hold signals of the SH circuits other than one of the three or more SH circuits and the pixel signal on the signal line, and then selects the reset level of the pixel signal after the discharge of the charge storage unit C14 that has been sampled and held by one SH circuit.

[0142] The first SH circuit SHC1 includes a capacitor Cp1, a transistor Tr1, switches SW1 to SW3, and a constant current source CS1.

[0143] One end of the capacitor Cp1 is connected to the vertical signal line VSL via the switch SW1, and can store a charge corresponding to a pixel signal, and the other end of the capacitor Cp1 is connected to the gate of the transistor Tr1.

[0144] The drain of transistor Tr1 is connected to constant current source CS1 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source CS1 is connected between the power supply voltage VDD node and the drain of transistor Tr1, and causes a constant current to flow through the drain of transistor Tr1. Transistor Tr1 causes a current corresponding to the gate potential to flow between its drain and source. As a result, the drain of transistor Tr1 has a potential corresponding to the gate potential of transistor Tr1. The drain of transistor Tr1 is connected to multiplexer MUX, and the drain voltage of transistor Tr1 is output as an output signal of first SH circuit SHC1.

[0145] The switch SW1 is connected between the capacitor Cp1 and the vertical signal line VSL. The switch SW2 is connected between the drain of the transistor Tr1 and one end of the capacitor Cp1. The switch SW3 is connected between the drain of the transistor Tr1 and the other end of the capacitor Cp1.

[0146] When the first SH circuit SHC1 samples the pixel signal on the vertical signal line VSL to the capacitor Cp1, the switches SW1 and SW3 are turned on (conductive). At this time, the switch SW2 is turned off (non-conductive). As a result, the pixel signal is transmitted to one end of the capacitor Cp1, and the capacitor node opposite the gate of the transistor Tr1 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp1 holds the pixel signal, the switches SW1 and SW3 are turned off and the switch SW2 is turned on. As a result, the pixel signal stored in the capacitor Cp1 is held. At this time, the transistor Tr1 is turned on (analog state) in accordance with the pixel signal, and the drain of the transistor Tr1 is maintained at a potential corresponding to the pixel signal. Therefore, the first SH circuit SHC1 outputs an output signal corresponding to the pixel signal from the drain of the transistor Tr1 to the multiplexer MUX.

[0147] Similar to the first SH circuit SHC1, the second SH circuit SHC2 is provided between the pixel array unit 101 and the comparator 121 and is configured to sample and hold pixel signals. The second SH circuit SHC2 includes a capacitor Cp2, a transistor Tr2, switches SW4 to SW6, and a constant current source CS2. The second SH circuit SHC2 samples pixel signals from the same vertical signal line VSL as the first SH circuit SHC1 at different timings. Therefore, the first and second SH circuits SHC1 and SHC2 can sample and hold multiple pixel signals with different sensitivities or conversion efficiencies from the same pixel PX.

[0148] One end of the capacitor Cp2 is connected to the vertical signal line VSL via the switch SW4, and can store a charge corresponding to a pixel signal, and the other end of the capacitor Cp2 is connected to the gate of the transistor Tr2.

[0149] The drain of transistor Tr2 is connected to constant current source CS2 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source CS2 is connected between the power supply voltage VDD node and the drain of transistor Tr2, and passes a constant current through the drain of transistor Tr2. Transistor Tr2 passes a current between its drain and source that corresponds to the potential of its gate. As a result, the drain of transistor Tr2 has a potential that corresponds to the potential of its gate. The drain of transistor Tr2 is connected to multiplexer MUX, and the drain voltage of transistor Tr2 is output as an output signal of second SH circuit SHC2.

[0150] The switch SW4 is connected between the capacitor Cp2 and the vertical signal line VSL. The switch SW5 is connected between the drain of the transistor Tr2 and one end of the capacitor Cp2. The switch SW6 is connected between the drain of the transistor Tr2 and the other end of the capacitor Cp2.

[0151] When the second SH circuit SHC2 samples the pixel signal on the vertical signal line VSL to the capacitor Cp2, the switches SW4 and SW6 are turned on. At this time, the switch SW5 is turned off. As a result, the pixel signal is transmitted to one end of the capacitor Cp2, and the capacitor node opposite the gate of the transistor Tr2 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp2 holds the pixel signal, the switches SW4 and SW6 are turned off and the switch SW5 is turned on. As a result, the pixel signal stored in the capacitor Cp2 is held. At this time, the gate of the transistor Tr2 is brought into a conductive state (analog state) corresponding to the pixel signal, and the drain of the transistor Tr2 is maintained at a potential corresponding to the pixel signal. Therefore, the second SH circuit SHC2 outputs an output signal corresponding to the pixel signal to the multiplexer MUX.

[0152] The third SH circuit SHC3, like the first SH circuit SHC1 and the second SH circuit SHC2, is provided between the pixel array unit 101 and the comparator 121 and is configured to sample and hold pixel signals. The third SH circuit SHC3 includes a capacitor Cp3, a transistor Tr3, switches SW7 to SW9, and a constant current source CS3. The third SH circuit SHC3 samples pixel signals from the same vertical signal line VSL as the first SH circuit SHC1 at different timings. Therefore, the first to third SH circuits SHC1, SHC2, and SHC3 can sample and hold multiple pixel signals with different sensitivities or conversion efficiencies from the same pixel PX.

[0153] One end of the capacitor Cp3 is connected to the vertical signal line VSL via the switch SW7, and can store a charge corresponding to a pixel signal, and the other end of the capacitor Cp3 is connected to the gate of the transistor Tr3.

[0154] The drain of transistor Tr3 is connected to constant current source CS3 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source CS3 is connected between the power supply voltage VDD node and the drain of transistor Tr3, and passes a constant current through the drain of transistor Tr3. Transistor Tr3 passes a current between its drain and source that corresponds to the potential of its gate. As a result, the drain of transistor Tr3 has a potential that corresponds to the potential of its gate. The drain of transistor Tr3 is connected to multiplexer MUX, and the drain voltage of transistor Tr3 is output as an output signal of the third SH circuit SHC3.

[0155] The switch SW7 is connected between the capacitor Cp3 and the vertical signal line VSL. The switch SW8 is connected between the drain of the transistor Tr3 and one end of the capacitor Cp3. The switch SW9 is connected between the drain of the transistor Tr3 and the other end of the capacitor Cp3.

[0156] When the third SH circuit SHC3 samples the pixel signal on the vertical signal line VSL to the capacitor Cp3, the switches SW7 and SW9 are turned on. At this time, the switch SW8 is turned off. As a result, the pixel signal is transmitted to one end of the capacitor Cp3, and the capacitor node opposite the gate of the transistor Tr3 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp3 holds the pixel signal, the switches SW7 and SW9 are turned off and the switch SW8 is turned on. As a result, the pixel signal stored in the capacitor Cp3 is held. At this time, the gate of the transistor Tr3 is turned on (in an analog state) in accordance with the pixel signal, and the drain of the transistor Tr3 is maintained at a potential corresponding to the pixel signal. Therefore, the third SH circuit SHC3 outputs an output signal corresponding to the pixel signal to the multiplexer MUX.

[0157] The pixel signals on the vertical signal line VSL held by the first to third SH circuits SHC1 to SCH3 are an ultra-low sensitivity reset level NH2DOL, an ultra-low sensitivity signal level SH2DOL, a high sensitivity reset level NH1, a high sensitivity signal level SH1, a medium sensitivity reset level NH2, a medium sensitivity signal level SH2, a low sensitivity signal level SL, or a low sensitivity reset level NL.

[0158] For example, the first SH circuit SHC1 samples and holds the low-sensitivity reset level NL and the ultra-low-sensitivity signal level SH2DOL with a time lag. The second SH circuit SHC2 samples and holds the low-sensitivity signal level SL, the ultra-low-sensitivity reset level NH2DOL, and the medium-sensitivity reset level NH2 with a time lag. The third SH circuit SHC3 samples and holds the ultra-low-sensitivity reset level NH2DOL, the medium-sensitivity reset signal NH2, and the low-sensitivity signal level SL with a time lag. Note that it is arbitrary which sensitivity pixel signals each of the first to third SH circuits SHC1 to SHC3 samples and holds.

[0159] The multiplexer MUX selects one of three or more hold signals sampled and held by three or more SH circuits and a pixel signal on a vertical signal line VSL, and supplies the selected signal to the ADC 105. The pixel signal on the vertical signal line VSL is supplied to the multiplexer MUX via a bypass line BPL.

[0160] The bypass line BPL directly outputs the pixel signal via the multiplexer MUX without using a capacitor or the like to sample and hold the pixel signal. Therefore, noise caused by the capacitors Cp1 and Cp2 and the transistors Tr1 and Tr2 is not carried over to the pixel signal. In other words, the bypass line BPL can be used when the signal degradation components added by the SH circuits SHC1 and SHC2 cannot be tolerated, for example, when it is desired to minimize noise near dark signals with high conversion efficiency.

[0161] (Multiplexer MUX) The multiplexer MUX is connected between the first to third SH circuits SHC1 to SHC3, the bypass line BPL, and the comparator 121. The multiplexer MUX can selectively connect any of the first to third SH circuits SHC1 to SHC3 and the bypass line BPL to the comparator 121 of the multiple ADCs 105 based on a selection signal. This allows the multiplexer MUX to selectively transmit to the comparator 121 a pixel signal sampled and held by any of the first to third SH circuits SHC1 to SHC3, or a pixel signal transmitted via the bypass line BPL. The multiplexer MUX selects, based on the selection signal, a pixel signal sampled and held by any of the first to third SH circuits SHC1 to SHC3, or a pixel signal transmitted via the bypass line BPL. The selection signal is supplied from the vertical scanning circuit 103. The vertical scanning circuit 103 sets the logic of the selection signal in accordance with, for example, the control signals TGL, TGS, FDG, FCG, and SEL of the pixel PX. The multiplexer MUX is configured by any switch circuit capable of performing the above operations.

[0162] (ADC 105) The ADC 105 performs AD conversion on pixel signals read out from the high dynamic range pixels PX shown in Fig. 3. For each pixel PX, the ADC 105 performs AD conversion in the order of an ultra-low sensitivity reset level NH2DOL, an ultra-low sensitivity signal level SH2DOL, a high sensitivity reset level NH1, a high sensitivity signal level SH1, a medium sensitivity reset level NH2, a medium sensitivity signal level SH2, a low sensitivity signal level SL, and a low sensitivity reset level NL. In the imaging device 1 according to the first embodiment, since it takes time to sample and hold the low-sensitivity reset level NL, before AD converting the low-sensitivity signal level SL and the low-sensitivity reset level NL, AD conversion is performed on the ultra-low-sensitivity reset level NH2DOL, ultra-low-sensitivity signal level SH2DOL, high-sensitivity reset level NH1, high-sensitivity signal level SH1, medium-sensitivity reset level NH2, and medium-sensitivity signal level SH2 of the adjacent pixel row, and then AD conversion is performed on the low-sensitivity signal level SL and low-sensitivity reset level NL of the corresponding pixel row.

[0163] The ADC 105 includes a comparator 121 and a counter 122 .

[0164] (Configuration and Function of Comparator 121) The comparator 121 includes an input comparison circuit 121a and an output circuit 121b.

[0165] The input comparison circuit 121a includes p-type transistors Tp1 and Tp2, n-type transistors Tn1 to Tn3, capacitors Cvsl, Cref, C16 to C18, an AZ switch SWAZ, and switches SW15 to SW17.

[0166] One end of the capacitors Cvsl and Cref is connected to the output of the sample-and-hold unit 125 and the reference signal RAMP, respectively. The other ends of the capacitors Cvsl and Cref are commonly connected to the gate of the transistor Tp1.

[0167] The transistors Tn1, Tp1, and Tn2 are connected in series in this order between a power supply voltage VDD node and ground GND.

[0168] The drain of the transistor Tn1 is connected to the power supply voltage VDD node, and the source of the transistor Tn1 is connected to the source of the transistor Tp1. The gate of the transistor Tn1 is connected to a switch SW15 and a capacitor C16. The transistor Tn1 functions as an LDO (Low Dropout) linear regulator.

[0169] As described above, the gate of transistor Tp1 is commonly connected to the other ends of capacitors Cvsl and Cref. The source of transistor Tp1 is connected to the source of transistor Tn1, and the drain of transistor Tp1 is connected to the drain of transistor Tn2 and the gate of transistor Tp2. When the sum of the output signal from multiplexer MUX of sample-and-hold unit 125 and reference signal RAMP from DAC 104 exceeds a threshold voltage, transistor Tp1 changes from a conductive state to a non-conductive state, thereby inverting the voltage level of the gate of transistor Tp2 from high to low. In other words, transistor Tp1 functions as an amplifier that amplifies and detects the level of the output signal from multiplexer MUX.

[0170] The gate of transistor Tp2 is connected to the drain of transistor Tp1. The source of transistor Tp2 is connected to the source of transistor Tn1 in common with the source of transistor Tp1. The drain of transistor Tp2 is connected to the drain of transistor Tn3. When transistor Tp1 changes from a conductive state to a non-conductive state, transistor Tp2 changes from a non-conductive state to a conductive state, thereby inverting the drain voltage of transistor Tp2 from low level to high level.

[0171] The transistor Tn2 is connected between the drain of the transistor Tp1 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp1. The transistor Tn3 is connected between the drain of the transistor Tp2 and the ground GND and functions as a constant current source for supplying a constant current to the transistor Tp2.

[0172] The AZ switch SWAZ is connected between the gate of the transistor Tp1 and the gate of the transistor Tp2, and performs an auto-zero operation by equalizing the potential between the gate and drain of the transistor Tp1 before the output signal of the sample-and-hold unit 125 is detected.

[0173] The output circuit 121b includes p-type transistors Tp3 and Tp4 and n-type transistors Tn4 and Tn5. Transistor Tp3 is connected between the power supply voltage VDD node and the output terminal OUT of the comparator 121. Transistor Tn5 is connected between the source of transistor Tn4 and ground GND. The gates of transistors Tp3 and Tn5 are connected in common. Transistors Tp3 and Tn5 serve to fix the output OUT to a high level outside the count period. Transistors Tp4 and Tn4 are connected in series between the power supply voltage VDD node and the drain of transistor Tn5. The node between transistors Tp4 and Tn4 forms the output terminal OUT. The gates of transistors Tp4 and Tn4 are connected in common to the output of the input comparison circuit 121a (the drain of transistor Tp2). Transistors Tp4 and Tn4 function as an inverter circuit.

[0174] When the drain voltage of the transistor Tp2 is inverted from low to high, the output terminal OUT of the comparator 121 is inverted from high to low by the transistors Tp4 and Tn4. The inversion of the voltage level of the output terminal OUT is used to stop the operation of the counter 122, thereby enabling AD conversion.

[0175] 8 is a timing diagram of the imaging device 1 according to the first embodiment. Fig. 8 shows the pixel drive order of the Nth pixel row (abbreviated as "row N") from the top, the pixel drive order of the (N+1)th pixel row (abbreviated as "row N+1"), the sample or hold (AD) order of the third SH circuit SHC3 and ADC 105, the sample or hold (AD) order of the second SH circuit SHC2 and ADC 105, the sample or hold (AD) order of the first SH circuit SHC1 and ADC 105, the order of pixel signals on the bypass wiring, the horizontal synchronization signal XHS, and output data after AD. In Figure 8, the sample or hold (AD) order of the third SH circuit SHC3 and ADC 105 is represented as Sample&Hold_3, the sample or hold (AD) order of the second SH circuit SHC2 and ADC 105 is represented as Sample&Hold_2, and the sample or hold (AD) order of the first SH circuit SHC1 and ADC 105 is represented as Sample&Hold_1.

[0176] The pixel PX in the Nth row connected to the vertical signal line VSL in Figure 7 outputs pixel signals to the vertical signal line VSL in the order of ultra-low sensitivity reset level NH2DOL, ultra-low sensitivity signal level SH2DOL, medium sensitivity reset level NH2, high sensitivity reset level NH1, high sensitivity signal level SH1, medium sensitivity signal level SH2, low sensitivity signal level SL, and low sensitivity reset level NL.

[0177] The pixel PX outputs a pixel signal of an ultra-low sensitivity reset level NH2DOL to the vertical signal line VSL from time t1 to t2. The third SH circuit SHC3 samples this reset level NH2DOL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t1 to t2. The first SH circuit SHC1 holds the low-sensitivity reset level NL of the (N-2)th row from time t1 to t2, and the ADC 105 performs AD conversion of the held reset level NL.

[0178] The pixel PX outputs a pixel signal of an ultra-low sensitivity signal level SH2DOL to the vertical signal line VSL from time t2 to t3. The first SH circuit SHC1 samples this signal level SH2DOL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t2 to t3. The third SH circuit SHC3 and the ADC 105 hold and AD convert the ultra-low sensitivity reset level NH2DOL sampled by the third SH circuit SHC3 from time t1 to t2 from time t2 to t3. The signal processing circuit 108 outputs the difference (NL-SL) between the ultra-low sensitivity reset level and the signal level of the (N-2)th row from time t2 to t3.

[0179] The pixel PX outputs a pixel signal of the medium-sensitivity reset level NH2 to the vertical signal line VSL from time t3 to t4. The third SH circuit SHC3 samples this reset level NH2. The second SH circuit SHC2 and the ADC 105 do not perform the sample operation or hold operation from time t3 to t4. The first SH circuit SHC1 and the ADC 105 hold and AD convert the ultra-low sensitivity signal level SH2DOL sampled by the first SH circuit SHC1 from time t2 to t3 from time t3 to t4. The signal processing circuit 108 outputs the difference (NL-SL) between the ultra-low sensitivity reset level and the signal level of the (N-2)th row from time t3 to t4, following on from time t2 to t3.

[0180] The pixel PX outputs a pixel signal of the high-sensitivity reset level NH1 to the vertical signal line VSL from time t4 to t5. The first to third SH circuits SHC1 to SHC3 and the ADC 105 do not perform sample and hold operations from time t4 to t5. The multiplexer MUX selects the high-sensitivity reset level NH1 on the vertical signal line VSL from time t4 to t5. The signal processing circuit 108 outputs the difference (NH2DOL-SH2DOL) between the ultra-low-sensitivity reset level and the signal level of the Nth row from time t4 to t5.

[0181] The pixel PX outputs a pixel signal of the high-sensitivity signal level SH1 to the vertical signal line VSL from time t5 to t6. The first to third SH circuits SHC1 to SHC3 and the ADC 105 do not perform sample and hold operations from time t5 to t6. The multiplexer MUX selects the high-sensitivity signal level SH1 on the vertical signal line VSL from time t5 to t6. The signal processing circuit 108 outputs the difference between the ultra-low-sensitivity reset level and the signal level (NH2DOL-SH2DOL) from time t5 to t6, as it did from time t4 to t5.

[0182] The pixel PX outputs a pixel signal of a medium-sensitivity signal level SH2 to the vertical signal line VSL from time t6 to t7. The first SH circuit SHC1 samples this signal level SH2. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t6 to t7. From time t6 to t7, the ADC 105 holds and AD-converts the medium-sensitivity reset level NH2 sampled by the third SH circuit SHC3 from time t3 to t4. From time t6 to t7, the signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and the signal level of the Nth row.

[0183] The pixel PX outputs a pixel signal of a low-sensitivity signal level SL to the vertical signal line VSL from time t7 to t8. The third SH circuit SHC3 samples this signal level SL. The second SH circuit SHC2 and the ADC 105 do not perform a sample operation or a hold operation from time t7 to t8. The first SH circuit SHC1 and the ADC 105 hold and AD convert the medium-sensitivity signal level SH2 sampled by the first SH circuit SHC1 from time t6 to t7 from time t7 to t8. The signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and the signal level of the Nth row from time t7 to t8, as it did from time t6 to t7.

[0184] The pixel PX outputs a pixel signal of the low-sensitivity reset level NL to the vertical signal line VSL from time t8 to t17. The low-sensitivity reset level NL is not determined until the discharge of the accumulated charge in the charge storage unit C14 is completed. Therefore, the detection period of the low-sensitivity reset level NL is extended. The third SH circuit SHC3 samples the low-sensitivity signal level SL of the Nth row from time t8 to t9. This sampling continues until time t16. The first SH circuit SHC1 samples the low-sensitivity reset level NL of the (N-1)th row from time t8 to t9. The second SH circuit SHC2 and the ADC 105 hold and AD-convert the low-sensitivity signal level SL of the (N-1)th row from time t8 to t9. The signal processing circuit 108 outputs the difference (NH2-SH2) between the high-sensitivity reset level and the signal level of the Nth row from time t8 to t9.

[0185] After time t9, while the third SH circuit SHC3 is waiting for the discharge of the charge storage unit C14 to be completed, readout of the pixel signals of the (N+1)th row begins. As with the Nth row, the pixel signals of the (N+1)th row are read out using the same vertical signal lines VSL as the Nth row in the order of an ultra-low sensitivity reset level NH2DOL, an ultra-low sensitivity signal level SH2DOL, a medium sensitivity reset level NH2, a high sensitivity reset level NH1, a high sensitivity signal level SH1, a medium sensitivity signal level SH2, a low sensitivity signal level SL, and a low sensitivity reset level NL.

[0186] From time t9 to t10, the pixel PX outputs the ultra-low-sensitivity reset level NH2 for the (N+1)th row to the vertical signal line VSL, and the second SH circuit SHC2 samples this reset level NH2. From time t9 to t10, the ADC 105 holds and AD-converts the low-sensitivity reset level NL for the (N-1)th row sampled by the first SH circuit SHC1 from time t8 to t9. From time t9 to t10, the ADC 105 waits for AD conversion of the low-sensitivity signal level SL for the Nth row sampled by the third SH circuit SHC3 until discharge of the charge storage unit C14 is completed. From time t9 to t10, the signal processing circuit 108 outputs the difference (NH2-SH2) between the high-sensitivity reset level and the signal level for the Nth row, as it did from time t8 to t9.

[0187] The pixel PX outputs the ultra-low sensitivity signal level SH2DOL of the (N+1)th row to the vertical signal line VSL from time t10 to t11, and the first SH circuit SHC1 samples this signal level SH2DOL. From time t10 to t11, the ADC 105 performs AD conversion on the ultra-low sensitivity reset level NH2DOL of the (N+1)th row sampled by the second SH circuit SHC2 from time t9 to t10. The third SH circuit SHC3 does not perform sample and hold from time t10 to t11. From time t10 to t11, the signal processing circuit 108 outputs the difference (NL-SL) between the low sensitivity reset level and the signal level of the (N-1)th row.

[0188] The pixel PX outputs a medium-sensitivity reset level NH2 for the (N+1)th row to the vertical signal line VSL from time t11 to t12, and the second SH circuit SHC2 samples this reset level NH2. The first SH circuit SHC1 and the third SH circuit SHC3 do not perform sample and hold operations from time t11 to t12. The signal processing circuit 108 outputs the difference (NL-SL) between the low-sensitivity reset level for the (N-1)th row and the signal level from time t11 to t12, as it did from time t10 to t11.

[0189] The pixel PX outputs the high-sensitivity reset level NH1 of the (N+1)th row to the vertical signal line VSL from time t12 to t13. The multiplexer MUX selects this reset level NH1. The first to third SH circuits SHC1 to SHC3 do not perform sample and hold operations from time t12 to t13. The signal processing circuit 108 outputs the difference (NH2DOL-SH2DOL) between the ultra-low-sensitivity reset level of the (N+1)th row and the signal level from time t12 to t13.

[0190] The pixel PX outputs the high-sensitivity signal level SH1 of the (N+1)th row to the vertical signal line VSL from time t13 to t14. The multiplexer MUX selects this signal level SH1. The first to third SH circuits SHC1 to SHC3 do not perform sample and hold operations from time t13 to t14. The signal processing circuit 108 outputs the difference (NH2DOL-SH2DOL) between the ultra-low-sensitivity reset level and the signal level of the (N+1)th row from time t13 to t14, following on from time t12 to t13.

[0191] The pixel PX outputs a medium-sensitivity signal level SH2 for the (N+1)th row to the vertical signal line VSL from time t14 to t15, and the first SH circuit SHC1 samples this signal level SH2. The second SH circuit SHC2 and the ADC 105 hold and AD-convert the medium-sensitivity reset level NH2 for the (N+1)th row sampled by the second SH circuit SHC2 from time t11 to t12. The third SH circuit SHC3 does not sample and hold from time t14 to t15. The signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and signal level for the (N+1)th row from time t14 to t15.

[0192] The pixel PX outputs the low-sensitivity signal level SL of the (N+1)th row to the vertical signal line VSL from time t15 to t16, and the second SH circuit SHC2 samples this signal level SL. From time t15 to t16, the first SH circuit SHC1 and the ADC 105 hold and AD-convert the medium-sensitivity signal level SH2 of the (N+1)th row sampled by the first SH circuit SHC1 from time t14 to t15. The third SH circuit SHC3 does not perform sampling and holding from time t15 to t16. From time t15 to t16, the signal processing circuit 108 outputs the difference (NH1-SH1) between the high-sensitivity reset level and signal level of the (N+1)th row, as it did from time t14 to t15.

[0193] From time t16 onwards, the pixel PX outputs the low-sensitivity reset level NL of the (N+1)th row to the vertical signal line VSL. The first SH circuit SHC1 samples the low-sensitivity reset level NL of the Nth row from time t16 to t17. The first SH circuit SHC1 and the ADC 105 hold and AD-convert the low-sensitivity signal level SL of the Nth row sampled by the first SH circuit SHC1 from time t7 to t8 from time t16 to t17. The second SH circuit SHC2 does not sample and hold the pixel signal from time t16 to t17. The signal processing circuit 108 outputs the difference (NH2-SH2) between the medium-sensitivity reset level of the (N+1)th row and the signal level from time t16 to t17.

[0194] From time t17 to t18, the first SH circuit SHC1 and the ADC 105 hold and AD convert the low-sensitivity reset level NL of the Nth row sampled by the first SH circuit SHC1 from time t16 to t17. From time t17 to t18, the signal processing circuit 108 outputs the difference (NH2-SH2) between the medium-sensitivity reset level and the signal level of the (N+1)th row, as was the case from time t16 to t17. Thereafter, from time t18 to t19, the signal processing circuit 108 outputs the difference (NL-SL) between the low-sensitivity reset level and the signal level of the Nth row.

[0195] Thus, in the first embodiment, during a standby period in which one of the three SH circuits SHC1 to SHC3 samples and holds the reset level of the ultra-low sensitivity pixel signal, at least one other SH circuit samples and holds the low-sensitivity, medium-sensitivity, and high-sensitivity pixel signals of another pixel group arranged in the second direction. More specifically, the multiplexer MUX selects one of the three hold signals sampled and held by the three SH circuits SHC1 to SHC3 and the pixel signal on the vertical signal line VSL, and supplies the selected signal to the analog-to-digital converter. Of the three SH circuits SHC1 to SHC3, the remaining SH circuits other than the SH circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low-sensitivity, medium-sensitivity, and high-sensitivity pixel signals within one horizontal line period. The SH circuit that samples and holds the low-sensitivity pixel signal samples and holds the reset level of the low-sensitivity pixel signal during the next horizontal line period, and the remaining SH circuits sample and hold the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals in groups of pixels adjacent in the second direction during the next horizontal line period.

[0196] Fig. 9 is a circuit diagram of the main components of an image pickup device 100 according to a comparative example. The image pickup device 100 according to the comparative example shown in Fig. 9 differs from the image pickup device 1 according to the first embodiment shown in Fig. 7 in that the number of SH circuits is reduced by one. Hereinafter, the two SH circuits that the image pickup device 100 according to the comparative example has for each vertical signal line will be referred to as the first and second SH circuits SHC1 and SHC2. The other configuration in Fig. 9 is the same as that in Fig. 7.

[0197] Fig. 10 is a timing diagram of the image pickup device 100 according to a comparative example. The operation from time t21 to t28 in Fig. 10 is the same as the operation from time t1 to t8 in Fig. 8, but in Fig. 10, the sampling operation of the third SH circuit SHC3 in Fig. 8 is performed by the second SH circuit SHC2.

[0198] Between times t28 and t29, the ADC 105 holds and AD-converts the low-sensitivity signal level SL sampled by the second SH circuit SHC2 between times t27 and t28. This process is performed between times t17 and t18 in FIG. 8. The first SH circuit SHC1 maintains the sampling operation of the low-sensitivity reset level NL until the discharge of the charge storage unit C14 is completed.

[0199] During the period from time t29 to t30, the pixel signals of the adjacent (N+1)th row are not read out, and the first SH circuit SHC1 waits until the discharge of the charge storage unit C14 is completed. At time t30, the first SH circuit SHC1 completes the sampling operation of the low-sensitivity reset level NL.

[0200] Between times t30 and t31, the first SH circuit SHC1 and the ADC 105 hold and AD convert the low-sensitivity reset level NL sampled by the first SH circuit SHC1 between times t29 and t30. Between times t28 and t30, the signal processing circuit 108 outputs the difference (NH2-SH2) between the medium-sensitivity reset level and the signal level. Thereafter, between times t31 and t32, the signal processing circuit 108 outputs the difference (NL-SL) between the low-sensitivity reset level and the signal level.

[0201] In this way, in the imaging device 100 according to the comparative example, if it takes a long time to read out pixel signals of some sensitivities, the time required for one horizontal line period to read out pixel signals of all sensitivities becomes longer, and the frame rate decreases.

[0202] In contrast, the imaging device 1 according to the first embodiment is provided with three SH circuits, and one of the SH circuits reads out pixels in an adjacent pixel row while reading out pixel signals of a certain sensitivity. This allows pixel signals of all sensitivities to be read out in a short time, and the horizontal line period can be shortened compared to the comparative example, thereby improving the frame rate.

[0203] Second Embodiment Various modifications are possible to the circuit configuration of the comparator 121 included in the ADC 105 in the first embodiment. Fig. 11 is a circuit diagram of the main components of an image pickup device 1a according to a second embodiment. In Fig. 11, circuit elements common to those in Fig. 7 are assigned the same reference numerals, and the following description will focus on the differences.

[0204] The imaging device 1a according to the second embodiment shown in Fig. 11 has a comparator 121 with a circuit configuration different from that of the imaging device 1 according to the first embodiment shown in Fig. 7. The circuit configuration other than the comparator 121 in the imaging device 1 in Fig. 11 is the same as that in Fig. 7.

[0205] The comparator 121 in Fig. 11 includes an input comparison circuit 121a and an output circuit 121b. The input comparison circuit 121a in Fig. 11 includes a current source CS5 that configures a differential amplifier, a pair of NMOS transistors T21 and T22, a pair of PMOS transistors T23 and T24, capacitors C1 to C4, switches SW21 to SW23, and a PMOS transistor T25 and an NMOS transistor T26 that are cascode-connected between a power supply voltage node and a ground node.

[0206] One end of capacitor C1 is connected to the output node of multiplexer MUX, and the other end of capacitor C1 is connected to the gate of transistor T21. One end of capacitor C2 receives reference signal RAMP, and the other end of capacitor C2 is connected to the gate of transistor T22. Switch SW21 is connected between the gate and drain of transistor T21, and when switch SW21 is turned on, the gate and drain of transistor T21 are short-circuited. Switch SW22 is connected between the gate and drain of transistor T22, and when switch SW22 is turned on, the gate and drain of transistor T22 are short-circuited.

[0207] The source of the transistor T23 is connected to the power supply voltage node, and the drain of the transistor T23 is connected to the drain of the transistor T21 and the output node of the input comparison circuit 121a. The gate of the transistor T23 is connected to the gate and drain of the transistor T24.

[0208] The source of the transistor T24 is connected to the power supply voltage node, and the drain of the transistor T24 is connected to the drain of the transistor T22. The capacitor C3 is connected between the power supply voltage node and the output node of the input comparison circuit 121a.

[0209] The output circuit 121b includes a PMOS transistor T25 and an NMOS transistor T26 cascode-connected between the power supply voltage node and the ground node, a PMOS transistor T27 and an NMOS transistor T28 cascode-connected between the power supply voltage node and the ground node, and a switch SW23 and a capacitor C4 connected in series between the drain of the transistor T26 and the ground node. The gate of the transistor T25 is connected to the output node of the input comparison circuit 121a. The gate of the transistor T26 is connected to the connection node between the switch SW23 and the capacitor C4.

[0210] The transistors T27 and T28 form an inverter. The drain of the transistor T25, the drain of the transistor T26, the gate of the transistor T27, and the gate of the transistor T28 are connected together.

[0211] Fig. 12 is a circuit diagram of a main part of an image pickup device 1b according to a modified example of the second embodiment. The image pickup device 1b according to the modified example shown in Fig. 12 has a different circuit configuration of a comparator 121 from the image pickup device 1 shown in Fig. 11.

[0212] 12 includes an input comparison circuit 121a and an output circuit 121b. The input comparison circuit 121a includes a current source CS5 that configures a differential amplifier, a pair of PMOS transistors T31 and T32, a pair of NMOS transistors T33 and T34, capacitors C1 to C5, switches SW31 to SW33, and a PMOS transistor T35 and an NMOS transistor T36 that are cascode-connected between a power supply voltage node and a ground node.

[0213] One end of capacitor C1 is connected to the output node of multiplexer MUX, and the other end of capacitor C1 is connected to the gate of transistor T31. A reference signal RAMP is input to one end of capacitor C2, and the other end of capacitor C2 is connected to the gate of transistor T31. Switch SW31 is connected between the gate and drain of transistor T31, and when switch SW31 is turned on, the gate and drain of transistor T31 are short-circuited. The drain of transistor T31 is connected to the drain and gate of transistor T33 and the gate of transistor T34.

[0214] One end of capacitor C5 is connected to the gate of transistor T32, and the other end of capacitor C5 is grounded. Switch SW32 is connected between the gate and drain of transistor T32, and when switch SW32 is turned on, the gate and drain of transistor T32 are short-circuited. The drain of transistor T32 is connected to the drain of transistor T34 and the gate of transistor T36.

[0215] The current source CS5 is connected between the power supply voltage node and the sources of the transistors T31 and T32.

[0216] The source of transistor T35 is connected to the power supply voltage node. A switch SW33 is connected between the gate and drain of transistor T35, and when switch SW33 is turned on, the gate and drain of transistor T35 are short-circuited. The drain of transistor T36 is connected to the drain of transistor T35 and the output node of input comparison circuit 121a, and the source of transistor T36 is grounded.

[0217] The output circuit 121b has PMOS transistors T37 to T39 and NMOS transistors T40 to T42. The transistors T37, T38, and T41 are cascode-connected between a power supply voltage node and a ground node. The transistors T39 and T42 form an inverter. The gate of the transistor T40 is connected to the output node of the input comparison circuit 121a and the input node of the output circuit 121b. The drain of the transistor T40 is connected to the drain of the transistor T38, the drain of the transistor T41, the gate of the transistor T39, and the gate of the transistor T42. The sources of the transistors T40 to T42 are grounded.

[0218] 13 is a voltage waveform diagram of the output node of the input comparison circuit 121a of FIG. 12. In the input comparison circuit 121a of FIG. 11, the gate voltage of transistor T21 changes according to the signal level of the pixel signal. Furthermore, a reference signal RAMP, whose signal level changes with time, is input to the gate of transistor T22. The input comparison circuit 121a outputs a signal indicating whether the gate voltages of transistors T21 and T22 match. However, because the signal levels of both the pixel signal and the reference signal RAMP change, the signal comparison range of the input comparison circuit 121a must be widened, and the power supply voltage of the input comparison circuit 121a must be set high.

[0219] In contrast, in the input comparison circuit 121a of Fig. 12 , a signal having a voltage level obtained by combining the pixel signal and the reference signal RAMP is input to the gate of transistor T31. The signal level of the pixel signal varies depending on the illuminance, but a reference signal having a fixed signal level is input to the gate of transistor T32. As shown in Fig. 13 , the input comparison circuit 121a of Fig. 12 detects the timing (black plot in Fig. 13 ) at which the signal obtained by combining the pixel signal and the reference signal becomes the same signal level as the reference signal, even if the signal level of the pixel signal changes. This makes it possible to narrow the signal comparison range of the input comparison circuit 121a, lower the power supply voltage of the input comparison circuit 121a, and reduce power consumption.

[0220] As described in the second embodiment above, the comparator 121 in the imaging device 1 according to the first embodiment can have various circuit configurations, and the comparator 121 described in the first and second embodiments is merely one example.

[0221] Third Embodiment In the image pickup devices 1, 1a, and 1b according to the first and second embodiments, the sample and hold unit 125 provided between the vertical signal line VSL and the ADC 105 has three SH circuits SHC1 to SHC3, but the sample and hold unit 125 may have three or more SH circuits. As the number of SH circuits increases, the number of pixel rows from which pixel signals are read out in parallel can be increased, but the circuit scale of the sample and hold unit 125 increases, and the operations of the sample and hold unit 125 and the ADC 105 become more complex.

[0222] 14 is a circuit diagram of the main components of an image pickup device 1c according to the third embodiment. In the image pickup device 1c according to the third embodiment, a sample-and-hold unit 125 arranged between each vertical signal line VSL and the ADC 105 includes four SH circuits SHC1 to SHC4 and a multiplexer MUX. In other words, the sample-and-hold unit 125 in FIG. 7 has one more SH circuit. The image pickup device 1 in FIG. 14 is configured similarly to the image pickup device 1 in FIG. 7, except that it has one more SH circuit.

[0223] 14 are referred to as the first to fourth SH circuits SHC1 to SHC4. The circuit configurations of the first to third SH circuits SHC1 to SHC3 are the same as those in FIG. 7, and therefore detailed description thereof will be omitted.

[0224] The fourth SH circuit SHC4, like the first to third SH circuits SHC1 to SHC3, is provided between the pixel array unit 101 and the comparator 121 and is configured to sample and hold pixel signals. The fourth SH circuit SHC4 includes a capacitor Cp4, a transistor Tr4, switches SW10 to SW12, and a constant current source CS4. The fourth SH circuit SHC4 samples pixel signals from the same vertical signal line VSL as the first SH circuit SHC1 at different timings. Therefore, the first to fourth SH circuits SHC1 to SHC4 can sample and hold multiple pixel signals with different sensitivities or conversion efficiencies from the same pixel PX.

[0225] One end of the capacitor Cp4 is connected to the vertical signal line VSL via the switch SW10, and can store a charge corresponding to a pixel signal, and the other end of the capacitor Cp4 is connected to the gate of the transistor Tr4.

[0226] The drain of transistor Tr4 is connected to constant current source CS4 and multiplexer MUX, and its source is connected to ground (reference voltage source) GND. Constant current source CS4 is connected between the power supply voltage VDD node and the drain of transistor Tr4, and passes a constant current through the drain of transistor Tr4. Transistor Tr4 passes a current between its drain and source that corresponds to the potential of its gate. As a result, the drain of transistor Tr4 has a potential that corresponds to the potential of its gate. The drain of transistor Tr4 is connected to multiplexer MUX, and the drain voltage of transistor Tr4 is output as the output signal of the fourth SH circuit SHC4.

[0227] The switch SW10 is connected between the capacitor Cp4 and the vertical signal line VSL. The switch SW11 is connected between the drain of the transistor Tr4 and one end of the capacitor Cp4. The switch SW12 is connected between the drain of the transistor Tr4 and the other end of the capacitor Cp4.

[0228] When the fourth SH circuit SHC4 samples the pixel signal on the vertical signal line VSL to the capacitor Cp4, the switches SW10 and SW12 are turned on. At this time, the switch SW11 is turned off. As a result, the pixel signal is transmitted to one end of the capacitor Cp4, and the capacitor node opposite the gate of the transistor Tr4 is set to a potential corresponding to the pixel signal. On the other hand, when the capacitor Cp4 holds the pixel signal, the switches SW10 and SW12 are turned off and the switch SW11 is turned on. As a result, the pixel signal stored in the capacitor Cp4 is held. At this time, the gate of the transistor Tr4 is brought into a conductive state (analog state) corresponding to the pixel signal, and the drain of the transistor Tr4 is maintained at a potential corresponding to the pixel signal. Therefore, the fourth SH circuit SHC4 outputs an output signal corresponding to the pixel signal to the multiplexer MUX.

[0229] 15 is a timing diagram of an image pickup device 1c according to the third embodiment. In the image pickup device 1c according to the third embodiment, the discharge period of the charge storage unit C14 is longer than that of the first embodiment shown in FIG. 8, and the discharge period of the charge storage unit C14 is set over two horizontal line periods. In FIG. 5, the sample or hold (AD) order of the fourth SH circuit SHC4 and the ADC 105 is represented as Sample&Hold_4, the sample or hold (AD) order of the third SH circuit SHC3 and the ADC 105 is represented as Sample&Hold_3, the sample or hold (AD) order of the second SH circuit SHC2 and the ADC 105 is represented as Sample&Hold_2, and the sample or hold (AD) order of the first SH circuit SHC1 and the ADC 105 is represented as Sample&Hold_1.

[0230] The operation from time t41 to t45 is the same as that from time t1 to t8 in FIG. 8. From time t41 to t45, the fourth SH circuit SHC4 in FIG. 14 operates in the same manner as the third SH circuit SHC3 in FIG. 8, and the third SH circuit SHC3 in FIG. 14 operates in the same manner as the first SH circuit SHC1 in FIG. 8. The fourth SH circuit SHC4 waits until time t53, having sampled the low-sensitivity signal level SL of the Nth row just before time t45. The third SH circuit SHC3 samples and holds the low-sensitivity reset level NL of the (N-2)th row during the period from time t45 to t46. The first SH circuit SHC1 holds the low-sensitivity signal level SL of the (N-2)th row at time t45. The first SH circuit SHC1 and the third SH circuit SHC3 sample and hold pixel signals of sensitivities other than low sensitivity on the (N+1)th row during the period from time t46 to t49.

[0231] The third SH circuit SHC3 samples and holds the low-sensitivity reset level NL of the (N-1)th row during the period from time t49 to t50. The second SH circuit SHC2 holds the low-sensitivity signal level SL of the (N-1)th row at time t49. The second SH circuit SHC2 and the third SH circuit SHC3 sample and hold pixel signals of sensitivities other than low sensitivity of the (N+2)th row during the period from time t50 to t53.

[0232] The fourth SH circuit SHC4 holds the low-sensitivity signal level SL of the Nth row at time t53. The third SH circuit SHC3 samples and holds the low-sensitivity reset level NL of the Nth row during the period from time t53 to t54. The third SH circuit SHC3 and the fourth SH circuit SHC4 sample and hold pixel signals of sensitivities other than low sensitivity of the (N+3)th row during the period from time t54 to t57.

[0233] In this way, the low-sensitivity reset level NL of the pixel PX to be read out in each pixel row is sampled after waiting until the discharge period of the charge storage section C14 ends, in order to ensure a discharge period spanning two horizontal line periods.

[0234] The signal processing circuit 108 outputs the difference (NL-SL) between the low-sensitivity reset level and signal level of the (N-3)th row from time t42 to t43, outputs the ultra-low-sensitivity difference (NH2DOL-SH2DOL) of the Nth row from time t43 to t44, outputs the high-sensitivity difference (NH1-SH1) of the Nth row from time t44 to t45, outputs the medium-sensitivity difference (NH2-SH2) of the Nth row from time t45 to t46, and outputs the low-sensitivity difference (NL-SL) of the (N-2)th row from time t46 to t47.

[0235] Next, the signal processing circuit 108 outputs the ultra-low sensitivity difference (NH2DOL-SH2DOL) of the (N+1)th row from time t47 to t48, outputs the high sensitivity difference (NH1-SH1) of the (N+1)th row from time t48 to t49, outputs the medium sensitivity difference (NH2-SH2) of the (N+1)th row from time t49 to t50, and outputs the low sensitivity difference (NL-SL) of the (N-1)th row from time t50 to t51.

[0236] Next, the signal processing circuit 108 outputs the ultra-low sensitivity difference (NH2DOL-SH2DOL) of the (N+2)th row from time t51 to t52, outputs the high sensitivity difference (NH1-SH1) of the (N+2)th row from time t52 to t53, outputs the medium sensitivity difference (NH2-SH2) of the (N+2)th row from time t53 to t54, and outputs the low sensitivity difference (NL-SL) of the Nth row from time t54 to t55.

[0237] Next, the signal processing circuit 108 outputs the ultra-low sensitivity difference (NH2DOL-SH2DOL) of the (N+3)th row from time t55 to t56, outputs the high sensitivity difference (NH1-SH1) of the (N+3)th row from time t56 to t57, outputs the medium sensitivity difference (NH2-SH2) of the (N+3)th row from time t57 to t58, and outputs the low sensitivity difference (NL-SL) of the (N+1)th row from time t58 to t59.

[0238] Next, the signal processing circuit 108 outputs the ultra-low sensitivity difference (NH2DOL-SH2DOL) of the (N+4)th row from time t59 to t60, outputs the high sensitivity difference (NH1-SH1) of the (N+4)th row from time t60 to t61, outputs the medium sensitivity difference (NH2-SH2) of the (N+4)th row from time t61 to t62, and then outputs the low sensitivity difference (NL-SL) of the (N+2)th row, although this is omitted in FIG. 15.

[0239] In this way, the multiplexer MUX according to the third embodiment selects one of the four hold signals sampled and held by the four sample and hold circuits SHC1 to SHC4 and the pixel signal on the vertical signal line VSL, and supplies the selected signal to the analog-to-digital converter. Of the four sample and hold circuits SHC1 to SHC4, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low-sensitivity, medium-sensitivity, and high-sensitivity pixel signals within one horizontal line period. The sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the reset level of the low-sensitivity pixel signal within two horizontal line periods following one horizontal line period. The remaining sample and hold circuits sample and hold the ultra-low-sensitivity, medium-sensitivity, and high-sensitivity pixel signals of two pixel groups adjacent in the second direction during the next two horizontal line periods.

[0240] The first SH circuit SHC1, the second SH circuit SHC2, and the fourth SH circuit SHC4 take turns sampling the low-sensitivity signal level SL, shifted by one horizontal line period, and then wait two horizontal line periods before sampling the low-sensitivity reset level NL. During the period in which the first SH circuit SHC1, the second SH circuit SHC2, or the fourth SH circuit SHC4 waits to sample the low-sensitivity reset level NL, other SH circuits are used to read out pixels in two adjacent pixel rows.

[0241] In this way, in the third embodiment, the sample-and-hold unit 125 is provided with four SH circuits SHC1 to SHC4, so that the low-sensitivity signal level SL is sampled, followed by a wait of two horizontal line periods before sampling the low-sensitivity reset level NL, and pixels in two adjacent pixel rows can be read out during this wait period. This ensures a sufficient discharge period for the charge storage unit C14 of the pixel PX without changing the one horizontal line period and the frame rate, thereby improving the image quality of the captured image.

[0242] (Fourth embodiment) The signal processing circuit 108 performs CDS processing to calculate the difference between the reset level and the signal level of the same sensitivity. As shown in the timing diagrams of Fig. 8 and Fig. 15, the timing for calculating the difference between the reset level and the signal level differs for each sensitivity. Therefore, it is desirable that the signal processing circuit 108 be provided with a delay circuit that adjusts the time of the difference between the reset level and the signal level for each sensitivity.

[0243] FIG. 16 is a diagram illustrating an example of the delay circuit 2 provided in the signal processing circuit 108. The delay circuit 2 has multiple latch circuits 2a that hold the above-described differences for each sensitivity. The example in FIG. 16 shows the timing diagram of the first embodiment shown in FIG. 8. The signal processing circuit 108 has a latch circuit 2a that delays the ultra-low sensitivity difference, a latch circuit 2b that delays the high sensitivity difference, and a latch circuit 2c that delays the medium sensitivity difference. These latch circuits 2a, 2b, and 2c can synchronize the timing of the differences between the ultra-low sensitivity, high sensitivity, and medium sensitivity. For example, the delay circuit 2 synchronizes the timing of multiple differential signals so that differential signals between multiple signal levels corresponding to four or more sensitivities and a reset level are output at the same time. More specifically, the delay circuit 2 synchronizes the timing of the multiple differential signals to match the timing at which one of the three or more sample-and-hold circuits holds a pixel signal output to the vertical signal line VSL from a pixel row having a charge storage unit C14 that has finished discharging.

[0244] On the other hand, since the low-sensitivity difference is generated later than the above-mentioned three differences, the signal processing circuit 108 has three latch circuits 2e, 2f, and 2g that further delay the above-mentioned three differences in accordance with the latch circuit 2d that delays the low-sensitivity difference, thereby making it possible to align the timing of the four sensitivity differences.

[0245] In this way, in the fourth embodiment, even if the timing for taking the difference between the reset level and signal level of some sensitivities is delayed, the delay time for the differences of other sensitivities can be adjusted to match that timing, thereby making it possible to align the timing for taking the differences of all sensitivities.

[0246] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0247] FIG. 17 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0248] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 17, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0249] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0250] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0251] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0252] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0253] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0254] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0255] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0256] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0257] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 17, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0258] FIG. 18 is a diagram showing an example of the installation position of the imaging unit 12031.

[0259] In FIG. 18, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0260] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0261] 18 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0262] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0263] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0264] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0265] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0266] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the imaging unit 12031 among the components described above. Specifically, the imaging device 1 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0267] The present technology may have the following configurations: (1) An imaging device comprising: pixels each having a photoelectric conversion element that accumulates a charge corresponding to the amount of incident light and that generate a pixel signal corresponding to the charge; signal lines that transmit the pixel signals; an analog-to-digital converter that converts the pixel signals on the signal lines into digital pixel signals; three or more sample-and-hold circuits that sample and hold the pixel signals on the signal lines; and a selection circuit that selects one of the three or more hold signals held by the three or more sample-and-hold circuits and the pixel signals on the signal lines and supplies the selected signal to the analog-to-digital converter. (2) The imaging device according to (1), comprising: a pixel array unit having a plurality of the pixels arranged in a first direction and a second direction that intersect with each other; and a plurality of signal lines that are arranged in the first direction and that transmit the pixel signals generated by two or more of the pixels arranged in the second direction, respectively; (3) The imaging device according to (2), wherein, of the three or more sample and hold circuits provided for each of the plurality of signal lines, a sample and hold circuit that samples and holds the pixel signal that takes time to stabilize samples and holds the pixel signal after a waiting period until the pixel signal stabilizes, and other sample and hold circuits sample and hold the pixel signals generated by other pixels during the waiting period. (4) The imaging device according to (3), wherein each of the plurality of pixels outputs a plurality of the pixel signals having different sensitivities at different times, and the three or more sample and hold circuits and the analog-to-digital converter perform a sampling operation, a holding operation, and an analog-to-digital conversion operation of the plurality of pixel signals having different sensitivities in parallel.(5) The imaging device according to (4), wherein each of the plurality of pixels switches the sensitivity of the corresponding pixel between four or more levels, and outputs the pixel signal divided into a signal level and a reset level for each sensitivity with a time lag, and the three or more sample and hold circuits provided for each of the plurality of signal lines sample and hold the signal level and the reset level of the pixel signal with a time lag for each sensitivity. (6) The imaging device according to (5), wherein the signal level and the reset level of the pixel signal of the same sensitivity are sampled and held by the same sample and hold circuit. (7) The imaging device according to any one of (2) to (6), wherein the pixel array unit has a plurality of pixel groups arranged in the second direction, each including two or more of the pixels arranged in the first direction, and wherein sample and hold circuits other than some of the three or more sample and hold circuits sample and hold pixel signals output to the signal lines from a pixel group other than one of the pixel groups during a period when the some sample and hold circuits are waiting to sample the pixel signal of one of the pixel groups. (8) The imaging device according to (7), wherein the pixels have charge accumulation units that store accumulated charges in the photoelectric conversion elements, the some of the sample and hold circuits wait until discharge of the charge accumulation units of the pixels to be read out of any of the pixel groups is completed, and then sample and hold the pixel signals, and the sample and hold circuits other than the some of the sample and hold circuits among the three or more sample and hold circuits sample and hold the pixel signals output to the signal lines from a pixel group other than any of the pixel groups during a discharge period of the charge accumulation units. (9) The imaging device according to (8), wherein the any of the pixel groups and the other pixel group are a first pixel group and a second pixel group that are adjacent to each other in the second direction.(10) The imaging device according to (9), wherein one sample and hold circuit of the three or more sample and hold circuits samples and holds a pixel signal output to the signal line from the first pixel group including the pixel having the charge accumulation portion that has finished discharging, and the other sample and hold circuits of the three or more sample and hold circuits sample and hold a pixel signal output from the second pixel group to the signal line during a discharging period of the charge accumulation portion. (11) The imaging device according to (10), wherein the other sample and hold circuit of the three or more sample and hold circuits samples and holds a reset level of the pixel signal after the charge accumulation portion is discharged, after the other sample and hold circuits sample and hold the pixel signal output from the second pixel group to the signal line and the analog-to-digital converter converts it into a digital pixel signal. (12) The imaging device according to any one of (8) to (12), wherein the selection circuit selects in turn hold signals of sample and hold circuits other than the one sample and hold circuit among the three or more sample and hold circuits and the pixel signal on the signal line during a period in which the one sample and hold circuit is on standby until discharging of the charge accumulation unit is completed, and then selects a reset level of the pixel signal after discharging of the charge accumulation unit that has been sampled and held by the one sample and hold circuit. (13) The imaging device according to any one of (8) to (12), wherein the pixel has a plurality of the photoelectric conversion elements each having a different light receiving area, and the charge accumulation unit holds charges photoelectrically converted by at least some of the plurality of photoelectric conversion elements. (14) The imaging device described in any one of (8) to (12), wherein the pixel has: a first photoelectric conversion element; a first floating diffusion region; a second floating diffusion region; a second photoelectric conversion element; a first transistor that switches whether or not to transfer at least a portion of the charge photoelectrically converted and accumulated in the first photoelectric conversion element and the charge held in the first floating diffusion region to the second floating diffusion region; and a second transistor that drains the charge held in the charge accumulation section, and the charge accumulation section holds the charge photoelectrically converted in the second photoelectric conversion element.(15) The imaging device according to any one of (8) to (14), further comprising: a signal processing circuit that generates, based on the digital pixel signal, a differential signal between a reset level and a signal level of the digital pixel signal for each of four or more sensitivities; and a delay circuit that aligns the timing of the differential signals so that the differential signals corresponding to the four or more sensitivities are output at the same timing. (16) The imaging device according to (15), wherein the delay circuit aligns the timing of the differential signals to match the timing at which one of the three or more sample and hold circuits holds a pixel signal output to the signal line from a pixel group having the charge accumulation section that has finished discharging. (17) The imaging device according to any one of (8) to (16), wherein each of the plurality of pixels generates four pixel signals, each divided into a signal level and a reset level, for four different sensitivities. (18) The imaging device described in (17), wherein the four sensitivities are ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity, and during a standby period in which any of the three or more sample-and-hold circuits samples and holds the reset level of the pixel signal of the ultra-low sensitivity, at least one other sample-and-hold circuit samples and holds the pixel signals of the low sensitivity, the medium sensitivity, and the high sensitivity in other pixel groups arranged in the second direction.(19) The imaging device described in (18), wherein the selection circuit selects one of the three hold signals sampled and held by the three sample and hold circuits and the pixel signal on the signal line and supplies the selected signal to the analog-to-digital converter; among the three sample and hold circuits, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals within one horizontal line period; the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the reset level of the low-sensitivity pixel signal in the horizontal line period following the one horizontal line period; and the remaining sample and hold circuits sample and hold the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals in the pixel groups adjacent in the second direction in the next horizontal line period. (20) The imaging device described in (18), wherein the selection circuit selects one of the four hold signals sampled and held by the four sample and hold circuits and the pixel signal on the signal line and supplies the selected one to the analog-to-digital converter; among the four sample and hold circuits, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the signal levels and reset levels of the ultra-low sensitivity, medium sensitivity, and high-sensitivity pixel signals within one horizontal line period; the sample and hold circuit that samples and holds the low-sensitivity pixel signal sample and hold the reset level of the low-sensitivity pixel signal within two horizontal line periods following the one horizontal line period; and the remaining sample and hold circuits sample and hold the ultra-low sensitivity, medium sensitivity, and high sensitivity pixel signals of two pixel groups adjacent in the second direction during the next two horizontal line periods.

[0268] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0269] 1, 1a, 1b, 1c Imaging device, 2 Delay circuit, 2a, 2b, 2c, 2d, 2e, 2f, 2g Latch circuit, 12 VSL boost circuit, 100 Imaging device, 101 Pixel array section, 102 Timing control circuit, 103 Vertical scanning circuit, 104 Charge storage section, 105 ADC, 106 Horizontal transfer scanning circuit, 107 Amplifier circuit, 108 Signal processing circuit, 109 Pixel drive line, 111 Horizontal transfer line, 121 Comparator, 121a Input comparison circuit, 121b Output circuit, 122 Counter, 123 Latch circuit, 125 Sample hold section, 310 Negative capacitance circuit, 511 Semiconductor chip, 512 Semiconductor chip, 513 Via region, 514 Via region, 516 Logic circuit, 517 Peripheral circuit

Claims

a pixel having a photoelectric conversion element that accumulates a charge according to the amount of incident light, and that generates a pixel signal according to the charge; a signal line for transmitting the pixel signal; an analog-to-digital converter for converting the pixel signal on the signal line into a digital pixel signal; three or more sample-and-hold circuits that sample and hold the pixel signals on the signal lines; a selection circuit that selects one of the three or more hold signals held by the three or more sample-and-hold circuits and the pixel signal on the signal line and supplies the selected signal to the analog-to-digital converter; Imaging device. 　 a pixel array unit having a plurality of the pixels arranged in a first direction and a second direction that intersect with each other; a plurality of the signal lines that are arranged in the first direction and transmit the pixel signals generated by two or more of the pixels that are arranged in the second direction, the three or more sample-and-hold circuits, the selection circuit, and the analog-to-digital converter are provided for each of the plurality of signal lines; The imaging device according to claim 1 . 　 Among the three or more sample and hold circuits provided for each of the plurality of signal lines, a sample and hold circuit that samples and holds the pixel signal that takes time to stabilize samples and holds the pixel signal after a waiting period until the pixel signal stabilizes, and other sample and hold circuits sample and hold the pixel signals generated by other pixels during the waiting period. The imaging device according to claim 2 . 　 each of the plurality of pixels outputs a plurality of pixel signals having different sensitivities at different times; the three or more sample-and-hold circuits and the analog-to-digital converter perform a sample operation, a hold operation, and an analog-to-digital conversion operation of the plurality of pixel signals having different sensitivities in parallel; The imaging device according to claim 3 . 　 each of the plurality of pixels switches the sensitivity of the corresponding pixel among four or more levels, and outputs the pixel signal divided into a signal level and a reset level for each sensitivity with a time lag; the three or more sample-and-hold circuits provided for each of the plurality of signal lines sample and hold the signal level and the reset level of the pixel signal with a time lag for each sensitivity; The imaging device according to claim 4 . 　 The signal level and the reset level of the pixel signals having the same sensitivity are sampled and held by the same sample-and-hold circuit. The imaging device according to claim 5 . 　 the pixel array unit has a plurality of pixel groups that each include two or more of the pixels arranged in the first direction and are arranged in the second direction; sample and hold circuits other than some of the sample and hold circuits among the three or more sample and hold circuits sample and hold pixel signals output to the signal line from a pixel group other than the one of the pixel groups during a period when the one of the sample and hold circuits is waiting to sample the pixel signal in the one of the pixel groups; The imaging device according to claim 2 . 　 the pixel has a charge storage unit that stores the accumulated charge of the photoelectric conversion element, the part of the sample and hold circuits waits until discharge of the charge accumulation unit of the pixel to be read out in any one of the pixel groups is completed, and then samples and holds the pixel signal; the sample and hold circuits excluding the part of the sample and hold circuits among the three or more sample and hold circuits sample and hold the pixel signals output to the signal lines from a pixel group different from any one of the pixel groups during a discharge period of the charge accumulation unit; The imaging device according to claim 7 . 　 the one pixel group and the different pixel group are a first pixel group and a second pixel group adjacent to each other in the second direction; The imaging device according to claim 8 . 　 one sample hold circuit among the three or more sample hold circuits samples and holds a pixel signal output to the signal line from the first pixel group including the pixel having the charge storage portion that has finished discharging; the sample and hold circuits other than the one sample and hold circuit among the three or more sample and hold circuits sample and hold pixel signals output from the second pixel group to the signal lines during a discharge period of the charge accumulation unit; The imaging device according to claim 9 . 　 the one sample and hold circuit among the three or more sample and hold circuits samples and holds a reset level of the pixel signal after the charge accumulation unit is discharged, after the sample and hold circuits other than the one sample and hold circuit sample and hold the pixel signal output from the second pixel group to the signal line and the analog-to-digital converter converts it into a digital pixel signal; The imaging device according to claim 10. 　 the selection circuit selects in turn the hold signals of the sample and hold circuits other than the one sample and hold circuit among the three or more sample and hold circuits and the pixel signal on the signal line during a period in which the one sample and hold circuit is waiting until the discharge of the charge accumulation unit is completed, and then selects a reset level of the pixel signal sampled and held by the one sample and hold circuit after the discharge of the charge accumulation unit. The imaging device according to claim 11. 　 The pixel has a plurality of the photoelectric conversion elements each having a different light receiving area, the charge accumulation unit holds charges photoelectrically converted by at least some of the plurality of photoelectric conversion elements. The imaging device according to claim 8 . 　 The pixel is a first photoelectric conversion element; a first floating diffusion region; a second floating diffusion region; a second photoelectric conversion element; a first transistor that switches whether or not to transfer at least a portion of the charges accumulated by photoelectric conversion in the first photoelectric conversion element and the charges held in the first floating diffusion region to the second floating diffusion region; a second transistor that discharges the charge stored in the charge storage portion; the charge accumulation unit holds charges photoelectrically converted by the second photoelectric conversion element. The imaging device according to claim 8 . 　 a signal processing circuit that generates, for each of four or more sensitivities based on the digital pixel signal, a difference signal between a reset level and a signal level of the digital pixel signal; a delay circuit that aligns the timing of the plurality of differential signals so that the plurality of differential signals corresponding to four or more sensitivities are output at the same timing; The imaging device according to claim 8 . 　 the delay circuit aligns the timing of the plurality of differential signals to a timing at which one of the three or more sample-and-hold circuits holds a pixel signal output to the signal line from the pixel group having the charge accumulation section that has finished discharging. The imaging device according to claim 15. 　 Each of the plurality of pixels generates four pixel signals having four different sensitivities, each divided into a signal level and a reset level. The imaging device according to claim 8 . 　 The four sensitivities are ultra-low sensitivity, low sensitivity, medium sensitivity, and high sensitivity; during a standby period in which any one of the three or more sample and hold circuits samples and holds a reset level of the pixel signal of the ultra-low sensitivity, at least one other sample and hold circuit samples and holds the pixel signals of the low sensitivity, the medium sensitivity, and the high sensitivity in another pixel group arranged in the second direction; The imaging device according to claim 17. 　 the selection circuit selects one of the three hold signals sampled and held by the three sample-and-hold circuits and the pixel signal on the signal line, and supplies the selected signal to the analog-to-digital converter; Among the three sample-and-hold circuits, the remaining sample-and-hold circuits other than the sample-and-hold circuit that samples and holds the pixel signal of the low sensitivity sample and hold the signal levels and reset levels of the pixel signals of the ultra-low sensitivity, the medium sensitivity, and the high sensitivity within one horizontal line period; a sample-and-hold circuit that samples and holds the low-sensitivity pixel signal samples and holds a reset level of the low-sensitivity pixel signal during a horizontal line period next to the horizontal line period; the remaining sample-and-hold circuits sample and hold the pixel signals of the very low sensitivity, the medium sensitivity, and the high sensitivity in the pixel groups adjacent in the second direction during the next horizontal line period; The imaging device according to claim 18. 　 the selection circuit selects one of the four hold signals sampled and held by the four sample-and-hold circuits and the pixel signal on the signal line, and supplies the selected signal to the analog-to-digital converter; Among the four sample and hold circuits, the remaining sample and hold circuits other than the sample and hold circuit that samples and holds the pixel signal of the low sensitivity sample and hold the signal levels and reset levels of the pixel signals of the ultra-low sensitivity, the medium sensitivity, and the high sensitivity within one horizontal line period; a sample-and-hold circuit that samples and holds the low-sensitivity pixel signal samples and holds a reset level of the low-sensitivity pixel signal within two horizontal line periods following the one horizontal line period; the remaining sample-and-hold circuits sample and hold the pixel signals of the very low sensitivity, the medium sensitivity, and the high sensitivity in two pixel groups adjacent in the second direction during the next two horizontal line periods; The imaging device according to claim 18.

Images