Multilayer ceramic electronic component

Abstract

The present invention provides a multilayer ceramic electronic component with which it is possible to suppress the occurrence of cracks in a laminate. In a multilayer ceramic electronic component (1), at the interface between a first main surface (TS1) of a laminate (10) and a conductive resin layer (60), the first main surface (TS1) includes a first contact surface (TS1A) having an Sdr of 0.1 or less. At the interface between a second main surface (TS2) of the laminate (10) and the conductive resin layer (60), the second main surface (TS2) includes a second contact surface (TS2A) having an Sdr of 0.1 or less.

Description

Multilayer ceramic electronic components

[0001] The present invention relates to a multilayer ceramic electronic component.

[0002] In recent years, multilayer ceramic capacitors as multilayer ceramic electronic components have been required to be durable in harsh environments, such as those exposed to bending stress due to thermal expansion. To address this demand, a technique using a thermosetting conductive resin paste for the external electrodes of a multilayer ceramic capacitor has been known. Patent Document 1 (JP-A-2003-102666) describes this type of technique. Patent Document 1 describes a multilayer ceramic capacitor having external electrodes with a layered structure in which an electrode layer formed by applying a conductive paste by dipping and baking the paste, a conductive epoxy-based thermosetting resin layer, a nickel-plated layer, and a tin-based layer are sequentially laminated.

[0003] Japanese Patent Application Publication No. 11-162771

[0004] The multilayer ceramic capacitor of Patent Document 1 can prevent cracks from occurring in the laminate due to stress relaxation caused by sacrificial fracture and deformation of the resin layer. However, in recent years, durability in even harsher environments has been required, and in such environments, the stress relaxation effect may not function well, resulting in cracks occurring in the laminate.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0006] A multilayer ceramic electronic component according to the present invention comprises: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, the external electrode layers comprising a fired electrode layer, a conductive resin layer disposed on the fired electrode layer, and a plating layer disposed on the conductive resin layer, wherein at the interface between the first main surface of the laminate and the conductive resin layer, the first main surface includes a first contact surface having an Sdr of 0.1 or less, and at the interface between the second main surface of the laminate and the conductive resin layer, the second main surface includes a second contact surface having an Sdr of 0.1 or less.

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0008] 7 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; FIG. 1 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. 1; FIG. 2 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2; FIG. 3 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2; FIG. 4 is a view showing a profile of a first contact surface of a laminate in Example 3; FIG. 5 is a view showing a profile of a second contact surface of a laminate in Comparative Example 1; FIG. 6 is a table showing experimental results of Experimental Example 1; FIG. 7 is a graph showing Sa and Sdr of a sample used in Experimental Example 1; FIG. 8 is an enlarged view of a portion V of the multilayer ceramic capacitor shown in FIG. 2; FIG. 9 is an enlarged view of a portion VI of the multilayer ceramic capacitor shown in FIG. 7;

[0009] Embodiments A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to a first embodiment of the present disclosure will now be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 1 taken along line II-II. FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along line III-III. FIG. 4 is a cross-sectional view of the multilayer ceramic capacitor 1 of FIG. 2 taken along line IV-IV.

[0010] The drawings may be drawn in a simplified schematic form to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is 10 for the sake of convenience, but this does not indicate the actual number of internal electrode layers 30. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to include a range within which similar functions can be expected.

[0011] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40 .

[0012] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0013] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 that face each other in a stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in a width direction W that is perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 that face each other in a length direction L that is perpendicular to the stacking direction T and the width direction W.

[0014] As shown in FIG. 1 , the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three faces of the laminate 10 intersect, and a ridge is a portion where two faces of the laminate 10 intersect. Incidentally, unevenness or the like may be formed on part or all of the surfaces constituting the laminate 10.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] 2 and 3 , the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12A as a first outer layer portion and a second main surface side outer layer portion 12B as a second outer layer portion, which are arranged to sandwich the inner layer portion 11 in the stacking direction T. When there is no need to particularly distinguish between the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B, the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B may be collectively referred to as outer layer portions 12. Furthermore, when there is no need to particularly distinguish between the first main surface TS1 and the second main surface TS2, the first main surface TS1 and the second main surface TS2 may be collectively referred to as the main surfaces.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second main surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor. The internal layer portion 11 is also referred to as an effective layer portion.

[0018] The dielectric layers 20 are made of a dielectric material, such as BaTiO ３ , CaTiO ３ , SrTiO ３ , or CaZrO ３ The dielectric material may be a dielectric ceramic containing components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, Ni compounds, etc., added to the above main components.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0020] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20 therebetween.

[0021] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0022] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31 and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other with the dielectric layer 20 interposed therebetween, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion 31B and the second lead portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W of the first opposing portion 31A and the width direction W of the first lead portion 31B may be the same, or one of the dimensions may be smaller. The width direction W of the second opposing portion 32A and the width direction W of the second lead portion 32B may be the same, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0028] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0031] The laminate 10 has side surface outer layer portions. The side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also referred to as W gaps or side gaps.

[0032] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion includes a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portion is also referred to as an L gap or end gap.

[0033] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A includes a first end face side external electrode 40A1, a first main surface side external electrode 40A2, and a first side surface side external electrode 40A3. The first end face side external electrode 40A1 is disposed on the first end face LS1. The first main surface side external electrode 40A2 is connected to the first end face side external electrode 40A1 and is disposed on a portion of the first main surface TS1 and the second main surface TS2 on the side of the first end face LS1. The first side surface side external electrode 40A3 is connected to the first end surface side external electrode 40A1 and is disposed on a portion of the first side surface WS1 and the second side surface WS2 on the first end surface LS1 side. In this manner, the first external electrode 40A is formed to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0035] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B includes a second end face side external electrode 40B1, a second main surface side external electrode 40B2, and a second side surface side external electrode 40B3. The second end face side external electrode 40B1 is disposed on the second end face LS2. The second main surface side external electrode 40B2 is connected to the second end face side external electrode 40B1 and is disposed on a portion of the first main surface TS1 and the second main surface TS2 on the second end face LS2 side. The second side surface side external electrode 40B3 is connected to the second end surface side external electrode 40B1 and is disposed on a portion of the first side surface WS1 and the second side surface WS2 on the second end surface LS2 side. In this manner, the second external electrode 40B is formed to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0036] As described above, in the laminate 10, capacitance is formed by the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 facing each other via the dielectric layer 20. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0037] The first external electrode 40A has a first base electrode layer 50A containing a metal component, a first conductive resin layer 60A disposed on the first base electrode layer 50A, and a first plating layer 70A disposed on the first conductive resin layer 60A.

[0038] The first base electrode layer 50A has a first end surface side base electrode layer 50A1, a first main surface side base electrode layer 50A2, and a first side surface side base electrode layer 50A3.

[0039] The first conductive resin layer 60A includes a first end surface side conductive resin layer 60A1, a first main surface side conductive resin layer 60A2, and a first side surface side conductive resin layer 60A3.

[0040] The first plating layer 70A includes a first end surface-side plating layer 70A1, a first main surface-side plating layer 70A2, and a first side surface-side plating layer 70A3. The first plating layer 70A may also have a two-layer structure including a first Ni plating layer 71A as a lower plating layer and a first Sn plating layer 72A as an upper plating layer. The first Ni plating layer 71A includes a first end surface-side Ni plating layer 71A1, a first main surface-side Ni plating layer 71A2, and a first side surface-side Ni plating layer 71A3. The first Sn plating layer 72A includes a first end surface-side Sn plating layer 72A1, a first main surface-side Sn plating layer 72A2, and a first side surface-side Sn plating layer 72A3.

[0041] The second external electrode 40B has a second base electrode layer 50B containing a metal component, a second conductive resin layer 60B disposed on the second base electrode layer 50B, and a second plating layer 70B disposed on the second conductive resin layer 60B.

[0042] The second base electrode layer 50B has a second end surface side base electrode layer 50B1, a second main surface side base electrode layer 50B2, and a second side surface side base electrode layer 50B3.

[0043] The second conductive resin layer 60B includes a second end surface side conductive resin layer 60B1, a second main surface side conductive resin layer 60B2, and a second side surface side conductive resin layer 60B3.

[0044] The second plating layer 70B includes a second end surface side plating layer 70B1, a second main surface side plating layer 70B2, and a second side surface side plating layer 70B3. The second plating layer 70B may also have a two-layer structure including a second Ni plating layer 71B as a lower plating layer and a second Sn plating layer 72B as an upper plating layer. The second Ni plating layer 71B includes a second end surface side Ni plating layer 71B1, a second main surface side Ni plating layer 71B2, and a second side surface side Ni plating layer 71B3. The second Sn plating layer 72B includes a second end surface side Sn plating layer 72B1, a second main surface side Sn plating layer 72B2, and a second side surface side Sn plating layer 72B3.

[0045] Here, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to a cross section LW at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40. When there is no need to distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the base electrode layer 50.

[0046] Furthermore, when there is no need to particularly distinguish between the first conductive resin layer 60A and the second conductive resin layer 60B, the first conductive resin layer 60A and the second conductive resin layer 60B may be collectively referred to as the conductive resin layer 60.

[0047] Furthermore, when it is not necessary to particularly distinguish between the first plating layer 70A and the second plating layer 70B, the first plating layer 70A and the second plating layer 70B may be collectively referred to as plating layer 70. When it is not necessary to particularly distinguish between the first Ni plating layer 71A and the second Ni plating layer 71B, the first Ni plating layer 71A and the second Ni plating layer 71B may be collectively referred to as Ni plating layer 71. When it is not necessary to particularly distinguish between the first Sn plating layer 72A and the second Sn plating layer 72B, the first Sn plating layer 72A and the second Sn plating layer 72B may be collectively referred to as Sn plating layer 72.

[0048] Next, a description will be given of the base electrode layer 50. The base electrode layer 50 has a first base electrode layer 50A and a second base electrode layer 50B.

[0049] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first internal electrode layer 31. The first base electrode layer 50A may also be disposed on a portion of the first main surface TS1, a portion of the second main surface TS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the first base electrode layer 50A is arranged such that the above-mentioned first end surface side base electrode layer 50A1 is arranged on the first end surface LS1, the above-mentioned first main surface side base electrode layer 50A2 is arranged so as to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the above-mentioned first side surface side base electrode layer 50A3 is arranged so as to extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0050] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is connected to the second internal electrode layer 32. The second base electrode layer 50B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the second base electrode layer 50B is arranged such that the above-mentioned second end surface side base electrode layer 50B1 is arranged on the second end surface LS2, the above-mentioned second main surface side base electrode layer 50B2 is arranged so as to extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the above-mentioned second side surface side base electrode layer 50B3 is arranged so as to extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0051] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers, i.e., baked electrode layers. The baked layer preferably contains a metal component and either a glass component or a ceramic component, or both. This improves the adhesion between the laminate 10 and the base electrode layer 50. The metal component includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, etc. The glass component includes, for example, at least one selected from B, Si, Ba, Mg, Al, Li, etc. The presence of a glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may be, for example, BaTiO ３ , CaTiO ３ , (Ba,Ca)TiO ３ , SrTiO ３ , CaZrO ３ It includes at least one selected from the following:

[0052] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer to obtain a laminate, and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by baking a layer containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0053] The thickness in the longitudinal direction of the first end face side base electrode layer 50A1 located on the first end face LS1 is preferably, for example, about 2 μm or more and 220 μm or less at the center of the first end face side base electrode layer 50A1 in the stacking direction T and width direction W. A more preferable range of the thickness in the longitudinal direction of the first end face side base electrode layer 50A1 is about 10 μm or more and 45 μm or less.

[0054] The thickness in the longitudinal direction of the second end face side base electrode layer 50B1 located on the second end face LS2 is preferably, for example, about 2 μm or more and 220 μm or less at the center of the second end face side base electrode layer 50B1 in the stacking direction T and the width direction W. A more preferable range of the thickness in the longitudinal direction of the second end face side base electrode layer 50B1 is about 10 μm or more and 45 μm or less.

[0055] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the first main surface-side base electrode layer 50A2 provided on this portion is preferably, for example, about 2 μm or more and 40 μm or less at the center of the first main surface-side base electrode layer 50A2 provided on this portion in the length direction L and width direction W. A more preferable range of the thickness in the stacking direction of the first main surface-side base electrode layer 50A2 is about 2 μm or more and 15 μm or less.

[0056] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the widthwise thickness of the first side surface-side base electrode layer 50A3 provided on this portion is preferably, for example, about 2 μm or more and 40 μm or less at the center of the first side surface-side base electrode layer 50A3 provided on this portion in the length direction L and the stacking direction T. A more preferable range of the widthwise thickness of the first side surface-side base electrode layer 50A3 is about 2 μm or more and 15 μm or less.

[0057] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness in the stacking direction of the second main surface-side base electrode layer 50B2 provided on this portion is preferably, for example, about 2 μm or more and 40 μm or less at the center of the second main surface-side base electrode layer 50B2 provided on this portion in the length direction L and width direction W. A more preferable range of the thickness in the stacking direction of the second main surface-side base electrode layer 50B2 is about 2 μm or more and 15 μm or less.

[0058] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness in the width direction of the second side surface side base electrode layer 50B3 provided on this portion is preferably, for example, about 2 μm or more and 40 μm or less at the center of the second side surface side base electrode layer 50B3 provided on this portion in the length direction L and the stacking direction T. A more preferable range of the thickness in the width direction of the second side surface side base electrode layer 50B3 is about 2 μm or more and 15 μm or less.

[0059] Next, a description will be given of the conductive resin layer 60. The conductive resin layer 60 has a first conductive resin layer 60A and a second conductive resin layer 60B.

[0060] The first conductive resin layer 60A is disposed so as to cover the first base electrode layer 50A. An end of the first conductive resin layer 60A is in contact with the laminate 10. The end of the first conductive resin layer 60A refers to a portion of the first conductive resin layer 60A that is closer to the second end face LS2 than the first base electrode layer 50A in the longitudinal direction L. In this embodiment, the first conductive resin layer 60A has the first end face-side conductive resin layer 60A1 disposed on the first end face LS1, the first main face-side conductive resin layer 60A2 disposed so as to extend from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, and the first side face-side conductive resin layer 60A3 disposed so as to extend from the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0061] The second conductive resin layer 60B is disposed so as to cover the second base electrode layer 50B. Preferably, an end of the second conductive resin layer 60B is in contact with the laminate 10. The end of the second conductive resin layer 60B refers to a portion of the second conductive resin layer 60B that is closer to the first end face LS1 than the second base electrode layer 50B in the longitudinal direction L. In this embodiment, the second conductive resin layer 60B has the second end face-side conductive resin layer 60B1 disposed on the second end face LS2, the second main face-side conductive resin layer 60B2 disposed so as to extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and the second side face-side conductive resin layer 60B3 disposed so as to extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0062] The conductive resin layer 60 has a resin portion and conductive fillers dispersed in the resin portion.

[0063] The resin portion of the conductive resin layer 60 may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin is one of the most suitable resins, due to its excellent heat resistance, moisture resistance, and adhesion. Furthermore, the resin portion of the conductive resin layer 60 preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0064] Because the conductive resin layer 60 contains such a resin portion, it is more flexible than the base electrode layer 50, which is made of, for example, a plating film or a fired product of a metal component and a glass component. Therefore, even when the multilayer ceramic capacitor 1 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer 60 functions as a buffer layer. Therefore, the conductive resin layer 60 suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0065] The conductive fillers are dispersed in a substantially uniform distribution within the resin portion, and are primarily responsible for the electrical conductivity of the conductive resin layer 60. Specifically, when multiple conductive fillers come into contact with each other, a conductive path is formed within the conductive resin layer 60, providing electrical continuity between the base electrode layer 50 and the plating layer 70.

[0066] The metal constituting the conductive filler may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, since Ag is a noble metal, it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metal powders.

[0067] Furthermore, the conductive filler may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive filler may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using a metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0068] The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0069] The conductive filler may have an average particle size of, for example, 0.3 μm or more and 10 μm or less.

[0070] The average particle size of the conductive filler contained in the conductive resin layer 60 is calculated by using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0071] Next, the surfaces of the laminate 10 where the ends of the first conductive resin layer 60A and the second conductive resin layer 60B are in contact will be described in detail.

[0072] The surface of the laminate 10 at the interface between the first main surface TS1 of the laminate 10 and the first and second main surface side conductive resin layers 60A2 and 60B2 is referred to as the first contact surface TS1A. That is, the surface of the first main surface TS1 of the laminate 10 that is in contact with the first and second main surface side conductive resin layers 60A2 and 60B2 is referred to as the first contact surface TS1A. Specifically, the first contact surface TS1A is a pair of surfaces provided on both sides of the first main surface TS1 in the X direction. More specifically, each first contact surface TS1A is a substantially rectangular region extending between both edges of the first main surface TS1 in the Y direction. The substantially rectangular shape also includes a bow-like curved shape. Specifically, each first contact surface TS1A may be a bow-like curved region that extends between both edges in the Y direction and is convex toward the center of the length direction L of the laminate 10.

[0073] Here, the surface of the laminate 10 at the interface between the first main surface TS1 of the laminate 10 and the first and second main surface side base electrode layers 50A2 and 50B2 is referred to as a first base contact surface TS1B. That is, the surface of the first main surface TS1 of the laminate 10 that is in contact with the first and second main surface side base electrode layers 50A2 and 50B2 is referred to as a first base contact surface TS1B. The area of ​​each first contact surface TS1A is preferably larger than the area of ​​each first base contact surface TS1B. Furthermore, in the LT cross section at the center in the W direction, the distance L1A in the length direction L of each first contact surface TS1A is preferably longer than the distance L1B in the length direction L of each first base contact surface. This ensures contact between the laminate 10 having the surface condition described below and the conductive resin layer 60, thereby more appropriately achieving the effects of the present disclosure.

[0074] The surface of the laminate 10 at the interface between the second main surface TS2 of the laminate 10 and the first and second main surface side conductive resin layers 60A2 and 60B2, i.e., the surfaces of the second main surface TS2 of the laminate 10 that are in contact with the first and second main surface side conductive resin layers 60A2 and 60B2, are referred to as second contact surfaces TS2A. Specifically, the second contact surfaces TS2A are a pair of surfaces provided on both sides of the second main surface TS2 in the X direction. More specifically, each second contact surface TS2A is a substantially rectangular region extending between both edges of the second main surface TS2 in the Y direction. The term "substantially rectangular" also includes a bow-shaped curved shape. Specifically, each second contact surface TS2A may be a bow-shaped curved region that extends between both edges in the Y direction and is convex toward the center of the length direction L of the laminate 10.

[0075] Here, the surface of the laminate 10 at the interface between the second main surface TS2 of the laminate 10 and the first and second main surface side base electrode layers 50A2 and 50B2 is referred to as a second base contact surface TS2B. That is, the surface of the second main surface TS2 of the laminate 10 that is in contact with the first and second main surface side base electrode layers 50A2 and 50B2 is referred to as a second base contact surface TS2B. The area of ​​each second contact surface TS2A is preferably larger than the area of ​​each second base contact surface TS2B. Furthermore, in the LT cross section at the center in the W direction, the distance L2A in the length direction L of each second contact surface TS2A is preferably longer than the distance L2B in the length direction L of each second base contact surface. This ensures contact between the laminate 10 having the surface condition described below and the conductive resin layer 60, thereby more appropriately achieving the effects of the present disclosure.

[0076] The exposed portions ES are defined as portions of the first and second main surfaces TS1 and TS2 of the laminate 10 that are not in contact with the external electrodes 40. The exposed portions ES are portions of the first and second main surfaces TS1 and TS2 that are sandwiched in the length direction L between the first and second main surface side external electrodes 40A2 and 40B2.

[0077] The surface roughness parameters (Sdr, Sa) of the first contact surface TS1A and the second contact surface TS2A will be described below.

[0078] Sdr (interface developed area ratio) is one of the surface roughness parameters, and indicates how much the developed area (surface area) of a defined region has increased relative to the area of ​​the defined region.

[0079] Sa (arithmetic mean height) is a parameter that expands Ra (arithmetic mean height of a line) to a surface. It represents the average of the absolute values ​​of the height differences of each point relative to the average plane of the surface.

[0080] Here, through repeated investigations, experiments, and simulations, the present inventors have found that what contributes significantly to the occurrence of cracks in the laminate 10 is not the commonly used line roughness parameter Ra (arithmetic mean roughness of a line) or the surface roughness parameter Sa (arithmetic mean height), which is an extension of Ra to a surface, but rather Sdr (developed area ratio of an interface), which is one of the surface roughness parameters. In other words, the present inventors have found that in order to suppress the occurrence of cracks in the laminate 10, it is more important to control Sdr and obtain a surface with an appropriately adjusted Sdr than to control Ra or Sa. This point will be explained using experimental examples described below.

[0081] In this embodiment, Sdr of the first contact surface TS1A and the second contact surface TS2A is 0.1 or less.

[0082] In this embodiment, the Sdr of the first contact surface TS1A and the second contact surface TS2A is preferably 0.025 or more, and the Sdr of the first contact surface TS1A and the second contact surface TS2A is preferably 0.025 or more and 0.1 or less.

[0083] In this embodiment, Sa of the first contact surface TS1A and the second contact surface TS2A may be 0.05 μm or more, or may be 0.1 μm or more. In this embodiment, Sa of the first contact surface TS1A and the second contact surface TS2A may be 0.5 μm or less, or may be 0.4 μm or less. Sa of the first contact surface TS1A and the second contact surface TS2A is preferably 0.05 μm or more and 0.5 μm or less, and may be 0.1 μm or more and 0.4 μm or less, for example.

[0084] Next, a method for measuring the surface roughness parameters (Sdr, Sa) of the surface of the laminate will be described.

[0085] First, a plating remover is used to remove the plating layer 70 of the external electrode 40 without damaging the laminate 10. Next, a solvent is used to remove the conductive resin layer 60 of the external electrode 40 without damaging the laminate 10.

[0086] Next, Sdr and Sa of the first contact surface TS1A and the second contact surface TS2A are measured by a measurement method in accordance with ISO 25178.

[0087] The measurement conditions are as follows: A 50 μm x 50 μm area is measured using a shape analysis laser microscope VK-X100 (manufactured by Keyence Corporation). Surface shape correction (quadratic surface correction) is performed on the obtained data using image analysis software. Gaussian filter processing is then performed. End effect correction is also performed. This allows the state of the first contact surface TS1A and the second contact surface TS2A to be measured appropriately. Note that filtering using a low-pass filter (S-filter) or a high-pass filter (L-filter) and shape correction (F-operation) are not performed. Finally, analysis software is used to determine the surface roughness parameters Sdr and Sa.

[0088] The surface roughness parameters Sdr and Sa are measured at the center of each first contact surface TS1A, and the average values ​​are defined as the surface roughness parameters Sdr and Sa of the first contact surface TS1A in this embodiment. The surface roughness parameters Sdr and Sa are measured at the center of each second contact surface TS2A, and the average values ​​are defined as the surface roughness parameters Sdr and Sa of the second contact surface TS2A in this embodiment.

[0089] It is preferable that the side surfaces of the laminate 10 have a similar surface. That is, of the first side surface WS1 of the laminate 10, the first side surface contact surface in contact with the conductive resin layer 60 preferably has an Sdr of 0.1 or less. Of the second side surface WS2 of the laminate 10, the second side surface contact surface in contact with the conductive resin layer 60 preferably has an Sdr of 0.1 or less. Furthermore, it is preferable that the Sdr of the first side surface contact surface and the second side surface contact surface is 0.025 or more. It is preferable that the Sdr of the first side surface contact surface and the second side surface contact surface is 0.025 or more and 0.1 or less. The Sa of the first side surface contact surface and the second side surface contact surface may be 0.05 μm or more, or may be 0.1 μm or more. The Sa of the first side surface contact surface and the second side surface contact surface may be 0.5 μm or less, or may be 0.4 μm or less. The Sa of the first contact surface TS1A and the second contact surface TS2A is preferably, for example, 0.05 μm or more and 0.5 μm or less, and may be 0.1 μm or more and 0.4 μm or less.

[0090] The longitudinal thickness of the first end surface side conductive resin layer 60A1 located on the first end surface LS1 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the first end surface side conductive resin layer 60A1.

[0091] The longitudinal thickness of the second end surface side conductive resin layer 60B1 located on the second end surface LS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the stacking direction T and width direction W of the second end surface side conductive resin layer 60B1.

[0092] When the first conductive resin layer 60A is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the first main surface side conductive resin layer 60A2 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the first main surface side conductive resin layer 60A2 provided on this portion.

[0093] When the first conductive resin layer 60A is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the first side surface side conductive resin layer 60A3 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first side surface side conductive resin layer 60A3 provided on this portion.

[0094] When the second conductive resin layer 60B is provided on a portion of the first main surface TS1 side and a portion of the second main surface TS2 side, the thickness in the stacking direction T of the second main surface side conductive resin layer 60B2 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second main surface side conductive resin layer 60B2 provided on this portion.

[0095] When the second conductive resin layer 60B is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the second side surface side conductive resin layer 60B3 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second side surface side conductive resin layer 60B3 provided on this portion.

[0096] Next, a description will be given of the plating layer 70. The plating layer 70 has a first plating layer 70A and a second plating layer 70B.

[0097] The first plating layer 70A is disposed so as to cover the first conductive resin layer 60A. In this embodiment, the first plating layer 70A is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the first plating layer 70A is disposed such that the first end face-side plating layer 70A1 described above is disposed on the first end face LS1, the first main face-side plating layer 70A2 described above is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the first side face-side plating layer 70A3 described above is disposed so as to extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0098] The second plating layer 70B is disposed so as to cover the second conductive resin layer 60B. In this embodiment, the second plating layer 70B is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the second plating layer 70B is disposed such that the second end face-side plating layer 70B1 described above is disposed on the second end face LS2, the second main face-side plating layer 70B2 described above is disposed so as to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the second side face-side plating layer 70B3 described above is disposed so as to extend from the second end face LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0099] The plating layer 70 preferably has a two-layer structure of a Ni plating layer 71 and a Sn plating layer 72. A first Sn plating layer 72A is preferably disposed on the first Ni plating layer 71A, and a second Sn plating layer 72B is preferably disposed on the second Ni plating layer 71B. In this embodiment, the first end surface side Ni plating layer 71A1 and the first end surface side Sn plating layer 72A1 are arranged on the first end surface LS1, the above-mentioned first main surface side Ni plating layer 71A2 and the first main surface side Sn plating layer 72A2 are arranged so as to extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the above-mentioned first side surface side Ni plating layer 71A3 and the first side surface side Sn plating layer 72A3 are arranged so as to extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2. Similarly, the second end face side Ni plating layer 71B1 and the second end face side Sn plating layer 72B1 are arranged on the second end face LS2, the above-mentioned second main face side Ni plating layer 71B2 and the second main face side Sn plating layer 72B2 are arranged so as to extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and the above-mentioned second side face side Ni plating layer 71B3 and the second side face side Sn plating layer 72B3 are arranged so as to extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0100] The Ni plating layer 71 prevents the base electrode layer 50 and the conductive resin layer 60 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer 72 improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0101] The thickness of each of the first Ni plating layer 71A and the first Sn plating layer 72A is preferably 1 μm or more and 15 μm or less.

[0102] The thickness of each of the second Ni plating layer 71B and the second Sn plating layer 72B is preferably 1 μm or more and 15 μm or less.

[0103] If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 in the stacking direction is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. The widthwise dimension of the multilayer ceramic capacitor 1 is defined as W. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0104] <Manufacturing Method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The multilayer ceramic capacitor 1 of this embodiment may be manufactured by any method as long as it satisfies the above-described requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0105] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0106] On the dielectric sheets, the conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0107] A predetermined number of dielectric sheets on which no pattern of internal electrode layers is printed are stacked to form a portion that will become the first main surface side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet on which the pattern of the first internal electrode layer 31 and a dielectric sheet on which the pattern of the second internal electrode layer 32 are printed are stacked in order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the pattern of the internal electrode layers is not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0108] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0109] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0110] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0111] The surface of the laminate 10 after firing is polished by barrel polishing. This polishing is an example of a processing step in which the Sdr of the main surface at the interface between the main surface of the laminate 10 and the conductive resin layer is adjusted to a desired value. The processing step can also be performed after forming a base electrode layer (fired electrode layer), which will be described later. In this barrel polishing, the laminate 10 having the surface disclosed herein can be obtained by adjusting the media material, media shape and size, polishing time, etc. Specifically, by reducing the mass of the media and setting a longer polishing time, a laminate 10 having a surface with a small surface roughness parameter Sdr can be obtained.

[0112] Furthermore, by reducing the mass of the media and setting a longer polishing time, the laminate 10 having the micronized layer of the present disclosure can be obtained. The thickness of the micronized layer can be controlled by adjusting the mass of the media and the rotation conditions of the barrel. For example, the lighter the mass of the media, the thinner the thickness of the micronized layer can be. Furthermore, by increasing the mass of the media, the thickness of the micronized layer can be increased.

[0113] A conductive paste that will become the base electrode layer 50 is applied to both end surfaces of the laminate 10. In this embodiment, the base electrode layer 50 is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0114] In this embodiment, dipping is performed so that the first base electrode layer 50A extends from the first end surface LS1 to portions of the first main surface TS1 and the second main surface TS2. Also, dipping is performed so that the second base electrode layer 50B extends from the second end surface LS2 to portions of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the first base electrode layer 50A extends to portions of the first side surface WS1 and the second side surface WS2. Also, dipping is preferably performed so that the second base electrode layer 50B extends to portions of the first side surface WS1 and the second side surface WS2.

[0115] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, it is preferable to form the baked layer by adding a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are baked simultaneously to form the laminate 10 with the baked layer formed.

[0116] Next, the conductive resin layer 60 is formed. In this embodiment, the conductive resin layer 60 is formed on the surface of the base electrode layer 50 and the surface of the laminate 10.

[0117] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and the conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0118] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 using a dipping method. In this embodiment, the dipping is performed so that the first conductive resin layer 60A extends from the first end surface LS1 to portions of the first main surface TS1 and the second main surface TS2. The dipping is also performed so that the second conductive resin layer 60B extends from the second end surface LS2 to portions of the first main surface TS1 and the second main surface TS2. At the same time, the dipping is preferably performed so that the first conductive resin layer 60A extends to portions of the first side surface WS1 and the second side surface WS2. The dipping is also preferably performed so that the second conductive resin layer 60B extends to portions of the first side surface WS1 and the second side surface WS2.

[0119] After the conductive resin paste is applied onto the base electrode layer 50 by a dipping method, a heat treatment is performed at a temperature of 200° C. to 550° C. This causes the resin portion to thermally harden, forming the conductive resin layer 60. The atmosphere during this heat treatment is N ２ In order to prevent the resin from scattering and the various metal components from being oxidized, it is preferable that the oxygen concentration be kept at 100 ppm or less.

[0120] Thereafter, a plating layer 70 is formed on the surface of the conductive resin layer 60. In this embodiment, a Ni plating layer 71 and a Sn plating layer 72 are formed on the conductive resin layer 60. The Ni plating layer 71 and the Sn plating layer 72 are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0121] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0122] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0123] In the multilayer ceramic capacitor 1 of this embodiment, the Sdr of the first contact surface TS1A and the second contact surface TS2A is 0.1 or less. Therefore, when a flexural stress occurs in the multilayer ceramic capacitor, the conductive resin layer peels off, which makes it possible to alleviate stress concentration during flexure of the laminate 10 and improve mechanical strength. In other words, flexure cracks in the laminate 10 can be suppressed.

[0124] 5A and 5B, and 6A and 6B, Experimental Example 1 conducted by the inventors to confirm the effects of the present disclosure will be described below. Experimental Example 1 evaluates the relationship between Sa and Sdr and the characteristics of the multilayer ceramic capacitor 1. Fig. 5A is a diagram showing the profile of the first contact surface of the laminate in Example 3. Fig. 5B is a diagram showing the profile of the second contact surface of the laminate in Comparative Example 3.

[0125] Examples are described below. Multilayer ceramic capacitors having different Sdr and Sa values ​​for the first contact surface TS1A and the second contact surface TS2A were fabricated in lots as samples of Examples 1 to 8 and Comparative Examples 1 to 4 shown in FIG. 6A according to the manufacturing method described in the above embodiment. The samples within each lot were manufactured under the same manufacturing conditions. For each example, five samples for measuring surface roughness parameters, 30 samples for flex crack tests, and 30 samples for electrode adhesive strength tests were taken from the same lot and prepared. The surface roughness parameters were evaluated using the average values ​​of the measurement results. The surface roughness parameters were measured according to the measurement method described in the above embodiment.

[0126] In manufacturing, each multilayer ceramic capacitor was fabricated according to the following specifications.

[0127] Dimensions of multilayer ceramic capacitor: 2.0 mm (L dimension) x 1.2 mm (W dimension) x 1.2 mm (T dimension) Ceramic material: BaTiO ３Electrostatic capacitance: 4.7 μF Rated voltage: 25 V Structure of external electrodes (1) Base electrode layer: electrode containing conductive metal (Cu) and glass component Thickness of base electrode layer at the center in the height direction located on the first end face and the second end face: 25 μm Thickness of base electrode layer at the center in the length direction located on the first main face and the second main face, the first side face and the second side face: 4 μm (2) Conductive resin layer Conductive resin layer: conductive filler: Ag Resin: epoxy-based Heat curing temperature: 200° C. Thickness of the first conductive resin layer at the center in the height direction located on the first end face and the second end face: 50 μm Thickness of the conductive resin layer at the center in the length direction located on the first main face and the second main face, the first side face and the second side face: 20 μm (3) Ni plating layer Ni plating layer thickness: The thickness of the Ni plating layer at the center in the height direction of the Ni plating layer located on the first end face and the second end face: 2 μm The thickness of the Ni plating layer at the center in the length direction of the Ni plating layer located on the first main face and the second main face, the first side face and the second side face: 2 μm (4) Sn plating layer Sn plating layer thickness: The thickness of the Sn plating layer at the center in the height direction of the Sn plating layer located on the first end face and the second end face: 1.5 μm The thickness of the Sn plating layer at the center in the length direction of the Sn plating layer located on the first main face and the second main face, the first side face and the second side face: 1 μm The experimental results are shown in FIG. 6A.

[0128] The method for measuring the number of flex cracks that occurred in the flex crack test is as follows.

[0129] First, the multilayer ceramic capacitor was mounted on a 1.6 mm thick mounting board using solder paste. Then, a push rod with a curvature radius of 1 μm was used to bend the board from the back side where the multilayer ceramic capacitor was not mounted, applying mechanical stress. The deflection amount was set to 5 mm, and the multilayer ceramic capacitor was bent for 60 seconds. The test conditions were stricter than the AEC-Q200 standard required for automotive electronic components.

[0130] After bending the substrate as described above, the multilayer ceramic capacitor was removed from the substrate, and the cross section was polished to observe whether or not cracks had occurred in the laminate. The cross section was polished so that the LT surface of the multilayer ceramic capacitor was exposed up to a position that was half the width of the multilayer ceramic capacitor in the width direction W connecting the first end face and the second end face.

[0131] For each lot, if the number of samples in which cracks occurred was less than 10 out of the 30 samples subjected to the above test, the evaluation result of the flex crack test was judged to be pass. If the number of samples in which cracks occurred was 10 or more, the evaluation result of the flex crack test was judged to be fail. Furthermore, if the number of samples in which cracks occurred among the passing samples was zero, the test was rated as excellent (◎), and if the number of samples in which cracks occurred was one to nine, the test was rated as good (◯).

[0132] In Examples 1 to 8, Sdr was 0.100 or less, and as a result, excellent results (◎) or good results (◯) were obtained.

[0133] In contrast, in Comparative Examples 1 to 4, Sdr exceeded 0.100, resulting in unfavorable results (×). Specifically, the number of samples in which flexural cracks occurred was 24 in Comparative Example 1, 22 in Comparative Example 2, 24 in Comparative Example 3, and 29 in Comparative Example 4. The reason that Comparative Examples 1 to 4 are less favorable than Examples 1 to 8 is that Sdr exceeded 0.100 in Comparative Examples 1 to 4, which means that the first and second contact surfaces of the laminate have fine irregularities that cannot be expressed by Sa. In such cases, regardless of the magnitude of Sa, the anchor effect prevents the first and second conductive resin layers from peeling off when flexural stress occurs in the multilayer ceramic capacitor. In other words, if the first and second conductive resin layers do not peel off when flexural stress occurs in the multilayer ceramic capacitor, the stress cannot be released, and as a result, cracks are likely to occur in the laminate of the multilayer ceramic capacitor.

[0134] 5A and 5B will be used to explain the profiles (roughness curves) of the first contact surface TS1A and the second contact surface TS2A of the laminate 10. Fig. 5A is a diagram showing the profile of the contact surface of Example 3 as an example of an embodiment. Fig. 5B is a diagram showing the profile of the contact surface of Comparative Example 3 as an example of a comparative example.

[0135] 5A, Example 3 has low Sa (Sa is 0.4 μm or less) and low Sdr (Sdr is 0.032), and is an example in which cracking of the laminate is excellently suppressed. From FIG. 5A, it can be seen that there are no fine irregularities on the first contact surface and the second contact surface of the laminate.

[0136] 5B, Comparative Example 1 is an example in which Sa is low (Sa is 0.4 μm or less) but Sdr is high (Sdr is 0.323), and thus crack suppression of the laminate is insufficient. From FIG. 5B, it can be seen that there are fine irregularities on the first contact surface and the second contact surface of the laminate.

[0137] As described above, both Example 3 and Comparative Example 3 had Sa of 0.4 μm or less, and more specifically, Sa of Comparative Example 3 was lower than Sa of Example 3. However, Example 3 had significantly better evaluation results in the flex crack test. This is thought to be because Sdr of Example 3 was lower than Sdr of Comparative Example 3, and Sdr of Example 3 was 0.100 or less.

[0138] Similarly, comparing Example 4 and Comparative Example 1, both Example 4 and Comparative Example 1 have very low Sa, specifically, Sa of about 0.1 μm. However, Example 4 had significantly better evaluation results in the flex crack test. This is thought to be because the Sdr of Example 4 was lower than that of Comparative Example 1, and the Sdr of Example 4 was 0.100 or less.

[0139] These results show that cracking of the laminate can be suppressed not simply by providing a surface with a low Sa, but also by providing a surface with a low Sdr. The parameter that influences the anchoring effect of fine irregularities is Sdr rather than Sa, and by keeping Sdr within a predetermined range, it is possible to suppress cracking of the laminate.

[0140] In Examples 1 to 4 and 7 to 8, Sdr was 0.100 or less and Sa was 0.4 μm or less, resulting in excellent results (◎) in the flex crack test. In Examples 5 and 6, Sdr was 0.100 or less and Sa exceeded 0.4 μm, resulting in good results (◯) in the flex crack test. As mentioned above, Sdr is the parameter that affects the anchor effect of fine irregularities more than Sa. Therefore, Sdr is thought to contribute more to suppressing cracks in the laminate. However, if Sa becomes too large, stress is likely to concentrate from large irregularities, making cracks more likely to occur. The reason the results of Examples 5 to 6 are lower than those of Examples 1 to 4 and 7 to 8 is that Sa exceeds 0.4 μm in Examples 5 and 6, causing stress to concentrate from large irregularities on the first and second contact surfaces.

[0141] The number of samples in which flexure cracks occurred in Examples 1 to 4 and 7 to 8 was 0, in Example 5 it was 5, and in Example 6 it was 7.

[0142] In the electrode adhesive strength test, the electrode adhesive strength was measured as follows.

[0143] First, the plated multilayer ceramic capacitor was solder-mounted on a substrate. Next, a lateral pushing experiment was conducted in which the multilayer ceramic capacitor was pushed in a direction parallel to the substrate. The multilayer ceramic capacitor was pushed with a force of 18 N for 60 seconds. If the multilayer ceramic capacitor did not come off the substrate, it was considered a pass; if it did come off, it was considered a fail.

[0144] Furthermore, a case where the number of failed samples was 0 was evaluated as excellent (◎), a case where the number of failed samples was 1 to 10 was evaluated as good (◯), and a case where the number of failed samples was 11 to 20 was evaluated as satisfactory (△).

[0145] In Examples 1 to 6, Sdr was 0.025 or more, and as a result, excellent results (◎) or good results (◯) were obtained in the electrode fixing strength test. In contrast, in Examples 7 and 8, Sdr was less than 0.025, and sufficient results (△) were obtained. The reason why the results of Examples 7 and 8 are lower than the results of Examples 1 to 6 is that in Examples 7 and 8, Sdr was less than 0.025 (i.e., the surface was too smooth), so the anchor effect was lost and the first conductive resin layer and the second conductive resin layer easily peeled off.

[0146] In order to alleviate stress concentration when the laminate 10 is bent, it is necessary for the conductive resin layer to peel off when bending stress occurs. However, if the conductive resin layer peels off too easily, there is a possibility that the conductive resin layer will peel off inadvertently. This situation is not desirable in terms of mountability, etc. Therefore, it is preferable that the adhesive strength is such that peeling does not occur in an electrode adhesive strength test, and Sdr is preferably 0.025 or more.

[0147] In Examples 2 to 6, Sa was 0.1 μm or more, and as a result, excellent results (◎) were obtained in the electrode fixing strength test. In contrast, in Example 1, although Sa was less than 0.1 μm, it was 0.05 μm or more, and a good result (◯) was obtained. The reason why the results of Example 1 were lower than those of Examples 2 to 6 is that in Example 1, Sa was less than 0.1 μm (the surface was too smooth), so the anchor effect was lost and the first conductive resin layer and the second conductive resin layer easily peeled off.

[0148] As described above, Sa is considered to have a lower contribution to the anchoring effect than Sdr. However, by setting Sa to 0.1 μm or more, the possibility of the first conductive resin layer and the second conductive resin layer being accidentally peeled off can be further reduced.

[0149] Considering the suppression of cracking in the laminate and the securing of a minimum electrode fixing strength, Sdr is preferably 0.025 or more and 0.1 or less. Sdr may be 0.025 or more and 0.1 or less, and Sa may be 0.05 μm or more, or Sa may be 0.1 μm or more. Alternatively, Sdr may be 0.025 or more and 0.1 or less, and Sa may be 0.05 μm or more and 0.5 μm or less, or 0.1 μm or more and 0.5 μm or less.

[0150] FIG. 6B is a graph with Sa (μm) on the horizontal axis and Sdr on the vertical axis. In the graph plots, (x) indicates Comparative Examples 1 to 4. (◯) indicates Examples 1 to 6. (△) indicates Examples 7 and 8. RS1 is the line indicating an Sdr of 0.1. When Sdr is 0.1 or less, excellent results (◎), good results (◯), or sufficient results (△) were obtained for both the flex cracking and electrode adhesion strength. Boxed RS2 indicates the range where Sdr is 0.025 or more and 0.1 or less, and Sa is 0.05 μm or more and 0.5 or less. Within the range of boxed RS2, excellent results (◎) or good results (◯) were obtained for both the flex cracking and electrode adhesion strength. From the above, it is preferable that Sdr is 0.1 or less. Furthermore, it is more preferable that Sdr is 0.025 or more and 0.1 or less, and Sa is 0.05 μm or more and 0.5 μm or less.

[0151] (Atomized Layer) The presence of the atomized layer ML was confirmed in the samples of Examples 1 to 8. The thickness of the atomized layer ML in each sample was thin, being 10 nm or more and 300 nm or less.

[0152] Here, the fine-grained layer ML has been confirmed on the surface where Sdr is 0.1 or less. With Sdr being 0.1 or less, when flexural stress occurs in the multilayer ceramic capacitor, the conductive resin layer peels off, alleviating stress concentration in the laminate 10. Furthermore, it is thought that the presence of the fine-grained layer ML, in which the grains on the surface of the laminate 10 are finely divided, reduces the starting points of cracks during flexure, making it possible to more effectively suppress flexural cracks in the laminate 10.

[0153] The micro-grain layer in this embodiment will be described in detail below with reference to Fig. 7 and Fig. 8. Fig. 7 is an enlarged view of part V of the multilayer ceramic capacitor 1 shown in Fig. 2. Fig. 8 is an enlarged view of part VI of the multilayer ceramic capacitor 1 shown in Fig. 7.

[0154] As shown in FIGS. 7 and 8 , the outer layer portion 12 includes a micronized layer ML disposed on the surface and a base layer BL disposed closer to the inner layer portion 11 than the micronized layer ML. More specifically, when the first contact surface TS1A and the second contact surface TS2A are collectively defined as the resin contact surface, the outer layer portion 12 includes a micronized layer ML disposed on the resin contact surface side between the resin contact surface and the inner layer portion 11, and a base layer BL disposed closer to the inner layer portion 11 than the micronized layer ML. The average particle diameter of the ceramic particles constituting the micronized layer ML is smaller than the average particle diameter of the ceramic particles constituting the base layer BL. The micronized layer ML is a layer composed of ceramic particles MG that are finer than the ceramic particles BG constituting the base layer BL. The ceramic particles MG constituting the micronized layer ML are preferably pulverized particles. Pulverized particles refer to particles that have been pulverized by the application of a mechanical external force. The pulverized particles are preferably crystalline particles. The crystalline particles refer to particles having crystallinity.

[0155] The thickness t of the fine-grained layer ML is preferably 300 nm or less. The thickness t of the fine-grained layer ML is more preferably 10 nm or more and 300 nm or less. The thickness t of the fine-grained layer ML may be 10% or less of the thickness T of the outer layer portion 12. The thickness t of the fine-grained layer ML may be 1% or less of the thickness T of the outer layer portion 12.

[0156] Preferably, the average particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more, and the average particle diameter d of the ceramic particles constituting the particle-sized layer ML is 50 nm or less. More preferably, the average particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more and 500 nm or less, and the average particle diameter d of the ceramic particles constituting the particle-sized layer ML is 10 nm or more and 50 nm or less. The average particle diameter of the ceramic particles constituting the base layer BL may be larger than the thickness of the particle-sized layer ML. That is, the thickness of the particle-sized layer ML may be smaller than the average particle diameter of the ceramic particles constituting the base layer BL.

[0157] It is preferable that a dislocation crystal layer is disposed between the fine-grained layer ML and the base layer BL. Here, the dislocation crystal layer refers to a particle layer having dislocations (hereinafter referred to as dislocation defects) which are lattice defects in the crystals of the grains constituting the particle layer.

[0158] The degree of irregularity of a surface S2 of the surface of the atomized layer ML that is farther away from the inner layer portion 11 is smaller than the degree of irregularity of a surface S1 of the surface of the atomized layer ML that is closer to the inner layer portion 11.

[0159] 8 shows an enlarged view of portion VI of the multilayer ceramic capacitor 1 shown in FIG. 7. Portion VI indicates a portion where the base electrode layer 50 is not formed. However, the above-described content also applies to portions of the main surface where the base electrode layer 50 is formed. The above-described content also applies to portions where the surface of the laminate 10 is exposed, i.e., exposed portions ES.

[0160] <Methods for Measuring and Confirming Various Structures> Next, methods for confirming various dimensions, such as the length, thickness, and degree of unevenness, of each part of the multilayer ceramic capacitor, as well as the state of the micro-grained layer, will be described. The degree of unevenness may be defined, for example, by the arithmetic average roughness (Ra). The LT cross section shown in FIGS. 7 and 8 can be observed, for example, as follows: The multilayer ceramic capacitor 1 is polished to the center position in the width direction. The cross section exposed by polishing is then observed with a transmission electron microscope (TEM). Furthermore, various dimensions, such as the length, thickness, and degree of unevenness, of each part of the multilayer ceramic capacitor, as well as the state of the micro-grained layer, can be measured and observed from the observed cross section.

[0161] For example, by observing the portion of the LT cross section exposed by polishing that includes the fine-grained layer with a transmission electron microscope (TEM), it is possible to measure various dimensions such as the average particle size of the particles, the thickness of the fine-grained layer, and the degree of surface irregularity of the fine-grained layer.Image analysis software (e.g., WinROOF manufactured by Mitani Shoji Co., Ltd.) can be used to measure various dimensions such as the average particle size of the particles, the thickness of the fine-grained layer, and the degree of surface irregularity of the fine-grained layer.

[0162] As for the measurement positions, for example, the thickness of the micronized layer at the longitudinal center of the first external electrode arranged on the first principal surface and the second principal surface, and the thickness of the micronized layer at the longitudinal center of the second external electrode arranged on the first principal surface and the second principal surface are measured, and the average value thereof is taken as the thickness of the micronized layer in this disclosure.

[0163] For example, the particle size of the particles in the atomized layer is measured by performing image processing on an electron analysis image of the particles taken by a transmission electron microscope (TEM) to identify the outline of each particle and converting it into a circle-equivalent diameter. The average particle size of the particles in the atomized layer is the average value of the measured individual particles.

[0164] The arithmetic mean roughness Ra, which is the degree of unevenness on the surface of the micronized layer, can also be calculated by extracting the contour lines of the surface of the micronized layer from an electron analysis image of the particles taken by a transmission electron microscope (TEM) using image analysis software. Note that when comparing the degrees of unevenness on the surface of the micronized layer, this is done by microscope observation of the LT cross section, rather than by surface measurement using a laser microscope, which was used to measure Sdr and Sa.

[0165] For example, a method for confirming whether a material is crystalline is to check whether a pattern specific to a crystal is obtained by electron diffraction using a transmission electron microscope (TEM).For example, a method for confirming whether a material has dislocation defects is to check whether a dislocation defect is present by observing an electron analysis image using a transmission electron microscope (TEM).

[0166] It is preferable that the side surfaces of the laminate 10 also have a similar surface. That is, the first side surface outer layer portion WG1 has a first side surface contact surface of the first side surface WS1 of the laminate 10 that is in contact with the conductive resin layer 60 and the counter electrode portion 11E, and a fine-grained layer ML arranged on the resin contact surface side between the first side surface WS1 and the counter electrode portion 11E, and a base layer BL arranged closer to the counter electrode portion 11E than the fine-grained layer ML. The second side surface outer layer portion WG2 has a second side surface contact surface of the second side surface WS2 of the laminate 10 that is in contact with the conductive resin layer 60 and the counter electrode portion 11E, and a fine-grained layer ML arranged closer to the resin contact surface between the second side surface WS2 and the counter electrode portion 11E, and a base layer BL arranged closer to the counter electrode portion 11E than the fine-grained layer ML. The above-mentioned content also applies to the portion of the side surface where the base electrode layer 50 is formed. The above-mentioned content also applies to the portion where the surface of the laminate 10 is exposed.

[0167] Experimental Example 2 The inventors conducted Experimental Example 2 to confirm the effects of the present disclosure. Experimental Example 2 evaluated the relationship between the micro-grain layer and the characteristics of the multilayer ceramic capacitor 1. FIG. 9 is a table showing the results of Experimental Example 2. The samples, evaluation items, and evaluation conditions for Experimental Example 2 are as follows. Using the above-described manufacturing method, samples were manufactured in lots, with the manufacturing conditions adjusted to vary the thickness of the micro-grain layer, as samples for Examples 9 to 18 and Comparative Example 5. The samples within each lot were manufactured under the same manufacturing conditions. For each Example, 10 samples were taken from the same lot to measure the thickness of the micro-grain layer and confirm processing stability, and 30 samples were taken from the same lot to prepare the samples for the deflection test. The average value of the measurement results was used for measuring the thickness of the micro-grain layer.

[0168] <Samples> The samples of Examples 9 to 18 and Comparative Example 5 were prepared so that the surface of the laminate after firing was barrel polished using the method described above so that the thickness of the fine-grained layer would be the value shown in Figure 9, by adjusting the barrel rotation conditions and the mass of the media. Comparative Example 5 is a sample that does not have a fine-grained layer. The specifications of the multilayer ceramic capacitor are as follows: - Dimensions of the multilayer ceramic capacitor: 2.0 mm (L dimension) x 1.2 mm (W dimension) x 1.2 mm (T dimension) - Ceramic material: BaTiO ３Electrostatic capacitance: 1.0 μF Rated voltage: 50 V Structure of outer layer Thickness of outer layer: 85 μm Average particle diameter of base layer: 200 nm Average particle diameter of micro-particle layer: 30 nm Structure of external electrode (1) Base electrode layer: electrode containing conductive metal (Cu) and glass component Thickness of base electrode layer at the center in the height direction located on the first end face and the second end face: 15 μm Thickness of base electrode layer at the center in the length direction located on the first main face and the second main face, the first side face and the second side face: 4 μm (2) Conductive resin layer Conductive resin layer: conductive filler: Ag Resin: epoxy-based Heat curing temperature: 200° C. Thickness of first conductive resin layer at the center in the height direction located on the first end face and the second end face: 20 μm (3) Ni plating layer Ni plating layer thickness: The thickness of the Ni plating layer at the center in the height direction of the Ni plating layer located on the first end face and the second end face: 2 μm The thickness of the Ni plating layer at the center in the height direction of the Ni plating layer located on the first main face and the second main face, the first side face and the second side face: 2 μm (4) Sn plating layer Sn plating layer thickness: The thickness of the Sn plating layer at the center in the height direction of the Sn plating layer located on the first end face and the second end face: 1.5 μm The thickness of the Sn plating layer at the center in the length direction of the Sn plating layer located on the first main face and the second main face, the first side face and the second side face: 1 μm

[0169] A deflection test was conducted on the above-prepared Examples 9 to 18 and Comparative Example 5. The deflection test was conducted to confirm the crack generation suppression effect, and the number of generated deflection cracks was confirmed to evaluate the deflection effect. In addition, the processing stability was confirmed and the thickness of the atomized layer was measured on the above-prepared Examples 9 to 18 and Comparative Example 5. Details of the deflection test, confirmation of processing stability, and measurement of the thickness of the atomized layer are described below.

[0170] <Deflection Test> The multilayer ceramic capacitor samples of Examples 9 to 18 and Comparative Example 5 were mounted on a mounting substrate using solder paste. The multilayer ceramic capacitor was oriented such that the first principal surface faced the mounting substrate. The thickness of the mounting substrate was 0.8 mm. A pressing tool was then pressed against the surface of the mounting substrate opposite the mounting surface to bend the mounting substrate. The pressing tool was a pressing rod with a diameter of 5 mm. The amount of deflection of the mounting substrate was 2.0 mm. The mounting substrate was held in its bent state for 5 seconds.

[0171] The multilayer ceramic capacitor was then removed from the mounting board and the presence or absence of cracks was confirmed. Specifically, the laminate was polished from the mounting surface (first main surface) side to expose an LW cross section passing through the center of the laminate in the stacking direction T. The polished surface was observed under a microscope to confirm the presence or absence of cracks in the laminate. The magnification of the microscope was 40x.

[0172] For each lot, if the number of samples in which cracks occurred was less than 10 out of the 30 samples subjected to the above test, the evaluation result of the flex crack test was judged to be pass. If the number of samples in which cracks occurred was 10 or more, the evaluation result of the flex crack test was judged to be fail. Furthermore, if the number of samples in which cracks occurred among the passing samples was zero, the test was rated as excellent (◎), and if the number of samples in which cracks occurred was one to nine, the test was rated as good (◯).

[0173] <Confirmation of processing stability and measurement of the thickness of the micro-grained layer> Processing stability was judged by checking whether at least a part of the micro-grained layer fell off from the outer layer portion during the manufacturing of the multilayer ceramic capacitor. The criterion for the processing stability evaluation result (◎) was that no micro-grained layer was missing from the laminate, which was judged as good. The criterion for the processing stability evaluation result (△) was that slight micro-grained layer was missing from the laminate, which was judged as fair.

[0174] Furthermore, the thickness of the atomized layer was measured according to the measurement method described above. Figure 9 shows the measurement results of the atomized layer thickness, the evaluation results of the flex crack test, and the confirmation results of the processing stability.

[0175] It was confirmed that the number of occurrences of flexure cracks was reduced in Examples 9 to 18, which included the micro-grained layer ML, compared to Comparative Example 5, in which the thickness of the micro-grained layer ML was 0 nm. From these results, it was confirmed that the number of occurrences of flexure cracks could be reduced by forming, in the main-surface-side outer layer portion 12 of the multilayer ceramic capacitor 1, the micro-grained layer ML composed of ceramic particles MG with a particle diameter d smaller than the particle diameter D of the ceramic particles BG constituting the base layer BL.

[0176] It was also found that processing stability could be ensured when the thickness t of the fine-grained layer ML was 300 nm or less. It was also confirmed that the number of occurrences of flexure cracks could be reduced when the thickness t of the fine-grained layer ML was 10 nm or more. Furthermore, it was confirmed that processing stability could be ensured while the number of occurrences of flexure cracks was reduced to zero when the thickness t of the fine-grained layer ML was 10 nm or more and 300 nm or less.

[0177] The Sdr of the first contact surface TS1A and the second contact surface TS2A of the samples of Examples 9 to 18 was 0.1 or less.

[0178] From the above, it was confirmed that particularly good results can be obtained when Sdr of the first contact surface TS1A and the second contact surface TS2A is 0.1 or less and the thickness t of the fine-grained layer ML is 10 nm or more and 300 nm or less.

[0179] The area of ​​the contact surface and the like of the present disclosure will be described in detail with reference to Fig. 10. Fig. 10 is a view of the multilayer ceramic capacitor 1 as viewed from the first main surface TS1 side.

[0180] Here, because the first principal surface TS1 and the second principal surface TS2 have the same structure, the first principal surface TS1 and the second principal surface TS2 are collectively referred to as the principal surface TS in Fig. 10. The first principal surface-side conductive resin layer 60A2 and the second principal surface-side conductive resin layer 60B2 are collectively defined as the principal surface conductive resin layer 602. The first principal surface-side base electrode layer 50A2 and the second principal surface-side base electrode layer 50B2 are collectively defined as the principal surface-side base electrode layer 502.

[0181] The flat surface region of the main surface TS is defined as a flat surface region excluding curved surfaces formed by, for example, chamfering, etc. In other words, the flat surface region is a substantially flat surface portion that does not include rounded portions with curvature provided on ridge lines, for example.

[0182] The first contact surface TS1A is defined as the resin contact surface. A portion of the resin contact surface that is located in the planar region of the main surface TS is defined as the resin contact surface planar region CS1. The resin contact surface planar region CS1 is a portion of the planar region of the main surface TS that comes into contact with the main surface conductive resin layer 602. The resin contact surface planar region CS1 can also be referred to as the planar region of the resin contact surface.

[0183] The first base contact surface TS1B is defined as the base contact surface. The portion of the base contact surface located in the planar region of the main surface TS is defined as the base contact surface planar region CS2. The base contact surface planar region CS2 is the portion of the planar region of the main surface TS that contacts the main surface-side base electrode layer 502. The base contact surface planar region CS2 can also be said to be the portion of the planar region of the main surface TS that contacts the baked layer, i.e., the baked electrode layer. The base contact surface planar region CS2 can also be said to be the planar region of the base contact surface.

[0184] Here, it is preferable that the area of ​​the resin contact surface flat region CS1 is larger than the area of ​​the substrate contact surface flat region CS2.

[0185] This ensures that the laminate 10 having the surface condition of the present disclosure and the conductive resin layer 60 are in contact with each other, and the effects of the present disclosure can be obtained more appropriately.

[0186] As previously described in the explanation of Figure 8, the internal structure of the surface and near the surface of the laminate 10 can be similar in the portion of the main surface where the laminate 10 contacts the conductive resin layer 60 and the portion where the laminate 10 contacts the base electrode layer 50.

[0187] That is, the resin contact surface planar region CS1 and the substrate contact surface planar region CS2, and the portion of the laminate 10 continuous with the resin contact surface planar region CS1 and the portion of the laminate 10 continuous with the substrate contact surface planar region CS2 may have similar characteristics.

[0188] For example, with respect to the resin contact surface flat region CS1, the outer layer portion 12 may include, between the resin contact surface flat region CS1 and the inner layer portion 11, a fine-grained layer ML disposed on the resin contact surface flat region CS1 side, and a base layer BL disposed on the inner layer portion 11 side of the fine-grained layer ML, and the particle diameter of the ceramic particles BG constituting the fine-grained layer ML may be smaller than the particle diameter of the ceramic particles BG constituting the base layer BL. Furthermore, the surface of the resin contact surface flat region CS1, which is the surface of the fine-grained layer ML, may have Sa of 0.05 μm or more and Sdr of 0.1 or less.

[0189] Similarly, the flat region CS2 of the substrate contact surface includes a fine-grained layer ML disposed on the side of the flat region CS2 of the substrate contact surface and a base layer BL disposed closer to the inner layer portion 11 than the fine-grained layer ML, and the particle diameter of the ceramic particles BG constituting the fine-grained layer ML may be smaller than the particle diameter of the ceramic particles BG constituting the base layer BL. Furthermore, the surface of the fine-grained layer ML, i.e., the surface of the flat region CS2 of the substrate contact surface, may have Sa of 0.05 μm or more and Sdr of 0.1 or less.

[0190] 10 , the length of the resin contact surface flat region CS1 at the center of the width of the laminate 10 is defined as D1. The length of the substrate contact surface flat region CS2 at the center of the width of the laminate 10 is defined as D2. It is preferable that D1 be longer than D2.

[0191] This ensures that the laminate 10 having the surface condition of the present disclosure and the conductive resin layer 60 are in contact with each other, and the effects of the present disclosure can be obtained more appropriately.

[0192] 10 , the resin contact surface flat region CS1 and the substrate contact surface flat region CS2 of the first external electrode 40A, and the resin contact surface flat region CS1 and the substrate contact surface flat region CS2 of the second external electrode 40B may have a convex shape toward the center position in the longitudinal direction of the laminate 10 in a top view. More specifically, the resin contact surface flat region CS1 and the substrate contact surface flat region CS2 may be arch-shaped curved regions extending between both edges in the Y direction that convex toward the center of the longitudinal direction L of the laminate 10. Here, the top view refers to viewing the main surface TS from a direction perpendicular to the main surface TS.

[0193] As shown in Figure 10, the length of the convex portion in the resin contact surface flat region CS1 is defined as D11, and the length of the convex portion in the substrate contact surface flat region CS2 is defined as D12. Here, the convex portion refers to the distance from the end of the portion with a constant widthwise length in the resin contact surface flat region CS1 and the substrate contact surface flat region CS2 to the apex of the convex portion in the longitudinal direction. In Figure 10, the end of the portion with a constant widthwise length is indicated by line A, and the apex is indicated by point B.

[0194] As shown in FIG. 10, D11 is preferably longer than D12.

[0195] As a result, the conductive resin layer 60 peels off while gradually increasing the peeling area from the apex of the convex shape of the resin contact surface flat region CS1, so that the initial peeling progresses smoothly and the subsequent peeling progresses more appropriately, thereby more appropriately achieving the effects of the present disclosure. Note that the surface of the resin contact surface flat region CS1 having a convex shape is the surface of the atomized layer ML, and Sdr is 0.1 or less.

[0196] Note that the characteristics indicating the surface shape, such as Sdr and Sa, of the first contact surface TS1A and the second contact surface TS2A, and the first substrate contact surface TS1B and the second substrate contact surface TS2B can be measured at exposed portions of the laminate 10 other than the first contact surface TS1A and the second contact surface TS2A, and the first substrate contact surface TS1B and the second substrate contact surface TS2B, to obtain similar results. That is, the internal structure of the surface and the vicinity of the surface of the laminate 10 can be the same in the exposed portion of the laminate 10, i.e., the exposed portion ES. It is preferable that the exposed surface ES also has a micro-grained layer ML. It is also effective to eliminate the starting point of cracks during deflection on the exposed surface ES. When measuring the surface roughness parameters and the structure near the surface of the laminate 10 on the first main surface TS1 and the second main surface TS2, the measurements can be performed, for example, at the center of the longitudinal direction L of the laminate 10, near the end of the external electrode 40.

[0197] The multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0198] (1) A multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a laminate 10 including a plurality of dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and having a first main surface TS1 and a second main surface TS2 facing in a height direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the height direction T and the width direction W, and an external electrode 40 connected to the internal electrode layers 30 (internal conductor layers 30). The external electrode 40 includes a base electrode layer 50 (fired electrode layer 50), a conductive resin layer 60 disposed on the base electrode layer 50 (fired electrode layer 50), and a plating layer 70 disposed on the conductive resin layer. At the interface between the first principal surface TS1 and the conductive resin layer 60, the first principal surface TS1 includes a first contact surface TS1A having an Sdr of 0.1 or less. At the interface between the second principal surface TS2 and the conductive resin layer 60, the second principal surface TS2 includes a second contact surface TS2A having an Sdr of 0.1 or less.

[0199] This makes it possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0200] (2) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the Sdr of the first contact surface TS1A is 0.025 or more, and the Sdr of the second contact surface TS2A is 0.025 or more.

[0201] This makes it possible to provide a multilayer ceramic electronic component that has good adhesion between the laminate and the external electrodes and that can further suppress the occurrence of cracks in the laminate.

[0202] (3) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, Sa of the first contact surface TS1A is 0.05 μm or more, and Sa of the second contact surface TS2A is 0.05 μm or more.

[0203] This makes it possible to provide a multilayer ceramic electronic component that has good adhesion between the laminate and the external electrodes and that can further suppress the occurrence of cracks in the laminate.

[0204] (4) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, Sa of the first contact surface TS1A is 0.1 or more, and Sa of the second contact surface TS2A is 0.1 or more.

[0205] This makes it possible to provide a multilayer ceramic electronic component that has good adhesion between the laminate and the external electrodes and that can further suppress the occurrence of cracks in the laminate.

[0206] (5) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, Sa of the first contact surface TS1A is 0.5 μm or less, and Sa of the second contact surface TS2A is 0.5 μm or less.

[0207] This makes it possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0208] (6) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the laminate 10 includes an inner layer portion 11 formed by alternately stacking dielectric layers 20 (ceramic layers 20) and internal electrode layers 30 (internal conductor layers 30), and main surface-side outer layer portions 12 (outer layer portions 12) arranged to sandwich the inner layer portion 11 from the first main surface TS1 side and the second main surface TS2 side. When the first contact surface TS1A and the second contact surface TS2A are collectively defined as the resin contact surface, the main surface-side outer layer portion 12 (outer layer portion 12) includes, between the resin contact surface and the inner layer portion 11, a fine-grained layer ML arranged on the resin contact surface side, and a base layer BL arranged closer to the inner layer portion 11 than the fine-grained layer ML. The average particle diameter of the ceramic particles constituting the fine-grained layer ML is smaller than the average particle diameter of the ceramic particles constituting the base layer BL.

[0209] This makes the grain boundaries finer, making it harder for reaction layers formed during plating or external electrode baking to corrode the grain boundaries, making it harder for cracks to start. Furthermore, the grain boundary pathways become more complex, making it harder for cracks to propagate. This makes it possible to provide a highly reliable multilayer ceramic electronic component that can prevent cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0210] (7) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the thickness of the micro-grained layer ML is 10 nm or more and 300 nm or less.

[0211] This prevents chipping of the fine-grained layer during processing, while further preventing cracks from occurring in the laminate of the multilayer ceramic electronic component. If the thickness t of the fine-grained layer ML is less than 10 nm, the stress dispersion effect is small, and the crack suppression effect is insufficient. If the thickness t of the fine-grained layer ML exceeds 300 nm, chipping of the fine-grained layer occurs, making it impossible to reproduce a stable and consistent processed state, and ensuring processing stability.

[0212] (8) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, when the first contact surface TS1A and the second contact surface TS2A are collectively defined as the resin contact surface, and the surface of the first main surface TS1 of the laminate 10 with which the fired electrode layer 50 is in contact and the surface of the second main surface TS2 of the laminate 10 with which the fired electrode layer 50 is in contact are defined as the base contact surface, the area of ​​the flat region in the resin contact surface is larger than the area of ​​the flat region in the base contact surface.

[0213] This ensures that the laminate 10 having the surface condition of the present disclosure and the conductive resin layer 60 are in contact with each other, and the effects of the present disclosure can be obtained more appropriately.

[0214] (9) In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment, the laminate 10 includes an inner layer portion 11 formed by alternately stacking dielectric layers 20 (ceramic layers 20) and internal electrode layers 30 (internal conductor layers 30), and main surface-side outer layer portions 12 (outer layer portions 12) arranged so as to sandwich the inner layer portion 11 from the first main surface TS1 side and the second main surface TS2 side, and the first contact surface TS1A and the second contact surface TS2A are collectively defined as a resin contact surface. The main surface-side outer layer portion 12 (outer layer portion 12) is provided with a micronized layer ML arranged on the resin contact surface side between the resin contact surface and the inner layer portion 11, and a base layer BL arranged on the inner layer portion 11 side of the micronized layer ML, the average particle diameter of the ceramic particles constituting the micronized layer ML is smaller than the average particle diameter of the ceramic particles constituting the base layer BL, and the resin contact surface formed by the surface of the micronized layer ML has Sa of 0.05 μm or more and Sdr of 0.1 or less.

[0215] As a result, when flexural stress occurs in the multilayer ceramic capacitor, the conductive resin layer peels off, alleviating stress concentration in the laminate 10, and further reducing the starting points for cracks during flexure, thereby more effectively suppressing flexural cracks in the laminate 10.

[0216] (10) The method for manufacturing the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a processing step, before forming the base electrode layer 50 (fired electrode layer 50) on the laminate 10 or after forming the base electrode layer 50 (fired electrode layer 50) on the laminate 10, of processing the laminate 10 so that the first main surface TS1 including the interface between the first main surface TS1 of the laminate 10 and the conductive resin layer 60 has an Sdr of 0.1 or less, and the second main surface TS2 including the interface between the second main surface TS2 of the laminate 10 and the conductive resin layer 60 has an Sdr of 0.1 or less.

[0217] This makes it possible to manufacture a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0218] Furthermore, the multilayer ceramic capacitor 1 of this embodiment has the following advantages.

[0219] (1) A multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment is a laminate 10 including a plurality of laminated dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and having a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W, and an inner layer portion 11 formed by alternately stacking the dielectric layers 20 and the internal electrode layers 30. the laminate 10 including an effective layer portion 11 and a main surface side outer layer portion 12 (outer layer portion 12) arranged so as to sandwich the inner layer portion 11 from the first main surface TS1 side and the second main surface TS2 side, a first external electrode 40A arranged on the first end face LS1, and a second external electrode 40B arranged on the second end face LS2, the main surface side outer layer portion 12 including a fine-grained layer ML arranged on the surface layer, and a base layer BL arranged on the inner layer portion 11 side of the fine-grained layer ML, and the particle diameter d of the ceramic particles MG constituting the fine-grained layer ML is smaller than the particle diameter D of the ceramic particles BG constituting the base layer BL.

[0220] This makes the grain boundaries finer, making it harder for reaction layers formed during plating or external electrode baking to corrode the grain boundaries, making it harder for cracks to start. Furthermore, the grain boundary pathways become more complex, making it harder for cracks to propagate. This makes it possible to provide a highly reliable multilayer ceramic electronic component that can prevent cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0221] (2) In the multilayer ceramic capacitor 1 of this embodiment, the ceramic particles MG that form the micro-grained layer ML are pulverized particles.

[0222] This makes the grain boundary paths more complex, making it possible to further suppress the occurrence of cracks in the laminate of the multilayer ceramic electronic component.

[0223] (3) In the multilayer ceramic capacitor 1 of this embodiment, the pulverized particles are crystal particles.

[0224] This can prevent cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0225] (4) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the micro-grained layer ML is 300 nm or less.

[0226] This makes it possible to suppress chipping of the fine-grained layer during processing, and to further suppress cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0227] (5) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the micro-grained layer ML is 10 nm or more and 300 nm or less.

[0228] This prevents chipping of the fine-grained layer during processing, while further preventing cracks from occurring in the laminate of the multilayer ceramic electronic component. If the thickness t of the fine-grained layer ML is less than 10 nm, the stress dispersion effect is small, and the crack suppression effect is insufficient. If the thickness t of the fine-grained layer ML exceeds 300 nm, chipping of the fine-grained layer occurs, making it impossible to reproduce a stable and consistent processed state, and ensuring processing stability.

[0229] (6) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the fine-grained layer ML is 10% or less of the thickness T of the main-surface-side outer layer portion 12 .

[0230] This makes it possible to suppress chipping of the fine-grained layer during processing, and to further suppress cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0231] (7) In the multilayer ceramic capacitor 1 of this embodiment, the thickness t of the fine-grained layer ML is 1% or less of the thickness T of the main-surface-side outer layer portion 12 .

[0232] This makes it possible to suppress chipping of the fine-grained layer during processing, and to further suppress cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0233] (8) In the multilayer ceramic capacitor 1 of this embodiment, the particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more, and the particle diameter d of the ceramic particles MG constituting the micro-grained layer ML is 50 nm or less.

[0234] This can further prevent cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0235] (9) In the multilayer ceramic capacitor 1 of this embodiment, the particle diameter D of the ceramic particles BG constituting the base layer BL is 200 nm or more and 500 nm or less, and the particle diameter d of the ceramic particles MG constituting the micro-grained layer ML is 10 nm or more and 50 nm or less.

[0236] This can further suppress the occurrence of cracks in the laminate of the multilayer ceramic electronic component. If the particle diameter d of the ceramic particles MG constituting the fine-grained layer ML is less than 10 nm, it is difficult to form the fine-grained layer necessary to obtain the crack suppression effect, and the crack suppression effect is difficult to obtain. If the particle diameter d of the ceramic particles MG constituting the fine-grained layer ML is more than 50 nm, the complexity of the grain boundary path is insufficient, and the crack suppression effect is difficult to obtain.

[0237] (10) In the multilayer ceramic capacitor 1 of this embodiment, a dislocation crystal layer having dislocations in the crystals of the grains that make up the grain layer is disposed between the fine-grained layer ML and the base layer BL.

[0238] This makes it possible to further suppress the occurrence of cracks in the laminate of the multilayer ceramic electronic component.

[0239] (11) In the multilayer ceramic capacitor 1 of this embodiment, the degree of unevenness of the surface S2 of the micro-grained layer ML that faces away from the inner layer portion 11 is smaller than the degree of unevenness of the surface S1 of the micro-grained layer ML that faces closer to the inner layer portion 11.

[0240] This makes it difficult for cracks to start and the grain boundary paths become more complex, making it difficult for cracks to progress, and thus making it possible to further suppress cracks from occurring in the laminate of the multilayer ceramic electronic component.

[0241] Furthermore, the multilayer ceramic electronic component of the present disclosure includes the following aspects, which provide the effects of the present disclosure.

[0242] <1> A multilayer ceramic electronic component comprising: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, wherein the external electrodes comprise a baked electrode layer, a conductive resin layer disposed on the baked electrode layer, and a plating layer disposed on the conductive resin layer, the conductive resin layer being in contact with the first main surface and the second main surface, wherein the first main surface has an Sdr of 0.1 or less, and the second main surface has an Sdr of 0.1 or less.

[0243] <2> The multilayer ceramic electronic component according to <1>, wherein the first main surface has an Sdr of 0.025 or more, and the second main surface has an Sdr of 0.025 or more.

[0244] <3> The multilayer ceramic electronic component according to <1> or <2>, wherein Sa of the first main surface is 0.05 μm or more, and Sa of the second main surface is 0.05 μm or more.

[0245] <4> The multilayer ceramic electronic component according to <1> or <2>, wherein Sa of the first main surface is 0.1 μm or more, and Sa of the second main surface is 0.1 μm or more.

[0246] <5> The multilayer ceramic electronic component according to <3> or <4>, wherein Sa of the first main surface is 0.5 μm or less, and Sa of the second main surface is 0.5 μm or less.

[0247] <6> The multilayer ceramic electronic component according to any one of <1> to <5>, wherein the laminate includes an inner layer portion formed by alternately stacking the ceramic layers and the internal conductor layers, and outer layer portions arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, wherein when the first main surface and the second main surface are collectively defined as a main surface, the outer layer portion includes: a fine-grained layer arranged on the main surface side between the main surface and the inner layer portion; and a base layer arranged on the inner layer portion side of the fine-grained layer, and wherein an average particle diameter of the ceramic particles constituting the fine-grained layer is smaller than that of the ceramic particles constituting the base layer.

[0248] <7> The multilayer ceramic electronic component according to <6>, wherein the micro-grained layer has a thickness of 10 nm or more and 300 nm or less.

[0249] <8> The multilayer ceramic electronic component according to any one of <1> to <7>, wherein an interface between the first main surface of the laminate and the conductive resin layer is defined as a first contact surface, an interface between the second main surface of the laminate and the conductive resin layer is defined as a second contact surface, the first contact surface and the second contact surface are collectively defined as a resin contact surface, and a surface of the first main surface of the laminate with which the fired electrode layer is in contact and a surface of the second main surface of the laminate with which the fired electrode layer is in contact are defined as base contact surfaces, wherein an area of ​​a flat region in the resin contact surface is larger than an area of ​​a flat region in the base contact surface.

[0250] <9> The multilayer ceramic electronic component according to any one of <1> to <8>, wherein the laminate includes an inner layer portion formed by alternately stacking the ceramic layers and the internal conductor layers, and outer layer portions arranged to sandwich the inner layer portion from the first main surface side and the second main surface side, wherein when the first main surface and the second main surface are collectively defined as a main surface, the outer layer portion comprises: a fine-grained layer arranged on the main surface side between the main surface and the inner layer portion; and a base layer arranged on the inner layer portion side of the fine-grained layer, wherein an average particle size of ceramic particles constituting the fine-grained layer is smaller than that of ceramic particles constituting the base layer, and the main surface formed by the surface of the fine-grained layer has Sa of 0.05 μm or more and Sdr of 0.1 or less.

[0251] <10> A method for manufacturing a multilayer ceramic electronic component comprising: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, wherein the external electrodes comprise a baked electrode layer, a conductive resin layer disposed on the baked electrode layer, and a plating layer disposed on the conductive resin layer, and the conductive resin layer is in contact with the first and second main surfaces, the method comprising: before or after forming the baked electrode layer on the laminate, processing the laminate so that Sdr of the first main surface is 0.1 or less and Sdr of the second main surface is 0.1 or less.

[0252] The dielectric material forming the dielectric layer 20 is not limited to the dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3, as exemplified above. These materials can be variously modified. For example, the dielectric material forming the dielectric layer 20 may be a material that does not contain Zn.

[0253] Furthermore, the configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 5. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a double structure, a triple structure, or a quadruple structure as shown in Figures 11, 12, and 13.

[0254] The multilayer ceramic capacitor 1 shown in FIG. 11 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 12 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 13 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this manner, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0255] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes.

[0256] In the above-described embodiment, a multilayer ceramic capacitor in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers has been described as an example of the multilayer ceramic electronic component. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramics as ceramic layers, thermistors using semiconductor ceramics as ceramic layers, and inductors using magnetic ceramics as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite.

[0257] The present invention is not limited to the configurations of the above-described embodiments, and can be applied by making appropriate modifications within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0258] REFERENCE SIGNS LIST 1 Multilayer ceramic capacitor (multilayer ceramic electronic component) 10 Laminate 11 Inner layer portion (effective layer portion) 12 Outer layer portion 20 Dielectric layer (ceramic layer) 30 Internal electrode layer (internal conductor layer) 40 External electrode 50 Base electrode layer 60 Conductive resin layer 70 Plating layer BL Base layer BG Ceramic particles ML Micronized layer MG Ceramic particles T Height direction TS1 First main surface TS1A First contact surface TS2 Second main surface TS2A Second contact surface W Width direction WS1 First side surface WS2 Second side surface L Length direction LS1 First end surface LS2 Second end surface

Claims

1. A multilayer ceramic electronic component comprising: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, wherein the external electrodes comprise a baked electrode layer, a conductive resin layer disposed on the baked electrode layer, and a plating layer disposed on the conductive resin layer; at the interface between the first main surface of the laminate and the conductive resin layer, the first main surface includes a first contact surface having an Sdr of 0.1 or less; and at the interface between the second main surface of the laminate and the conductive resin layer, the second main surface includes a second contact surface having an Sdr of 0.1 or less.

2. The multilayer ceramic electronic component according to claim 1, wherein the Sdr of the first contact surface is 0.025 or more, and the Sdr of the second contact surface is 0.025 or more.

3. A multilayer ceramic electronic component according to claim 1 or 2, wherein the first contact surface has a thickness Sa of 0.05 μm or more, and the second contact surface has a thickness Sa of 0.05 μm or more.

4. A multilayer ceramic electronic component according to claim 1 or 2, wherein the first contact surface has a thickness Sa of 0.1 μm or more, and the second contact surface has a thickness Sa of 0.1 μm or more.

5. A multilayer ceramic electronic component according to claim 3 or 4, wherein the first contact surface has a thickness Sa of 0.5 μm or less, and the second contact surface has a thickness Sa of 0.5 μm or less.

6. The multilayer ceramic electronic component according to any one of claims 1 to 5, wherein the laminate includes an inner layer portion formed by alternately stacking the ceramic layers and the internal conductor layers, and outer layer portions arranged to sandwich the inner layer portion from the first principal surface side and the second principal surface side, and when the first contact surface and the second contact surface are collectively defined as a resin contact surface, the outer layer portion comprises: an atomized layer arranged on the resin contact surface side between the resin contact surface and the inner layer portion; and a base layer arranged on the inner layer portion side of the atomized layer, and the average particle diameter of the ceramic particles constituting the atomized layer is smaller than the average particle diameter of the ceramic particles constituting the base layer.

7. The multilayer ceramic electronic component according to claim 6, wherein the thickness of the fine-grained layer is 10 nm or more and 300 nm or less.

8. A multilayer ceramic electronic component according to any one of claims 1 to 7, wherein when the first contact surface and the second contact surface are collectively defined as a resin contact surface, and the surface of the first main surface of the laminate with which the fired electrode layer is in contact and the surface of the second main surface of the laminate with which the fired electrode layer is in contact are defined as base contact surfaces, the area of ​​the flat region of the resin contact surface is larger than the area of ​​the flat region of the base contact surface.

9. The multilayer ceramic electronic component according to any one of claims 1 to 8, wherein the laminate includes an inner layer portion formed by alternately stacking the ceramic layers and the internal conductor layers, and outer layer portions arranged to sandwich the inner layer portion from the first principal surface side and the second principal surface side, and when the first contact surface and the second contact surface are collectively defined as a resin contact surface, the outer layer portion comprises: a fine-grained layer arranged on the resin contact surface side between the resin contact surface and the inner layer portion, and a base layer arranged on the inner layer portion side of the fine-grained layer, the average particle size of the ceramic particles constituting the fine-grained layer is smaller than the average particle size of the ceramic particles constituting the base layer, and the resin contact surface formed by the surface of the fine-grained layer has Sa of 0.05 μm or more and Sdr of 0.1 or less.

10. A method for manufacturing a multilayer ceramic electronic component comprising: a laminate including a plurality of ceramic layers and a plurality of internal conductor layers, and having first and second main surfaces opposing each other in a height direction, first and second side surfaces opposing each other in a width direction perpendicular to the height direction, and first and second end surfaces opposing each other in a length direction perpendicular to the height direction and the width direction; and external electrodes connected to the internal conductor layers, wherein the external electrodes comprise a baked electrode layer, a conductive resin layer disposed on the baked electrode layer, and a plating layer disposed on the conductive resin layer, the method comprising: a processing step, before or after forming the baked electrode layer on the laminate, of processing the first main surface of the laminate, including the interface between the first main surface and the conductive resin layer, so that Sdr is 0.1 or less, and the second main surface of the laminate, including the interface between the second main surface of the laminate and the conductive resin layer, so that Sdr is 0.1 or less.

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