Power semiconductor module

Abstract

This power semiconductor module may comprise: a first substrate having a first region and a second region at one side of the first region; a power semiconductor element disposed over the first region of the first substrate; a second substrate disposed over the power semiconductor element; and a power terminal disposed over the second region of the first substrate and horizontally overlapping the second substrate. The second substrate may be provided with a via terminal electrically connected to the power semiconductor element.

Description

power semiconductor modules

[0001] The present disclosure relates to a power semiconductor module.

[0002] Unlike system semiconductors or memory that process and store information or signals, power semiconductor devices are core components that convert, store, distribute, and control the power entering electronic devices, and are widely used in most electronic products.

[0003] In recent years, in line with the global trend toward strengthening environmental protection, eco-friendly vehicles such as electric and hydrogen-powered vehicles are gaining widespread attention, replacing conventional fossil fuel-powered vehicles. Eco-friendly vehicles utilize numerous power semiconductor components. Eco-friendly vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] Although Si power semiconductor devices have been widely used in the past, there is a strong demand for the development of new power semiconductor devices due to their low power, low dielectric breakdown characteristics, and low thermal conductivity.

[0005] Accordingly, active research is being conducted on power semiconductor devices based on compound semiconductors such as SiC, GaN, and Ga2O3, which have energy bandgaps approximately three times greater than conventional Si power semiconductor devices. These compound semiconductor-based power semiconductor devices possess high power, high dielectric breakdown characteristics, and high thermal conductivity.

[0006] In particular, eco-friendly vehicles require high-current inverters, such as inverters capable of 700 A or more. The inverters comprise multiple power semiconductor modules to convert power. Each of the multiple power semiconductor modules comprises multiple power semiconductor devices.

[0007] As illustrated in Fig. 1, the power semiconductor device includes power semiconductor devices (30, 40) based on compound semiconductors. A plurality of power semiconductor devices (30, 40) are disposed between a first substrate (10) and a second substrate (20). A gate electrode (30a) and a source electrode (30b) of each of the first power semiconductor devices (30) are electrically connected to the second substrate (20), and a gate electrode (40a) and a source electrode (40b) of each of the second power semiconductor devices (40) are electrically connected to the first substrate (10).

[0008] Meanwhile, the power semiconductor module includes a terminal (or lead frame) (50) arranged between a first substrate (10) and a second substrate (20).

[0009] As mentioned above, in power semiconductor modules employed in inverters for eco-friendly automobiles, the higher the current, the larger the cross-sectional area of ​​the terminal (50) must be. Typically, because the area of ​​the inverter is limited, the larger the required current, the thicker the terminal (50) becomes.

[0010] In this case, since the thickness of the terminal (50) is greater than the thickness of the power semiconductor element (30, 40), the upper or lower portion of the power semiconductor element (30, 40) is spaced apart from the first substrate (10) or the second substrate (20). To compensate for this spacing, a spacer (70, 80) is placed on the upper or lower portion of the power semiconductor element (30, 40), so there is a problem that the thickness of the power semiconductor module increases. In addition, since a spacer (70, 80) is provided for each of the power semiconductor elements (30, 40), as the number of power semiconductor elements (30, 40) increases, the number of spacers (70, 80) also increases, so there is a problem that the material cost increases.

[0011] Meanwhile, as illustrated in FIG. 1, a terminal (50) that supplies power or a signal to a power semiconductor element (30, 40) is placed on the side of the power semiconductor element (30, 40), so that the physical distance or current path between the terminal (50) and the power semiconductor element (30, 40) increases, causing a problem in that not only power or a signal is lost, but also switching operation becomes unstable.

[0012] In addition, since all terminals (50) must be provided within a limited space on the side of the power semiconductor element (30, 40), there is a significant restriction on increasing the cross-sectional area of ​​each terminal (50), and there is a problem of electrical short-circuiting occurring between each terminal (50).

[0013] The present disclosure is intended to solve the above-mentioned and other problems.

[0014] Accordingly, the present disclosure provides a power semiconductor module capable of reducing thickness.

[0015] Additionally, the present disclosure provides a power semiconductor module capable of reducing material costs.

[0016] Additionally, the present disclosure provides a higher power semiconductor module.

[0017] In addition, the present disclosure provides a power semiconductor module capable of stable switching operation.

[0018] Additionally, the present disclosure provides a power semiconductor module capable of preventing electrical shorts between terminals.

[0019] Additionally, the present disclosure provides a power semiconductor module that does not require a lead frame.

[0020] The present disclosure is not limited to what has been described, but includes things that can be understood through the description of the disclosure.

[0021] According to one aspect of the present disclosure to achieve the above or other purposes, a power semiconductor module includes a first substrate having a first region and a second region on one side of the first region; a power semiconductor element disposed on the first region of the first substrate; a second substrate disposed on the power semiconductor element; and a power terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; wherein the second substrate has a via terminal electrically connected to the power semiconductor element.

[0022] The second substrate may include a first metal layer disposed on a lower side of the first insulating layer; and a second metal layer disposed on an upper side of the first insulating layer. The via terminal may be formed by penetrating the first metal layer, the insulating layer, and the second metal layer.

[0023] The upper surface of the above via terminal and the upper surface of the above power terminal can be parallel.

[0024] The above power semiconductor module may include the second substrate and an insulating member arranged on the outer periphery of the via terminal and the power terminal.

[0025] The above via terminal includes a first via terminal and a second via terminal, and the first via terminal and the second via terminal can be electrically insulated by the insulating layer and the insulating portion.

[0026] The power semiconductor device includes a gate electrode and a source electrode, and the first via terminal and the second via terminal can be electrically connected to the gate electrode and the source electrode, respectively.

[0027] The power semiconductor device further includes a drain electrode, and the power terminal can be electrically connected to the first drain electrode.

[0028] A step portion is formed on the upper surface of the second region, and the power terminal can be coupled to the step portion.

[0029] The above power semiconductor module may further include a support molding portion that extends from one side of the first substrate and supports a side of the power terminal.

[0030] According to another aspect of the present disclosure, a power semiconductor module includes a first substrate having a first region and a second region on one side of the first region; a power semiconductor element disposed on the first region of the first substrate; a second substrate having a third region disposed on the power semiconductor element and a fourth region on one side of the third region; and a conductive post disposed between the second region and the fourth region; wherein the second substrate may have a via terminal electrically connected to the power semiconductor element and a power terminal electrically connected to the first substrate.

[0031] The second substrate may include a first insulating layer; a first metal layer disposed on a lower side of the first insulating layer; and a second metal layer disposed on an upper side of the first insulating layer. The via terminal and the power terminal may be formed by penetrating the first metal layer, the insulating layer, and the second metal layer.

[0032] The upper surface of the above via terminal and the upper surface of the above power terminal can be parallel.

[0033] The second substrate may include an insulating portion arranged on the outer periphery of the via terminal and the power terminal.

[0034] The above via terminal includes a first via terminal and a second via terminal, and the first via terminal and the second via terminal can be electrically insulated by the insulating layer and the insulating portion.

[0035] The first metal layer and the second metal layer include an insulating pattern between the via terminal and the power terminal, and the via terminal and the power terminal can be electrically insulated by the insulating layer, the insulating portion, and the insulating pattern.

[0036] The effects of power semiconductor modules and power conversion devices according to these aspects are described as follows.

[0037] At least one of these aspects has the advantage of reducing material costs by eliminating the need for spacers.

[0038] According to at least one of these aspects, there is an advantage that the thickness can be reduced by eliminating the need for a spacer.

[0039] According to at least one of these aspects, there is an advantage in that a higher power semiconductor module can be realized by increasing the thickness of the terminals on both sides of the power semiconductor device without increasing the overall thickness.

[0040] According to at least one of these aspects, there is an advantage that the process can be simplified and the process time can be shortened because a lead frame is not used.

[0041] According to at least one of these aspects, there is an advantage in that stable switching operation can be achieved by minimizing the physical distance or current path between the terminal and the power semiconductor element.

[0042] According to at least one of these aspects, there is an advantage in that some terminals are arranged on the upper side of the power semiconductor device, so that the cross-sectional area of ​​each terminal arranged on the side of the power semiconductor device can be increased or electrical shorts between each terminal can be prevented.

[0043] The accompanying drawings are included to provide a further understanding of the present disclosure and may be incorporated into and constitute a part of the present disclosure. Furthermore, the accompanying drawings may serve to illustrate features of the present disclosure and, together with the description of the disclosure, to explain the principles of the present disclosure.

[0044] In the drawing:

[0045] Figure 1 is a cross-sectional view illustrating a conventional power semiconductor module.

[0046] FIG. 2 is a circuit diagram illustrating an inverter according to one aspect of the present disclosure.

[0047] FIG. 3 is a plan view illustrating a power semiconductor module according to the first aspect of the present disclosure.

[0048] FIG. 4 is a cross-sectional view illustrating a power semiconductor module according to the second aspect of the present disclosure.

[0049] FIG. 5 is a cross-sectional view illustrating a power semiconductor module according to a third aspect of the present disclosure.

[0050] Fig. 6 is a perspective view illustrating the first substrate of Fig. 5.

[0051] FIG. 7 is a cross-sectional view illustrating a power semiconductor module according to the fourth aspect of the present disclosure.

[0052] FIG. 8 is a plan view illustrating a power semiconductor module according to the fifth aspect of the present disclosure.

[0053] The sizes, shapes, and dimensions of components depicted in the drawings may differ from the actual components. Furthermore, even if the same components are depicted with different sizes, shapes, and dimensions across drawings, this is merely an example within the drawings, and the same components may have the same sizes, shapes, and dimensions across drawings.

[0054] Hereinafter, aspects disclosed in the present specification will be described in detail with reference to the attached drawings, and regardless of the drawing numbers, identical or similar components will be given the same reference numbers, and redundant descriptions thereof will be omitted. The suffixes 'module' and 'part' used for components in the following description are given or used interchangeably in consideration of the ease of writing the specification, and do not have distinct meanings or roles in themselves. In addition, the attached drawings are intended to facilitate easy understanding of aspects disclosed in the present specification, and the technical ideas disclosed in the present specification are not limited by the attached drawings. In addition, when an element such as a layer, region, or substrate is referred to as existing 'on' another element, this includes that it may be directly on the other element, or that other intermediate elements may exist therebetween.

[0055] FIG. 2 is a circuit diagram illustrating an inverter according to one aspect of the present disclosure.

[0056] Referring to FIG. 2, an inverter (1000) according to one aspect of the present disclosure may be applied to applications such as three-phase motors or compressors. The inverter (1000) may output three-phase power. The inverter (1000) may be a power conversion device or may be included in a power conversion device. The inverter (1000) may include a switching circuit.

[0057] An inverter (1000) according to one aspect of the present disclosure can convert DC power into AC power and supply the converted AC power to a load (1200) to drive the load. In the inverter (1000) according to one aspect of the present disclosure, a converter may be connected to the input side to convert AC power into DC power. In this case, the DC power converted by the converter can be converted into AC power by the inverter (1000) and then used to drive the load (1200). The load (1200) may be a motor or an electric motor, but is not limited thereto.

[0058] An inverter (1000) according to one aspect of the present disclosure may include, but is not limited to, a three-phase inverter. In this case, a phase difference of 120 degrees may be present between the first phase, the second phase, and the third phase. An inverter (1000) according to one aspect of the present disclosure may include a plurality of legs (100A, 100B, 100C). For example, the first leg (100A), the second leg (100B), and the third leg (100C) may be connected in parallel to a load (1200), i.e., a motor, through a first node (N1), a second node (N2), and a third node (N3), respectively. The first leg (100A) may include a first arm (100a) and a second arm (100b) that are connected in series to each other, the second leg (100B) may include a third arm (100c) and a fourth arm (100d) that are connected in series to each other, and the third leg (100C) may include a fifth arm (100e) and a sixth arm (100f) that are connected in series to each other. Here, the first arm (100a), the third arm (100c), and the fifth arm (100e) may be referred to as upper arms, and the second arm (100b), the fourth arm (100d), and the sixth arm (100f) may be referred to as lower arms. Each of the first arm (100a) to the sixth arm (100f) may be referred to as a switching module, a submodule, or the like.

[0059] The first arm (100a) to the sixth arm (100f) may each include switching units (Q1 to Q6) and diodes (100a-2 to 100f-2). The switching units (Q1 to Q6) and the diodes (100a-2 to 100f-2) may be formed simultaneously using the same semiconductor process. The switching units (Q1 to Q6) may include power semiconductor devices.

[0060] In order for DC power to be converted into AC power by the inverter (1000) according to one aspect of the present disclosure, the switching units (Q1 to Q6) of each of the first arm (100a) to the sixth arm (100f) can be controlled to turn on / off.

[0061] For example, when the first switching unit (Q1) of the first arm (100a) of the first leg (100A) is in the ON state, the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) and / or the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) may be in the ON state. Accordingly, DC power may be supplied to the first phase inductor of the motor.

[0062] For example, when the third switching unit (Q3) of the third arm (100c) of the second leg (100B) is turned on, the sixth switching unit (Q6) of the sixth arm (100f) of the third leg (100C) and / or the second switching unit (Q2) of the second arm (100b) of the first leg (100A) may be turned on. Accordingly, DC power may be supplied to the second phase inductor of the motor. The second phase may be 120 degrees behind the first phase.

[0063] For example, when the fifth switching unit (Q5) of the fifth arm (100e) of the third leg (100C) is turned on, the second switching unit (Q2) of the second arm (100b) of the first leg (100A) and / or the fourth switching unit (Q4) of the fourth arm (100d) of the second leg (100B) may be turned on. Accordingly, DC power may be supplied to the third phase inductor of the motor. The third phase may be 120 degrees behind the second phase.

[0064] Accordingly, AC power can be generated by the DC power supplied to each of the first phase inductor, the second phase inductor, and the third inductor.

[0065] Meanwhile, although not shown, in order to increase the internal pressure characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple numbers, each connected in series with each other.

[0066] Although not shown, in order to increase the current characteristics, the switching units of each of the first arm (100a) to the sixth arm (100f), i.e., the power semiconductor elements (Q1 to Q6), may be provided in multiple units connected in parallel with each other.

[0067] Meanwhile, the switching units (Q1 to Q6) and diodes (100a-2 to 100f-2) constituting the first arm (100a) to the sixth arm (100f) can be packaged to form a power semiconductor module.

[0068] As an example, the first leg (100A), the second leg (100B), and the third leg (100C) may be configured as a first power semiconductor module, a second power semiconductor module, and a third power semiconductor module, respectively. For example, the first arm (100a) and the second arm (100b) of the first leg (100A) may be packaged to form a first power semiconductor module. For example, the third arm (100c) and the fourth arm (100d) of the second leg (100B) may be packaged to form a second power semiconductor module. For example, the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) may be packaged to form a third power semiconductor module.

[0069] As another example, the first leg (100A), the second leg (100B), and the third leg (100C) may be configured as a single power semiconductor module. That is, the first arm (100a) and the second arm (100b) of the first leg (100A), the third arm (100c) and the fourth arm (100d) of the second leg (100B), and the fifth arm (100e) and the sixth arm (100f) of the third leg (100C) may be single-packaged to form a single power semiconductor module.

[0070] Meanwhile, VDC represents the input voltage, which can be, for example, DC voltage. CDC represents a capacitor that can charge the input voltage (VDC).

[0071] Fig. 3 is a plan view illustrating a power semiconductor module according to the first aspect of the present disclosure. Fig. 4 is a cross-sectional view illustrating a power semiconductor module according to the second aspect of the present disclosure. The cross-sectional view illustrated in Fig. 4 may be a view taken along line AA' of the power semiconductor module of Fig. 3.

[0072] Referring to FIGS. 3 and 4, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a support molding part (270), etc.

[0073] The first substrate (210) and the second substrate (220) may each include an insulating layer (211, 221), a first metal layer (213, 223), a second metal layer (215, 225), etc. The insulating layers (211, 221) may be made of a material having excellent insulating properties, heat transfer properties, and / or heat dissipation properties. For example, the insulating layers (211, 221) may be made of an inorganic material, a ceramic material, an alumina material, a plastic material, a glass material, etc.

[0074] The first metal layer (213, 223) may include a plurality of circuit patterns. The first metal layer (223) of the second substrate (220) may not have a circuit pattern formed thereon.

[0075] A plurality of circuit patterns can be electrically connected to the first power semiconductor element (230) and the second power semiconductor element (240). To this end, the first metal layer (213, 223) can be formed of a metal material having excellent electrical conductivity. For example, the first metal layer (213, 223) can have a single-layer structure or a multi-layer structure made of copper (Cu), gold (Au), aluminum (Al), platinum (Pt), or the like.

[0076] The second metal layer (215, 225) can quickly discharge heat generated from the first power semiconductor element (230) and the second power semiconductor element (240) to the outside. Therefore, the second metal layer (215, 225) can be formed of a material having excellent heat dissipation properties. For example, the second metal layer (215, 225) can be aluminum (Al) or an aluminum alloy, but is not limited thereto. The second metal layer (215, 225) can be called a heat dissipation layer or a heat dissipation plate.

[0077] The first power semiconductor element (230) and the second power semiconductor element (240) may be disposed between the first substrate (210) and the second substrate (220). The first power semiconductor element (230) and the second power semiconductor element (240) may be bonded to the first substrate (210) and the second substrate (220), respectively, using a flip-chip bonding method, but this is not limited thereto. For example, the first power semiconductor element (230) and the second power semiconductor element (240) may be electrically connected to the first substrate (210) and the second substrate (220) using a sintering bonding method.

[0078] In the present disclosure, the first power semiconductor element (230) and the second power semiconductor element (240) may each include at least two power semiconductor elements. For example, the first power semiconductor element (230) may include two or more power semiconductor elements connected in parallel to each other along the second direction (Y). For example, the second power semiconductor element (240) may include two or more power semiconductor elements connected in parallel to each other along the second direction (Y).

[0079] The first power semiconductor element (230) may include a first semiconductor layer (231), a first drain electrode (234), a first gate electrode (232), a first source electrode (233), etc. The second power semiconductor element (240) may include a second semiconductor layer (241), a second drain electrode (244), a second gate electrode (242), a second source electrode (243), etc.

[0080] The first semiconductor layer (231) and the second semiconductor layer (241) can be formed using a semiconductor process on a substrate based on a semiconductor compound such as SiC, GaN, or Ga2O3. At this time, the substrate is a growth substrate and can include a sapphire substrate, a compound semiconductor substrate such as GaN, a ceramic series substrate, etc.

[0081] In the first power semiconductor element (230), the first drain electrode (234) may be disposed on the lower side of the first semiconductor layer (231), and the first gate electrode (232) and the first source electrode (233) may be disposed on the upper side of the first semiconductor layer (231). That is, the first gate electrode (232) and the first source electrode (233) may be disposed on the upper surface of the first semiconductor layer (231) facing the second substrate (220), and the first drain electrode (234) may be disposed on the lower surface of the first semiconductor layer (231) facing the first substrate (210). The first drain electrode (234) of the first power semiconductor element (230) may be electrically connected to the first substrate (210), and the first gate electrode (232) and the first source electrode (233) of the first power semiconductor element (230) may be electrically connected to the second substrate (220). As will be described later, the first gate electrode (232) may be electrically connected to a via terminal (251), and the first source electrode (233) may be electrically connected to a via terminal (252).

[0082] Since the first gate electrode (232) and the first source electrode (233) are disposed on the same upper surface of the first semiconductor layer (231), the first gate electrode (232) and the first source electrode (233) can be positioned spaced apart from each other so that a short circuit does not occur between them. Since the first gate electrode (232) and the first source electrode (233) are disposed on the same upper surface of the first semiconductor layer (231), the first power semiconductor element (230) can have a flip-chip structure.

[0083] In the second power semiconductor element (240), the second drain electrode (244) may be disposed on the lower side of the second semiconductor layer (241), and the second gate electrode (242) and the second source electrode (243) may be disposed on the upper side of the second semiconductor layer (241). That is, the second gate electrode (242) and the second source electrode (243) may be disposed on the upper surface of the second semiconductor layer (241) facing the second substrate (220), and the second drain electrode (244) may be disposed on the lower surface of the second semiconductor layer (241) facing the first substrate (210). The second drain electrode (244) of the second power semiconductor element (240) may be electrically connected to the second substrate (220), and the second gate electrode (242) and the second source electrode (243) of the second power semiconductor element (240) may be electrically connected to the first substrate (210). As will be described later, the second gate electrode (242) may be electrically connected to a via terminal (253), and the second source electrode (243) may be electrically connected to a via terminal (254).

[0084] Since the second gate electrode (242) and the second source electrode (243) are disposed on the same upper surface of the second semiconductor layer (241), the second gate electrode (242) and the second source electrode (243) can be positioned spaced apart from each other so that a short circuit does not occur between them. Since the second gate electrode (242) and the second source electrode (243) are disposed on the same upper surface of the second semiconductor layer (241), the second power semiconductor element (240) can have a flip-chip structure.

[0085] Meanwhile, as described above, the first metal layer (213) in the first substrate (210) may include a plurality of circuit patterns. The power terminal (255) and the first drain electrode (234) of the first power semiconductor element (230) may be electrically connected through a first circuit pattern among the plurality of circuit patterns. The power terminal (256) and the second drain electrode (244) of the second power semiconductor element (240) may be electrically connected through a second circuit pattern among the plurality of circuit patterns.

[0086] The upper surfaces of the via terminals (251 to 254) and the power terminals (255, 256) may be parallel, but are not limited thereto.

[0087] The first substrate (210) and the second substrate (220) may have different sizes. For example, the size of the second substrate (220) may be smaller than the size of the first substrate (210).

[0088] The first substrate (210) may have a first region (210-1) and a second region (210-2). The second region (210-2) may be located on one side of the first region (210-1).

[0089] In this case, the first power semiconductor element (230) and the second power semiconductor element (240) may be placed on the first region (210-1) of the first substrate (210). The power terminals (255, 256) may be placed on the second region (210-2).

[0090] For example, the first power semiconductor element (230) and the second power semiconductor element (240) may be arranged to overlap horizontally. For example, the second substrate (220) may vertically overlap with the first region (210-1) of the first substrate (210), but may not vertically overlap with the second region (210-2) of the first substrate (210). The power terminals (255, 256) may not vertically overlap with the second substrate (220).

[0091] Meanwhile, in the present disclosure, the second substrate (220) may be placed on the first power semiconductor element (230) and the second power semiconductor element (240). The second substrate (220) may be placed on the first region (210-1) of the first substrate (210).

[0092] The second substrate (220) may include a plurality of terminals. For example, the second substrate (220) may include a plurality of via terminals (251 to 254).

[0093] The second substrate (220) may include a plurality of vias (291 to 294). The vias (291 to 294) are holes formed by vertically penetrating the second substrate (220) and may be referred to as via holes or through holes.

[0094] The first via terminal (251) may be placed on the first via (291), the second via terminal (252) may be placed on the second via (292), the third via terminal (253) may be placed on the third via (293), and the fourth via terminal (254) may be placed on the fourth via (294).

[0095] For smooth power supply, it may be preferable that the width of the via terminal (292) connected to the first source electrode (233) be larger than the width of the via terminal (291) connected to the first gate electrode (232). For smooth power supply, it may be preferable that the width of the via terminal (254) connected to the second source electrode (243) be larger than the width of the via terminal (253) connected to the second gate electrode (242).

[0096] The via terminals (251 to 254) may have a lower surface exposed from the lower surface of the second substrate (220) and an upper surface exposed from the upper surface of the second substrate (220).

[0097] For example, the via terminal (251) may be vertically overlapped with the first gate electrode (232) of the first power semiconductor element (230) and electrically connected to the first gate electrode (232), and the via terminal (252) may be vertically overlapped with the first source electrode (233) of the first power semiconductor element (230) and electrically connected to the first source electrode (233). For example, the via terminal (253) may be vertically overlapped with the second gate electrode (242) of the second power semiconductor element (240) and electrically connected to the second gate electrode (242), and the via terminal (254) may be vertically overlapped with the second source electrode (243) of the second power semiconductor element (240) and electrically connected to the second source electrode (243).

[0098] The lower surface of the via terminal (251) and the upper surface of the first gate electrode (232) can be surface-bonded using a sintered metal. The lower surface of the via terminal (252) and the upper surface of the first source electrode (233) can be surface-bonded using a sintered metal. The lower surface of the via terminal (253) and the upper surface of the second gate electrode (242) can be surface-bonded using a sintered metal. The lower surface of the via terminal (254) and the upper surface of the second source electrode (243) can be surface-bonded using a sintered metal.

[0099] The distance between the via terminals (251 to 254) can be set by taking into consideration the distance between the first power semiconductor element (230) and the second power semiconductor element (240), the distance between the first gate electrode (232) and the first source electrode (233) of the first power semiconductor element (230), the distance between the second gate electrode (242) and the second source electrode (243) of the second power semiconductor element (240), etc.

[0100] In the drawing, the size of each of the via terminals (251 to 254) is depicted as being smaller than the sizes of the first gate electrode (232), the first source electrode (233), the second gate electrode (242), and the second source electrode (243). However, each of the via terminals (251 to 254) may have a size larger than the sizes of the first gate electrode (232), the first source electrode (233), the second gate electrode (242), and the second source electrode (243).

[0101] As described above, the first drain electrode (234) of the first power semiconductor element (230) can be surface-bonded to the first circuit pattern on the first substrate (210) via a sintered metal. The second drain electrode (244) of the second power semiconductor element (240) can be surface-bonded to the second circuit pattern on the first substrate (210) via a sintered metal.

[0102] Via terminals (251 to 254) can be assigned as signal terminals, power terminals, output terminals, etc.

[0103] For example, via terminals (251) and (253) may be assigned as signal terminals, via terminals (254) may be assigned as power terminals, and via terminals (252) may be assigned as output terminals. In this case, gate signals may be supplied to via terminals (251) and (253), and AC voltage may be supplied as input voltage to via terminals (254).

[0104] The via terminal (252) assigned as the output terminal may be a member for outputting an output voltage generated by turning on / off the first power semiconductor element (230) and the second power semiconductor element (240). To this end, the first source electrode (233) of the first power semiconductor element (230) and the second drain electrode (244) of the second power semiconductor element (240) may be electrically connected. For example, the first source electrode (233) of the first power semiconductor element (230) may be electrically connected to the via terminal (252), and the second drain electrode (244) of the second power semiconductor element (240) may be electrically connected to the power terminal (256) through a second circuit pattern on the first substrate (210). In this case, the via terminal (252) and the power terminal (256) may be electrically connected inside or outside the power semiconductor module. Accordingly, the output voltage generated by turning on / off the first power semiconductor element (230) and the second power semiconductor element (240) can be output through the via terminal (252).

[0105] As an example, a conductive post, such as a copper post, may be positioned between the first power semiconductor element (230) and the second power semiconductor element (240) inside the power semiconductor module. In this case, a side of the first source electrode (233) of the first power semiconductor element (230) and a second circuit pattern on the first substrate (210) are electrically connected through the copper post, thereby electrically connecting the via terminal (252) and the power terminal (256) inside the power semiconductor module.

[0106] As another example, the upper side of the power semiconductor module may be mounted on the driving unit. In this case, the via terminal (252) and the power terminal (256) of the power semiconductor module are electrically connected through the driving unit, thereby allowing the via terminal (252) and the power terminal (256) to be electrically connected from the outside of the power semiconductor module.

[0107] The driving unit may include a signal supply unit, a power supply unit, etc. When the upper side of the power semiconductor module is mounted on the driving unit, the via terminal (251) and the via terminal (253) may be electrically connected to the signal supply unit of the driving unit, and the power terminal (255) and the via terminal (254) may be electrically connected to the power supply unit. Accordingly, a gate signal may be supplied to the first gate electrode (232) of the first power semiconductor element (230) and the second gate electrode (242) of the second power semiconductor element (240) through the via terminal (251) and the via terminal (253) by the signal supply unit.

[0108] According to the present disclosure, via terminals (251 to 254) can be positioned on the first power semiconductor element (230) and the second power semiconductor element (240). Accordingly, a physical distance or current path between the via terminals (251 to 254) and the first power semiconductor element (230) and the second power semiconductor element (240) can be minimized, thereby enabling stable switching operation.

[0109] According to the present disclosure, since the via terminals (251 to 254) do not need to be arranged together with the power terminals (255, 256) on the side of the first power semiconductor element (230) and the second power semiconductor element (240), the cross-sectional area of ​​each of the power terminals (255, 256) assigned as the power terminals can be increased, thereby realizing a high-power semiconductor module. In addition, since a sufficient gap can be maintained between a plurality of power terminals (255) or between a plurality of power terminals (256), an electrical short can be prevented.

[0110] Meanwhile, an insulating portion (260) may be formed on the outer periphery of each of the via terminals (251 to 254) on the second substrate (220).

[0111] The second substrate (220) may include an insulating portion (260) around each of the via terminals (251 to 254) within the vias (291 to 294). The insulating portion (260) may be made of an inorganic material such as SiO2 or SiN, but is not limited thereto. The insulating portion (260) may prevent the via terminals (251 to 254) from being electrically shorted with the first metal layer or the second metal layer.

[0112] The via terminals (291 to 294) can be electrically insulated by the insulating layer (221) and the insulating portion (260).

[0113] Meanwhile, referring again to FIGS. 3 and 4, the power terminal (255) may be placed on the second region (210-2) of the first substrate (210). The power terminal (255) may not vertically overlap with the second substrate (220).

[0114] Power terminals (255) may be provided in multiple numbers along the second direction (Y). For example, the power terminals (255) may be electrically connected to the first drain electrode (234) of the first power semiconductor element (230) through the first circuit pattern on the first substrate (210).

[0115] Since the power terminal (255) must carry a high current, its cross-sectional area must be large. In addition, multiple power terminals (255) must be arranged within a predetermined area in the second direction (Y). In this case, since it is difficult to increase the width of the power terminal (255), its thickness must be increased.

[0116] In the present disclosure, the thickness (T11) of the power terminal (255) may be greater than the thickness of the first power semiconductor element (230) or the second power semiconductor element (240). For example, the thickness (T11) of the power terminal (255) may be equal to or greater than the sum of the thickness of the first power semiconductor element (230) (or the second power semiconductor element (240)) and the thickness of the second substrate (220). Accordingly, the cross-sectional area of ​​the power terminal (255) is increased, so that a high-power power semiconductor module capable of flowing a high current can be implemented.

[0117] The power terminal (255) may be horizontally overlapped with the second substrate (220). That is, the power terminal (255) may be positioned higher than the upper surface of the first power semiconductor element (230) and may be positioned so as to be level with the upper surface of the second substrate (220). In other words, the upper surface of the power terminal (255) and the upper surface of the second substrate (220) may be positioned on the same horizontal line. In this case, the power terminal (255) may have an exposed upper surface.

[0118] Although not shown, the power terminal (255) may be positioned lower than the upper surface of the first power semiconductor element (230), and the support molding part (270) may be positioned on the upper surface of the power terminal (255).

[0119] Meanwhile, as illustrated in Fig. 1, in a conventional power semiconductor module, a terminal (50) larger than the thickness of the power semiconductor element (30, 40) is placed between the first substrate (10) and the second substrate (20). In this case, a spacer (70, 80) must be placed on the upper or lower portion of the power semiconductor element (30, 40). Accordingly, the thickness of the power semiconductor module increases and the material cost increases.

[0120] However, in the present disclosure, the size of the second substrate (220) is made smaller than the size of the first substrate (210), so that the power terminal (255) can be placed on the second region (210-2) of the first substrate (210) that does not vertically overlap with the second substrate (220). Therefore, a spacer is not required, so material costs can be reduced. In addition, even if a power terminal (255) having the same thickness as the existing one is employed, the thickness of the power semiconductor module can be reduced at least by the thickness of the existing spacer.

[0121] Meanwhile, the power terminal (256) may be placed on the second region (210-2) of the first substrate (210). The power terminal (256) may not vertically overlap with the second substrate (220).

[0122] A plurality of power terminals (256) may be provided along the second direction (Y). The power terminals (256) may be electrically connected to the second drain electrode (244) of the second power semiconductor element (240) through the second circuit pattern on the first substrate (210).

[0123] Since the power terminal (256) must carry a high current, its cross-sectional area must be large. In addition, multiple power terminals (256) must be arranged within a predetermined area in the second direction (Y). In this case, since it is difficult to increase the width of the power terminal (256), its thickness must be increased.

[0124] In the present disclosure, the thickness (T12) of the power terminal (256) may be greater than the thickness of the first power semiconductor element (230) or the second power semiconductor element (240). For example, the thickness (T12) of the power terminal (256) may be equal to or greater than the sum of the thickness of the first power semiconductor element (230) (or the second power semiconductor element (240)) and the thickness of the second substrate (220). Accordingly, the cross-sectional area of ​​the power terminal (256) is increased, so that a high-power power semiconductor module capable of flowing a high current can be implemented.

[0125] In this case, the power terminal (256) may be horizontally overlapped with the second substrate (220). That is, the power terminal (256) may be positioned higher than the upper surface of the first power semiconductor element (230) and may be positioned so as to be on the same level as the upper surface of the second substrate (220). In other words, the upper surface of the power terminal (256) and the upper surface of the second substrate (220) may be positioned on the same horizontal line. In this case, the power terminal (256) may have an exposed upper surface.

[0126] Although not shown, the power terminal (256) may be positioned lower than the upper surface of the second power semiconductor element (240), and the support molding part (270) may be positioned on the upper surface of the power terminal (256).

[0127] Meanwhile, as illustrated in Fig. 1, in a conventional power semiconductor module, a terminal (50) larger than the thickness of a power semiconductor element (30, 40) is disposed between the first substrate (10) and the second substrate (20). In this case, a spacer (70, 80) must be disposed on the upper or lower portion of the power semiconductor element (30, 40). Accordingly, the thickness of the power semiconductor module increases. In addition, when the power semiconductor module is equipped with eight first power semiconductor elements (230) and eight power semiconductor elements, 16 spacers are required, which increases material costs.

[0128] However, in the present disclosure, the size of the second substrate (220) is made smaller than the size of the first substrate (210), so that the power terminal (256) can be placed on the third region (210-3) of the first substrate (210) that does not vertically overlap with the second substrate (220). Therefore, since a spacer is not required, material costs can be reduced. In addition, even if a power terminal (256) having the same thickness as the existing one is employed, the thickness of the power semiconductor module can be reduced at least by the thickness of the existing spacer.

[0129] Meanwhile, as shown in FIG. 1, a lead frame was placed on a first substrate (10) using a pick and place process, and the lead frame was cut using a cutting and bending process, thereby forming a terminal (50) on the first substrate (10).

[0130] In contrast, in the present disclosure, the power terminals (255, 256) may be conductive dot members, conductive clips, etc., individually manufactured in advance. Accordingly, since a conventional lead frame is not used, equipment or processes for performing a pick-and-place process, cutting, and bending process are not required, and thus the process can be simplified and the process time can be shortened.

[0131] Referring again to FIGS. 3 and 4, the support molding portion (270) can be placed on the first substrate (210).

[0132] The support molding part (270) can surround each of the first substrate (210), the first power semiconductor element (230), the second power semiconductor element (240), the second substrate (220), and the power terminals (255, 256).

[0133] The support molding part (270) may be disposed on the upper and side portions of the first substrate (210). Although not shown, the support molding part (270) may also be disposed on the lower side of the first substrate (210). The support molding part (270) may surround the side portion of the first power semiconductor element (230). The support molding part (270) may surround the side portion of the second power semiconductor element (240). The support molding part (270) may be disposed on the side portion and the lower side of the second substrate (220). The support molding part (270) may be disposed on the side portion and the lower side of the power terminal (255). The support molding part (270) may be disposed on the side portion and the lower side of the power terminal (256).

[0134] The support molding part (270) can be formed to extend from one side of the first substrate (210) and support the side of the power terminals (255, 256). The support molding part (270) can be arranged between the side of the power terminal (255) and the side of the first power semiconductor element (230). The support molding part (270) can be arranged between the side of the power terminal (255) and the side of the second substrate (220). The support molding part (270) can be arranged between the side of the power terminal (256) and the side of the second power semiconductor element (240). The support molding part (270) can be arranged between the side of the power terminal (256) and the side of the second substrate (220).

[0135] The support molding portion (270) may be formed of a resin material with excellent insulating performance. For example, the support molding portion (270) may be formed of an EMC (Epoxy Molding Compound) molding material, but is not limited thereto. The EMC molding material may be a sealing material that protects the first power semiconductor element (230) and the second power semiconductor element (240) from heat, moisture, impact, insulation breakdown, etc.

[0136] Meanwhile, since the support molding part (270) is not arranged on the upper surface of each of the via terminals (251 to 254) and the power terminals (255, 256), the upper surface of each of the via terminals (251) to the power terminals (256) can be exposed to the outside.

[0137] In the present disclosure, when a power semiconductor module in which the upper surfaces of each of the via terminals (251 to 254) and the power terminals (255, 256) are exposed is mounted on a driving unit, the via terminals (251 to 254) and the power terminals (255, 256) can be electrically connected to a signal supply unit and a power supply unit of the driving unit. Accordingly, a process for separately electrically connecting each of the via terminals (251 to 254) and the power terminals (255, 256) to an external power line, etc., is not required, so the process can be simplified. In addition, defects that may occur during the process for separate electrical connection can be prevented. In addition, since each of the via terminals (251 to 254) and the power terminals (255, 256) is electrically connected to the signal supply unit and the power supply unit of the driving unit through surface contact, electrical disconnection due to contact defects can be prevented and current loss can be minimized.

[0138] Fig. 5 is a cross-sectional view illustrating a power semiconductor module according to a third aspect of the present disclosure. Fig. 6 is a perspective view illustrating the first substrate of Fig. 5.

[0139] The cross-sectional view illustrated in Fig. 5 may be a view of the power semiconductor module of Fig. 3 cut along line AA'.

[0140] The third aspect of the present disclosure may be similar to the second aspect of the present disclosure (Fig. 4) except that the first substrate (210) is provided with a step portion (280, 285). Components having the same shape, structure, and / or function as those of the second aspect of the present disclosure (Fig. 4) in the third aspect of the present disclosure are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0141] Referring to FIGS. 3 and 5, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a support molding part (270), etc.

[0142] The first substrate (210) may have a first region (210-1) and a second region (210-2). The first power semiconductor element (230) and the second power semiconductor element (240) may be disposed on the first region (210-1) of the first substrate (210). The power terminals (255, 256) may be disposed on the second region (210-2) of the first substrate (210). In addition, the first power semiconductor element (230) and the second power semiconductor element (240) may be disposed between the first substrate (210) and the second substrate (220).

[0143] Meanwhile, as illustrated in FIG. 6, the first substrate (210) may have a step portion (280, 285) having an upper surface (210-2a, 210-3a) of the second region (210-2) that is lower than the upper surface (210-1a) of the first region (210-1). For example, the first metal layer (213) corresponding to the first region (210-1) of the first substrate (210) may not be removed, and the upper surface of the first metal layer (213) corresponding to each of the second regions (210-2) of the first substrate (210) may be removed. Accordingly, a step portion (280, 285) having an upper surface (210-2a, 210-3a) of the second region (210-2) that is lower than an upper surface (210-1a) of the first region (210-1) can be formed. The depth removed from the step portion (280, 285) can be set in consideration of the thickness of the first metal layer (213), the thickness (T21, T22) of each of the power terminals (255, 256), etc.

[0144] The power terminal (255) can be coupled to the first step (280), and the power terminal (256) can be coupled to the second step (285).

[0145] As the power terminal (255) is arranged on the first step portion (280), the thickness (T21) of the power terminal (255) may be greater than the thickness (T11) of the power terminal (255) in the second side (Fig. 4) of the present disclosure. In this case, even if the width of the power terminal (255) is the same as the width of the power terminal (255) in the second side (Fig. 4) of the present disclosure, the cross-sectional area may increase. Accordingly, a larger current may flow in the power terminal (255), so that a high-power semiconductor module may be implemented.

[0146] As the power terminal (256) is arranged on the second step portion (285), the thickness (T22) of the power terminal (256) may be greater than the thickness (T12) of the power terminal (256) in the second side (Fig. 4) of the present disclosure. In this case, even if the width of the power terminal (256) is the same as the width of the power terminal (256) in the second side (Fig. 4) of the present disclosure, the cross-sectional area may increase. Accordingly, a larger current may flow in the power terminal (256), so that a high-power semiconductor module may be implemented.

[0147] Meanwhile, in FIG. 6, it is shown that the first step portion (280) and the second step portion (285) have the same shape along the second direction (Y).

[0148] Alternatively, although not shown, a plurality of first step portions (280) and a plurality of second step portions (285) may be formed to correspond to a plurality of power terminals (255) and a plurality of power terminals (256), respectively. That is, in the second region (210-2) of the first substrate (210), the upper surface (210-2a) of the second region (210-2) corresponding to the plurality of power terminals (255) is formed with a first step portion (280) that is lower than the upper surface (210-1a) of the first region (210-1), but the upper surface (210-2a) of the other second region (210-2) may be positioned on the same horizontal line as the upper surface (210-1a) of the first region (210-1). In the second region (210-2) of the first substrate (210), the upper surface (210-3a) of the second region (210-2) corresponding to the plurality of power terminals (256) is formed with a second step (285) that is lower than the upper surface (210-1a) of the first region (210-1), but the upper surface (210-3a) of the other second region (210-2) can be positioned on the same horizontal line as the upper surface (210-1a) of the first region (210-1).

[0149] Fig. 7 is a cross-sectional view illustrating a power semiconductor module according to the fourth aspect of the present disclosure. Fig. 8 is a plan view illustrating a power semiconductor module according to the fifth aspect of the present disclosure. The cross-sectional view illustrated in Fig. 8 may be a view taken along line BB' of the power semiconductor module of Fig. 7.

[0150] A fourth aspect of the present disclosure may be similar to the second aspect (Fig. 4) of the present disclosure, except that the power terminals (265 266) are arranged on the second substrate (220) via the fifth via (295) and the sixth via (296). In the fourth aspect of the present disclosure, components having the same shape, structure, and / or function as those in the second aspect of the present disclosure (Fig. 4) are given the same drawing reference numerals, and a detailed description thereof is omitted.

[0151] Referring to FIGS. 7 and 8, the power semiconductor module may include a first substrate (210), a second substrate (220), a first power semiconductor element (230), a second power semiconductor element (240), a support molding part (270), etc.

[0152] Since the first substrate (210), the first power semiconductor element (230), the second power semiconductor element (240), and the support molding part (270) have already been described, a detailed description thereof is omitted.

[0153] The second substrate (220) may have a size corresponding to the size of the first substrate (210). In this case, the second substrate (220) may include via terminals (251 to 254) arranged corresponding to the first region (210-1) of the first substrate (210), and power terminals (265, 266) arranged corresponding to the second region (210-2) of the first substrate (210).

[0154] For this purpose, vias (291 to 296) may be formed in the second substrate (220). Via terminals (251 to 254) may be formed in the vias (291 to 294), and power terminals (265, 266) may be formed in the vias (295, 296).

[0155] A first power semiconductor element (230) and a second power semiconductor element (240) may be disposed on a first region (210-1) of a first substrate (210), and a second substrate (220) may be disposed on the first power semiconductor element (230) and the second power semiconductor element (240). In this case, via terminals (251 to 254) on the second substrate (220) may be electrically connected to the first power semiconductor element (230) and the second power semiconductor element (240). For example, the via terminal (251) may be electrically connected to the first gate electrode (232) of the first power semiconductor element (230), and the via terminal (252) may be electrically connected to the first source electrode (233) of the first power semiconductor element (230). For example, the via terminal (253) may be electrically connected to the second gate electrode (242) of the second power semiconductor element (240), and the via terminal (254) may be electrically connected to the second source electrode (243) of the second power semiconductor element (240).

[0156] Since high voltage (or high current) is supplied to the power terminals (265 266), the size (or diameter) of each of the power terminals (265 266) may be formed to be larger than the size (or diameter) of each of the via terminals (251 to 254) to withstand the high voltage (or high current).

[0157] As illustrated in Fig. 1, in a conventional power semiconductor module, not only the signal terminal but also the power terminal and the output terminal are all arranged on both sides of the power semiconductor element (330, 40). In this case, since the number of terminals is large in a limited space, it is difficult to increase the size of the power terminal or the output terminal to which a high voltage is supplied.

[0158] However, according to the present disclosure, the via terminals (251 to 254) may be arranged in the central region of the second substrate (220), and only the power terminals (265 266) may be arranged on both sides of the second substrate (220). In this case, since the number of terminals on both sides of the second substrate (220) is reduced, the size of each of the power terminals (265 266) is designed to be increased, so that a high-power semiconductor module can be implemented.

[0159] Meanwhile, the second substrate (220) may include an insulating layer (221), an insulating portion (260), and an insulating pattern (261, 262).

[0160] For example, the first insulating layer (221) can electrically insulate the first metal layer (223) and the second metal layer (225).

[0161] For example, the insulation (260) may be arranged around each of the via terminals (251 to 254) and the power terminals (265, 266) within the vias (291 to 296). Each of the via terminals (251 to 254) and the power terminals (265, 266) may be electrically insulated from the first metal layer (223) or the second metal layer (225) by the insulation (260).

[0162] Insulating patterns (261, 262) can be placed between via terminals (251 to 254) and power terminals (265, 266).

[0163] For example, the insulating patterns (261, 262) may be arranged around each of the power terminals (265, 266). The insulating patterns (261, 262) may be filled in the recesses (301, 302) from which the second metal layer (225), the first insulating layer (221), and the first metal layer (223) are removed. That is, the recesses (301, 302) may be formed by removing the second metal layer (225), the first insulating layer (221), and the first metal layer (223) so that the upper surface of the support molding part (270) is exposed along the perimeter of each of the power terminals (265, 266).

[0164] Although not shown, the first insulating layer (221) and the first metal layer (223) may not be removed, and only the second metal layer (225) may be removed, thereby forming recesses (301, 302).

[0165] Insulating patterns (261, 262) may be placed in recesses (301, 302). The drawing illustrates that insulating patterns (261, 262) are placed in recesses (301, 302). However, insulating patterns (261, 262) may not be placed in recesses (301, 302). That is, recesses (301, 302) may remain as empty spaces.

[0166] When the power terminals (265, 266) are provided in plurality, recesses (301, 302) may be formed along the circumference of each of the plurality of power terminals (265) and along the circumference of each of the plurality of power terminals (266). These recesses (301, 302) may be connected to each other, but are not limited thereto. In this case, the second metal layer (or second metal pattern) disposed around the circumference of the power terminals (265, 266) by the recesses (301, 302) may be physically spaced apart from the second metal layer disposed around the circumference of each of the via terminals (251 to 254).

[0167] The via terminals (251 to 254) and the power terminals (265, 266) can be electrically insulated by the insulating layer (221), the insulating portion (260), and the insulating pattern (261, 262).

[0168] As described above, since the power terminals (265 266) are supplied with a high voltage of 1200 V or more, the power terminals (265 266) may be electrically shorted with the second metal layer due to a defect in the insulation (260), etc. However, according to the present disclosure, recesses (301, 302) in which the second metal layer is removed are formed around each of the power terminals (265 266), and insulating patterns (261, 262) are arranged in the recesses (301, 302), so that the power terminals (265 266) may be electrically insulated from the second metal layer.

[0169] Meanwhile, the power semiconductor module may include a first conductive post (271) and a second conductive post (272). The first conductive post (271) and the second conductive post (272) may each include a post having excellent electrical conductivity.

[0170] The first conductive post (271) and the second conductive post (272) can be sintered bonded together with the first power semiconductor element (230) and the second power semiconductor element (240).

[0171] Specifically, a sintered metal may be formed on a first substrate (210) through a printing method. Thereafter, a first conductive post (271), a second conductive post (272), a first power semiconductor element (230), and a second power semiconductor element (240) may be positioned on the substrate. Thereafter, the first conductive post (271), the second conductive post (272), the first power semiconductor element (230), and the second power semiconductor element (240) may be thermally compressed, whereby the first conductive post (271), the second conductive post (272), the first power semiconductor element (230), and the second power semiconductor element (240) may be fixed to and electrically connected to the first substrate (210). For example, a first drain electrode (234) of the first power semiconductor element (230) and a lower side of the first conductive post (271) may be electrically connected to a first circuit pattern of the first substrate (210). The second drain electrode (244) of the second power semiconductor element (240) and the lower side of the second conductive post (272) can be electrically connected to the second circuit pattern of the first substrate (210).

[0172] Thereafter, the sintered metal can be formed on the second substrate (220) through a printing method. Thereafter, the second substrate (220) can be positioned so that the surface on which the sintered metal is formed faces the first substrate (210) and then thermally compressed. Accordingly, the via terminals (251 to 254) and the power terminals (265 and 266) on the second substrate (220) can be fixed to and electrically connected to the first power semiconductor element (230), the second power semiconductor element (240), the first conductive post (271), and the second conductive post (272). For example, the via terminal (251) and the via terminal (252) can be electrically connected to the first gate electrode (232) and the first source electrode (233), respectively, of the first power semiconductor element (230). For example, the via terminal (253) and the via terminal (254) may be electrically connected to the second gate electrode (242) and the second source electrode (243), respectively, of the second power semiconductor element (240). For example, the power terminal (265) may be electrically connected to the upper side of the first conductive post (271), and the power terminal (266) may be electrically connected to the upper side of the second conductive post (272).

[0173] A first conductive post (271) may be placed between a second region (210-2) of a first substrate (210) and a power terminal (265) of a second substrate (220). Through the first conductive post (271), the power terminal (265) may be electrically connected to a first circuit pattern of the first substrate (210).

[0174] For example, the size (or width) of the first conductive post (271) may be larger than the size (or width) of the power terminal (265). In this case, even if misalignment occurs when the first conductive post (271) is sintered and bonded to the second region (210-2) of the first substrate (210), a stable electrical connection can be made without an electrical short circuit occurring between the power terminal (265) and the first conductive post (271).

[0175] The second conductive post (272) may be arranged between the second region (210-2) of the first substrate (210) and the power terminal (266) of the second substrate (220). The power terminal (266) may be electrically connected to the second circuit pattern of the first substrate (210) through the second conductive post (272). For example, the size (or width) of the second conductive post (272) may be larger than the size (or width) of the power terminal (266). In this case, even if misalignment occurs when the second conductive post (272) is sintered bonded to the second region (210-2) of the first substrate (210), the power terminal (266) and the second conductive post (272) may be stably electrically connected without causing an electrical short circuit.

[0176] Considering heat dissipation performance, etc., it may be desirable that the height of the first conductive post (271) be the same as the height of the first power semiconductor element (230). Considering heat dissipation performance, etc., it may be desirable that the height of the first conductive post (272) be the same as the height of the second power semiconductor element (240).

[0177] The above detailed description should not be construed as limiting in any respect and should be considered illustrative. The scope of the above-described aspects should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalency range of the above-described aspects are intended to be included within the scope of the above-described aspects.

Claims

1. A first substrate having a first region and a second region on one side of the first region; A power semiconductor element disposed on the first region of the first substrate; A second substrate disposed on the power semiconductor element; and A power terminal disposed on the second region of the first substrate and horizontally overlapping the second substrate; The second substrate has a via terminal electrically connected to the power semiconductor element. Power semiconductor modules.

2. In paragraph 1, The above second substrate, First insulating layer; A first metal layer disposed on the lower side of the first insulating layer; and A second metal layer disposed on the upper side of the first insulating layer; The above via terminal is formed by penetrating the first metal layer, the insulating layer, and the second metal layer. Power semiconductor modules.

3. In paragraph 1, The upper surface of the above via terminal and the upper surface of the above power terminal are parallel. Power semiconductor modules.

4. In paragraph 2, The second substrate includes an insulating portion arranged on the outer periphery of the via terminal and the power terminal. Power semiconductor modules.

5. In paragraph 4, The above via terminal includes a first via terminal and a second via terminal, The first via terminal and the second via terminal are electrically insulated by the insulating layer and the insulating portion. Power semiconductor modules.

6. In paragraph 5, The above power semiconductor device includes a gate electrode and a source electrode, The first via terminal and the second via terminal are electrically connected to the gate electrode and the source electrode, respectively. Power semiconductor modules.

7. In paragraph 6, The above power semiconductor device further includes a drain electrode, The above power terminal is electrically connected to the first drain electrode, Power semiconductor modules.

8. In paragraph 7, A step portion is formed on the upper surface of the second region, The above power terminal is coupled to the above step, Power semiconductor modules.

9. In paragraph 1, Further comprising a support molding portion formed to extend from one side of the first substrate and support the side of the power terminal; Power semiconductor modules.

10. A first substrate having a first region and a second region on one side of the first region; A power semiconductor element disposed on the first region of the first substrate; A second substrate having a third region disposed on the power semiconductor element and a fourth region on one side of the third region; and A conductive post disposed between the second region and the fourth region; The second substrate has a via terminal electrically connected to the power semiconductor element and a power terminal electrically connected to the first substrate. Power semiconductor modules.

11. In paragraph 10, The above second substrate, First insulating layer; A first metal layer disposed on the lower side of the first insulating layer; and A second metal layer disposed on the upper side of the first insulating layer; The above via terminal and the power terminal are formed by penetrating the first metal layer, the insulating layer and the second metal layer. Power semiconductor modules.

12. In paragraph 11, The upper surface of the above via terminal and the upper surface of the above power terminal are parallel, Power semiconductor modules.

13. In paragraph 11, The second substrate includes an insulating portion arranged on the outer periphery of the via terminal and the power terminal. Power semiconductor modules.

14. In paragraph 13, The above via terminal includes a first via terminal and a second via terminal, The first via terminal and the second via terminal are electrically insulated by the insulating layer and the insulating portion. Power semiconductor modules.

15. In paragraph 13, The first metal layer and the second metal layer, Including an insulating pattern between the above via terminal and the above power terminal, The above via terminal and the power terminal are electrically insulated by the insulating layer, the insulating portion and the insulating pattern. Power semiconductor modules.

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