Display apparatus and electronic device including same

Abstract

This display apparatus may include: first to third sub-pixels arranged in a first direction and each including a pixel circuit; a light sensing pixel including a sensor circuit; a data line electrically connected to each of the second and third sub-pixels; a readout line electrically connected to the light sensing pixel; a horizontal bridge line extending in the first direction; a first vertical bridge line extending in a second direction and disposed in the second sub-pixel; and a second vertical bridge line extending in the second direction and disposed in the third sub-pixel. In a plan view, the second vertical bridge line may be disposed between the readout line and the data line of the third sub-pixel. The second vertical bridge line may include a first sub-electrode and a second sub-electrode spaced apart from each other.

Description

Display device and electronic device including same

[0001] The present invention relates to a display device and an electronic device including the same.

[0002] As interest in information displays has grown recently, research and development on display devices are continuously being conducted.

[0003] The present invention can provide a display device with improved reliability and an electronic device including the same.

[0004] A display device according to one or more embodiments may include first to third sub-pixels arranged along a first direction, each including a pixel circuit; a light-sensing pixel including a sensor circuit; a data line electrically connected to each of the second and third sub-pixels; a readout line electrically connected to the light-sensing pixel; a horizontal bridge line extending along the first direction; a first vertical bridge line extending in a second direction and arranged in the second sub-pixel; and a second vertical bridge line extending in the second direction and arranged in the third sub-pixel. When viewed in a plan view, the second vertical bridge line may be arranged between the readout line and the data line of the third sub-pixel. The second vertical bridge line may include a first sub-electrode and a second sub-electrode arranged to be spaced apart from each other.

[0005] In one or more embodiments, the first sub-electrode may be electrically connected to the horizontal bridge line. The first sub-electrode and the second sub-electrode may be electrically isolated from each other.

[0006] In one or more embodiments, the data line, the first vertical bridge line, and the second vertical bridge line may be arranged on the same layer.

[0007] In one or more embodiments, the display device may further include a reset voltage line electrically connected to the light-sensitive pixel and configured to supply a reset voltage. The reset voltage line may include a first line disposed on the same layer as the data line and the first and second vertical bridge lines and spaced apart from them; a second line disposed below the first line and electrically connected to the first line; and a third line disposed below the second line and electrically connected to the second line.

[0008] In one or more embodiments, the third wiring may extend in the first direction, the second wiring may extend in the second direction, and the first wiring may extend in the second direction. The reset voltage wiring may form a mesh structure.

[0009] In one or more embodiments, the display device may further include a first power wire electrically connected to each of the first to third sub-pixels and configured to receive a first driving voltage; a second power wire electrically connected to each of the first to third sub-pixels and configured to receive a second driving voltage; and a third power wire electrically connected to each of the first to third sub-pixels and configured to receive a third driving voltage. The first driving voltage, the second driving voltage, and the third driving voltage may be direct current voltages having a constant voltage level.

[0010] In one or more embodiments, the second sub-electrode may be electrically connected to at least one of the first power wire, the second power wire, and the third power wire.

[0011] In one or more embodiments, the second sub-electrode may be electrically connected to the first power wiring.

[0012] In one or more embodiments, the second sub-electrode may be electrically connected to the second power wiring.

[0013] In one or more embodiments, the second sub-electrode may be electrically connected to the third power wiring.

[0014] In one or more embodiments, the light-sensitive pixel may be disposed between the second sub-pixel and the third sub-pixel.

[0015] In one or more embodiments, the first sub-pixel, the second sub-pixel, and the third sub-pixel may each include a light-emitting element configured to emit light. The light-sensing pixel may include a light-receiving element configured to output a sensing signal corresponding to the light.

[0016] In one or more embodiments, the first sub-electrode and the second sub-electrode may be electrically separated and arranged in the same row along the second direction.

[0017] In one or more embodiments, the display device may further include a first via layer including a first via hole disposed on the horizontal bridge line and exposing an area of ​​the horizontal bridge line; a pad electrode disposed on the first via layer and electrically connected to the horizontal bridge line through the first via hole; and a second via layer including a second via hole disposed on the pad electrode and exposing an area of ​​the pad electrode. When viewed in a plan view, the second vertical bridge line may be separated into the first sub-electrode overlapping the second via hole and the second sub-electrode not overlapping the second via hole near the second via hole.

[0018] In one or more embodiments, the display device may further include a substrate; first, second, third, fourth, fifth, sixth, seventh, eighth, and ninth insulating layers sequentially disposed on the substrate; a first conductive layer disposed between the second insulating layer and the third insulating layer; a second conductive layer disposed between the third insulating layer and the fourth insulating layer; a third conductive layer disposed between the fifth insulating layer and the sixth insulating layer; a fourth conductive layer disposed between the sixth insulating layer and the seventh insulating layer; a fifth conductive layer disposed between the seventh insulating layer and the eighth insulating layer; and a sixth conductive layer disposed between the eighth insulating layer and the ninth insulating layer. The fourth conductive layer may include the horizontal bridge line, the fifth conductive layer may include the leadout line, and the sixth conductive layer may include the first and second vertical bridge lines and the data line.

[0019] A display device according to one or more embodiments may include first to third sub-pixels arranged along a first direction, each including a pixel circuit; a light-sensing pixel including a sensor circuit and disposed between the second sub-pixel and the third sub-pixel; a data line electrically connected to each of the second and third sub-pixels; a readout line electrically connected to the light-sensing pixel; a horizontal bridge line extending along the first direction; a first vertical bridge line extending in a second direction and disposed in the second sub-pixel; a second vertical bridge line extending in the second direction and disposed in the third sub-pixel; and a power line electrically connected to each of the first to third sub-pixels and configured to receive a first driving voltage. The second vertical bridge line may include a first sub-electrode and a second sub-electrode that are disposed to be spaced apart from each other. The first sub-electrode may be electrically connected to the horizontal bridge line, and the second sub-electrode may be electrically connected to the power line.

[0020] In one or more embodiments, when viewed in a plan view, the second vertical bridge line may be disposed between the readout line and the data line of the third sub-pixel.

[0021] In one or more embodiments, the second sub-electrode may be a shielding member that prevents coupling capping between the readout line and the data line of the third sub-pixel.

[0022] An electronic device according to one or more embodiments may include a processor that provides input image data to a display device; and the display device that displays an image based on the input image data. The display device may include a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged along a first direction; a light-sensing pixel arranged between the second sub-pixel and the third sub-pixel; a data line electrically connected to each of the second and third sub-pixels; a readout line electrically connected to the light-sensing pixel; a horizontal bridge line extending along the first direction; a first vertical bridge line extending along a second direction and arranged in the second sub-pixel; and a second vertical bridge line extending along the second direction and arranged in the third sub-pixel. When viewed in a plan view, the second vertical bridge line may be arranged between the readout line and the third data line. The second vertical bridge line may include a first sub-electrode and a second sub-electrode that are arranged to be spaced apart from each other. The above first sub-electrode can be electrically connected to the horizontal bridge line.

[0023] In one or more embodiments, the display device may further include a power wiring configured to be electrically connected to each of the first to third sub-pixels and to receive a first driving voltage. The first sub-electrode and the second sub-electrode may be electrically separated. The second sub-electrode may be electrically connected to the power wiring.

[0024] According to one or more embodiments, a vertical bridge line may be arranged between a data line and a lead-out line. The vertical bridge line may be disconnected (or a portion of the vertical bridge line may be removed) near a connection point where the horizontal bridge line and the vertical bridge line are electrically connected, thereby separating the vertical bridge line into a first sub-electrode and a second sub-electrode. By electrically connecting the second sub-electrode to a power line that receives a voltage having a constant voltage level, the second sub-electrode may be utilized as a shielding member that prevents coupling capping that may occur between the data line and the lead-out line. Accordingly, the reliability of a display device and an electronic device including the same may be improved.

[0025] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0026] FIG. 1 is a schematic block diagram illustrating a display device according to one or more embodiments.

[0027] FIG. 2 is a schematic block diagram illustrating one or more embodiments of the display device of FIG. 1.

[0028] FIG. 3 is a schematic plan view illustrating a display device according to one or more embodiments.

[0029] Figure 4 is a schematic enlarged view showing the EA1 portion of Figure 3.

[0030] FIG. 5 is a schematic drawing showing an example of the arrangement of pixel circuits and sensor circuits in the display area of ​​the display panel included in the display device of FIG. 2.

[0031] FIG. 6 is a schematic drawing showing an example of a display area of ​​a display panel included in the display device of FIG. 2.

[0032] FIG. 7 is a schematic circuit diagram showing an example of a sub-pixel and a light-sensing pixel included in the display area of ​​FIG. 1.

[0033] FIG. 8 is a schematic cross-sectional view illustrating an area of ​​a display device according to one or more embodiments.

[0034] Fig. 9 is a schematic cross-sectional view showing the reflection path of light in the display device of Fig. 8.

[0035] FIG. 10 is a schematic plan view illustrating sub-pixels and light-sensitive pixels according to one or more embodiments.

[0036] FIG. 11 is a schematic plan view showing only the first, second, fifth, sixth, seventh, eighth, ninth, and eleventh transistors and the configurations included in the first conductive layer in FIG. 10.

[0037] Fig. 12 is a schematic plan view showing only the components included in the second challenge layer in Fig. 10.

[0038] FIG. 13 is a schematic plan view showing only the third, fourth, and tenth transistors and the components included in the third conductive layer in FIG. 10.

[0039] Fig. 14 is a schematic plan view showing only the components included in the fourth challenge layer in Fig. 10.

[0040] Fig. 15 is a schematic plan view showing only the components included in the fifth challenge layer in Fig. 10.

[0041] Fig. 16 is a schematic plan view showing only the components included in the 6th challenge layer in Fig. 10.

[0042] FIG. 17 is a schematic plan view showing only the components included in the fourth conductive layer, fifth conductive layer, and sixth conductive layer in FIG. 10.

[0043] Figure 18 is a schematic cross-sectional view taken along line Ⅰ-Ⅰ' of Figure 17.

[0044] FIG. 19 is a schematic plan view showing sub-pixels and light-sensitive pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one or more embodiments.

[0045] FIG. 20 is a schematic diagram showing the connection relationship of some wires in one area of ​​a display area of ​​a display device according to one or more embodiments.

[0046] FIG. 21 is a schematic plan view showing sub-pixels and light-sensitive pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one or more embodiments.

[0047] Figure 22 is a schematic enlarged view showing the EA2 portion of Figure 21.

[0048] Figure 23 is a schematic cross-sectional view taken along line Ⅱ-Ⅱ' of Figure 22.

[0049] FIG. 24 is a schematic plan view showing sub-pixels and light-sensitive pixels arranged in first and second pixel rows located in one area of ​​a display area of ​​a display device according to one or more embodiments.

[0050] Figure 25 is a schematic enlarged view showing the EA3 portion of Figure 24.

[0051] FIG. 26 is a schematic block diagram illustrating an electronic device according to one or more embodiments.

[0052] Figure 27 is a schematic diagram showing an example of the electronic device of Figure 26 implemented as a smartphone.

[0053] Fig. 28 is a schematic drawing showing an example of the electronic device of Fig. 26 implemented as a tablet PC.

[0054] The present disclosure may be modified in various ways and take various forms. Specific embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the present disclosure to specific embodiments, but rather to encompass all modifications, equivalents, and alternatives falling within the technical scope of the present disclosure.

[0055] In describing each drawing, similar reference numerals are used to designate similar components. In the attached drawings, the dimensions of structures are shown exaggerated for clarity of the present invention. Terms such as first, second, etc. may be used to describe various components, but these components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, without departing from the scope of the present invention, a first component could be referred to as a second component, and similarly, a second component could also be referred to as a first component.

[0056] In this application, terms such as "include" or "have" are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but should be understood to not preemptively exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof. In addition, when a part such as a layer, film, region, or plate is said to be "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. In addition, in this specification, when a part such as a layer, film, region, or plate is said to be formed on another part, the direction in which it is formed is not limited to the upper direction, but also includes the case where it is formed in the side or lower direction. Conversely, when a part such as a layer, film, region, or plate is said to be "under" another part, this includes not only the case where it is "directly below" the other part, but also the case where there is another part in between.

[0057] Hereinafter, with reference to the attached drawings, embodiments of the present invention and other details necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail. In the following description, singular expressions also include plural expressions, unless the context clearly indicates that only the singular is included.

[0058] For the purposes of this disclosure, the expressions "one or more," "an," and "selected" used before a list of elements modify the list of elements as a whole and do not modify individual elements within the list. For example, "one or more of X, Y, and Z," "one or more of X, Y, or Z," "one or more selected from the group consisting of X, Y, and Z" can mean X alone, Y alone, Z alone, any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, XZ, YZ, ZZ, etc.), or any variation thereof. Similarly, the expression "one or more of A and / or B" can include A, B, or A and B. The term "and / or" as used herein means any combination that includes one or more of the items included in the associated list. For example, the expression "A and / or B" can include A, B, or A and B. Furthermore, the term "may" when describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0059] Additionally, any numerical range disclosed and / or described herein is intended to include all subranges of the same numerical precision subsumed within the stated range. For example, a range "from 1.0 to 10.0" includes all subranges between the stated minimum value of 1.0 and the stated maximum value of 10.0, e.g., a range having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10 (e.g., from 2.4 to 7.6). Every maximum numerical limitation set forth herein includes every lower numerical limitation subsumed within that range, and every minimum numerical limitation set forth herein includes every upper numerical limitation subsumed within that range. Accordingly, Applicants reserve the right to amend this specification (including the claims) to expressly recite all subranges subsumed within the ranges expressly recited herein.

[0060] Considering the entirety of this disclosure, those skilled in the art will appreciate that each suitable feature included in the various embodiments of this disclosure can be combined, partially or fully, with one another, and technically interconnected to operate in a variety of suitable ways. Furthermore, unless otherwise stated or implied, each embodiment can be implemented independently or in combination with one another in any suitable manner.

[0061] FIG. 1 is a schematic block diagram illustrating a display device (DD) according to one or more embodiments.

[0062] Referring to FIG. 1, a display device (DD) according to embodiments may include a display panel (100) and a driving circuit (200). In one or more embodiments, the driving circuit (200) may include a panel driving unit (210) and a sensor driving unit (220).

[0063] The display device (DD) may be implemented as a self-luminous display device including a plurality of self-luminous elements. For example, the display device (DD) may be an organic light-emitting display device including an organic light-emitting element. However, the present invention is not limited thereto, and the display device (DD) may also be implemented as a display device including an inorganic light-emitting element, a display device including light-emitting elements composed of a composite of inorganic and / or organic materials, a display device displaying an image using quantum dots, etc.

[0064] The display device (DD) may be a flat display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, and / or a rollable display device. In addition, the display device (DD) may be applied to a transparent display device, a head-mounted display device, and / or a wearable display device.

[0065] The display panel (100) may include a display area (DA) and a non-display area (NDA). The display area (DA) may be an area in which a sub-pixel (SPX) (or pixel) is provided. The sub-pixel (SPX) may include at least one light-emitting element. For example, the light-emitting element may include a light-emitting layer (for example, an organic light-emitting layer). A portion that is emitted by the light-emitting element may be defined as a light-emitting area. The display device (DD) may display an image in the display area (DA) by driving the sub-pixel (SPX) in response to image data.

[0066] The non-display area (NDA) may be an area provided around the display area (DA) or at the edge of the display area (DA). In one or more embodiments, the non-display area (NDA) may comprehensively refer to an area remaining on the display panel (100) excluding the display area (DA). For example, the non-display area (NDA) may include a wiring area, a pad area, and / or various dummy areas.

[0067] The display area (DA) may include a photosensitive pixel (PSR). The photosensitive pixel (PSR) may be referred to as a photosensor. The photosensitive pixel (PSR) may include a photodetector including a photodetector layer. Within the display area (DA), the photodetector layer of the photodetector may be spaced apart from the light-emitting layer of the light-emitting element.

[0068] A plurality of light-sensing pixels (PSR) may be spaced apart from each other and distributed throughout the entire display area (DA). However, this is not limited thereto, and only a portion of the display area (DA) may be set as a suitable sensing area (e.g., a predetermined sensing area), and light-sensing pixels (PSR) may be provided in the corresponding sensing area. In addition, light-sensing pixels (PSR) may also be provided in at least a portion of the non-display area (NDA).

[0069] A photosensitive pixel (PSR) can detect light emitted from a light source (e.g., a light emitting element of a sub-pixel (SPX)) that is reflected by an external object (e.g., a user's finger). For example, a user's fingerprint can be detected through the photosensitive pixel (PSR). Although the photosensitive pixel (PSR) is described below as being used for fingerprint detection as an example, in various one or more embodiments, the photosensitive pixel (PSR) can detect various biometric information such as an iris, vein, etc.

[0070] The driving circuit (200) may include a panel driving unit (210) and a sensor driving unit (220). The panel driving unit (210) and the sensor driving unit (220) may be implemented as independent integrated circuits (ICs). According to one or more embodiments, the driving circuit (200) may be implemented as a single integrated circuit. In this case, at least a portion of the sensor driving unit (220) may be included in the panel driving unit (210) or may operate in conjunction with the panel driving unit (210).

[0071] The panel driver (210) can scan the sub-pixels (SPX) of the display area (DA) and supply a data signal corresponding to image data (or image) to the sub-pixels (SPX). The display panel (100) can display an image corresponding to the data signal.

[0072] The panel driver (210) can supply a driving signal for light sensing (e.g., fingerprint sensing) to the sub-pixel (SPX). This driving signal can be provided to cause the sub-pixel (SPX) to emit light and act as a light source for the light-sensing pixel (PSR). The panel driver (210) can also supply the driving signal for light sensing and / or other driving signals to the light-sensing pixel (PSR). However, this is not limited thereto, and the driving signals for light sensing can be supplied to the light-sensing pixel (PSR) by the sensor driver (220).

[0073] The sensor driving unit (220) can detect biometric information, such as a user's fingerprint, based on a detection signal received from a photosensitive pixel (PSR). According to one or more embodiments, the sensor driving unit (220) may also supply the driving signals to the photosensitive pixel (PSR) and / or the sub-pixel (SPX).

[0074] The panel driver (210) provides a readout control signal (RCS, see FIG. 2) to the sensor driver (220), and the sensor driver (220) can read out (or sample) a detection signal in conjunction with the panel driver (210) based on the readout control signal (RCS). For example, the sensor driver (220) can read out or sample the detection signal in units of at least one pixel row (or horizontal line) in response to the readout control signal (RCS).

[0075] FIG. 2 is a schematic block diagram illustrating one or more embodiments of the display device (DD) of FIG. 1.

[0076] Referring to FIGS. 1 and 2, the display device (DD) may include a display panel (100) and a driving unit (200).

[0077] The display panel (100) may include signal lines, sub-pixels (SPX), and photo-sensing pixels (PSR). The signal lines may include scan lines (S1 to Sn), data lines (D1 to Dm), readout lines (RX1 to RXo), and a reset line (RSTL) (or reset control line). Here, n, m, and o may each be a natural number.

[0078] The sub-pixel (SPX) may be arranged or positioned in an area (e.g., a pixel area) defined by scan lines (S1 to Sn) and data lines (D1 to Dm). The photo-sensing pixel (PSR) may be arranged or positioned in an area defined by scan lines (S1 to Sn) and readout lines (RX1 to RXo). The sub-pixel (SPX) and the photo-sensing pixel (PSR) may be arranged in a two-dimensional array in the display area (DA) of the display panel (100), but are not limited thereto.

[0079] The sub-pixel (SPX) can be electrically connected to at least one of the scan lines (S1 to Sn) and at least one of the data lines (D1 to Dm). The photo-sensing pixel (PSR) can be electrically connected to one of the scan lines (S1 to Sn), one of the readout lines (RX1 to RXo), and a reset line (RSTL). The connection configuration between the sub-pixel (SPX), the photo-sensing pixel (PSR), and the signal lines will be described later with reference to FIG. 7.

[0080] The display panel (100) may be provided with power voltages (VDD, VSS, VRST, VCOM) required for driving sub-pixels (SPX) and photo-sensing pixels (PSR). The power voltages (VDD, VSS, VRST, VCOM) may be supplied from a power supply unit. The power supply unit may be implemented as a power management integrated circuit (PMIC).

[0081] The driving circuit (200) may include a scan driving unit (211), a data driving unit (212), a control unit (213), a reset circuit (221), and a readout circuit (222). For example, the scan driving unit (211), the data driving unit (212), and the control unit (213) may be included in the panel driving unit (210), and the reset circuit (221) and the readout circuit (222) may be included in the sensor driving unit (220), but are not limited thereto. According to one or more embodiments, the reset circuit (221) may also be included in the panel driving unit (210).

[0082] The scan driver (211) can be electrically connected to the sub-pixel (SPX) and the light-sensing pixel (PSR) through the scan lines (S1 to Sn). The scan driver (211) can generate scan signals based on a scan control signal (SCS) and supply the scan signals to the scan lines (S1 to Sn). The scan control signal (SCS) includes a start signal, a clock signal, etc., and can be provided to the scan driver (211) from the control unit (213). For example, the scan driver (211) can be implemented as a shift register that sequentially shifts a pulse-type start signal using clock signals to generate and output the scan lines (S1 to Sn). The scan driver (211) can selectively drive the sub-pixel (SPX) and the light-sensing pixel (PSR) while scanning the display panel (100).

[0083] The scan driver (211) may be formed together with the sub-pixel (SPX) of the display panel (100), but is not limited thereto. According to one or more embodiments, the scan driver (211) may also be implemented as an integrated circuit (IC).

[0084] The sub-pixel (SPX) selectively driven by the scan driver (211) can emit light with a brightness corresponding to a data signal provided to a corresponding data line among the data lines (D1 to Dm). The photo-sensing pixel (PSR) selectively driven by the scan driver (211) can output an electrical signal (e.g., a detection signal) corresponding to the detected light to the corresponding readout line. For example, the sub-pixel (SPX) selectively driven through the ith scan line (Si) can emit light with a brightness corresponding to the data signal supplied to the jth data line (Dj) (where i and j are natural numbers). For example, the photo-sensing pixel (PSR) selectively driven through the ith scan line (Si) can output an electrical signal corresponding to the detected light to the kth readout line (RXk) (where k is a natural number).

[0085] The data driving unit (212) can generate a data signal (or data voltage) based on image data (DATA2) and a data control signal (DCS) provided from the control unit (213), and supply the data signal to the display panel (100) (or sub-pixel (SPX)) through the data lines (D1 to Dm). The data control signal (DCS) is a signal that controls the operation of the data driving unit (212) and can include a horizontal start signal, a data clock signal, etc. For example, the data driving unit (212) can include a shift register that generates a sampling signal by shifting the horizontal start signal in synchronization with the data clock signal, a latch that latches image data (DATA2) in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., data in digital form) into a data signal in analog form, and a buffer (or amplifier) ​​that outputs the data signal to a corresponding data line (e.g., the j-th data line (Dj)).

[0086] The control unit (213) may receive input image data (DATA1) and a control signal (CS) from an external device (e.g., a graphics processor, an application processor, a first processor), generate a scan control signal (SCS) and a data control signal (DCS) based on the control signal (CS), and convert the input image data (DATA1) to generate image data (DATA2). The control signal (CS) may include a vertical synchronization signal, a horizontal synchronization signal, a reference clock signal, etc. The vertical synchronization signal may indicate the start of frame data (i.e., data corresponding to a frame section in which one frame image is displayed), and the horizontal synchronization signal may indicate the start of a data row (i.e., one data row among a plurality of data rows included in the frame data). The control unit (213) may convert the input image data (DATA1) into image data (DATA2) having a format that matches the pixel arrangement in the display panel (100).

[0087] Additionally, the control unit (213) can generate a reset control signal and a readout control signal (RCS) based on the control signal (CS).

[0088] The reset circuit (221) can be commonly connected to all light-sensing pixels (PSR) provided in the display panel (100) through one reset line (RSTL). The reset circuit (221) can simultaneously supply a reset signal (RST) to all light-sensing pixels (PSR) in response to a reset control signal. Since the reset signal (RST) is simultaneously supplied to all light-sensing pixels (PSR), the reset signal (RST) can be referred to as a global reset signal.

[0089] The readout circuit (222) receives a detection signal from a photodetector pixel (PSR) through readout lines (RX to RXo) and can perform signal processing on the detection signal.

[0090] For example, the readout circuit (222) can perform a correlated double sampling (CDS) operation to remove noise from a detection signal provided from a photosensitive pixel (PSR). The timing of the correlated double sampling operation of the readout circuit (222) can be determined by a readout control signal (RCS). The readout circuit (222) can convert an analog detection signal into a digital signal (or digital value). A configuration for the correlated double sampling and analog-to-digital conversion is provided for each of the readout lines (RX1 to RXo), and the readout circuit (222) can process the detection signals provided from the readout lines (RX1 to RXo) in parallel.

[0091] The processed detection signals, i.e., the read-out detection signals, are transmitted to an external device (e.g., an application processor) as a single sensing data (or biometric information), and biometric authentication (e.g., fingerprint authentication, etc.) can be performed based on the sensing data. According to one or more embodiments, the read-out detection signals are supplied to the control unit (213), and the control unit (213) can also perform biometric authentication.

[0092] FIG. 3 is a schematic plan view showing a display device (DD) according to one or more embodiments, and FIG. 4 is a schematic enlarged view showing a portion EA1 of FIG. 3.

[0093] Referring to FIGS. 3 and 4, the display device (DD) (or display panel (100)) may include a substrate (SUB) in which a display area (DA) and a non-display area (NDA) are defined.

[0094] The display device (DD) may be provided in various shapes, for example, but is not limited to, a rectangular plate having two pairs of sides that are parallel to each other.

[0095] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate.

[0096] The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and / or a crystalline glass substrate.

[0097] The flexible substrate may be one of a film substrate including a polymeric organic material and / or a plastic substrate. For example, the flexible substrate may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and / or cellulose acetate propionate.

[0098] The display area (DA) may include a first area (DA) and a second area (DA2). For example, the display area (DA) may include a second area (DA2) located in the center and first areas (DA1) positioned on both sides of the second area (DA2). The first area (DA1) may be an area located in the outer direction rather than the center direction of the display panel (100) with the second area (DA2) as the center, but is not limited thereto.

[0099] Sub-pixels (see “SPX” in FIG. 1) and light-sensing pixels (see “PSR” in FIG. 1) may be arranged in each of the first area (DA1) and the second area (DA2).

[0100] The display device (DD) can display an image in the first area (DA1) and the second area (DA2) and detect a user's fingerprint, etc. by selectively driving a sub-pixel (SPX) and a light-sensing pixel (PSR) in response to input image data.

[0101] The non-display area (NDA) may include a fan-out area (FTA) and a pad area (PDA).

[0102] The pad area (PDA) may be located closest to the edge of the non-display area (NDA).

[0103] A fan-out area (FTA) may be positioned adjacent to a display panel (DA) in a non-display area (NDA). For example, the fan-out area (FTA) may be a region of the non-display area (NDA) located between a pad area (PDA) and a display area (DA). According to one or more embodiments, the non-display area (NDA) may include an anti-static circuit region in which an anti-static circuit is positioned to prevent static electricity generation and is electrically connected to signal lines located in the display area (DA).

[0104] A wiring part (LP) can be located in the fan-out area (FTA), and a pad part (PDP) can be located in the pad area (PDA).

[0105] The wiring unit (LP) can be electrically connected to the sub-pixels (SPX) and / or the light-sensing pixels (PSR) and transmit a suitable signal (e.g., a predetermined signal) applied from the driver unit (see “200” in FIG. 1) to the signal lines. The wiring unit (LP) can include fan-out lines that electrically connect the driver unit (200) and the sub-pixels (SPX) and / or the light-sensing pixels (PSR) in the fan-out area (FTA).

[0106] In one or more embodiments, the wiring portion (LP) may be located in a central portion of a fan-out area (FTA) corresponding to a second area (DA2) of the display area (DA). The wiring portion (LP) may include a first wiring portion (LP1) and a second wiring portion (LP2). The first wiring portion (LP1) may be electrically connected to data lines (D5, D6, D7, and Dk) located in the second area (DA2) of the display area (DA) through a first contact hole (CH1). The second wiring portion (LP2) may be electrically connected to data lines (D1, D2, D3, and D4) located in the first area (DA1) of the display area (DA) through a second contact hole (CH2) and bridge lines (BRL).

[0107] Signal lines to which various signals are applied may be arranged in the first area (DA1) and the second area (DA2). For example, data lines (D1 to Dk) to which data signals for controlling brightness in each sub-pixel (SPX) are applied may be arranged in the first area (DA1) and the second area (DA2). In addition to the data lines (D1 to Dk), various signal lines such as power lines and scan lines may be arranged in the first area (DA1) and the second area (DA2).

[0108] The data lines (D1 to Dk) may extend along the second direction (DR2) in the display area (DA). In FIGS. 3 and 4 , the first to fourth data lines (D1 to D4) may be positioned in the first area (DA1) adjacent to one side (e.g., the left side) of the second area (DA2). In addition, four data lines may be positioned in the first area (DA1) adjacent to the other side (e.g., the right side) of the second area (DA2). For convenience of explanation, four data lines are illustrated as being positioned in the first area (DA1), but the present invention is not limited thereto.

[0109] Each of the fifth to kth data lines (D5 to Dk) located in the second area (DA2) may be electrically connected to the first wiring (LP1). For example, in the second area (DA2), each of the fifth data line (D5), the sixth data line (D6), and the seventh data line (D7) may be electrically connected to the corresponding first wiring (LP1) through the first contact hole (CH1).

[0110] The first to fourth data lines (D1 to D4) located in the first area (DA1) may be electrically connected to a bridge line (BRL). The bridge line (BRL) may be arranged to pass through the display area (DA) bypassing a portion of the display area (DA) adjacent to the non-display area (NDA).

[0111] A first data line (D1) may be electrically connected to a first bridge line (BRL1), a second data line (D2) may be electrically connected to a second bridge line (BRL2), a third data line (D3) may be electrically connected to a third bridge line (BRL3), and a fourth data line (D4) may be electrically connected to a fourth bridge line (BRL4).

[0112] Each of the first to fourth bridge lines (BRL1 to BRL4) may extend from the second area (DA2) to the first area (DA1). For example, each of the first to fourth bridge lines (BRL1 to BRL4) may be routed from the central portion (or inner side) of the display area (DA) to the edge (or outer side) of the display area (DA). Each of the first to fourth bridge lines (BRL1 to BRL4) may be electrically connected to the first to fourth data lines (D1 to D4) through a via hole (VIH) and may be electrically connected to a corresponding second wiring (LP2) through a second contact hole (CH2).

[0113] In Fig. 4, the second bridge line (BRL2) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the second data line (D2) through the via hole (VIH). The third bridge line (BRL3) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the third data line (D3) through the via hole (VIH). The fourth bridge line (BRL4) may have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2), and the other end electrically connected to the fourth data line (D4) through the via hole (VIH).

[0114] The second to fourth bridge lines (BRL2 to BRL4) may each have one end electrically connected to the second wiring (LP2) through the second contact hole (CH2) between the second display area (DA2) and the non-display area (NDA), and the other end electrically connected to the second to fourth data lines (D2 to D4) through the via hole (VIH) in the first area (DA1). That is, the second to fourth bridge lines (BRL2 to BRL4) may each receive an input signal (e.g., a data signal) from the second wiring (LP2) and transmit the same to the second to fourth data lines (D2 to D4), respectively. The second to fourth bridge lines (BRL2 to BRL4) may be arranged on the same layer as the second wiring (LP2) or may be arranged on a different layer.

[0115] The fifth to seventh data lines (D5 to D7) of FIG. 4 may be arranged in the same layer, or some may be arranged in different layers. For example, the fifth to seventh data lines (D5 to D7) may be arranged alternately in different layers.

[0116] As described above, by not directly connecting the data line to the wiring unit (LP) in a part of the display area (DA) (for example, the first area (DA1)), but bypassing a part of the display area (DA) and transmitting the input signal of the wiring unit (LP) to the data line through a bridge line (BRL), the area of ​​the non-display area (NDA) outside the display area (DA) can be effectively reduced.

[0117] FIG. 5 is a schematic drawing showing an example of the arrangement of pixel circuits and sensor circuits in a display area of ​​a display panel included in the display device of FIG. 2, and FIG. 6 is a schematic drawing showing an example of the display area of ​​a display panel included in the display device of FIG. 2.

[0118] Referring to FIGS. 1 to 6, sub-pixels (SPX1 to SPX4) and a plurality of light detection sensors (PSR1 to PSR4) may be arranged in a display area (DA) of a display panel (100).

[0119] The display area (DA) can be divided into pixel rows (R1 to R4). Each of the pixel rows (R1 to R4) extends in a first direction (DR1) and can be arranged along a second direction (DR2). Each of the pixel rows (R1 to R4) can include sub-pixels (SPX1 to SPX4). Each of the sub-pixels (SPX1 to SPX4) can include one of the pixel circuits (PXC11 to PXC48) and one of the light-emitting elements (LED1 to LED4).

[0120] In one or more embodiments, the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) can emit light of a first color, light of a second color, and light of a third color, respectively. The light of the first color, light of the second color, and light of the third color can be lights of different colors. Each of the light of the first color, light of the second color, and light of the third color can be one of red light, green light, and / or blue light. A first light-emitting element (LED1) emitting light of a first color may be positioned in a first sub-pixel (SPX1), a second light-emitting element (LED2) emitting light of a second color may be positioned in a second sub-pixel (SPX2), a third light-emitting element (LED3) emitting light of a third color may be positioned in a third sub-pixel (SPX3), and a fourth light-emitting element (LED4) emitting light of a second color may be positioned in a fourth sub-pixel (SPX4). The second light-emitting element (LED2) and the fourth light-emitting element (LED4) may emit light of the same color.

[0121] In Fig. 6, each of the light-emitting elements (LED1 to LED4) can be understood as a light-emitting region corresponding to a light-emitting layer. However, this is for convenience of explanation, and the color of the light emitted by each of the light-emitting elements (LED1 to LED4), the position, area, shape, etc. of each of the light-emitting elements (LED1 to LED4) are not limited thereto.

[0122] In one or more embodiments, each of the odd-numbered pixel rows including the first pixel row (R1) (or the first horizontal line) and the third pixel row (R3) (or the third horizontal line) may have sub-pixels (SPX1 to SPX4) arranged in the order of a first sub-pixel (SPX1) emitting red light, a second sub-pixel (SPX2) emitting green light, a third sub-pixel (SPX3) emitting blue light, and a fourth sub-pixel (SPX4) emitting green light, with respect to the first direction (DR1).

[0123] In each of the even-numbered pixel rows including the second pixel row (R2) (or second horizontal line) and the fourth pixel row (R4) (or fourth horizontal line), the sub-pixels (SPX1 to SPX4) may be arranged in the order of the third sub-pixel (SPX3), the fourth sub-pixel (SPX4), the first sub-pixel (SPX1), and the second sub-pixel (SPX2) with respect to the first direction (DR1).

[0124] In one or more embodiments, the first sub-pixel (SPX1) and the second sub-pixel (SPX2) may constitute a first sub-pixel unit (SPU1), and the third sub-pixel (SPX3) and the fourth sub-pixel (SPX4) may constitute a second sub-pixel unit (SPU2). In odd-numbered pixel rows (R1, R3), the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) may be arranged alternately, and in even-numbered pixel rows (R2, R4), the second sub-pixel unit (SPU2) and the first sub-pixel unit (SPU1) may be arranged alternately, as opposed to the odd-numbered pixel rows (R1, R3).

[0125] It can be understood that the first and second adjacent sub-pixel units (SPU1, SPU2) constitute one pixel unit (PU). For example, FIG. 6 shows a pixel unit (PU) of each of the first pixel row (R1) and the second pixel row (R2). However, the present invention is not limited thereto, and the arrangement of the sub-pixels (SPX1 to SPX4) may be variously changed.

[0126] In the first pixel row (R1), pixel circuits (PXC11 to PXC18) corresponding to the sub-pixels (SPX1 to SPX4) of the first pixel row (R1) may be arranged along the first direction (DR1). In the second pixel row (R2), pixel circuits (PXC21 to PXC28) corresponding to the sub-pixels (SPX1 to SPX4) of the second pixel row (R2) may be arranged along the first direction (DR1). In the third pixel row (R3), pixel circuits (PXC31 to PXC38) corresponding to the sub-pixels (SPX1 to SPX4) of the third pixel row (R3) may be arranged along the first direction (DR1). In the fourth pixel row (R4), pixel circuits (PXC41 to PXC48) corresponding to each of the sub-pixels (SPX1 to SPX4) of the fourth pixel row (R4) can be arranged along the first direction (DR1).

[0127] In FIG. 5, the first, second, third, and fourth pixel circuits (PXC11, PXC12, PXC13, PXC14) of the first pixel row (R1) may be included in one pixel unit (PU), and the fifth, sixth, seventh, and eighth pixel circuits (PXC15, PXC16, PXC17, PXC18) of the first pixel row (R1) may be included in another unit (PU).

[0128] Similarly, the first to fourth pixel circuits (PXC21 to PXC24) of the second pixel row (R2), the fifth to eighth pixel circuits (PXC25 to PXC28) of the second pixel row (R2), the first to fourth pixel circuits (PXC31 to PXC34) of the third pixel row (R3), the fifth to eighth pixel circuits (PXC35 to PXC38) of the third pixel row (R3), the first to fourth pixel circuits (PXC41 to PXC44) of the fourth pixel row (R4), and the fifth to eighth pixel circuits (PXC45 to PXC48) of the fourth pixel row (R4) may also be included in different pixel units (PUs).

[0129] In one or more embodiments, each of the pixel rows (R1 to R4) may include light-receiving elements (LRD1 to LRD4). In FIG. 6, the light-receiving elements (LRD1 to LRD4) may be understood as light-receiving areas corresponding to light-receiving layers, respectively. However, this is for convenience of explanation, and the positions, areas, shapes, etc. of the light-receiving elements (LRD1 to LRD4) may be variously changed.

[0130] The light-receiving elements (LRD1, LRD2) of the first pixel row (R1) may overlap with at least some of the pixel circuits (PXC11 to PXC14) of the first pixel row (R1) and the sensor circuits (SC11, SC12) of the first pixel row (R1), respectively. The light-receiving elements (LRD3, LRD4) of the second pixel row (R2) may overlap with at least some of the pixel circuits (PXC21 to PXC24) of the second pixel row (R2) and the sensor circuits (SC21, SC22) of the second pixel row (R2), respectively.

[0131] In one or more embodiments, the first light-receiving element (LRD1) may overlap at least a portion of the first sensor circuit (SC11) of the first pixel row (R1), and the third light-receiving element (LRD3) may overlap at least a portion of the first sensor circuit (SC21) of the second pixel row (R2).

[0132] Additionally, the second light-receiving element (LRD2) may overlap at least a portion of the second sensor circuit (SC12) of the first pixel row (R1), and the fourth light-receiving element (LRD4) may overlap at least a portion of the second sensor circuit (SC22) of the second pixel row (R2).

[0133] The light-receiving elements (LRD1 to LRD4) may be formed within the display area (DA) in the same arrangement as shown in FIG. 6, but are not limited thereto.

[0134] In one or more embodiments, the sensor circuits (SC11 to SC44) may be electrically connected to corresponding photodetectors. The first sensor circuit (SC11) of the first pixel row (R1) may be electrically connected to the first photodetector (LRD1) to form a first photodetector pixel (PSR1). That is, the first sensor circuit (SC11) and the first photodetector (LRD1) may form the first photodetector pixel (PSR1). The second sensor circuit (SC12) of the first pixel row (R1) may be electrically connected to the second photodetector (LRD2) to form a second photodetector pixel (PSR2). That is, the second sensor circuit (SC12) and the second photodetector (LRD2) may form the second photodetector pixel (PSR2). The first sensor circuit (SC21) of the second pixel row (R2) may be electrically connected to the third light-receiving element (LRD3) to form a third light-sensing pixel (PSR3). That is, the first sensor circuit (SC21) and the third light-receiving element (LRD3) may form the third light-sensing pixel (PSR3). The second sensor circuit (SC22) of the second pixel row (R2) may be electrically connected to the fourth light-receiving element (LRD4) to form a fourth light-sensing pixel (PSR4). That is, the second sensor circuit (SC22) and the fourth light-receiving element (LRD4) may form the fourth light-sensing pixel (PSR4). However, the present invention is not limited thereto, and according to one or more embodiments, only some of the sensor circuits (SC11 to SC44) may be provided, and the some may be connected to a plurality of light-receiving elements.

[0135] The first sensor circuit (SC11) of the first pixel row (R1) may be arranged between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2) included in the pixel unit (PU). For example, the first and second pixel circuits (PXC11, PXC12) of the first pixel row (R1) may be included in the first sub-pixel unit (SPU1), and the third and fourth pixel circuits (PXC13, PXC14) of the first pixel row (R1) may be included in the second sub-pixel unit (SPU2). Accordingly, at least two pixel circuits (for example, PXC13, PXC14) may be arranged between the first sensor circuit (SC11) and the second sensor circuit (SC12) that are adjacent to each other in the first pixel row (R1).

[0136] The second sensor circuit (SC12) of the first pixel row (R1), the first sensor circuit (SC21) of the second pixel row (R2), and the second sensor circuit (SC22) of the second pixel row (R2) may be arranged between the first sub-pixel unit (SPU1) and the second sub-pixel unit (SPU2), similarly to the first sensor circuit (SC11) of the first pixel row (R1).

[0137] Fig. 7 is a schematic circuit diagram showing an example of a sub-pixel (SPX) and a light-sensing pixel (PSR) included in the display area of ​​Fig. 1. For convenience of explanation, Fig. 7 illustrates a sub-pixel (SPX) located on the i-th horizontal line (or i-th pixel row) and connected to the j-th data line (Dj).

[0138] Referring to FIGS. 1 and 7, the sub-pixel (SPX) and the light-sensing pixel (PSR) can be arranged in the i-th horizontal line.

[0139] A sub-pixel (SPX) may include a light-emitting element (LED) and a pixel circuit (PXC). In one or more embodiments, the pixel circuit (PXC) may include first, second, third, fourth, fifth, sixth, seventh, and eighth transistors (T1, T2, T3, T4, T5, T6, T7, and T8), a storage capacitor (Cst), and a boost capacitor (Cbst).

[0140] A first transistor (T1) (or driving transistor) may be electrically connected between a first power wire (PL1) and a first electrode (or anode electrode) of a light-emitting element (LED). The first transistor (T1) may include a gate electrode electrically connected to a first node (N1). The first transistor (T1) may control an amount of current (or driving current) flowing from the first power wire (PL1) to the electrode (EP) (or power wire) via the light-emitting element (LED) based on a voltage of the first node (N1). A first power voltage (VDD) is supplied to the first power wire (PL1), a second power voltage (VSS) is supplied to the electrode (EP), and the first power voltage (VDD) may be set to a voltage higher than the second power voltage (VSS).

[0141] The second transistor (T2) may be electrically connected between the j-th data line (Dj) and the second node (N2). The gate electrode of the second transistor (T2) may be connected to the 1i-th scan line (S1i) (or the first scan line). The second transistor (T2) may be turned on when the first scan signal (GW[i]) (e.g., the first scan signal having a low level) is supplied to the 1i-th scan line (S1i), thereby electrically connecting the j-th data line (Dj) and the second node (N2). When each of the first transistor (T1) and the third transistor (T3) is turned on, the second transistor (T2) may transmit the data signal of the j-th data line (Dj) to the second node (N2) in response to the first scan signal (GW[i]).

[0142] A third transistor (T3) may be electrically connected between a first node (N1) and a third node (N3). A gate electrode of the third transistor (T3) may be electrically connected to a 4i scan line (S4i) (or a third scan line). The third transistor (T3) may be turned on when a fourth scan signal (GC[i]) is supplied to the 4i scan line (S4i).

[0143] The fourth transistor (T4) may be electrically connected between the first node (N1) and the second power line (PL2). The gate electrode of the fourth transistor (T4) may be electrically connected to the secondi scan line (S2i) (or the second scan line). A first initialization power voltage (Vint1) may be provided to the second power line (PL2). The fourth transistor (T4) may be turned on by the second scan signal (GI[i]) supplied to the secondi scan line (S2i). When the fourth transistor (T4) is turned on, the first initialization power voltage (Vint1) may be supplied to the first node (N1) (i.e., the gate electrode of the first transistor (T1)).

[0144] The fifth transistor (T5) may be electrically connected between the first power line (PL1) and the second node (N2). A gate electrode of the fifth transistor (T5) may be electrically connected to the ith light emission control line (Ei). A sixth transistor (T6) may be electrically connected between the third node (N3) and a light emitting element (LED) (or a fourth node (N4)). A gate electrode of the sixth transistor (T6) may be electrically connected to the ith light emission control line (Ei). The fifth transistor (T5) and the sixth transistor (T6) may be turned off when a light emission control signal (EM[i]) (for example, a high-level light emission control signal (EM[i])) is supplied to the ith light emission control line (Ei), and may be turned on when a low-level light emission control signal (EM[i]) is supplied to the ith light emission control line (Ei).

[0145] The seventh transistor (T7) may be electrically connected between a first electrode (i.e., a fourth node (N4)) of a light emitting element (LED) and a third power line (PL3). A gate electrode of the seventh transistor (T7) may be electrically connected to a third i scan line (S3i). A second initialization power voltage (Vint2) may be supplied to the third power line (PL3). According to one or more embodiments, the second initialization power voltage (Vint2) may be different from the first initialization power voltage (Vint1). The seventh transistor (T7) may be turned on by a third scan signal (GB[i]) supplied to the third i scan line (S3i) to supply the second initialization power voltage (Vint2) to the first electrode of the light emitting element (LED).

[0146] The eighth transistor (T8) may be electrically connected between the second node (N2) and the fourth power line (PL4). The gate electrode of the eighth transistor (T8) may be electrically connected to the third i scan line (S3i). A bias voltage (VOBS) may be supplied to the fourth power line (PL4). The eighth transistor (T8) may be turned on by the third scan signal (GB[i]) supplied to the third i scan line (S3i) to supply the bias voltage (VOBS) to the second node (N2).

[0147] A storage capacitor (Cst) may be connected or formed between the first power wire (PL1) and the first node (N1).

[0148] A boost capacitor (Cbst) (or capacitor) may be connected or formed between the gate electrode of the second transistor (T2) and the gate electrode of the first transistor (T1) (e.g., the first node (N1)).

[0149] A photosensitive pixel (PSR) may include a sensor circuit (SC) and a light receiving element (LRD). The sensor circuit (SC) may include ninth, tenth, and eleventh transistors (T9, T10, T11).

[0150] The ninth and eleventh transistors (T9, T11) can be connected in series between the sixth power wiring (PL6) and the kth readout line (RXk) (where k is a natural number).

[0151] The ninth transistor (T9) (or the first sensor transistor) may be electrically connected between the sixth power line (PL6) and the eleventh transistor (T11). A gate electrode of the ninth transistor (T9) may be electrically connected to a fifth node (N5) (or sensor node). The ninth transistor (T9) may control a current flowing from the sixth power line (PL6) to the kth readout line (RXk) through the eleventh transistor (T11) in response to a voltage of the fifth node (N5). A common voltage (VCOM) may be supplied to the sixth power line (PL6).

[0152] According to one or more embodiments, the sixth power wire (PL6) is electrically connected to or formed integrally with the third power wire (PL3), and the common voltage (VCOM) applied to the sixth power wire (PL6) may be equal to, but not limited to, the second initialization power voltage (Vint2). According to one or more other embodiments, the sixth power wire (PL6) is electrically connected to or formed integrally with the second power wire (PL2), and the common voltage (VCOM) applied to the sixth power wire (PL6) may be equal to the first initialization power voltage (Vint1).

[0153] An eleventh transistor (T11) ("second sensor transistor" or "switching transistor") may be electrically connected between the ninth transistor (T9) and the k-th readout line (RXk). A gate electrode of the eleventh transistor (T11) may be connected to the 1i scan line (S1i). That is, the gate electrode of the eleventh transistor (T11) and the gate electrode of the second transistor (T2) may share the 1i scan line (S1i).

[0154] The tenth transistor (T10) (or the third sensor transistor) may be electrically connected between the fifth power line (PL5) (or the reference power line) and the fifth node (N5). The gate electrode of the tenth transistor (T10) may be electrically connected to the reset line (RSTL). A reset voltage (VRST) may be supplied to the fifth power line (PL5). The reset voltage (VRST) may be a DC voltage having a constant level. For example, the reset voltage (VRST) may be about -7 V, but is not limited thereto.

[0155] At least one light-receiving element (LRD) can be electrically connected between the fifth node (N5) and the electrode (EP) to which the second power supply voltage (VSS) is applied.

[0156] A light-receiving device (LRD) can generate a charge (or current) based on incident light. That is, the light-receiving device (LRD) can perform the function of photoelectric conversion. For example, the light-receiving device (LRD) can be implemented as a photodiode.

[0157] When the tenth transistor (T10) is turned on by a reset signal (RST) supplied to the reset line (RSTL), a reset voltage (VRST) can be supplied to the fifth node (N5). For example, the voltage of the fifth node (N5) can be reset by the reset voltage (VRST). After the reset voltage (VRST) is applied to the fifth node (N5), the light-receiving element (LRD) can perform a photoelectric conversion function.

[0158] The voltage of the fifth node (N5) may change depending on the operation of the light-receiving element (LRD). The voltage of the fifth node (N5) (or the charge or current generated in the light-receiving element (LRD)) may change depending on the intensity of light incident on the light-receiving element (LRD) and the time for which the light is incident (or the time for which the light-receiving element (LRD) is exposed to light).

[0159] When the 11th transistor (T11) is turned on by the first scan signal (GW[i]) supplied to the first scan line (S1i), a detection value (current and / or voltage) generated based on the voltage of the fifth node (N5) can flow to the kth readout line (RXk).

[0160] In one or more embodiments, each of the pixel circuit (PXC) and the sensor circuit (SC) may include a P-type transistor and an N-type transistor. The third transistor (T3), the fourth transistor (T4), and the tenth transistor (T10) may be formed as oxide semiconductor transistors including an oxide semiconductor (or a second type semiconductor). For example, the third transistor (T3), the fourth transistor (T4), and the tenth transistor (T10) may be N-type oxide semiconductor transistors and may include an oxide semiconductor layer as an active layer, but are not limited thereto.

[0161] The remaining transistors (e.g., the first, second, fifth, sixth, seventh, eighth, ninth, and eleventh transistors (T1, T2, T5, T6, T7, T8, T9, T11)) are formed as polysilicon transistors including silicon semiconductors (or first type semiconductors) and may include a polysilicon semiconductor layer as an active layer. For example, the active layer may be formed through a low-temperature polysilicon process (e.g., a low-temperature poly-silicon (LTPS) process).

[0162] Hereinafter, with reference to FIGS. 8 and 9, the stacked structure (or cross-sectional structure) of a sub-pixel (SPX) including a light-emitting element (LED) and a photodetector pixel (PSR) including a light-receiving element (LRD) will be described.

[0163] FIG. 8 is a schematic cross-sectional view showing an area of ​​a display device (DD) according to one or more embodiments, and FIG. 9 is a schematic cross-sectional view showing a reflection path of light in the display device (DD) of FIG. 8.

[0164] In FIGS. 8 and 9, a cross-section of a portion corresponding to the sixth transistor (T6) among the first to eighth transistors (T1 to T8) illustrated in FIG. 7 and a cross-section of a portion corresponding to the tenth transistor (T10) among the ninth to eleventh transistors (T9 to T11) illustrated are illustrated.

[0165] Referring to FIGS. 1 to 9, the display device (DD) may include a sub-pixel (SPX) and a light-sensing pixel (PSR) provided in one area of ​​a substrate (SUB).

[0166] A pixel circuit layer (PCL) of a sub-pixel (SPX) and a pixel circuit layer (PCL) of a light-sensing pixel (PSR) may be disposed on a substrate (SUB). At least one insulating layer may be disposed on the pixel circuit layer (PCL). The insulating layer may include a first insulating layer (INS1), a second insulating layer (INS2), a third insulating layer (INS3), a fourth insulating layer (INS4), a fifth insulating layer (INS5), a sixth insulating layer (INS6), a seventh insulating layer (INS7), an eighth insulating layer (INS8), and a ninth insulating layer (INS9) sequentially laminated on the substrate (SUB) along a third direction (DR3).

[0167] A first insulating layer (INS1) (or buffer layer) may be disposed on the substrate (SUB). The first insulating layer (INS1) may prevent impurities from diffusing into the sixth transistor (T6) and the tenth transistor (T10). The first insulating layer (INS1) may be an inorganic film including an inorganic material (or substance). The first insulating layer (INS1) may be silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), and / or aluminum oxide (AlO x) may be included. The first insulating layer (INS1) may be provided as a single layer, but may also be provided as a multi-layer of at least two layers or more. The first insulating layer (INS1) may be omitted depending on the material of the substrate (SUB) and process conditions.

[0168] The second insulating layer (INS2) (or first gate insulating layer) may be disposed on the first insulating layer (INS1). The second insulating layer (INS2) may include the same material as the first insulating layer (INS1) or may include a suitable (or selected) material from among the materials exemplified as constituent materials of the first insulating layer (INS1). For example, the second insulating layer (INS2) may be an inorganic film including an inorganic material.

[0169] The third insulating layer (INS3) (or second gate insulating layer) may be disposed on the second insulating layer (INS2). The third insulating layer (INS3) may include the same material as the first insulating layer (INS1) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first insulating layer (INS1).

[0170] The fourth insulating layer (INS4) (or the first interlayer insulating layer) may be disposed on the third insulating layer (INS3). The fourth insulating layer (INS4) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0171] The fifth insulating layer (INS5) (or third gate insulating layer) may be disposed on the fourth insulating layer (INS4). The fifth insulating layer (INS5) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0172] The sixth insulating layer (INS6) (or second interlayer insulating layer) may be disposed on the fifth insulating layer (INS5). The sixth insulating layer (INS6) may be an inorganic film including an inorganic material or an organic film including an organic material.

[0173] The seventh insulating layer (INS7) (or the first via layer) may be disposed on the sixth insulating layer (INS6). The seventh insulating layer (INS7) may be an inorganic film including an inorganic material or an organic film including an organic material. The inorganic film may be, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and / or aluminum oxide (AlO x ) may be included. The organic film may include, for example, polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylene sulfides resin, and / or benzocyclobutene resin. In one or more embodiments, the seventh insulating layer (INS7) may be an organic film.

[0174] The eighth insulating layer (INS8) (or the second via layer) may be disposed on the seventh insulating layer (INS7). The eighth insulating layer (INS8) may include the same material as the seventh insulating layer (INS7) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the seventh insulating layer (INS7). For example, the eighth insulating layer (INS8) may be an organic film including an organic material.

[0175] The ninth insulating layer (INS9) (or third via layer) may be disposed on the eighth insulating layer (INS8). The ninth insulating layer (INS9) may include the same material as the seventh insulating layer (INS7) or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the seventh insulating layer (INS7). For example, the ninth insulating layer (INS9) may be an organic film including an organic material.

[0176] The pixel circuit layer (PCL) may include at least one conductive layer disposed between the above-described insulating layers. For example, the conductive layers may include a first conductive layer (CL1) disposed between a second insulating layer (INS2) and a third insulating layer (INS3), a second conductive layer (CL2) disposed between a third insulating layer (INS3) and a fourth insulating layer (INS4), a third conductive layer (CL3) disposed between a fifth insulating layer (INS5) and a sixth insulating layer (INS6), a fourth conductive layer (CL4) disposed between a sixth insulating layer (INS6) and a seventh insulating layer (INS7), a fifth conductive layer (CL5) disposed between a seventh insulating layer (INS7) and an eighth insulating layer (INS8), and a sixth conductive layer (CL6) disposed between an eighth insulating layer (INS8) and a ninth insulating layer (INS9). The insulating layers and conductive layers are not limited to the embodiments described above, and according to one or more embodiments, other insulating layers and other conductive layers may be disposed within the pixel circuit layer (PCL) in addition to the insulating layers and the conductive layers.

[0177] In one or more embodiments, a first semiconductor layer may be disposed between a first insulating layer (INS1) and a second insulating layer (INS2). The first semiconductor layer may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. The first semiconductor layer may include, but is not limited to, low-temperature polysilicon. The first semiconductor layer may include a first semiconductor region having high conductivity and a second semiconductor region having low conductivity. The first semiconductor region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region doped with a P-type dopant, and an N-type transistor may include a doped region doped with an N-type dopant. The second semiconductor region may be an undoped region or a region doped at a lower concentration than the first semiconductor region. The conductivity of the first semiconductor region may be greater than the conductivity of the second semiconductor region. The first semiconductor region may substantially function as an electrode or a signal wiring. The second semiconductor region may substantially correspond to the active pattern (or channel region) of the transistor. A portion of the first semiconductor layer may be the active pattern region of the transistor, another portion of the first semiconductor layer may be the source / drain region (or source / drain electrode) of the transistor, and another portion of the first semiconductor layer may be, but is not limited to, a connection electrode or a connection signal wiring.

[0178] In one or more embodiments, a second semiconductor layer may be disposed between the fourth insulating layer (INS4) and the fifth insulating layer (INS5). The second semiconductor layer may include an oxide semiconductor. The oxide semiconductor may include a plurality of regions that are distinguished depending on whether a metal oxide is reduced. A region in which the metal oxide is reduced (hereinafter referred to as a “reduced region”) may have greater conductivity than a region in which the metal oxide is not reduced (hereinafter referred to as a “non-reduced region”). The reduced region may be substantially utilized as a source / drain region or a signal wiring of the transistor. The non-reduced region may substantially correspond to an active pattern (or channel region) of the transistor. A portion of the second semiconductor layer may be an active pattern of the transistor, another portion may be a source / drain region (or a source / drain electrode) of the transistor, and another portion may be a signal transmission region, but is not limited thereto.

[0179] A sixth transistor (T6) and a tenth transistor (T10) may be arranged in the pixel circuit layer (PCL).

[0180] The sixth transistor (T6) may include a gate electrode (GE6, hereinafter referred to as “sixth gate electrode”), a first semiconductor pattern (SCP1), a first terminal (TE1), and a second terminal (TE2). The tenth transistor (T10) may include a gate electrode (GE10, hereinafter referred to as “tenth gate electrode”), a fourth semiconductor pattern (SCP4), a third terminal (TE3), and a fourth terminal (TE4).

[0181] A first semiconductor pattern (SCP1) is disposed on a first insulating layer (INS1) and may be formed of a first semiconductor layer. The first semiconductor pattern (SCP1) may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the other end of the channel region. A second insulating layer (INS2) may be disposed on the first semiconductor pattern (SCP1).

[0182] The sixth gate electrode (GE6) is disposed on the second insulating layer (INS2) and may be formed of a first conductive layer (CL1). The first conductive layer (CL1) may be formed as a single layer or multiple layers made of molybdenum, copper, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and / or oxides and / or alloys thereof. For example, the first conductive layer (CL1) may be formed as a multiple layer in which titanium, copper, and / or indium main oxides are sequentially or repeatedly stacked, but is not limited thereto. The sixth gate electrode (GE6) may overlap a region of the first semiconductor pattern (SCP1). A region of the first semiconductor pattern (SCP1) overlapping the sixth gate electrode (GE6) may be a channel region of the sixth transistor (T6). A third insulating layer (INS3) may be disposed on the sixth gate electrode (GE6).

[0183] The first terminal (TE1) and the second terminal (TE2) may be disposed on the sixth insulating layer (INS6). The first terminal (TE1) and the second terminal (TE2) may be formed of a fourth conductive layer (CL4). The fourth conductive layer (CL4) may be formed as a single layer and / or multiple layers made of molybdenum, copper, aluminum, chromium, gold, silver, titanium, nickel, neodymium, indium, tin, and oxides or alloys thereof.

[0184] The first terminal (TE1) can be electrically connected to a second contact area of ​​the first semiconductor pattern (SCP1) through a first contact portion (CNT1) penetrating the second insulating layer (INS2), the third insulating layer (INS3), the fourth insulating layer (INS4), the fifth insulating layer (INS5), and the sixth insulating layer (INS6). The first terminal (TE1) can be electrically connected to an anode electrode (AE) of a light emitting element (LED). The second terminal (TE2) can be electrically connected to a first contact area of ​​the first semiconductor pattern (SCP1) through another first contact portion (CNT1) penetrating the second insulating layer (INS2), the third insulating layer (INS3), the fourth insulating layer (INS4), the fifth insulating layer (INS5), and the sixth insulating layer (INS6).

[0185] A seventh insulating layer (INS7) may be placed on the first terminal (TE1) and the second terminal (TE2).

[0186] A fourth semiconductor pattern (SCP4) may be disposed on a fourth insulating layer (INS4). The fourth semiconductor pattern (SCP4) may be formed of a second semiconductor layer. The fourth semiconductor pattern (SCP4) may include a channel region, a first contact region connected to one end of the channel region, and a second contact region connected to the other end of the channel region. A fifth insulating layer (INS5) may be disposed on the fourth semiconductor pattern (SCP4).

[0187] The tenth gate electrode (GE10) may be disposed on the fifth insulating layer (INS5). The tenth gate electrode (GE10) may be formed of a third conductive layer (CL3). The third conductive layer (CL3) may include the same material as the first conductive layer (CL1) or the fourth conductive layer (CL4), or may include a suitable (or selected) material from among the materials exemplified as constituent materials of the first conductive layer (CL1) or the fourth conductive layer (CL4). The tenth gate electrode (GE10) may overlap a region of the fourth semiconductor pattern (SCP4). A region of the fourth semiconductor pattern (SCP4) overlapping the tenth gate electrode (GE10) may be a channel region of the tenth transistor (T10).

[0188] A sixth insulating layer (INS6) may be placed on the tenth gate electrode (GE10).

[0189] The third terminal (TE3) and the fourth terminal (TE4) may be arranged on the sixth insulating layer (INS6). The third terminal (TE3) and the fourth terminal (TE4) may be formed of the fourth conductive layer (CL4).

[0190] The third terminal (TE3) may be electrically connected to a first contact area of ​​the fourth semiconductor pattern (SCP4) through a second contact portion (CNT2) penetrating the fifth insulating layer (INS5) and the sixth insulating layer (INS6). The fourth terminal (TE4) may be electrically connected to a second contact area of ​​the fourth semiconductor pattern (SCP4) through another second contact portion (CNT2) penetrating the fifth insulating layer (INS5) and the sixth insulating layer (INS6). The third terminal (TE3) and the fourth terminal (TE4) may be spaced apart from each other on the sixth insulating layer (INS6). A seventh insulating layer (INS7) may be disposed on the third terminal (TE3) and the fourth terminal (TE4).

[0191] A storage capacitor (Cst) may be arranged in the pixel circuit layer (PCL). The storage capacitor (Cst) may include a lower electrode (LE) and an upper electrode (UE).

[0192] The lower electrode (LE) may be disposed on the second insulating layer (INS2). The lower electrode (LE) may be composed of a first conductive layer (CL1) and may be provided on the same layer as the sixth gate electrode (GE6), but is not limited thereto. A third insulating layer (INS3) may be disposed on the lower electrode (LE).

[0193] The upper electrode (UE) may be disposed on the third insulating layer (INS3). The upper electrode (UE) may be composed of, but is not limited to, a second conductive layer (CL2). The second conductive layer (CL2) may include the same material as the first conductive layer (CL1) or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) or the fourth conductive layer (CL4). The upper electrode (UE) may overlap the lower electrode (LE) with the third insulating layer (INS3) interposed therebetween to form a capacitance.

[0194] A first connection wiring (CNL1), a second connection wiring (CNL2), a first bridge pattern (BRP1), and a second bridge pattern (BRP2) may be arranged in the pixel circuit layer (PCL).

[0195] The first connection wiring (CNL1) and the second connection wiring (CNL2) may be arranged on the seventh insulating layer (INS7). The first connection wiring (CNL1) and the second connection wiring (CNL2) may be formed of a fifth conductive layer (CL5). The fifth conductive layer (CL5) may include the same material as the first conductive layer (CL1) or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) or the fourth conductive layer (CL4). The first connection wiring (CNL1) may be electrically connected to the first terminal (TE1) of the sixth transistor (T6) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7). The second connection wiring (CNL2) may be electrically connected to the third terminal (TE3) of the tenth transistor (T10) through another first via hole (VIH1) penetrating the seventh insulating layer (INS7). An eighth insulating layer (INS8) may be disposed on the first connection wiring (CNL1) and the second connection wiring (CNL2).

[0196] The first bridge pattern (BRP1) and the second bridge pattern (BRP2) may be disposed on the eighth insulating layer (INS8). The first bridge pattern (BRP1) and the second bridge pattern (BRP2) may be formed of a sixth conductive layer (CL6). The sixth conductive layer (CL6) may include the same material as the first conductive layer (CL1) or the fourth conductive layer (CL4), or may include one or more materials suitable (or selected) from among the materials exemplified as constituent materials of the first conductive layer (CL1) or the fourth conductive layer (CL4). The first bridge pattern (BRP1) may be electrically connected to the first connection wiring (CNL1) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8). The second bridge pattern (BRP2) may be electrically connected to the second connection wiring (CNL2) through another second via hole (VIH2) penetrating the eighth insulating layer (INS8). A ninth insulating layer (INS9) may be disposed on the first and second bridge patterns (BRP1, BRP2).

[0197] A display element layer (DPL) may be arranged on a pixel circuit layer (PCL) of a sub-pixel (SPX), and a sensor layer (SSL) may be arranged on a pixel circuit layer (PCL) of a light-sensing pixel (PSR).

[0198] A light emitting element (LED) and a bank (BNK) may be arranged on a display element layer (DPL). The light emitting element (LED) may include an anode electrode (AE) (or pixel electrode), an emission layer (EML), and a cathode electrode (CE) (or common electrode). The light emitting element (LED) may be electrically connected to a sixth transistor (T6) through a first bridge pattern (BRP1) and a first connection wire (CNL1). The emission layer (EML) may include a hole transport layer, an organic material layer (or a light generating layer), an electron transport layer, etc.

[0199] A light-receiving element (LRD) and a bank (BNK) may be arranged on the sensor layer (SSL). The light-receiving element (LRD) may be an optical fingerprint sensor. The light-receiving element (LRD) can recognize a fingerprint by sensing light reflected by the ridges (FR) of a finger (F) and the valleys (FV) between the ridges (FR). For example, when a user's finger (F) comes into contact with the window (WD), first light (L1) output from the light-emitting element (LED) (or the light-emitting layer (EML)) is reflected by the ridges (FR) and / or valleys (FV) of the finger (F), and the reflected second light (L2) can reach the light-receiving element (LRD) (or the light-receiving layer (OPL)) of the sensor layer (SSL). The light-receiving element (LRD) can recognize the pattern of the user's fingerprint by distinguishing the second light (L2) reflected from the ridge (FR) of the finger (F) and the second light (L2) reflected from the valley (FV) of the finger (F). The light-receiving element (LRD) can be electrically connected to the tenth transistor (T10). The light-receiving element (LRD) can include a first electrode (EL1) (or a first sensor electrode), a light-receiving layer (OPL) (or a photoelectric conversion layer), and a second electrode (EL2) (or a second sensor electrode).

[0200] The anode electrode (AE) and the first electrode (EL1) may be disposed on the ninth insulating layer (INS9). The anode electrode (AE) and the first electrode (EL1) may be formed of a metal layer such as silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, an alloy thereof, and / or indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), but are not limited thereto. The anode electrode (AE) may be electrically connected to the first bridge pattern (BRP1) through a third via hole (VIH3) penetrating the ninth insulating layer (INS9). The first electrode (EL1) may be electrically connected to the second bridge pattern (BRP2) through another third via hole (VIH3) penetrating the ninth insulating layer (INS9).

[0201] The anode electrode (AE) and the first electrode (EL1) can be formed simultaneously or sequentially through patterning using a mask.

[0202] The bank (BNK) may be a pixel defining film that defines (or partitions) an emission area (EMA) of a sub-pixel (SPX) and a light-receiving area (FXA) of a light-sensing pixel (PSR). The bank (BNK) may be an organic film including an organic material (or substance). The organic material may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, and / or a polyimide resin. The bank (BNK) may be arranged on a ninth insulating layer (INS9) in a non-emission area (NEA) of the sub-pixel (SPX) and the light-sensing pixel (PSR).

[0203] According to one or more embodiments, the bank (BNK) may include a light-absorbing material or may be coated with a light-absorbing agent to absorb light introduced from the outside. For example, the bank (BNK) may include, but is not limited to, a carbon-based black pigment. The bank (BNK) may also include an opaque metal material having high light absorption, such as chromium, molybdenum, an alloy of molybdenum and titanium, tungsten, vanadium, niobium, tantalum, manganese, cobalt, and / or nickel. The bank (BNK) may include openings corresponding to an emission area (EMA) and a light-receiving area (FXA).

[0204] An emission layer (EML) may be disposed on the anode electrode (AE). The emission layer (EML) may include an organic emission layer. Depending on the organic material included in the emission layer (EML), the emission layer (EML) may emit light of, but is not limited to, red light, green light, and / or blue light.

[0205] A light-receiving layer (OPL) may be placed on the first electrode (EL1). The light-receiving layer (OPL) can detect the intensity of light by emitting electrons in response to light of a specific wavelength band.

[0206] The optical receiving layer (OPL) may include a low molecular weight organic substance (or material). For example, the optical receiving layer (OPL) is composed of a phthalocyanine compound including one or more metals selected from the group consisting of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La), and zinc (Zn).

[0207] Alternatively, the low-molecular-weight organic material included in the light-receiving layer (OPL) may be composed of two layers (bi-layers) including a layer including a phthalocyanine compound and a layer including C60, which include one or more metals selected from the group consisting of copper (Cu), iron (Fe), nickel (Ni), cobalt (Co), manganese (Mn), aluminum (Al), palladium (Pd), tin (Sn), indium (In), lead (Pb), titanium (Ti), rubidium (Rb), vanadium (V), gallium (Ga), terbium (Tb), cerium (Ce), lanthanum (La), and zinc (Zn), or may be composed of a single mixed layer in which a phthalocyanine compound and C60 are mixed. However, the present invention is not limited to the above-described embodiments, and the light-receiving layer (OPL) may include a high-molecular-weight organic layer according to one or more embodiments.

[0208] A cathode electrode (CE) may be disposed on the light-emitting layer (EML), and a second electrode (EL2) may be disposed on the light-receiving layer (OPL). The cathode electrode (CE) and the second electrode (EL2) may be a common electrode integrally formed in the display area (DA). A second power voltage (VSS) may be supplied to the cathode electrode (CE) and the second electrode (EL2).

[0209] The cathode electrode (CE) and the second electrode (EL2) may be formed of a metal layer such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, etc. and / or a transparent conductive layer such as ITO, IZO, ZnO, ITZO, etc. In one or more embodiments, the cathode electrode (CE) and the second electrode (EL2) may be formed of a multilayer including a double layer or more including a metal thin layer, for example, a triple layer of ITO / Ag / ITO.

[0210] A thin film encapsulation layer (TFE) can be formed over the entire surface of the cathode electrode (CE) and the second electrode (EL2).

[0211] A thin film encapsulation layer (TFE) may be formed as a single layer, but may also be formed as a multilayer. The thin film encapsulation layer (TFE) may include a plurality of insulating layers covering a light emitting element (LED) and a light receiving element (LRD). Specifically, the thin film encapsulation layer (TFE) may include at least one inorganic film and / or at least one organic film. For example, the thin film encapsulation layer (TFE) may have a structure in which inorganic films and organic films are alternately laminated.

[0212] A color filter layer (CFL) may be disposed on a thin film encapsulation layer (TFE). The color filter layer (CFL) may include a light-shielding pattern and a color filter. The light-shielding pattern may be disposed on the thin film encapsulation layer (TFE) to correspond to a non-emission area (NEA) surrounding an emission area (EMA) of a sub-pixel (SPX) and a light-receiving area (FXA) of a light-sensing pixel (PSR), and the color filter may be disposed on the thin film encapsulation layer (TFE) to correspond to the emission area (EMA) and the light-receiving area (FAX). The above-described color filter layer (CFL) may also be utilized as an anti-reflection layer that blocks external light reflection.

[0213] A window (WD) may be placed on the color filter layer (CFL).

[0214] The window (WD) can protect the exposed surface of the display device (DD) (or display panel (see "100" in FIG. 1)). The window (WD) can protect the display device (DD) from external impact and provide an input surface and / or a display surface to the user. The window (WD) (or color glass) can have a multilayer structure selected from a glass substrate, a plastic film, and a plastic substrate. This multilayer structure can be formed through a continuous process or an adhesive process using an adhesive layer. The window (WD) can have flexibility in whole or in part.

[0215] FIG. 10 is a schematic plan view showing sub-pixels (SPX1 to SPX4) and a light-sensing pixel (PSR1) according to one or more embodiments, FIG. 11 is a schematic plan view showing only the first, second, fifth, sixth, seventh, eighth, ninth, and eleventh transistors (T1, T2, T5, T6, T7, T8, T9, T11) and the components included in the first conductive layer (CL1) in FIG. 10, FIG. 12 is a schematic plan view showing only the components included in the second conductive layer (CL2) in FIG. 10, FIG. 13 is a schematic plan view showing only the third, fourth, and tenth transistors (T3, T4, T10) and the components included in the third conductive layer (CL3) in FIG. 10, and FIG. 14 is a schematic plan view showing only the components included in the fourth conductive layer (CL4) in FIG. 10, FIG. 15 is a schematic plan view showing only the components included in the fifth conductive layer (CL5) in FIG. 10, FIG. 16 is a schematic plan view showing only the components included in the sixth conductive layer (CL6) in FIG. 10, FIG. 17 is a schematic plan view showing only the components included in the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in FIG. 10, and FIG. 18 is a schematic cross-sectional view taken along line Ⅰ-Ⅰ' in FIG. 17.

[0216] For convenience of explanation, in FIGS. 10 to 18, the first sub-pixel (SPX1), the second sub-pixel (SPX2), the third sub-pixel (SPX3), the fourth sub-pixel (SPX4), and the first light-sensing pixel (PSR1) are illustrated arranged in the same pixel row (or the same horizontal line).

[0217] Referring to FIGS. 1 to 18, a first sub-pixel (SPX1), a second sub-pixel (SPX2), a third sub-pixel (SPX3), and a fourth sub-pixel (SPX4) may be arranged along a first direction (DR1) in a display area (DA). A first light-sensing pixel (PSR1) may be arranged between the second sub-pixel (SPX2) and the third sub-pixel (SPX3).

[0218] Each of the first to fourth sub-pixels (SPX1 to SPX4) may include a pixel circuit (PXC). For example, the first sub-pixel (SPX1) may include a first pixel circuit (PXC1), the second sub-pixel (SPX2) may include a second pixel circuit (PXC2), the third sub-pixel (SPX3) may include a third pixel circuit (PXC3), and the fourth sub-pixel (SPX4) may include a fourth sub-pixel (PXC4). The first light-sensing pixel (PSR1) may include a sensor circuit (SC). The first pixel circuit (PXC1) corresponds to the eleventh pixel circuit (PXC11) of FIG. 6, the second pixel circuit (PXC2) corresponds to the twelfth pixel circuit (PXC12) of FIG. 6, the third pixel circuit (PXC3) corresponds to the thirteenth pixel circuit (PXC13) of FIG. 6, the fourth pixel circuit (PXC4) corresponds to the fourteenth pixel circuit (PXC14) of FIG. 6, and the sensor circuit (SC) corresponds to the eleventh sensor circuit (SC11) of FIG. 6. With respect to the sensor circuit (SC), the pixel circuits (PXC1, PXC2) on the left and the pixel circuits (PXC3, PXC4) on the right are symmetrical to each other and may be substantially the same. For convenience, FIGS. 10 to 17 illustrate the second pixel circuit (PXC2), the sensor circuit (SC), and the third pixel circuit (PXC3).

[0219] The first to fourth sub-pixels (SPX1 to SPX4) may include a substrate (SUB), a pixel circuit layer (PCL), a display element layer (DPL), a thin film encapsulation layer (TFE), a color filter layer (CFL), and a window (WD). The first photo-sensing pixel (PSR1) may include a substrate (SUB), a pixel circuit layer (PCL), a sensor layer (SSL), an encapsulation layer (TFE), a color filter layer (CFL), and a window (WD).

[0220] The substrate (SUB) may be capable of transmitting light by including a transparent insulating material. The substrate (SUB) may be a rigid substrate or a flexible substrate.

[0221] The pixel circuit layer (PCL) may include first to fourth pixel circuits (PXC1 to PXC4), a sensor circuit (SC), and signal wires.

[0222] A light-emitting element (see "LED" in Fig. 8) electrically connected to each of the first to fourth pixel circuits (PXC1 to PXC4) may be disposed on the display element layer (DPL). A light-receiving element (see "LRD" in Fig. 8) electrically connected to the sensor circuit (SC) may be disposed on the sensor layer (SSL).

[0223] The pixel circuit layer (PCL) may include a first insulating layer (INS1), a second insulating layer (INS2), a third insulating layer (INS3), a fourth insulating layer (INS4), a fifth insulating layer (INS5), a sixth insulating layer (INS6), a seventh insulating layer (INS7), an eighth insulating layer (INS8), and a ninth insulating layer (INS9) sequentially laminated along a third direction (DR3) from one surface of the substrate (SUB).

[0224] In addition, the pixel circuit layer (PCL) may have at least one conductive layer and at least one semiconductor layer arranged thereon. For example, the pixel circuit layer (PCL) may include a first semiconductor layer, a first conductive layer (CL1), a second conductive layer (CL2), a second semiconductor layer, a third conductive layer (CL3), a fourth conductive layer (CL4), a fifth conductive layer (CL5), and a sixth conductive layer (CL6) sequentially stacked along a third direction (DR3) from one surface of the substrate (SUB).

[0225] Signal lines may be arranged in the display area (DA) where the first to fourth sub-pixels (SPX1 to SPX4) and the first light-sensing pixel (PSR1) are located. For example, the first to twentieth lines (WL1 to WL20), the second and third data lines (D2, D3), the first power line (PL1), and the first and second vertical bridge lines (BRL1_V, BRL2_V) may be arranged in the display area (DA).

[0226] The first wiring (WL1) may extend in the first direction (DR1) and may be composed of a first conductive layer (CL1). The first wiring (WL1) may be the 3i scan line (S3i) described with reference to FIG. 7. One region of the first wiring (WL1) may be a gate electrode (hereinafter, referred to as a “seventh gate electrode”) of the seventh transistor (T7) of each of the second and third pixel circuits (PXC2, PXC3). In addition, another region of the first wiring (WL1) may be a gate electrode (hereinafter, referred to as a “eighth gate electrode”) of the eighth transistor (T8) of each of the second and third pixel circuits (PXC2, PXC3).

[0227] The second wiring (WL2) may extend in the first direction (DR1) and be arranged to be spaced apart from the first wiring (WL1). The second wiring (WL2) may be composed of a first conductive layer (CL1). The second wiring (WL2) may be the 1i scan line (S1i) described with reference to FIG. 7. One area of ​​the second wiring (WL2) may be a gate electrode (hereinafter referred to as “second gate electrode”) of the second transistor (T2) of each of the second and third pixel circuits (PXC2, PXC3).

[0228] The third wiring (WL3) may extend in the first direction (DR1) and be arranged to be spaced apart from the first and second wirings (WL1, WL2). The third wiring (WL3) may be formed of a first conductive layer (CL1). In one or more embodiments, the third wiring (WL3) may be the ith light emission control line (Ei) described with reference to FIG. 7. One region of the third wiring (WL3) may be a gate electrode (hereinafter, referred to as a “fifth gate electrode”) of the fifth transistor (T5) of each of the second and third pixel circuits (PXC2, PXC3). In addition, another region of the third wiring (WL3) may be a gate electrode (hereinafter, referred to as a “sixth gate electrode”) of the sixth transistor (T6) of each of the second and third pixel circuits (PXC2, PXC3).

[0229] The fourth wiring (WL4) extends in the first direction (DR1) and may be composed of a second conductive layer (CL2). The fourth wiring (WL4) may be a dummy line overlapping the eighth wiring (WL8) composed of the third conductive layer (CL3), but is not limited thereto.

[0230] The fifth wiring (WL5) may extend in the first direction (DR1) and may be formed of a second conductive layer (CL2). The fifth wiring (WL5) may be arranged to be spaced apart from the fourth wiring (WL4). The fifth wiring (WL5) may be a dummy line overlapping the ninth wiring (WL9) formed of the third conductive layer (CL3), but is not limited thereto.

[0231] The sixth wiring (WL6) may extend in the first direction (DR1) and may be formed of a second conductive layer (CL2). The sixth wiring (WL6) may be arranged to be spaced apart from the fourth and fifth wirings (WL4, WL5). The sixth wiring (WL6) may be a dummy line overlapping the tenth wiring (WL10) formed of the third conductive layer (CL3), but is not limited thereto.

[0232] The seventh wiring (WL7) extends in the first direction (DR1) and may be formed of a third conductive layer (CL3). In one or more embodiments, the seventh wiring (WL7) may be the sixth power wiring (PL6) described with reference to FIG. 7 in each of the second to fourth sub-pixels (SPX2 to SPX4). The seventh wiring (WL7) may be supplied with a common voltage (see "VCOM" in FIG. 7) (or a second initialization power voltage (Vint2)).

[0233] The eighth wiring (WL8) may extend in the first direction (DR1) and may be arranged to be spaced apart from the seventh wiring (WL7). The eighth wiring (WL8) may be composed of a third conductive layer (CL3). The eighth wiring (WL8) may be the 4i scan line (S4i) described with reference to FIG. 7. One area of ​​the eighth wiring (WL8) may be a gate electrode (hereinafter, referred to as “third gate electrode”) of the third transistor (T3) of each of the second and third pixel circuits (PXC2, PXC3).

[0234] The ninth wiring (WL9) may extend in the first direction (DR1) and be arranged to be spaced apart from the seventh and eighth wirings (WL7, WL8). The ninth wiring (WL9) may be formed of a third conductive layer (CL3). The ninth wiring (WL9) may be the 2i scan line (S2i) described with reference to FIG. 7. One area of ​​the ninth wiring (WL9) may be a gate electrode (hereinafter, referred to as a “fourth gate electrode”) of the fourth transistor (T4) of each of the second and third pixel circuits (PXC2, PXC3).

[0235] The tenth wiring (WL10) may extend in the first direction (DR1) and may be arranged to be spaced apart from the seventh to ninth wirings (WL7 to WL9). The tenth wiring (WL10) may be formed of a third conductive layer (CL3). The tenth wiring (WL10) may be the sixth power wiring (PL6) described with reference to FIG. 7 in the first sub-pixel (SPX1). The tenth wiring (WL10) may be supplied with a common voltage (VCOM) (or a second initialization power voltage (Vint2)). In one or more embodiments, the seventh wiring (WL7) and the tenth wiring (WL10) may be supplied with the same voltage, for example, the common voltage (VCOM).

[0236] The eleventh wiring (WL11) extends in the first direction (DR1) and may be arranged to be spaced apart from the seventh to tenth wirings (WL7 to WL10). The eleventh wiring (WL11) may be formed of a third conductive layer (CL3). The eleventh wiring (WL11) may be the reset line (RSTL) described with reference to FIG. 7. One area of ​​the eleventh wiring (WL11) may be the gate electrode of the tenth transistor (T10) of the sensor circuit (SC) (hereinafter, referred to as the “tenth gate electrode”). The tenth gate electrode may be the tenth gate electrode (GE10) described with reference to FIG. 8.

[0237] The twelfth wiring (WL12) may extend in the first direction (DR1) and may be formed of a fourth conductive layer (CL4). The twelfth wiring (WL12) may be the fourth power wiring (PL4) described with reference to FIG. 7. The twelfth wiring (WL12) may be supplied with a bias voltage (refer to “VOBS” in FIG. 7). The twelfth wiring (WL12) may be electrically connected to the first semiconductor pattern (SCP1) of the eighth transistor (T8) of each of the second and third pixel circuits (PXC2, PXC3).

[0238] The thirteenth wiring (WL13) may extend in the first direction (DR1) and be spaced apart from the twelfth wiring (WL12). The thirteenth wiring (WL13) may be formed of a fourth conductive layer (CL4). The thirteenth wiring (WL13) may be a horizontal bridge line (BRL_H). The thirteenth wiring (WL13) may be electrically connected to a corresponding data line among the data lines located in the first area (refer to “DA1” in FIG. 3) of the display area (DA). The thirteenth wiring (WL13) may overlap the fourth connection pattern (CNP4) of each of the second and third sub-pixels (SPX2, SPX3). In one or more embodiments, the thirteenth wiring (WL13) may be electrically connected to the fourth connection pattern (CNP4) of the third sub-pixel (SPX3).

[0239] The fourth connection pattern (CNP4) may be formed of a fifth conductive layer (CL5). The fourth connection pattern (CNP4) of the second sub-pixel (SPX2) may overlap the 13th wiring (WL13), but may be physically and / or electrically separated from the 13th wiring (WL13). The fourth connection pattern (CNP4) of the third sub-pixel (SPX3) may overlap the 13th wiring (WL13) and be electrically connected to the 13th wiring (WL13) through a corresponding first via hole (VIH1). In the second sub-pixel (SPX2), the fourth connection pattern (CNP4) may be arranged to be spaced apart from the fifth connection pattern (CNP5). In the third sub-pixel (SPX3), the fourth connection pattern (CNP4) can be formed integrally with the fifth connection pattern (CNP5) of the third sub-pixel (SPX3) to form a pad electrode (PDE).

[0240] The fourteenth wiring (WL14) may extend in the first direction (DR1) and may be arranged to be spaced apart from the twelfth and thirteenth wirings (WL12, WL13). The fourteenth wiring (WL14) may be formed of a fourth conductive layer (CL4). The fourteenth wiring (WL14) may be the second power wiring (PL2) described with reference to FIG. 7. The fourteenth wiring (WL14) may be supplied with a first initialization power voltage (refer to “Vint1” in FIG. 7). The fourteenth wiring (WL14) may be electrically connected to a third semiconductor pattern (SCP3) of a fourth transistor (T4) of each of the second and third pixel circuits (PXC2, PXC3).

[0241] The fifteenth wiring (WL15) may extend in the first direction (DR1) and may be arranged to be spaced apart from the twelfth to fourteenth wirings (WL12 to WL14). The fifteenth wiring (WL15) may be formed of a fourth conductive layer (CL4). The fifteenth wiring (WL15) may be the fifth power wiring (PL5) described with reference to FIG. 7. The fifteenth wiring (WL15) may be supplied with a reset voltage (see “VRST” in FIG. 7). The fifteenth wiring (WL15) may be electrically connected to the fourth semiconductor pattern (SCP4) of the tenth transistor (T10) of the sensor circuit (SC).

[0242] The sixteenth wiring (WL16) may extend in the second direction (DR2) and may be formed of a fifth conductive layer (CL5). The sixteenth wiring (WL16) may be electrically connected to the fifteenth wiring (WL15) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7). The sixteenth wiring (WL16) may be located within the first photosensitive pixel (SPR1) where the sensor circuit (SC) is located, but is not limited thereto.

[0243] The seventeenth wiring (WL17) may extend in the second direction (DR2) and be arranged to be spaced apart from the sixteenth wiring (WL16). The seventeenth wiring (WL17) may be composed of a fifth conductive layer (CL5). The seventeenth wiring (WL17) may be the kth lead-out line (RXk, hereinafter referred to as “lead-out line”) described with reference to FIG. 7. The seventeenth wiring (WL17) may be electrically connected to the eighth conductive pattern (CP8) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0244] The eighth conductive pattern (CP8) may be formed of a fourth conductive layer (CL4). The eighth conductive pattern (CP8) may be arranged in the first photosensitive pixel (PSR1) and may be electrically connected to the seventeenth wiring (WL17) through a corresponding first via hole (VIH1). In addition, the eighth conductive pattern (CP8) may be electrically connected to the second semiconductor pattern (SCP2) of the eleventh transistor (T11) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0245] The eighteenth wiring (WL18) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The eighteenth wiring (WL18) may be arranged between the first sub-pixel (SPX1) and the second sub-pixel (SPX2). The eighteenth wiring (WL18) may be the third power wiring (PL3) described with reference to FIG. 7 in each of the first and second sub-pixels (SPX1, SPX2). The eighteenth wiring (WL18) may be supplied with the second initialization power voltage (Vint2). The eighteenth wiring (WL18) may be electrically connected to the first connection pattern (CNP1) of each of the first and second sub-pixels (SPX1, SPX2) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0246] The first connection pattern (CNP1) may be formed of a fifth conductive layer (CL5). The first connection pattern (CNP1) may be electrically connected to the eighteenth wiring (WL18) through a corresponding second via hole (VIH2). In addition, the first connection pattern (CNP1) may be electrically connected to the seventh conductive pattern (CP7) of each of the first and second sub-pixels (SPX1, SPX2) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0247] The seventh conductive pattern (CP7) may be formed of a fourth conductive layer (CL4). The seventh conductive pattern (CP7) may be electrically connected to the first connection pattern (CNP1) through a corresponding first via hole (VIH1). In addition, the seventh conductive pattern (CP7) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2) in the second sub-pixel (SPX2).

[0248] The nineteenth wiring (WL19) may extend in the second direction (DR2) and may be arranged to be spaced apart from the eighteenth wiring (WL18). The nineteenth wiring (WL19) may be formed of a sixth conductive layer (CL6). The nineteenth wiring (WL19) may be arranged between the third sub-pixel (SPX3) and the fourth sub-pixel (SPX4). The nineteenth wiring (WL19) may be electrically connected to the first connection pattern (CNP1) of each of the third and fourth sub-pixels (SPX3, SPX3) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0249] The first connection pattern (CNP1) may be formed of a fifth conductive layer (CL5). The first connection pattern (CNP1) may be electrically connected to the nineteenth wiring (WL19) through a corresponding second via hole (VIH2). In addition, the first connection pattern (CNP1) may be electrically connected to the fourteenth wiring (WL14) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7). According to one or more embodiments, the first connection pattern (CNP1) may be electrically connected to the seventh conductive pattern (CP7) of each of the third and fourth sub-pixels (SPX3, SPX4) through another first via hole (VIH1) penetrating the seventh insulating layer (INS7). The 19th wiring (WL19) is electrically connected to the 14th wiring (WL14) through the first connection pattern (CNP1) and can be supplied with the first initialization power voltage (Vint1).

[0250] The 20th wiring (WL20) may extend in the second direction (DR2) and may be arranged to be spaced apart from the 18th and 19th wirings (WL18, WL19). The 20th wiring (WL20) may be formed of a sixth conductive layer (CL6). The 20th wiring (WL20) may be positioned within the first light-sensing pixel (PSR1). The 20th wiring (WL20) may be electrically connected to the 16th wiring (WL16) formed of the 5th conductive layer (CL5) through a second via hole (VIH2) penetrating the 8th insulating layer (INS8). The 16th wiring (WL16) may be electrically connected to the 15th wiring (WL15) formed of the 4th conductive layer (CL4) through a corresponding first via hole (VIH1). The fifteenth wiring (WL15), the sixteenth wiring (WL16), and the twentieth wiring (WL20), which are electrically connected to each other, can be supplied with a reset voltage (VRST).

[0251] In one or more embodiments, the fifteenth wiring (WL15) may be a horizontal power wiring of the fifth power wiring (PL5), the sixteenth wiring (WL16) may be a first vertical power wiring of the fifth power wiring (PL5), and the twentieth wiring (WL20) may be a second vertical power wiring of the fifth power wiring (PL5). The fifteenth wiring (WL15) extending in the first direction (DR1) and composed of the fourth conductive layer (CL4), the sixteenth wiring (WL16) extending in the second direction (DR2) and composed of the fifth conductive layer (CL5), and the twentieth wiring (WL20) extending in the second direction (DR2) and composed of the sixth conductive layer (CL6) may be electrically connected to each other to form the fifth power wiring (PL5) in a mesh structure. That is, the fifth power wire (PL5) may have a mesh structure due to the fifteenth wire (WL15), the sixteenth wire (WL16), and the twentieth wire (WL20) being electrically connected to each other.

[0252] The second data line (D2) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The second data line (D2) may be arranged in the same layer as the 18th to 20th wires (WL18 to WL20) and may be arranged spaced apart from the 18th to 20th wires (WL18 to WL20). The second data line (D2) may be the j-th data line (Dj) described with reference to FIG. 7. The second data line (D2) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the second pixel circuit (PXC2).

[0253] The third data line (D3) may extend in the second direction (DR2) and may be formed of a sixth conductive layer (CL6). The third data line (D3) may be arranged on the same layer as the second data line (D2) and may be arranged spaced apart from the second data line (D2). The third data line (D3) may be the j-th data line (Dj) described with reference to FIG. 7. The third data line (D3) may be electrically connected to the first semiconductor pattern (SCP1) of the second transistor (T2) of the third pixel circuit (PXC3).

[0254] A first vertical bridge line (BRL1_V) may extend in a second direction (DR2) and may be formed of a sixth conductive layer (CL6). The first vertical bridge line (BRL1_V) may be disposed on the same layer as the second and third data lines (D2, D3) and may be disposed spaced apart from the second and third data lines (D2, D3). The first vertical bridge line (BRL1_V) may overlap a part of a configuration of a second pixel circuit (PXC2) within the second sub-pixel (SPX2). The first vertical bridge line (BRL1_V) may be electrically connected to a corresponding data line among the data lines located in the first area (DA1). The first vertical bridge line (BRL1_V) may electrically connect the data line to a fan-out line located in a fan-out area (an "FTA" area in FIG. 3) of a non-display area (see "NDA" in FIG. 3). The first vertical bridge line (BRL1_V) can be electrically connected to the fifth connection pattern (CNP5) of the second sub-pixel (SPX2) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8).

[0255] The second vertical bridge line (BRL2_V) may extend in the second direction (DR2) and may be arranged to be spaced apart from the first vertical bridge line (BRL2_V). The second vertical bridge line (BRL2_V) may be formed of a sixth conductive layer (CL6). The second vertical bridge line (BRL2_V) may overlap with a part of a configuration of a third pixel circuit (PXC3) within a third sub-pixel (SPX3). The second vertical bridge line (BRL2_V) may be electrically connected to a corresponding data line among data lines located in the first area (DA). The second vertical bridge line (BRL2_V) may be electrically connected to a corresponding fan-out line located in a fan-out area (FTA) and the data line.

[0256] In one or more embodiments, the second vertical bridge line (BRL2_V) may include a first sub-electrode (SUE1) and a second sub-electrode (SUE2). The first sub-electrode (SUE1) and the second sub-electrode (SUE2) may be positioned in the same column along the second direction (DR2) and may be spaced apart from each other. The first sub-electrode (SUE1) and the second sub-electrode (SUE2) may be electrically isolated.

[0257] The first sub-electrode (SUE1) may be positioned at the lower portion within the third sub-pixel (SPX3) when viewed on a plane, and the second sub-electrode (SUE2) may be positioned at the central portion and the upper portion within the third sub-pixel (SPX3).

[0258] The first sub-electrode (SUE1) may be electrically connected to a pad electrode (PDE) of a third sub-pixel (SPX3) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8). The pad electrode (PDE) may be formed of a fifth conductive layer (CL5). One end of the pad electrode (PDE) may be electrically connected to the first sub-electrode (SUE1) through a corresponding second via hole (VIH2). The other end of the pad electrode (PDE) may be electrically connected to a thirteenth wiring (WL13) (or horizontal bridge line (BRL_H)) through a first via hole (VIH1) penetrating the seventh insulating layer (INS7). When viewed in a plan view, the first sub-electrode (SUE1) may overlap the pad electrode (PDE).

[0259] The second sub-electrode (SUE2) may be electrically connected to the first power line (PL1) of the third sub-pixel (SPX3) through a second via hole (VIH2) penetrating the eighth insulating layer (INS8). The first power line (PL1) may be formed of a fifth conductive layer (CL5). When viewed in a plan view, the second sub-electrode (SUE2) may be disposed to be spaced apart from the second via hole (VIH2) located at the connection point between the pad electrode (PDE) and the first sub-electrode (SUE1) while not overlapping with the pad electrode (PDE). When viewed in a plan view, the second sub-electrode (SUE2) may be located on the upper side of the second via hole (VIH2) based on the second via hole (VIH2). Additionally, when viewed on a plane, the second sub-electrode (SUE2) may be placed between the 17th wiring (WL17) (or the readout wiring (RXk)) and the third data line (D3).

[0260] The first power line (PL1) may extend in the second direction (DR2) and may be formed of a fifth conductive layer (CL5). The first power line (PL1) may be the first power line (PL1) described with reference to FIG. 7. The first power line (PL1) may be supplied with a first power voltage (VDD). The first power voltage (VDD) may be a DC voltage having a constant voltage level. The first sub-pixel (SPX1) and the second sub-pixel (SPX2) may share one first power line (PL1), and the third sub-pixel (SPX3) and the fourth sub-pixel (SPX4) may share one first power line (PL1). The first power line (PL1) of the third sub-pixel (SPX3) may be electrically connected to the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) through a corresponding second via hole (VIH2). In this case, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) can be supplied with the first power voltage (VDD).

[0261] In each of the second and third sub-pixels (SPX2, SPX3), the first power wiring (PL1) can be electrically connected to the first conductive pattern (CP1) composed of the fourth conductive layer (CL4) through the first via hole (VIH1) penetrating the seventh insulating layer (INS7).

[0262] The first conductive pattern (CP1) is formed of a fourth conductive layer (CL4) and can be electrically connected to a first power line (PL1) through a corresponding first via hole (VIH1). In addition, the first conductive pattern (CP1) can be electrically connected to a first semiconductor pattern (SCP1) of a fifth transistor (T5) of each of the second and third pixel circuits (PXC2, PXC3) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the first conductive pattern (CP1) can be electrically connected to an upper electrode (UE) formed of a second conductive layer (CL2) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), and the fourth insulating layer (INS4).

[0263] The first pixel circuit (PXC1), the second pixel circuit (PXC2), the third pixel circuit (PXC3), and the fourth pixel circuit (PXC4) may have substantially similar or identical structures. For example, the first and second pixel circuits (PXC1, PXC2) located on the left side of the sensor circuit (SC) and the third and fourth pixel circuits (PXC3, PXC4) located on the right side of the sensor circuit (SC) may be symmetrical to each other. That is, the first pixel circuit (PXC1) and the third pixel circuit (PXC3) may be symmetrical to each other, and the second pixel circuit (PXC2) and the fourth pixel circuit (PXC4) may be symmetrical to each other. In one or more embodiments, the first pixel circuit (PXC1) and the second pixel circuit (PXC2) may be mirror symmetrical, and the third pixel circuit (PXC3) and the fourth pixel circuit (PXC4) may be mirror symmetrical, but are not limited thereto.

[0264] In the following, for convenience, the description will focus on the second pixel circuit (PXC2), and any duplicate description will not be repeated.

[0265] The second pixel circuit (PXC2) may include first, second, third, fourth, fifth, sixth, seventh, and eighth transistors (T1, T2, T3, T4, T5, T6, T7, T8) and a storage capacitor (Cst).

[0266] The first transistor (T1) may include a first active pattern (ACT1) and a first gate electrode (GE1).

[0267] The first active pattern (ACT1) may be a region of the first semiconductor pattern (SCP1) that overlaps the first gate electrode (GE1). The first semiconductor pattern (SCP1) may be a first semiconductor layer. The first active pattern (ACT1) may be a channel region of the first transistor (T1).

[0268] The channel region may be, for example, an intrinsic semiconductor pattern that is not doped with impurities. The remaining region of the semiconductor pattern excluding the channel region may be a doped semiconductor pattern.

[0269] A region of the first semiconductor pattern (SCP1) that does not overlap with the first gate electrode (GE1) and is connected to one side of the first active pattern (ACT1) (or channel region) (for example, the right side of the first active pattern (ACT1) in a plan view) may be a first contact region. A region of the first semiconductor pattern (SCP1) that does not overlap with the first gate electrode (GE1) and is connected to the other side of the first active pattern (ACT1) (for example, the left side of the first active pattern (ACT1) in a plan view) may be a second contact region. The first contact region and the second contact region may extend in opposite directions from the first active pattern (ACT1).

[0270] The first contact area is connected to one side of the first active pattern (ACT1) and can be connected to the first semiconductor pattern (SCP1) of the second transistor (T2) and the first semiconductor pattern (SCP1) of the fifth transistor (T5). The second contact area is connected to the other side of the first active pattern (ACT1) and can be connected to the first semiconductor pattern (SCP1) of the sixth transistor (T6).

[0271] The first gate electrode (GE1) overlaps the first active pattern (ACT1) and may be formed of a first conductive layer (CL1). The first gate electrode (GE1) may be an island-shaped conductive pattern. The first gate electrode (GE1) may be electrically connected to the third transistor (T3) and the fourth transistor (T4) through the third conductive pattern (CP3).

[0272] The third conductive pattern (CP3) may be composed of a fourth conductive layer (CL4). One end of the third conductive pattern (CP3) may be electrically connected to the first gate electrode (GE1) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), and the third insulating layer (INS3). The other end of the third conductive pattern (CP3) may be electrically connected to a region of the third semiconductor pattern (SCP3) shared by the third transistor (T3) and the fourth transistor (T4) through a second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5).

[0273] The second transistor (T2) may include a second active pattern (ACT2) and a second gate electrode.

[0274] The second active pattern (ACT2) may be a region of the first semiconductor pattern (SCP1) that overlaps the second wiring (WL2). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The second active pattern (ACT2) may be a channel region of the second transistor (T2).

[0275] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to one side of the second active pattern (ACT2) (for example, the lower side of the second active pattern (ACT2) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the second wiring (WL2) and is connected to the other side of the second active pattern (ACT2) (for example, the upper side of the second active pattern (ACT2) in a plan view) may be a second contact area. The first contact area may be connected to one side of the second active pattern (ACT2) and may be electrically connected to the sixth conductive pattern (CP6). The second contact area may be connected to the other side of the second active pattern (ACT2) and may be connected to the first contact area of ​​the first transistor (T1).

[0276] The sixth conductive pattern (CP6) may be composed of a fourth conductive layer (CL4). The sixth conductive pattern (CP6) may be electrically connected to a first semiconductor pattern (SCP1) corresponding to a first contact area of ​​a second transistor (T2) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the sixth conductive pattern (CP6) may be electrically connected to a third connection pattern (CNP3) through a first via hole (VIH1).

[0277] The third connection pattern (CNP3) is formed of a fifth conductive layer (CL5) and can be electrically connected to a sixth conductive pattern (CP6) through a first via hole (VIH1) penetrating a seventh insulating layer (INS7). In addition, the third connection pattern (CNP3) can be electrically connected to a second data line (D2) formed of a sixth conductive layer (CL6) through a second via hole (VIH2) penetrating an eighth insulating layer (INS8).

[0278] The first contact area of ​​the first semiconductor pattern (SCP1) of the second transistor (T2) can be electrically connected to the second data line (D2) through the sixth conductive pattern (CP6) and the third connection pattern (CNP3).

[0279] The second gate electrode may be an area of ​​the second wiring (WL2) that overlaps the second active pattern (ACT2).

[0280] The third transistor (T3) may include a third active pattern (ACT3) and a third gate electrode.

[0281] The third active pattern (ACT3) is a region of the third semiconductor pattern (SCP3) that overlaps the eighth wiring (WL8) and may constitute a channel region of the third transistor (T3). The third semiconductor pattern (SCP3) may be formed of a second semiconductor layer.

[0282] An area of ​​a third semiconductor pattern (SCP3) that does not overlap with the eighth wiring (WL8) and is connected to one side of the third active pattern (ACT3) (for example, the upper side of the third active pattern (ACT3) in a plan view) may be a first contact area, and an area of ​​a third semiconductor pattern (SCP3) that does not overlap with the eighth wiring (WL8) and is connected to the other side of the third active pattern (ACT3) (for example, the lower side of the third active pattern (ACT3) in a plan view) may be a second contact area. The first contact area may be connected to one side of the third active pattern (ACT3) and may be electrically connected to the first transistor (T1) and the sixth transistor (T6) via the fifth conductive pattern (CP5). The second contact area may be connected to the other side of the third active pattern (ACT3) and may be connected to the third semiconductor pattern (SCP3) of the fourth transistor (T4).

[0283] The fifth conductive pattern (CP5) may be formed of a fourth conductive layer (CL4). One end of the fifth conductive pattern (CP5) may be electrically connected to a first contact area of ​​a third transistor (T3) through a sixth insulating layer (INS6) and a second contact portion (CNT2) penetrating the fifth insulating layer (INS5). The other end of the fifth conductive pattern (CP5) may be electrically connected to a region of a first semiconductor pattern (SCP1) shared by the first transistor (T1) and the sixth transistor (T6) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0284] The third gate electrode may be an area of ​​the eighth wiring (WL8) overlapping the third active pattern (ACT3).

[0285] The fourth transistor (T4) may include a fourth active pattern (ACT4) and a fourth gate electrode.

[0286] The fourth active pattern (ACT4) is an area of ​​the third semiconductor pattern (SCP3) that overlaps the ninth wiring (WL9) and may constitute a channel area of ​​the fourth transistor (T4). The third semiconductor pattern (SCP3) may be formed of a second semiconductor layer.

[0287] An area of ​​the third semiconductor pattern (SCP3) that does not overlap with the ninth wiring (WL9) and is connected to one side of the fourth active pattern (ACT4) (for example, an upper side of the fourth active pattern (ACT4) in a plan view) may be a first contact area, and an area of ​​the third semiconductor pattern (SCP3) that does not overlap with the ninth wiring (WL9) and is connected to the other side of the fourth active pattern (ACT4) (for example, a lower side of the fourth active pattern (ACT4) in a plan view) may be a second contact area. The first contact area may be connected to one side of the fourth active pattern (ACT4) and may be connected to the third semiconductor pattern (SCP3) of the third transistor (T3). The second contact area is connected to the other side of the fourth active pattern (ACT4) and can be electrically connected to a fourteenth wiring (WL14) formed of a fourth conductive layer (CL4) through a corresponding second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5).

[0288] The fourth gate electrode may be an area of ​​the ninth wiring (WL9) that overlaps the fourth active pattern (ACT4).

[0289] The fifth transistor (T5) may include a fifth active pattern (ACT5) and a fifth gate electrode.

[0290] The fifth active pattern (ACT5) is a region of the first semiconductor pattern (SCP1) that overlaps the third wiring (WL3) and may constitute a channel region of the fifth transistor (T5). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer.

[0291] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to one side of the fifth active pattern (ACT5) (for example, the upper side of the fifth active pattern (ACT5) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to the other side of the fifth active pattern (ACT5) (for example, the lower side of the fifth active pattern (ACT5) in a plan view) may be a second contact area. The first contact area may be connected to one side of the fifth active pattern (ACT5) and may be electrically connected to the first conductive pattern (CP1) through a corresponding first contact portion (CNT1). The second contact area may be connected to the other side of the fifth active pattern (ACT5) and may be connected to the first semiconductor pattern (SCP1) of each of the first and second transistors (T1, T2).

[0292] The fifth gate electrode may be an area of ​​the third wiring (WL3) that overlaps the fifth active pattern (ACT5).

[0293] The sixth transistor (T6) may include a sixth active pattern (ACT6) and a sixth gate electrode.

[0294] The sixth active pattern (ACT6) is an area of ​​the first semiconductor pattern (SCP1) that overlaps the third wiring (WL3), and may be a channel area of ​​the sixth transistor (T6). The first semiconductor pattern (SCP1) may be composed of a first semiconductor layer.

[0295] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to one side of the sixth active pattern (ACT6) (for example, an upper side of the sixth active pattern (ACT6) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the third wiring (WL3) and is connected to the other side of the sixth active pattern (ACT6) (for example, a lower side of the sixth active pattern (ACT6) in a plan view) may be a second contact area. The first contact area may be connected to one side of the sixth active pattern (ACT6) and the first semiconductor pattern (SCP1) of the seventh transistor (T7), respectively. The second contact area may be connected to the other side of the sixth active pattern (ACT6) and the first semiconductor pattern (SCP1) of the first transistor (T1), respectively. Additionally, the second contact area can be electrically connected to the fifth conductive pattern (CP5) through the corresponding first contact portion (CNT1).

[0296] The sixth gate electrode may be an area of ​​the third wiring (WL3) that overlaps the sixth active pattern (ACT6).

[0297] The seventh transistor (T7) may include a seventh active pattern (ACT7) and a seventh gate electrode.

[0298] The seventh active pattern (ACT7) may be a region of the first semiconductor pattern (SCP1) overlapping the first wiring (WL1). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The seventh active pattern (ACT7) may be a channel region of the seventh transistor (T7).

[0299] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to one side of the seventh active pattern (ACT7) (for example, the lower side of the seventh active pattern (ACT7) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to the other side of the seventh active pattern (ACT7) (for example, the upper side of the seventh active pattern (ACT7) in a plan view) may be a second contact area. The first contact area may be connected to one side of the seventh active pattern (ACT7), connected to the first semiconductor pattern (SCP1) of the sixth transistor (T6), and electrically connected to the fourth conductive pattern (CP4). The second contact area may be connected to the other side of the seventh active pattern (ACT7) and electrically connected to the first conductive pattern (CP1).

[0300] The fourth conductive pattern (CP4) may be formed of a fourth conductive layer (CL4). The fourth conductive pattern (CP4) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) through a corresponding first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the fourth conductive pattern (CP4) may be electrically connected to the second connection pattern (CNP2).

[0301] The second connection pattern (CNP2) may be formed of a fifth conductive layer (CL5). One end of the second connection pattern (CNP2) may be electrically connected to a fourth conductive pattern (CP4) through a corresponding first via hole (VIH1) penetrating the seventh insulating layer (INS7). In addition, the other end of the second connection pattern (CNP2) may be electrically connected to a first bridge pattern (BRP1) formed of a sixth conductive layer (CL6) through a corresponding second via hole (VIH2).

[0302] The first bridge pattern (BRP1) may be formed of a sixth conductive layer (CL6). The first bridge pattern (BRP1) may be electrically connected to the second connection pattern (CNP2) through a corresponding second via hole (VIH2) penetrating the eighth insulating layer (INS8). The first bridge pattern (BRP1) may be electrically connected to the first semiconductor pattern (SCP1) of the seventh transistor (T7) and the first semiconductor pattern (SCP1) of the sixth transistor (T6) through the second connection pattern (CNP2) and the fourth conductive pattern (CP4). In one or more embodiments, the first bridge pattern (BRP1) may be electrically connected to an anode electrode (see "AE" in FIG. 8) of a light-emitting element (see "LED" in FIG. 8) through a third via hole (see "VIH3" in FIG. 8) penetrating the ninth insulating layer (INS9).

[0303] The seventh gate electrode may be an area of ​​the first wiring (WL1) that overlaps the seventh active pattern (ACT7).

[0304] The eighth transistor (T8) may include an eighth active pattern (ACT8) and an eighth gate electrode.

[0305] The eighth active pattern (ACT8) may be a region of the first semiconductor pattern (SCP1) overlapping the first wiring (WL1). The first semiconductor pattern (SCP1) may be formed of a first semiconductor layer. The eighth active pattern (ACT8) may be a channel region of the eighth transistor (T8).

[0306] An area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to one side of the eighth active pattern (ACT8) (for example, an upper side of the eighth active pattern (ACT8) in a plan view) may be a first contact area, and an area of ​​the first semiconductor pattern (SCP1) that does not overlap with the first wiring (WL1) and is connected to the other side of the eighth active pattern (ACT8) (for example, a lower side of the eighth active pattern (ACT8) in a plan view) may be a second contact area. The first contact area may be connected to one side of the eighth active pattern (ACT8) and may be electrically connected to a twelfth wiring (WL12). The second contact area may be connected to the other side of the eighth active pattern (ACT8) and may be electrically connected to a second conductive pattern (CP2).

[0307] The 12th wiring (WL12) composed of the 4th conductive layer (CL4) can be electrically connected to the first contact area of ​​the first semiconductor pattern (SCP1) of the 8th transistor (T8) through the first contact portion (CNT1) penetrating the 6th insulating layer (INS6), the 5th insulating layer (INS5), the 4th insulating layer (INS4), the 3rd insulating layer (INS3), and the 2nd insulating layer (INS2).

[0308] The second conductive pattern (CP2) is formed of a fourth conductive layer (CL4) and can be electrically connected to a second contact area of ​​the first semiconductor pattern (SCP1) of the eighth transistor (T8) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the second conductive pattern (CP2) can be electrically connected to the first semiconductor pattern (SCP1) of the fifth transistor (T5) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2).

[0309] The eighth gate electrode may be an area of ​​the first wiring (WL1) that overlaps the eighth active pattern (ACT8).

[0310] The storage capacitor (Cst) may include a lower electrode (LE) and an upper electrode (UE).

[0311] The lower electrode (LE) may be formed integrally with the first gate electrode (GE1). The lower electrode (LE) may be composed of a first conductive layer (CL1).

[0312] The upper electrode (UE) may overlap the lower electrode (LE) and may be formed of a second conductive layer (CL2). The upper electrode (UE) may include an opening (OPN) from which a portion thereof is removed. A portion of the lower electrode (LE) overlapping the upper electrode (UE) may be exposed by the opening (OPN). The upper electrode (UE) may be electrically connected to the first conductive pattern (CP1).

[0313] The sensor circuit (SC) may be located between the second pixel circuit (PXC2) and the third pixel circuit (PXC3). However, this is not limited to this, and the location of the sensor circuit (SC) may be changed in various ways.

[0314] The sensor circuit (SC) may include a ninth transistor (T9), a tenth transistor (T10), and an eleventh transistor (T11).

[0315] The ninth transistor (T9) may include a ninth active pattern (ACT9) and a ninth gate electrode (GE9).

[0316] The ninth active pattern (ACT9) may be a region of the second semiconductor pattern (SCP2) overlapping the ninth gate electrode (GE9). The second semiconductor pattern (SCP2) may be formed of a first semiconductor layer. The second semiconductor pattern (SCP2) may be arranged to be spaced apart from the first semiconductor pattern (SCP1). The ninth active pattern (ACT9) may be a channel region of the ninth transistor (T9).

[0317] A region of the second semiconductor pattern (SCP2) that does not overlap with the ninth gate electrode (GE9) and is connected to one side of the ninth active pattern (ACT9) (for example, the left side of the ninth active pattern (ACT9) in a plan view) may be a first contact region. A region of the second semiconductor pattern (SCP2) that does not overlap with the ninth gate electrode (GE9) and is connected to the other side of the ninth active pattern (ACT9) (for example, the right side of the ninth active pattern (ACT9) in a plan view) may be a second contact region.

[0318] The first contact area may be connected to one side of the ninth active pattern (ACT9) and the second semiconductor pattern (SCP2) of the eleventh transistor (T11), respectively. The second contact area may be connected to the other side of the ninth active pattern (ACT9) and may be electrically connected to the ninth conductive pattern (CP9).

[0319] The ninth conductive pattern (CP9) may be positioned within the first light-sensing pixel (PSR1) and may be formed of a fourth conductive layer (CL4). The ninth conductive pattern (CP9) may be electrically connected to a first contact area of ​​the ninth transistor (T9) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). In addition, the ninth conductive pattern (CP9) may be electrically connected to a seventh wiring (WL7) through a second contact portion (CNT2) penetrating the sixth insulating layer (INS6).

[0320] The ninth gate electrode (GE9) overlaps with the ninth active pattern (ACT9) and may be formed of a first conductive layer (CL1). The ninth gate electrode (GE9) may be an island-shaped conductive pattern. The ninth gate electrode (GE9) may be electrically connected to the tenth transistor (T10) through the tenth conductive pattern (CP10).

[0321] The tenth conductive pattern (CP10) may be formed of a fourth conductive layer (CL4). One end of the tenth conductive pattern (CP10) may be electrically connected to the ninth gate electrode (GE9) through a first contact portion (CNT1) penetrating the sixth insulating layer (INS6), the fifth insulating layer (INS5), the fourth insulating layer (INS4), the third insulating layer (INS3), and the second insulating layer (INS2). The other end of the tenth conductive pattern (CP1) may be electrically connected to the fourth semiconductor pattern (SCP4) of the tenth transistor (T10) through a second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5). In addition, the tenth conductive pattern (CP10) may be electrically connected to the sixth connection pattern (CNP6) through a first via hole (VIH1).

[0322] The sixth connection pattern (CNP6) may be formed of a fifth conductive layer (CL5). The sixth connection pattern (CNP6) may be electrically connected to the tenth conductive pattern (CP10) through a corresponding first via hole (VIH1) penetrating the seventh insulating layer (INS7). In addition, the sixth connection pattern (CNP6) may be electrically connected to the second bridge pattern (BRP2) through a second via hole (VIH2).

[0323] The second bridge pattern (BRP2) may be formed of a sixth conductive layer (CL6). The second bridge pattern (BRP2) may be electrically connected to the sixth connection pattern (CNP6) through a corresponding second via hole (VIH2) penetrating the eighth insulating layer (INS8). The second bridge pattern (BRP2) may be electrically connected to the ninth gate electrode (GE9) of the ninth transistor (T9) and the fourth semiconductor pattern (SCP4) of the tenth transistor (T10) through the sixth connection pattern (CNP6) and the tenth conductive pattern (CP10).

[0324] The second bridge pattern (BRP2) can be electrically connected to the first electrode (see "EL1" in FIG. 8) of the light-receiving element (see "LRD" in FIG. 8) of the sensor circuit (SC). The second bridge pattern (BRP2) can be formed by the same process as the first bridge pattern (BRP1), contain the same material, and be provided in the same layer.

[0325] The tenth transistor (T10) may include a tenth active pattern (ACT10) and a tenth gate electrode.

[0326] The tenth active pattern (ACT10) may be a region of the fourth semiconductor pattern (SCP4) overlapping the eleventh wiring (WL11). The fourth semiconductor pattern (SCP4) may be formed of a second semiconductor layer. The fourth semiconductor pattern (SCP4) may be arranged to be spaced apart from the third semiconductor pattern (SCP3). The tenth active pattern (ACT10) may be a channel region of the tenth transistor (T10).

[0327] A region of the fourth semiconductor pattern (SCP4) that does not overlap with the eleventh wiring (WL11) and is connected to one side of the tenth active pattern (ACT10) (for example, the upper side of the tenth active pattern (ACT10) in a plan view) may be a first contact region. A region of the fourth semiconductor pattern (SCP4) that does not overlap with the eleventh wiring (WL11) and is connected to the other side of the tenth active pattern (ACT10) (for example, the lower side of the tenth active pattern (ACT10) in a plan view) may be a second contact region.

[0328] The first contact area may be connected to one side of the tenth active pattern (ACT10) and may be electrically connected to the fifteenth wiring (WL15) through the second contact portion (CNT2) penetrating the sixth insulating layer (INS6) and the fifth insulating layer (INS5). The second contact area may be connected to the other side of the tenth active pattern (ACT10) and may be electrically connected to the ninth gate electrode (GE9) of the ninth transistor (T9) through the tenth conductive pattern (CP10).

[0329] The tenth gate electrode may be an area of ​​the eleventh wiring (WL11) overlapping the tenth active pattern (ACT10).

[0330] The eleventh transistor (T11) may have a dual gate structure in which sub-transistors are connected in series to prevent leakage current. For example, the eleventh transistor (T11) may include an 11a transistor (T11a) and an 11b transistor (T11b).

[0331] The 11a transistor (T11a) may include an 11a active pattern (ACT11a) and an 11a gate electrode.

[0332] The 11a active pattern (ACT11a) may be a region of the second semiconductor pattern (SCP2) overlapping the second wiring (WL2). The second semiconductor pattern (SCP2) may be formed of the first semiconductor layer. The 11a active pattern (ACT11a) may be a channel region of the 11a transistor (T11a).

[0333] A region of the second semiconductor pattern (SCP2) that does not overlap with the second wiring (WL2) and is connected to one side of the 11a active pattern (ACT11a) (for example, the upper side of the 11a active pattern (ACT11a) in a plan view) may be a first contact region. A region of the second semiconductor pattern (SCP2) that does not overlap with the second wiring (WL2) and is connected to the other side of the 11a active pattern (ACT11a) (for example, the lower side of the 11a active pattern (ACT11a) in a plan view) may be a second contact region.

[0334] The first contact area may be connected to one side of the 11a active pattern (ACT11a) and the second semiconductor pattern (SCP2) of the ninth transistor (T9), respectively. The second contact area may be connected to the other side of the 11a active pattern (ACT11a) and the second semiconductor pattern (SCP2) of the 11b transistor (T11b), respectively.

[0335] The 11a gate electrode may be an area of ​​the second wiring (WL2) overlapping the 11a active pattern (ACT11a).

[0336] The 11b transistor (T11b) may include an 11b active pattern (ACT11b) and an 11b gate electrode.

[0337] The 11b active pattern (ACT11b) may be a region of the second semiconductor pattern (SCP2) that overlaps with a protrusion protruding in the second direction (DR2) from the second wiring (WL2) extending along the first direction (DR1). The second semiconductor pattern (SCP2) may be formed of the first semiconductor layer. The 11b active pattern (ACT11b) may be a channel region of the 11b transistor (T11b).

[0338] An area of ​​the second semiconductor pattern (SCP2) that does not overlap with the protrusion of the second wiring (WL2) and is connected to one side of the 11b active pattern (ACT11b) (for example, the left side of the 11b active pattern (ACT11b) in a plan view) may be a first contact area. An area of ​​the second semiconductor pattern (SCP2) that does not overlap with the protrusion of the second wiring (WL2) and is connected to the other side of the 11b active pattern (ACT11b) (for example, the right side of the 11b active pattern (ACT11b) in a plan view) may be a second contact area.

[0339] The first contact area may be connected to each of the 11b active pattern (ACT11b) and the second semiconductor pattern (SCP2) of the 11a transistor (T11a). The second contact area may be connected to the 11b active pattern (ACT11b) and electrically connected to the 17th wiring (WL17) via the 8th conductive pattern (CP8).

[0340] In one or more embodiments, the seventeenth wiring (WL17) (or the lead-out line (RXk)) and the third data line (D3) may be formed of different conductive layers and positioned on different layers. For example, the seventeenth wiring (WL17) may be formed of a fifth conductive layer (CL5) and positioned on a seventh insulating layer (INS7), and the third data line (D3) may be formed of a sixth conductive layer (CL6) and positioned on an eighth insulating layer (INS8). In this case, a separation distance between the seventeenth wiring (WL17) (or the lead-out line (RXk)) and the third data line (D3) may be secured. In addition, when viewed in a plan view, a second vertical bridge line (BRL2_V) formed by the same process as the third data line (D3) may be positioned between the seventeenth wiring (WL17) (or the lead-out line (RXk)) and the third data line (D3). The second vertical bridge line (BRL2_V) may include a first sub-electrode (SUE1) and a second sub-electrode (SUE2) that are spaced apart from each other. The first sub-electrode (SUE1) may be electrically connected to a 13th wiring (WL13) corresponding to a horizontal bridge line (BRL_H) through the fourth and fifth connection patterns (CNP4, CNP5) constituting the pad electrode (PDE). The second sub-electrode (SUE2) may be electrically connected to a first power wiring (PL1) and may be supplied with the same voltage as the first power wiring (PL1), for example, a first power voltage (VDD). That is, a DC voltage having a constant voltage level may be applied to the second sub-electrode (SUE2).

[0341] A second sub-electrode (SUE2) supplied with a first power voltage (VDD) may be arranged between the 17th wiring (WL17) (or lead-out line (RXk)) and the third data line (D3) when viewed in a plan view. The second sub-electrode (SUE2) may be utilized as a shielding member that reduces or prevents coupling caps occurring between the 17th wiring (WL17) (or lead-out line (RXk)) and the third data line (D3). In other words, when the second sub-electrode (SUE2) is used as a shielding member and a distance is secured between the 17th wiring (WL17) (or the lead-out line (RXk)) and the third data line (D3), the phenomenon in which the data signal transmitted to the third data line (D3) (or the detection signal transmitted to the 17th wiring (WL17)) is affected by the detection signal transmitted to the 17th wiring (WL17) (or the data signal transmitted to the third data line (D3)) can be reduced or prevented. That is, the phenomenon in which the 17th wiring (WL17) (or the lead-out line (RXk)) is coupled with an adjacent data line, for example, the third data line (D3), can be reduced or prevented. Accordingly, noise generated in the detection signal applied to the 17th wiring (WL17) (or the lead-out line (RXk)) by the data signal applied to the third data line (D3) can be reduced. Accordingly, the fingerprint sensitivity and fingerprint sensing accuracy in the first photodetector pixel (PSR1) can be improved, thereby further improving the reliability of the display device (see “DD” in FIG. 1).

[0342] In addition, according to the above-described embodiment, the second sub-electrode (SUE2) can be used as a power wire by being electrically connected to the first power wire (PL1) and receiving the first power voltage (VDD). In this case, the wiring resistance of the first power wire (PL1) is reduced, thereby preventing a defect due to a signal delay of the first power wire (PL1).

[0343] FIG. 19 is a schematic plan view showing sub-pixels and light-sensing pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DD) of a display device according to one or more embodiments.

[0344] In Fig. 19, for convenience of explanation, only the components included in the fourth conductive layer, fifth conductive layer, and sixth conductive layer in the sub-pixels and light-sensing pixels arranged in the first and second pixel rows (R1, R2) are shown.

[0345] In Fig. 19, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0346] Referring to FIG. 19, in the first pixel row (R1), an eleventh sub-pixel (SPX11) (or a first sub-pixel), a twelfth sub-pixel (SPX12) (or a second sub-pixel), a thirteenth sub-pixel (SPX13) (or a third sub-pixel), and a fourteenth sub-pixel (SPX14) (or a fourth sub-pixel) may be arranged along a first direction (DR1). In the second pixel row (R2), a twenty-first sub-pixel (SPX21) (a first sub-pixel), a twenty-second sub-pixel (SPX22) (or a second sub-pixel), a twenty-third sub-pixel (SPX23) (or a third sub-pixel), and a twenty-fourth sub-pixel (SPX24) (or a fourth sub-pixel) may be arranged along a first direction (DR1). A first light-sensing pixel (PSR1) may be positioned between the 12th sub-pixel (SPX12) and the 13th sub-pixel (SPX13) in the first pixel row (R1). A second light-sensing pixel (PSR2) may be positioned between the 22nd sub-pixel (SPX22) and the 23rd sub-pixel (SPX23) in the second pixel row (R2).

[0347] A first horizontal bridge line (BRL1_H) (or a thirteenth wiring (WL13)) extending in a second direction (DR2) may be provided in a first pixel row (R1), and a second horizontal bridge line (BRL2_H) (or a thirteenth wiring (WL13)) extending in the second direction (DR2) and spaced apart from the first horizontal bridge line (BRL1_H) may be provided in a second pixel row (R2). According to one or more embodiments, the first horizontal bridge line (BRL1_H) (or the thirteenth wiring (WL13)) may extend in the first direction (DR1), and the second horizontal bridge line (BRL2_H) (or the thirteenth wiring (WL13)) may be spaced apart from the first horizontal bridge line (BRL1_H) and extend in the first direction (DR1).

[0348] The eleventh sub-pixel (SPX11) may include an eleventh pixel circuit (PXC11), the twelfth sub-pixel (SPX12) may include a twelfth pixel circuit (PXC12), the thirteenth sub-pixel (SPX13) may include a thirteenth pixel circuit (PXC13), and the fourteenth sub-pixel (SPX14) may include a fourteenth pixel circuit (PXC14). The first light-sensing pixel (PSR1) may include a first sensor circuit (SC1).

[0349] The 21st sub-pixel (SPX21) may include a 21st pixel circuit (PXC21), the 22nd sub-pixel (SPX22) may include a 22nd pixel circuit (PXC22), the 23rd sub-pixel (SPX23) may include a 23rd pixel circuit (PXC23), and the 24th sub-pixel (SPX23) may include a 24th pixel circuit (PXC24). The second light-sensing pixel (PSR2) may include a second sensor circuit (SC2).

[0350] A first vertical bridge line (BRL1_V) may be provided in common to the 12th sub-pixel (SPX12) and the 22nd sub-pixel (SPX22) adjacent in the second direction (DR2). A second vertical bridge line (BRL2_V) may be provided in common to the 13th sub-pixel (SPX13) and the 23rd sub-pixel (SPX23) adjacent in the second direction (DR2).

[0351] In one or more embodiments, the second vertical bridge line (BRL2_V) may be separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) by disconnecting (or removing) a region in a wiring separation area (WSA). The wiring separation area (WSA) may be a region in which the second vertical bridge line (BRL2_V) in the 23rd sub-pixel (SPX23) is separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) based on a 21st via hole (VIH21). The second vertical bridge line (BRL2_V) may include a first sub-electrode (SUE1) electrically connected to a pad electrode (PDE) in the 23rd sub-pixel (SPX23) and a second sub-electrode (SUE2) electrically separated from the pad electrode (PDE) and spaced apart from the first sub-electrode (SUE1) in a second direction (DR2).

[0352] The first sub-electrode (SUE1) may be electrically connected to a pad electrode (PDE) formed of a fifth conductive layer (see "CL5" in FIG. 15) through one second via hole (VIH2), for example, a twenty-first via hole (VIH21), penetrating the eighth insulating layer (see "INS8" in FIG. 18). The pad electrode (PDE) may be electrically connected to a second horizontal bridge line (BRL2_H) through one first via hole (VIH1) penetrating the seventh insulating layer (see "INS7" in FIG. 18).

[0353] The second sub-electrode (SUE2) may be electrically connected to the first power line (PL1) of the 23rd sub-pixel (SPX23) through a second via hole (VIH2), for example, the 22nd via hole (VIH22), which penetrates the 8th insulating layer (INS8). According to one or more embodiments, the second sub-electrode (SUE2) may also be electrically connected to the first power line (PL1) in the 13th sub-pixel (SPX13).

[0354] When viewed in a planar manner, the second sub-electrode (SUE2) may be positioned on the upper side of the first sub-electrode (SUE1) (or the 21st via hole (VIH21)). The second sub-electrode (SUE2) may extend from the upper side of the 21st via hole (VIH21) in the 23rd sub-pixel (SPX23) to the 13th sub-pixel (SPX13) in the opposite direction in the second direction (DR2).

[0355] In one or more embodiments, the second vertical bridge line (BRL2_V) may be separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) at a wiring separation area (WSA) located above a connection point (for example, a point where the 21st via hole (VIH21) is located) electrically connected to the second horizontal bridge line (BRL2_H). The first sub-electrode (SUE1) may be electrically connected to the second horizontal bridge line (BRL2_H) through a pad electrode (PDE) and may be electrically connected to a corresponding data line located in a first area (see "A1" of FIG. 3) of the display area (DA). That is, the first sub-electrode (SUE1) may be electrically connected to the second horizontal bridge line (BRL2_H) and utilized as the bridge line (BRL) described with reference to FIGS. 3 and 4. The second sub-electrode (SUE2) may be electrically connected to the first power line (PL1) through the 22nd via hole (VIH22) and may be utilized as the first power line (PL1). Accordingly, a first power voltage (refer to “VDD” in FIG. 7) having a constant voltage level may be supplied to the second sub-electrode (SUE2). When viewed in a plan view, the second sub-electrode (SUE2) supplied with the first power voltage (VDD) may be disposed between the 17th wire (WL17) (or lead-out line) and the third data line (D3) and may be utilized as a shielding member that reduces or prevents coupling caps that may occur between the 17th wire (WL17) and the third data line (D3).

[0356] In the above-described embodiments, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) is electrically connected to the first power line (PL1) and supplied with the first power voltage (VDD), but is not limited thereto. According to one or more embodiments, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) may be electrically connected to another power line supplied with a DC voltage having a constant voltage level. For example, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) may be electrically connected to an electrode (refer to "EP" in FIG. 7) supplied with the second power voltage (refer to "VSS" in FIG. 7).

[0357] FIG. 20 is a schematic diagram showing the connection relationship of some wires in one area of ​​a display area (DA) of a display device according to one or more embodiments.

[0358] In Fig. 20, for convenience of explanation, only some signal wirings in the sub-pixels and light-sensing pixels arranged in each of the first to fourth pixel rows (R1 to R4) are illustrated.

[0359] In Fig. 20, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0360] Referring to FIG. 20, the display area (DA) may be divided into pixel rows (R1 to R4). The pixel rows (R1 to R4) may extend in a first direction (DR1) and be arranged in a second direction (DR2). Each of the pixel rows (R1 to R4) may include first to seventh sub-pixels (SPX1 to SPX7). The first to seventh sub-pixels (SPX1 to SPX7) may include pixel circuits. In addition, each of the pixel rows (R1 to R4) may include first to third photo-sensing pixels (PSR1 to PSR3). The first to third photo-sensing pixels (PSR1 to PSR3) may include sensor circuits.

[0361] In one or more embodiments, the sub-pixels (SPX1 to SPX7) may be arranged in the first direction (DR1) in the following order: a first sub-pixel (SPX1), a second sub-pixel (SPX2), a third sub-pixel (SPX3), a fourth sub-pixel (SPX4), a fifth sub-pixel (SPX5), a sixth sub-pixel (SPX6), and a seventh sub-pixel (SPX7) in each of the first to fourth pixel rows (R1 to R4). In each of the first to fourth pixel rows (R1 to R4), a first photo-sensing pixel (PSR1) may be arranged between the second sub-pixel (SPX2) and the third sub-pixel (SPX3), a second photo-sensing pixel (PSR2) may be arranged between the fourth sub-pixel (SPX4) and the fifth sub-pixel (SPX5), and a third photo-sensing pixel (PSR3) may be arranged between the sixth sub-pixel (SPX6) and the seventh sub-pixel (SPX7).

[0362] In the first pixel row (R1), pixel circuits (PXC11 to PXC17) corresponding to the sub-pixels (SPX1 to SPX7) of the first pixel row (R1) may be arranged along the first direction (DR1). In the first pixel row (R1), sensor circuits (SC11 to SC13) corresponding to the light-sensing pixels (PSR1 to PSR3) of the first pixel row (R1) may be arranged along the first direction (DR1).

[0363] In the second pixel row (R2), pixel circuits (PXC21 to PXC27) corresponding to the sub-pixels (SPX1 to SPX7) of the second pixel row (R2) may be arranged along the first direction (DR1). In the second pixel row (R2), sensor circuits (SC21 to SC23) corresponding to the light-sensing pixels (PSR1 to PSR3) of the second pixel row (R2) may be arranged along the first direction (DR1).

[0364] In the third pixel row (R3), pixel circuits (PXC31 to PXC37) corresponding to the sub-pixels (SPX1 to SPX7) of the third pixel row (R3) may be arranged along the first direction (DR1). In the third pixel row (R3), sensor circuits (SC31 to SC33) corresponding to the light-sensing pixels (PSR1 to PSR3) of the third pixel row (R3) may be arranged along the first direction (DR1).

[0365] In the fourth pixel row (R4), pixel circuits (PXC41 to PXC47) corresponding to the sub-pixels (SPX1 to SPX7) of the fourth pixel row (R4) may be arranged along the first direction (DR1). In the fourth pixel row (R4), sensor circuits (SC41 to SC43) corresponding to the light-sensing pixels (PSR1 to PSR3) of the fourth pixel row (R4) may be arranged along the first direction (DR1).

[0366] A first horizontal bridge line (BRL1_H) may be arranged in the first pixel row (R1), a second horizontal bridge line (BRL2_H) may be arranged in the second pixel row (R2), a third horizontal bridge line (BRL3_H) may be arranged in the third pixel row (R3), and a fourth horizontal bridge line (BRL4_H) may be arranged in the fourth pixel row (R4).

[0367] A first vertical bridge line (BRL1_V), a first data line (D1), and a first power line (PL1) may be arranged in the first sub-pixels (SPX1) of the first to fourth pixel rows (R1 to R4). A second vertical bridge line (BRL2_V), a second data line (D2), and a first power line (PL1) may be arranged in the second sub-pixels (SPX2) of the first to fourth pixel rows (R1 to R4). A third vertical bridge line (BRL3_V), a third data line (D3), and a first power line (PL1) may be arranged in the third sub-pixels (SPX3) of the first to fourth pixel rows (R1 to R4). A fourth vertical bridge line (BRL4_V), a fourth data line (D4), and a first power line (PL1) may be arranged in the fourth sub-pixels (SPX4) of the first to fourth pixel rows (R1 to R4). A fifth vertical bridge line (BRL5_V), a fifth data line (D5), and a first power line (PL1) may be arranged in the fifth sub-pixels (SPX5) of the first to fourth pixel rows (R1 to R4). A sixth vertical bridge line (BRL6_V), a sixth data line (D6), and a first power line (PL1) may be arranged in the sixth sub-pixels (SPX6) of the first to fourth pixel rows (R1 to R4). A seventh vertical bridge line (BRL7_V), a seventh data line (D7), and a first power line (PL1) may be arranged in the seventh sub-pixels (SPX7) of the first to fourth pixel rows (R1 to R4).

[0368] A first readout line (RX1) may be arranged in the first photosensitive pixel (PSR1) of the first to fourth pixel rows (R1 to R4). A second readout line (RX2) may be arranged in the second photosensitive pixel (PSR2) of the first to fourth pixel rows (R1 to R4). A third readout line (RX3) may be arranged in the third photosensitive pixel (PSR3) of the first to fourth pixel rows (R1 to R4).

[0369] When viewed on a plane, a third vertical bridge line (BRL3_V) may be arranged between the first lead-out line (RX1) and the third data line (D3), a fifth vertical bridge line (BRL5_V) may be arranged between the second lead-out line (RX2) and the fifth data line (D5), and a seventh vertical bridge line (BRL7_V) may be arranged between the third lead-out line (RX3) and the seventh data line (D7).

[0370] Each of the third, fifth, and seventh vertical bridge lines (BRL3_V, BRL5_V, BRL7_V) may be separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) by removing a region from the wiring separation area (WSA). In other words, each of the third, fifth, and seventh vertical bridge lines (BRL3_V, BRL5_V, BRL7_V) may include a first sub-electrode (SUE1) and a second sub-electrode (SUE2) that are spaced apart from each other. The first sub-electrode (SUE1) and the second sub-electrode (SUE2) may be positioned in the same row in the second direction (DR2).

[0371] The first sub-electrode (SUE1) of each of the third, fifth, and seventh vertical bridge lines (BRL3_V, BRL5_V, BRL7_V) may be electrically connected to a corresponding horizontal bridge line through a second via hole (VIH2). For example, the first sub-electrode (SUE1) of the third vertical bridge line (BRL3_V) may be electrically connected to the fourth horizontal bridge line (BRL4_H) through a twenty-first via hole (VIH21). The first sub-electrode (SUE1) of the fifth vertical bridge line (BRL5_V) may be electrically connected to the third horizontal bridge line (BRL3_H) through a twenty-first via hole (VIH21). The first sub-electrode (SUE1) of the seventh vertical bridge line (BRL7_V) can be electrically connected to the second horizontal bridge line (BRL2_H) through the twenty-first via hole (VIH21).

[0372] The second sub-electrode (SUE2) of each of the third, fifth, and seventh vertical bridge lines (BRL3_V, BRL5_V, BRL7_V) may be electrically connected to the first power line (PL1) through the second via hole (VIH2). For example, the second sub-electrode (SUE2) of the third vertical bridge line (BRL3_V) may be electrically connected to the first power line (PL1) arranged in the third sub-pixel (SPX3) of the fourth pixel row (R4) through the twenty-second via hole (VIH22). The second sub-electrode (SUE2) of the fifth vertical bridge line (BRL5_V) may be electrically connected to the first power line (PL1) of the fifth sub-pixel (SPX5) of the third pixel row (R3) through the twenty-second via hole (VIH22). The second sub-electrode (SUE2) of the seventh vertical bridge line (BRL7_V) can be electrically connected to the first power wiring (PL1) of the seventh sub-pixel (SPX7) of the second pixel row (R2) through the 22nd via hole (VIH22).

[0373] The second sub-electrode (SUE2) of the third vertical bridge line (BRL3_V) may extend from the fourth pixel row (R4) to the first pixel row (R1) in the opposite direction of the second direction (DR2) based on the 21st via hole (VIH21) (or wiring separation area (WSA)), which is a connection point between the fourth horizontal bridge line (BRL4_H) and the first sub-electrode (SUE1) of the third vertical bridge line (BRL3_V).

[0374] The second sub-electrode (SUE2) of the fifth vertical bridge line (BRL5_V) may extend from the third pixel row (R3) to the first pixel row (R1) in the opposite direction of the second direction (DR2) based on the 21st via hole (VIH21) (or wiring separation area (WSA)), which is a connection point between the third horizontal bridge line (BRL3_H) and the first sub-electrode (SUE1) of the fifth vertical bridge line (BRL5_V).

[0375] The second sub-electrode (SUE2) of the seventh vertical bridge line (BRL7_V) may extend from the second pixel row (R2) to the first pixel row (R1) in the opposite direction of the second direction (DR2) based on the twenty-first via hole (VIH21) (or wiring separation area (WSA)), which is a connection point between the second horizontal bridge line (BRL2_H) and the first sub-electrode (SUE1) of the seventh vertical bridge line (BRL7_V).

[0376] The second sub-electrode (SUE2) of the third vertical bridge line (BRL3_V) is electrically connected to a corresponding first power line (PL1) and can receive a first power voltage (refer to “VDD” in FIG. 7) from the first power line (PL1). The second sub-electrode (SUE2) of the third vertical bridge line (BRL3_V) is arranged between the first readout line (RX1) and the third data line (D3) to reduce or prevent a coupling cap that may occur between the first readout line (RX1) and the third data line (D3).

[0377] The second sub-electrode (SUE2) of the fifth vertical bridge line (BRL5_V) is electrically connected to a corresponding first power line (PL1) and can receive a first power voltage (VDD) from the first power line (PL1). The second sub-electrode (SUE2) of the fifth vertical bridge line (BRL5_V) is arranged between the second readout line (RX2) and the fifth data line (D5) to reduce or prevent coupling caps that may occur between the second readout line (RX2) and the fifth data line (D5).

[0378] The second sub-electrode (SUE2) of the seventh vertical bridge line (BRL7_V) is electrically connected to a corresponding first power line (PL1) and can receive a first power voltage (VDD) from the first power line (PL1). The second sub-electrode (SUE2) of the seventh vertical bridge line (BRL7_V) is arranged between the third readout line (RX3) and the seventh data line (D7) to reduce or prevent coupling caps that may occur between the third readout line (RX3) and the seventh data line (D7).

[0379] FIG. 21 is a schematic plan view showing sub-pixels and light-sensing pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DD) of a display device according to one or more embodiments, FIG. 22 is a schematic enlarged view showing a portion EA2 of FIG. 21, and FIG. 23 is a schematic cross-sectional view taken along lines II to II' of FIG. 22.

[0380] For convenience of explanation, in FIGS. 21 to 23, only the components included in the fourth conductive layer (CL4), the fifth conductive layer (CL5), and the sixth conductive layer (CL6) in the sub-pixels and light-sensing pixels arranged in the first and second pixel rows (R1, R2) are illustrated.

[0381] In Figs. 21 to 23, in order to avoid redundant explanation, differences from the above-described embodiment will be explained.

[0382] Referring to FIGS. 21 to 23, a first horizontal bridge line (BRL1_H) (or a thirteenth wiring (WL13)) extending along a second direction (DR2) may be provided to a first pixel row (R1), and a second horizontal bridge line (BRL2_H) (or a thirteenth wiring (WL13)) extending along the second direction (DR2) and spaced apart from the first horizontal bridge line (BRL1_H) may be provided to a second pixel row (R2). A second vertical bridge line (BRL2_V) may be commonly provided to a thirteenth sub-pixel (SPX13) and a thirteenth sub-pixel (SPX23) adjacent in the second direction (DR2). According to one or more embodiments, the first horizontal bridge line (BRL1_H) (or the thirteenth wiring (WL13)) may extend along the first direction (DR1), and the second horizontal bridge line (BRL2_H) (or the thirteenth wiring (WL13)) may be spaced apart from the first horizontal bridge line (BRL1_H) and may extend along the first direction (DR1).

[0383] In one or more embodiments, the second vertical bridge line (BRL2_V) may be separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) by disconnecting (or removing) a portion of the wiring separation area (WSA). The second vertical bridge line (BRL2_V) may include a first sub-electrode (SUE1) electrically connected to a second pad electrode (PDE2) in the 23rd sub-pixel (SPX23), and a second sub-electrode (SUE2) electrically separated from the second pad electrode (PDE2) and spaced apart from the first sub-electrode (SUE1) in the second direction (DR2).

[0384] The first sub-electrode (SUE1) may be electrically connected to a second pad electrode (PDE2) formed of a fifth conductive layer (CL5) through a second via hole (VIH2), for example, a twenty-first via hole (VIH21), penetrating the eighth insulating layer (INS8). The second pad electrode (PDE2) may be electrically connected to a second horizontal bridge line (BRL2_H) through a first via hole (VIH1), for example, an eleventh via hole (VIH11), penetrating the seventh insulating layer (INS7). The second horizontal bridge line (BRL2_H) may be electrically connected to a first sub-electrode (SUE1) of the second vertical bridge line (BRL2_V) through the second pad electrode (PDE2).

[0385] The second sub-electrode (SUE2) may be electrically connected to a first pad electrode (PDE1) formed of a fifth conductive layer (CL5) and arranged in a thirteenth sub-pixel (SPX13) through a second via hole (VIH2), for example, a twenty-third via hole (VIH23), penetrating the eighth insulating layer (INS8). The first pad electrode (PDE1) may be electrically connected to a first horizontal bridge line (BRL1_H) formed of a fourth conductive layer (CL4) through a first via hole (VIH1), for example, a thirteenth via hole (VIH13), penetrating the seventh insulating layer (INS7). In other words, the second sub-electrode (SUE2) may be electrically connected to the first horizontal bridge line (BRL1_H) through the first pad electrode (PDE1).

[0386] In one or more embodiments, the second sub-electrode (SUE2) may be electrically isolated from a second horizontal bridge line (BRL2_H) located in a second pixel row (R2) and electrically connected to a first horizontal bridge line (BRL1_H) located in a first pixel row (R1).

[0387] In one or more embodiments, the first horizontal bridge line (BRL1_H) may be electrically connected to a first connection pattern (CNP1) formed of a fifth conductive layer (CL5) in the twelfth sub-pixel (SPX12). The first connection pattern (CNP1) may be electrically connected to the first horizontal bridge line (BRL1_H) formed of a fourth conductive layer (CL4) through a first via hole (VIH1), for example, a twelfth via hole (VIH12), penetrating the seventh insulating layer (INS7). In addition, the first connection pattern (CNP1) may be electrically connected to an eighteenth wiring (WL18) formed of a sixth conductive layer (CL6) at a boundary between the eleventh sub-pixel (SPX11) and the twelfth sub-pixel (SPX12). For example, the 18th wiring (WL18) may be electrically connected to the first connection pattern (CNP1) through a second via hole (VIH2), for example, a 22nd via hole (VIH22), that penetrates the 8th insulating layer (INS8).

[0388] In one or more embodiments, the second sub-electrode (SUE2) electrically connected to the first horizontal bridge line (BRL1_H) may be electrically connected to the eighteenth wiring (WL18) via the first connection pattern (CNP1). The eighteenth wiring (WL18) may be supplied with the second initialization power voltage (Vint2) described with reference to FIG. 7. The second initialization power voltage (Vint2) may be a DC voltage having a constant voltage level. When viewed in a plan view, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) supplied with the second initialization power voltage (Vint2) may be arranged between the seventeenth wiring (WL17) (or readout line) and the third data line (D3), thereby reducing or preventing a coupling cap that may occur between the seventeenth wiring (WL17) and the third data line (D3).

[0389] FIG. 24 is a schematic plan view showing sub-pixels and light-sensitive pixels arranged in first and second pixel rows (R1, R2) located in one area of ​​a display area (DA) of a display device according to one or more embodiments, and FIG. 25 is a schematic enlarged view showing part EA3 of FIG. 24.

[0390] In FIGS. 24 and 25, for convenience of explanation, only the components included in the fourth conductive layer (CL4), the fifth conductive layer (CL5), and the sixth conductive layer (CL6) in the sub-pixels and light-sensing pixels arranged in the first and second pixel rows (R1, R2) are illustrated.

[0391] In Figs. 24 and 25, in order to avoid redundant explanation, the differences from the above-described embodiment will be explained.

[0392] Referring to FIGS. 24 and 25, a first horizontal bridge line (BRL1_H) (or a 13th wiring (WL13)) extending in a second direction (DR2) may be provided to a first pixel row (R1), and a second horizontal bridge line (BRL2_H) (or a 13th wiring (WL13)) extending in the second direction (DR2) and spaced apart from the first horizontal bridge line (BRL1_H) may be provided to a second pixel row (R2). A second vertical bridge line (BRL2_V) may be commonly provided to a 13th sub-pixel (SPX13) and a 23rd sub-pixel (SPX23) adjacent in the second direction (DR2). According to one or more embodiments, the first horizontal bridge line (BRL1_H) (or the thirteenth wiring (WL13)) may extend along the first direction (DR1), and the second horizontal bridge line (BRL2_H) (or the thirteenth wiring (WL13)) may be spaced apart from the first horizontal bridge line (BRL1_H) and may extend along the first direction (DR1).

[0393] In one or more embodiments, the second vertical bridge line (BRL2_V) may be separated into a first sub-electrode (SUE1) and a second sub-electrode (SUE2) by disconnecting (or removing) a portion of the wiring separation area (WSA). The second vertical bridge line (BRL2_V) may include a first sub-electrode (SUE1) electrically connected to a second pad electrode (PDE2) in the 23rd sub-pixel (SPX23), and a second sub-electrode (SUE2) electrically separated from the second pad electrode (PDE2) and spaced apart from the first sub-electrode (SUE1) in the second direction (DR2).

[0394] In one or more embodiments, the second sub-electrode (SUE2) may be electrically connected to a first pad electrode (PDE1) disposed in the 13th sub-pixel (SPX13) and may be electrically connected to a first horizontal bridge line (BRL1_H) through the first pad electrode (PDE1). The second sub-electrode (SUE2) may be electrically isolated from a second horizontal bridge line (BRL2_H) located in a second pixel row (R2) and electrically connected to the first horizontal bridge line (BRL1_H) located in a first pixel row (R1).

[0395] In one or more embodiments, the first horizontal bridge line (BRL1_H) may be electrically connected to a first connection pattern (CNP1) formed of a fifth conductive layer (CL5) in the 13th sub-pixel (SPX13). The first connection pattern (CNP1) may be electrically connected to a first horizontal bridge line (BRL1_H) formed of a fourth conductive layer (CL4) through a first via hole (VIH1), for example, a twelfth via hole (VIH12), which penetrates the seventh insulating layer (see "INS7" in FIG. 23). In addition, the first connection pattern (CNP1) may be electrically connected to a nineteenth wiring (WL19) formed of a sixth conductive layer (CL6) at a boundary between the 13th sub-pixel (SPX13) and the 14th sub-pixel (SPX14). For example, the 19th wiring (WL19) may be electrically connected to the first connection pattern (CNP1) through a second via hole (VIH2), for example, a 22nd via hole (VIH22), that penetrates the 8th insulating layer (see “INS8” in FIG. 23).

[0396] In one or more embodiments, the second sub-electrode (SUE2) electrically connected to the first horizontal bridge line (BRL1_H) may be electrically connected to the nineteenth wiring (WL19) via the first connection pattern (CNP1). The nineteenth wiring (WL19) may be supplied with the first initialization power voltage (Vint1) described with reference to FIG. 7. The first initialization power voltage (Vint1) may be a DC voltage having a constant voltage level. When viewed in a plan view, the second sub-electrode (SUE2) of the second vertical bridge line (BRL2_V) supplied with the first initialization power voltage (Vint1) may be arranged between the seventeenth wiring (WL17) (or readout line) and the third data line (D3), thereby reducing or preventing a coupling cap that may occur between the seventeenth wiring (WL17) and the third data line (D3).

[0397] FIG. 26 is a schematic block diagram showing an electronic device (1000) according to one or more embodiments, FIG. 27 is a schematic drawing showing an example in which the electronic device (1000) of FIG. 26 is implemented as a smartphone, and FIG. 28 is a schematic drawing showing an example in which the electronic device (1000) of FIG. 26 is implemented as a tablet PC.

[0398] Referring to FIGS. 26 to 28, the electronic device (1000) may include a processor (1010), a memory device (1020), a storage device (1030), an input / output device (1040), a power supply (1050), and a display device (1060). In this case, the display device (1060) may be the display device (DD) of FIGS. 1 and 2. In addition, the electronic device (1000) may further include several ports that may communicate with a video card, a sound card, a memory card, a USB device, or the like, or communicate with other systems. In one or more embodiments, as illustrated in FIG. 27, the electronic device (1000) may be implemented as a smartphone. In one or more other embodiments, as illustrated in FIG. 28, the electronic device (1000) may be implemented as a tablet PC. However, this is exemplary, and the electronic device (1000) is not limited to the above-described examples. For example, the electronic device (1000) may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a vehicle navigation system, a computer monitor, a laptop, a head-mounted display device, etc.

[0399] The processor (1010) may perform specific calculations or tasks. According to one or more embodiments, the processor (1010) may be a microprocessor, a central processing unit, an application processor, etc. The processor (1010) may be connected to other components via an address bus, a control bus, a data bus, etc. According to one or more embodiments, the processor (1010) may also be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

[0400] The memory device (1020) can store data necessary for the operation of the electronic device (1000). For example, the memory device (1020) may include a non-volatile memory device such as an Erasable Programmable Read-Only Memory (EPROM) device, an Electrically Erasable Programmable Read-Only Memory (EEPROM) device, a flash memory device, a Phase Change Random Access Memory (PRAM) device, a Resistance Random Access Memory (RRAM) device, a Nano Floating Gate Memory (NFGM) device, a Polymer Random Access Memory (PoRAM) device, a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM) device, and / or a volatile memory device such as a Dynamic Random Access Memory (DRAM) device, a Static Random Access Memory (SRAM) device, a mobile DRAM device, and the like.

[0401] The storage device (1030) may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc.

[0402] The input / output device (1040) may include input means such as a keyboard, keypad, touchpad, touchscreen, mouse, etc., and output means such as a speaker, printer, etc. According to one or more embodiments, a display device (1060) may be included in the input / output device (1040).

[0403] The power supply (1050) can supply power required for the operation of the electronic device (1000). For example, the power supply (1050) can be a power management integrated circuit (PMIC).

[0404] The display device (1060) can display an image corresponding to visual information of the electronic device (1000). At this time, the display device (1060) may be, but is not limited to, an organic light-emitting display device or a quantum dot light-emitting display device. The display device (1060) can be connected to other components via the above buses or other communication links.

[0405] Although the present disclosure has been described above with reference to embodiments thereof, it will be understood by those skilled in the art or having ordinary knowledge in the art that various modifications and changes to the present disclosure may be made without departing from the technical scope of the present disclosure as set forth in the claims to be described below.

[0406] Therefore, the technical scope of the present invention is not limited to the contents described in the detailed description of the specification, but may be defined by the patent claims.

Claims

1. First to third sub-pixels arranged along the first direction and each including a pixel circuit; A light-sensitive pixel including a sensor circuit; A data line electrically connected to each of the second and third sub-pixels; A readout line electrically connected to the above light-sensitive pixel; A horizontal bridge line extending along the first direction; a first vertical bridge line extending in the second direction and arranged in the second sub-pixel; and a second vertical bridge line extending in the second direction and arranged in the third sub-pixel; When viewed on a plane, the second vertical bridge line is arranged between the readout line and the data line of the third sub-pixel, A display device, wherein the second vertical bridge line includes a first sub-electrode and a second sub-electrode that are spaced apart from each other.

2. In paragraph 1, The first sub-electrode is electrically connected to the horizontal bridge line, A display device wherein the first sub-electrode and the second sub-electrode are electrically separated from each other.

3. In paragraph 2, A display device, wherein the data line, the first vertical bridge line, and the second vertical bridge line are arranged on the same layer.

4. In paragraph 3, Further comprising a reset voltage wiring electrically connected to the above light-sensitive pixel and configured to receive a reset voltage, The above reset voltage wiring is A first wiring line arranged on the same layer as the data line and the first and second vertical bridge lines and spaced apart from each other; A second wire disposed below the first wire and electrically connected to the first wire; and A display device comprising a third wiring positioned below the second wiring and electrically connected to the second wiring.

5. In paragraph 4, The third wiring extends in the first direction, the second wiring extends in the second direction, and the first wiring extends in the second direction. The above reset voltage wiring forms a mesh structure, the display device.

6. In paragraph 4, A first power wiring electrically connected to each of the first to third sub-pixels and configured to receive a first driving voltage; A second power wiring electrically connected to each of the first to third sub-pixels and configured to receive a second driving voltage; and Further comprising a third power supply wire electrically connected to each of the first to third sub-pixels and configured to receive a third driving voltage, A display device, wherein the first driving voltage, the second driving voltage, and the third driving voltage are direct current voltages having a constant voltage level.

7. In paragraph 6, A display device, wherein the second sub-electrode is electrically connected to at least one of the first power wiring, the second power wiring, and the third power wiring.

8. In paragraph 7, A display device in which the second sub-electrode is electrically connected to the first power wiring.

9. In paragraph 7, A display device, wherein the second sub-electrode is electrically connected to the second power wiring.

10. In paragraph 7, A display device in which the second sub-electrode is electrically connected to the third power wiring.

11. In paragraph 1, A display device wherein the light-sensitive pixel is disposed between the second sub-pixel and the third sub-pixel.

12. In paragraph 1, The first sub-pixel, the second sub-pixel, and the third sub-pixel each include a light-emitting element configured to emit light, A display device, wherein the light-sensitive pixel includes a light-receiving element configured to output a detection signal corresponding to the light.

13. In paragraph 1, A display device wherein the first sub-electrode and the second sub-electrode are electrically separated and arranged in the same column along the second direction.

14. In paragraph 13, A first via layer including a first via hole disposed on the horizontal bridge line and exposing an area of ​​the horizontal bridge line; A pad electrode disposed on the first via layer and electrically connected to the horizontal bridge line through the first via hole; and Further comprising a second via layer including a second via hole disposed on the pad electrode and exposing an area of ​​the pad electrode, A display device, wherein when viewed on a plane, the second vertical bridge line is separated into the first sub-electrode overlapping the second via hole near the second via hole and the second sub-electrode not overlapping the second via hole.

15. In paragraph 1, substrate; First, second, third, fourth, fifth, sixth, seventh, eighth, and ninth insulating layers sequentially arranged on the substrate; A first conductive layer disposed between the second insulating layer and the third insulating layer; A second conductive layer disposed between the third insulating layer and the fourth insulating layer; A third conductive layer disposed between the fifth insulating layer and the sixth insulating layer; A fourth conductive layer disposed between the sixth insulating layer and the seventh insulating layer; A fifth conductive layer disposed between the seventh insulating layer and the eighth insulating layer; and Further comprising a sixth conductive layer disposed between the eighth insulating layer and the ninth insulating layer, A display device, wherein the fourth conductive layer includes the horizontal bridge line, the fifth conductive layer includes the leadout line, and the sixth conductive layer includes the first and second vertical bridge lines and the data line.

16. First to third sub-pixels arranged along the first direction and each including a pixel circuit; A light-sensitive pixel including a sensor circuit and disposed between the second sub-pixel and the third sub-pixel; A data line electrically connected to each of the second and third sub-pixels; A readout line electrically connected to the above light-sensitive pixel; A horizontal bridge line extending along the first direction; A first vertical bridge line extending in the second direction and arranged in the second sub-pixel; A second vertical bridge line extending in the second direction and arranged in the third sub-pixel; and It includes a power wiring electrically connected to each of the first to third sub-pixels and configured to receive a first driving voltage, The second vertical bridge line includes a first sub-electrode and a second sub-electrode spaced apart from each other, A display device, wherein the first sub-electrode is electrically connected to the horizontal bridge line, and the second sub-electrode is electrically connected to the power wiring.

17. In paragraph 16, A display device, wherein when viewed on a plane, the second vertical bridge line is disposed between the readout line and the data line of the third sub-pixel.

18. In paragraph 17, A display device, wherein the second sub-electrode is a shielding member that prevents coupling cap between the readout line and the data line of the third sub-pixel.

19. A processor providing input image data to a display device; and Including the display device that displays an image based on the input image data, The above display device, First sub-pixel, second sub-pixel, and third sub-pixel arranged along the first direction; A light-sensitive pixel disposed between the second sub-pixel and the third sub-pixel; A data line electrically connected to each of the second and third sub-pixels; A readout line electrically connected to the above light-sensitive pixel; A horizontal bridge line extending along the first direction; a first vertical bridge line extending along the second direction and arranged in the second sub-pixel; and a second vertical bridge line extending along the second direction and arranged in the third sub-pixel; When viewed on a plane, the second vertical bridge line is arranged between the lead-out line and the third data line, The second vertical bridge line includes a first sub-electrode and a second sub-electrode spaced apart from each other, An electronic device wherein the first sub-electrode is electrically connected to the horizontal bridge line.

20. In paragraph 19, Further comprising a power wiring electrically connected to each of the first to third sub-pixels and configured to receive a first driving voltage, The first sub-electrode and the second sub-electrode are electrically separated, An electronic device wherein the second sub-electrode is electrically connected to the power wiring.

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