Shared unidirectional timing signals

Abstract

A multi-channel (e.g., two channel) memory device (e.g., dynamic random access memory —DRAM) shares a unidirectional read timing signal and a unidirectional write timing signal between the multiple channels. The write timing signal is transmitted to the memory device by a controller. The read timing signal is generated from the write timing signal by the memory device and transmitted to the controller. The write timing signal may be transmitted continuously. The read timing signal may be intermittently transmitted when any of the multiple channels are transmitting data to the controller. The command and address functions may be shared by the multiple channels. In an embodiment, the command and address functions may be separate for each of the multiple channels. A multi-channel device may comprise at least two identical memory device dies that are co-packaged and share unidirectional timing signals via an interface internal to the package.

Description

SHARED UNIDIRECTIONAL TIMING SIGNALSBRIEF DESCRIPTION OF THE DRAWINGS

[0001] Figure l is a block diagram illustrating a memory system.

[0002] Figure 2 is a block diagram illustrating a shared command / address bus memory system.

[0003] Figure 3 is a block diagram illustrating dual independent channel memory system.

[0004] Figure 4 is a block diagram illustrating a data buffered dual independent channel memory system.

[0005] Figure 5 is a block diagram illustrating a stacked die memory system.

[0006] Figure 6 is a block diagram illustrating a dual-channel memory device.

[0007] Figures 7A-7B are a timing diagrams illustrating an example method of operating a memory device.

[0008] Figure 8 is a block diagram illustrating a co-packaged memory die memory system.

[0009] Figure 9 is a flowchart illustrating a method of operating a memory device.

[0010] Figure 10 is a flowchart illustrating a method of operating a controller.

[0011] Figure 11 is a flowchart illustrating a method of transmitting data retrieved from memory arrays.

[0012] Figure 12 is a flowchart illustrating a method of receiving data retrieved from memory arrays.

[0013] Figure 13 is a flowchart illustrating a method of sharing timing signals.

[0014] Figure 14 is a block diagram illustrating a processing system.DETAILED DESCRIPTION OF THE EMBODIMENTS

[0015] In an embodiment, a multi-channel (e.g., two channel) memory device (e.g., dynamic random access memory — DRAM) shares a unidirectional read timing signal and a unidirectional write timing signal between the multiple channels. The write timing signal is transmitted to the memory device by a controller. The read timing signal is generated from the write timing signal by the memory device and transmitted to the controller. The write timing signal may be transmitted continuously. The read timing signal may be intermittently transmitted when any of the multiple channels are transmitting data to the controller.

[0016] In an embodiment, the command and address functions may be shared by the multiple channels. In an embodiment, the command and address functions may be separate for each of the multiple channels. In an embodiment, a multi-channel device may compriseat least two identical memory device dies that are co-packaged and share unidirectional timing signals via an interface internal to the package.

[0017] The descriptions and embodiments disclosed herein are made primarily with references to DRAM devices and DRAM memory arrays. This, however, should be understood to be a first example due at least to the widespread adoption of DRAM technology. It should be understood that other memory technologies may also benefit from the methods and / or apparatus described herein. These memory technologies include, but are not limited to static random access memory (SRAM), non-volatile memory (such as flash), conductive bridging random access memory (CBRAM — a.k.a., programmable metallization cell — PMC), resistive random access memory (a.k.a., RRAM or ReRAM), magnetoresistive random-access memory (MRAM), Spin-Torque Transfer (STT-MRAM), phase change memory (PCM), and the like, and / or combinations thereof. Accordingly, it should be understood that in the disclosures and / or descriptions given herein, these aforementioned technologies may be substituted for, included with, and / or encompassed within, the references to DRAM, DRAM devices, and / or DRAM arrays made herein.

[0018] Figure 1 is a block diagram illustrating a memory system. In Figure 1, memory system 100 comprises memory device 110 and memory controller 120. Memory device 110 includes read data strobe interface 113r, write strobe interface 113w, channel A datapath circuitry 114a, channel B datapath circuitry 114b, control circuitry 115, channel A memory array(s) 130a, channel B memory array(s) 130b, channel A interface 140a, and channel B interface 140b. Channel A interface 140a of memory device 110 is operatively coupled with channel A datapath circuitry 114a and control circuitry 115. Channel A datapath circuitry 114a is operatively coupled with memory array 130a and control circuitry 115. Memory array 130a is also operatively coupled with control circuitry 115. Channel B interface 140b of memory device 110 is operatively coupled with channel B datapath circuitry 114b and control circuitry 115. Channel B datapath circuitry 114b is operatively coupled with memory array 130b and control circuitry 115. Memory array 130b is also operatively coupled with control circuitry 115. Control circuitry 115 of memory device 110 is also operatively coupled with read data strobe interface 113r and write strobe interface 113w.

[0019] Controller 120 and memory device 110 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 120, manages the flow of data going to and from memory devices and / or memory modules. Memory device 110 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 110may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 110 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 120 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0020] Controller 120 includes read data strobe interface 123r, write strobe interface 123w, channel A datapath circuitry 124a, channel B datapath circuitry 124b, control circuitry 125, channel A interface 150a, and channel B interface 150b. Channel A interface 150a of controller 120 is operatively coupled with channel A datapath circuitry 124a and control circuitry 125. Channel A datapath circuitry 124a is also operatively coupled with control circuitry 115. Memory array 130a is also operatively coupled with control circuitry 115. Channel B interface 150b of controller 120 is operatively coupled with channel B datapath circuitry 124b and control circuitry 125. Channel B datapath circuitry 114b is also operatively coupled with control circuitry 125. Control circuitry 125 of controller 120 is also operatively coupled with read data strobe interface 123r and write strobe interface 123w.

[0021] Controller 120 is operatively coupled to channel A interface 140a of memory device 110 via channel A interface 150a. Controller 120 is operatively coupled to channel B interface 140b of memory device 110 via channel B interface 150b. Controller 120 is operatively coupled to read data strobe interface 113r of memory device 110 via read data strobe interface 123r. Controller 120 is operatively coupled to write strobe interface 113w of memory device 110 via write strobe interface 123w.

[0022] Channel A interface 140a includes command, address, and data transfer functions. Channel A interface 140a and channel A datapath circuitry 114a, under the control of control circuitry 115, access memory array 130a. Channel A interface 140a includes a command address (CA) bus interface and a data (DQ) bus interface. Channel B interface 140b includes command, address, and data transfer functions. Channel B interface 140b and channel B datapath circuitry 114b, under the control of control circuitry 115, access memory array 130b. Channel B interface 140b includes a command address (CA) bus interface and a data (DQ) bus interface. Channel A interface 140a is operated (e.g., receives commands and addresses and communicates data) to access memory array 130a independent of the accesses of memory array 130b via channel B interface 140b. Likewise, channel B interface 140b isoperated to access memory array 130b independent of the accesses of memory array 130a via channel A interface 140a.

[0023] In an embodiment, read data strobe interface 113r and read data strobe interface 123r communicate a timing reference signal (e.g., read data strobe) that is used to synchronize data transfers from memory device 110 to controller 120 via both channel A interface 140a (and thus also channel A interface 150a) and channel B interface 140b (and thus also channel B interface 150b). Similarly, in an embodiment, write strobe interface 113w and write strobe interface 123w communicate a timing reference signal (e.g., write data strobe or write clock) that is used to synchronize data transfers from controller 120 to memory device 110 via both channel A interface 140a (and thus also channel A interface 150a) and channel B interface 140b (and thus also channel B interface 150b).

[0024] Figure 2 is a block diagram illustrating a shared command / address bus memory system. In Figure 2, memory system 200 comprises memory device 210 and memory controller 220. Memory device 210 includes shared (channel A and channel B) command / address (CA) interface 211, read data strobe interface 213r, write strobe interface 213w, channel A datapath circuitry 214a, channel B datapath circuitry 214b, control circuitry 215, channel A memory array(s) 230a, channel B memory array(s) 230b, channel A data (DQ) interface 212a, and channel B data interface 212b. Shared CA interface 211 is operatively coupled with control circuitry 215. Channel A DQ interface 212a of memory device 210 is operatively coupled with channel A datapath circuitry 214a and control circuitry 215. Channel A datapath circuitry 214a is operatively coupled with memory array 230a and control circuitry 215. Memory array 230a is also operatively coupled with control circuitry 215. Channel B DQ interface 212b of memory device 210 is operatively coupled with channel B datapath circuitry 214b and control circuitry 215. Channel B datapath circuitry 214b is operatively coupled with memory array 230b and control circuitry 215. Memory array 230b is also operatively coupled with control circuitry 215. Control circuitry 215 of memory device 210 is also operatively coupled with read data strobe interface 213r and write strobe interface 213w.

[0025] Controller 220 and memory device 210 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 220, manages the flow of data going to and from memory devices and / or memory modules. Memory device 210 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 210 may be a device that adheres to, or is compatible with, a dynamic random access memory(DRAM) specification. In an embodiment, memory device 210 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 220 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0026] Controller 220 includes shared CA interface 221, read data strobe interface 223r, write strobe interface 223w, channel A datapath circuitry 224a, channel B datapath circuitry 224b, control circuitry 225, channel A DQ interface 222a, and channel B DQ interface 222b. Shared CA interface 221 is operatively coupled with control circuitry 225. Channel A DQ interface 222a of controller 220 is operatively coupled with channel A datapath circuitry 224a and control circuitry 225. Channel A datapath circuitry 224a is also operatively coupled with control circuitry 215. Memory array 230a is also operatively coupled with control circuitry 215. Channel B DQ interface 222b of controller 220 is operatively coupled with channel B datapath circuitry 224b and control circuitry 225. Channel B datapath circuitry 214b is also operatively coupled with control circuitry 225. Control circuitry 225 of controller 220 is also operatively coupled with read data strobe interface 223r and write strobe interface 223w.

[0027] Controller 220 is operatively coupled to CA interface 211 of memory device 210 via CA interface 221. Controller 220 is operatively coupled to channel A DQ interface 212a of memory device 210 via channel A DQ interface 222a. Controller 220 is operatively coupled to channel B DQ interface 212b of memory device 210 via channel B DQ interface 222b. Controller 220 is operatively coupled to read data strobe interface 213r of memory device 210 via read data strobe interface 223r. Controller 220 is operatively coupled to write strobe interface 213w of memory device 210 via write strobe interface 223 w.

[0028] Shared CA interface 211 includes command and address functions for accessing memory array 230a and memory array 230b. Channel A DQ interface 212a includes data transfer functions for accessing memory array 230a. Channel A DQ interface 212a and channel A datapath circuitry 214a, under the control of control circuitry 215, transfer data to / from memory array 230a. Channel B DQ interface 212b includes data transfer functions for accessing memory array 230b. Channel B DQ interface 212b and channel B datapath circuitry 214b, under the control of control circuitry 215, transfer data to / from memory array 230b.

[0029] In an embodiment, channel A DQ interface 212a is operated, with the exception of the time multiplexing (e.g., interleaving, alternating, and / or interspersing) of commands communicated via shared CA interface 211, to access memory array 230a independent of the accesses of memory array 230b via channel B DQ interface 212b. Likewise, in this embodiment, channel B DQ interface 212b is operated, with the exception of the time multiplexing (e.g., interleaving, alternating, and / or interspersing) of commands communicated via shared CA interface 211, to access memory array 230b independent of the accesses of memory array 230a via channel A DQ interface 212a. In an embodiment, commands communicated via shared CA interface 211 access both memory array 230a and memory array 230b in lockstep and are therefore not independent of the accesses to the other memory array 230a-230b.

[0030] In an embodiment, read data strobe interface 213r and read data strobe interface 223r communicate a timing reference signal (e.g., read data strobe) that is used to synchronize data transfers from memory device 210 to controller 220 via both channel A DQ interface 212a (and thus also channel A DQ interface 222a) and channel B DQ interface 212b (and thus also channel B DQ interface 222b). Similarly, in an embodiment, write strobe interface 213w and write strobe interface 223 w communicate a timing reference signal (e.g., write data strobe or write clock) that is used to synchronize data transfers from controller 220 to memory device 210 via both channel A DQ interface 212a (and thus also channel A DQ interface 222a) and channel B DQ interface 212b (and thus also channel B DQ interface 222b).

[0031] Figure 3 is a block diagram illustrating dual independent channel memory system. In Figure 3, memory system 300 comprises memory device 310 and memory controller 320. Memory device 310 includes channel A command / address (CA) interface 311a (CAA) and channel B CA interface 311b (CAB), read strobe interface 313r, write strobe interface 313w, channel A datapath circuitry 314a, channel B datapath circuitry 314b, control circuitry 315, channel A memory array(s) 330a, channel B memory array(s) 330b, channel A data (DQ) interface 312a, and channel B data interface 312b.

[0032] Channel A CA interface 31 la is operatively coupled with control circuitry 315. Channel A DQ interface 312a of memory device 310 is operatively coupled with channel A datapath circuitry 314a and control circuitry 315. Channel A datapath circuitry 314a is operatively coupled with memory array 330a and control circuitry 315. Memory array 330a is also operatively coupled with control circuitry 315.

[0033] Channel B CA interface 31 lb is operatively coupled with control circuitry 315. Channel B DQ interface 312b of memory device 310 is operatively coupled with channel B datapath circuitry 314b and control circuitry 315. Channel B datapath circuitry 314b is operatively coupled with memory array 330b and control circuitry 315. Memory array 330b is also operatively coupled with control circuitry 315. Control circuitry 315 of memory device 310 is also operatively coupled with read strobe interface 313r and write strobe interface 313w.

[0034] Controller 320 and memory device 310 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 320, manages the flow of data going to and from memory devices and / or memory modules. Memory device 310 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 310 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 310 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 320 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0035] Controller 320 includes channel A CA interface 321a, channel B CA interface 321b read strobe interface 323r, write strobe interface 323 w, channel A datapath circuitry 324a, channel B datapath circuitry 324b, control circuitry 325, channel A DQ interface 322a, and channel B DQ interface 322b. Channel A CA interface 321a is operatively coupled with control circuitry 325. Channel A DQ interface 322a of controller 320 is operatively coupled with channel A datapath circuitry 324a and control circuitry 325. Channel A datapath circuitry 324a is also operatively coupled with control circuitry 315.

[0036] Channel B CA interface 321b is operatively coupled with control circuitry 325. Channel B DQ interface 322b of controller 320 is operatively coupled with channel B datapath circuitry 324b and control circuitry 325. Channel B datapath circuitry 314b is also operatively coupled with control circuitry 325. Control circuitry 325 of controller 320 is also operatively coupled with read strobe interface 323r and write strobe interface 323w.

[0037] Controller 320 is operatively coupled to channel A CA interface 311a via channel A CA interface 321a. Controller 320 is operatively coupled to channel A DQ interface 312aof memory device 310 via channel A DQ interface 322a. Controller 320 is operatively coupled to channel B CA interface 311b via channel B CA interface 321b. Controller 320 is operatively coupled to channel B DQ interface 312b of memory device 310 via channel B DQ interface 322b. Controller 320 is operatively coupled to read strobe interface 313r of memory device 310 via read strobe interface 323r. Controller 320 is operatively coupled to write strobe interface 313w of memory device 310 via write strobe interface 323 w.

[0038] Channel A CA interface 311a includes command and address functions for accessing memory array 330a. Channel A DQ interface 312a includes data transfer functions for accessing memory array 330a. Channel A DQ interface 312a and channel A datapath circuitry 314a, under the control of control circuitry 315, transfer data to / from memory array 330a. Channel B CA interface 311b includes command and address functions for accessing memory array 330b. Channel B DQ interface 312b includes data transfer functions for accessing memory array 330b. Channel B DQ interface 312b and channel B datapath circuitry 314b, under the control of control circuitry 315, transfer data to / from memory array 330b.

[0039] Channel A CA interface 311a and channel A DQ interface 312a are operated (e.g., receives commands and addresses and communicates data) to access memory array 330a independent of the accesses of memory array 330b via Channel B CA interface 311b and channel B DQ interface 312b. Likewise, channel B CA interface 311b and channel B DQ interface 312b are operated (e.g., receives commands and addresses and communicates data) to access memory array 330b independent of the accesses of memory array 330a via Channel A CA interface 311a and channel A DQ interface 312a.

[0040] In an embodiment, read strobe interface 313r and read strobe interface 323r communicate a timing reference signal (e.g., read data strobe) that is used to synchronize data transfers from memory device 310 to controller 320 via both channel A DQ interface 312a (and thus also channel A DQ interface 322a) and channel B DQ interface 312b (and thus also channel B DQ interface 322b). Similarly, in an embodiment, write strobe interface 313w and write strobe interface 323w communicate a timing reference signal (e.g., write data strobe or write clock) that is used to synchronize data transfers from controller 320 to memory device 310 via both channel A DQ interface 312a (and thus also channel A DQ interface 322a) and channel B DQ interface 312b (and thus also channel B DQ interface 322b).

[0041] Figure 4 is a block diagram illustrating a data buffered dual independent channel memory system. In Figure 4, memory system 400 comprises memory device 410, memory controller 420, and data buffer 460. Memory device 410 includes channel Acommand / address (CA) interface 411a (CAA) and channel B CA interface 411b (CAB), read strobe interface 413r, write strobe interface 413w, channel A datapath circuitry 414a, channel B datapath circuitry 414b, control circuitry 415, channel A memory array(s) 430a, channel B memory array(s) 430b, channel A data (DQ) interface 412a, and channel B data interface 412b.

[0042] Channel A CA interface 41 la is operatively coupled with control circuitry 415. Channel A DQ interface 412a of memory device 410 is operatively coupled with channel A datapath circuitry 414a and control circuitry 415. Channel A datapath circuitry 414a is operatively coupled with memory array 430a and control circuitry 415. Memory array 430a is also operatively coupled with control circuitry 415.

[0043] Channel B CA interface 41 lb is operatively coupled with control circuitry 415. Channel B DQ interface 412b of memory device 410 is operatively coupled with channel B datapath circuitry 414b and control circuitry 415. Channel B datapath circuitry 414b is operatively coupled with memory array 430b and control circuitry 415. Memory array 430b is also operatively coupled with control circuitry 415. Control circuitry 415 of memory device 410 is also operatively coupled with read strobe interface 413r and write strobe interface 413w.

[0044] Controller 420, memory device 410, and data buffer (DB) 460 may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 420, manages the flow of data going to and from memory devices and / or memory modules. Memory device 410 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 410 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 410 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 420 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0045] Controller 420 includes channel A CA interface 421a, channel B CA interface 421b read strobe interface 423r, write strobe interface 423 w, channel A datapath circuitry 424a, channel B datapath circuitry 424b, control circuitry 425, channel A DQ interface 422a,and channel B DQ interface 422b. Channel A CA interface 421a is operatively coupled with control circuitry 425. Channel A DQ interface 422a of controller 420 is operatively coupled with channel A datapath circuitry 424a and control circuitry 425. Channel A datapath circuitry 424a is also operatively coupled with control circuitry 425.

[0046] Channel B CA interface 421b is operatively coupled with control circuitry 425. Channel B DQ interface 422b of controller 420 is operatively coupled with channel B datapath circuitry 424b and control circuitry 425. Channel B datapath circuitry 424b is also operatively coupled with control circuitry 425. Control circuitry 425 of controller 420 is also operatively coupled with read strobe interface 423r and write strobe interface 423w.

[0047] Data buffer 460 includes memory-side read strobe interface 463r, memory-side write strobe interface 463w, channel A datapath circuitry 464a, channel B datapath circuitry 464b, control circuitry 465, memory-side channel A DQ interface 462a, memory-side channel B DQ interface 462b, controller-side read strobe interface 468r, controller-side write strobe interface 468w, controller-side channel A DQ interface 467a, and controller-side channel B DQ interface 467b. Control circuitry 465 includes write strobe timing circuitry 466.

[0048] Memory-side channel A DQ interface 462a of data buffer 460 is operatively coupled with channel A datapath circuitry 464a and control circuitry 465. Channel A datapath circuitry 464a is also operatively coupled with control circuitry 465. Controller-side channel A DQ interface 467a of data buffer 460 is operatively coupled with channel A datapath circuitry 464a and control circuitry 465. Thus, it should be understood that memory-side channel A DQ interface 462a and controller-side channel A DQ interface 467a may be operatively coupled via channel A datapath circuitry 464a under the control of control circuitry 565.

[0049] Memory-side channel B DQ interface 462b of data buffer 460 is operatively coupled with channel B datapath circuitry 464b and control circuitry 465. Channel B datapath circuitry 464b is also operatively coupled with control circuitry 465. Controller-side channel B DQ interface 467b of data buffer 460 is operatively coupled with channel B datapath circuitry 464b and control circuitry 465. Thus, it should be understood that memory-side channel B DQ interface 462b and controller-side channel B DQ interface 467b may be operatively coupled via channel B datapath circuitry 464b under the control of control circuitry 565.

[0050] Controller 420 is operatively coupled to controller-side channel A DQ interface 467a of data buffer 460 via channel A DQ interface 422a. Memory device 410 is operatively coupled to memory-side channel A DQ interface 462a of data buffer 460 via memory-sidechannel A DQ interface 412a. Controller 420 is operatively coupled to controller-side channel B DQ interface 467b of data buffer 460 via channel B DQ interface 422b. Memory device 410 is operatively coupled to memory-side channel B DQ interface 462b of data buffer 460 via memory-side channel B DQ interface 412b. Controller 420 is operatively coupled to controller-side read strobe interface 468r of data buffer 460 via read strobe interface 423r. Controller 420 is operatively coupled to controller-side write strobe interface 468w of data buffer 460 via write strobe interface 423 w. Memory device 410 is operatively coupled to memory-side read strobe interface 463r of data buffer 460 via read strobe interface 413r. Memory device 410 is operatively coupled to memory-side write strobe interface 463 w of data buffer 460 via write strobe interface 413w.

[0051] Controller 420 is operatively coupled to channel A CA interface 411a via channel A CA interface 421a. Controller 420 is operatively coupled to channel B CA interface 411b via channel B CA interface 421b. Channel A CA interface 411a includes command and address functions for accessing memory array 430a. Channel A DQ interface 412a includes data transfer functions for accessing memory array 430a. Channel A DQ interface 412a and channel A datapath circuitry 414a, under the control of control circuitry 415, transfer data to / from memory array 430a. Channel B CA interface 411b includes command and address functions for accessing memory array 430b. Channel B DQ interface 412b includes data transfer functions for accessing memory array 430b. Channel B DQ interface 412b and channel B datapath circuitry 414b, under the control of control circuitry 415, transfer data to / from memory array 430b.

[0052] Channel A CA interface 411a and channel A DQ interface 412a are operated (e.g., receives commands and addresses and communicates data) to access memory array 430a independent of the accesses of memory array 430b via Channel B CA interface 411b and channel B DQ interface 412b. Likewise, channel B CA interface 411b and channel B DQ interface 412b are operated (e.g., receives commands and addresses and communicates data) to access memory array 430b independent of the accesses of memory array 430a via Channel A CA interface 411a and channel A DQ interface 412a.

[0053] In an embodiment, read strobe interface 413r, memory-side read strobe interface 463r, controller-side read strobe interface 468r, and read strobe interface 423r communicate a timing reference signal (e.g., read data strobe) that is used to synchronize data transfers from memory device 410 to data buffer 460 and from data buffer 460 to controller 420 via both channel A DQ interface 412a (and thus also memory-side channel A DQ interface 462a, controller-side channel A DQ interface 467a, and channel A DQ interface 422a) and channelB DQ interface 412b (and thus also memory-side channel B DQ interface 462b, controllerside channel B DQ interface 467b, and channel B DQ interface 422b). Similarly, in an embodiment, write strobe interface 423w, controller-side write strobe interface 468w, memory-side write strobe interface 463 w, and write strobe interface 413w communicate a timing reference signal (e.g., write data strobe or write clock) that is used to synchronize data transfers from controller 420 to memory device 410 via both channel A DQ interface 422a (and thus also controller-side channel A DQ interface 467a, memory-side channel A DQ interface 462a, and channel A DQ interface 412a) and channel B DQ interface 422b (and thus also controller-side channel B DQ interface 467b, memory-side channel B DQ interface 462b, and channel B DQ interface 412b).

[0054] In an embodiment, a buffer device (e.g., a RCD - not shown in Figure 4) may be operatively coupled between interface 421a and interface 411a, and also between interface 421b and interface 411b. This buffer device may redrive and / or retime the command and address signals. In an embodiment, this buffer device circuitry and / or functionality may be part of DB 460.

[0055] Control circuitry 465 includes write strobe timing circuitry 466. Write strobe timing circuitry 466 may, in some embodiments, clean up (e.g. reduce jitter) and / or phase align a write clock signal received via controller-side write strobe interface 468w before transmission by memory-side write strobe interface 463w. Write strobe timing circuitry 466 may include one or more of delay-locked loop circuitry, phase-locked loop circuitry, and phase interpolator circuitry.

[0056] Figure 5 is a block diagram illustrating a stacked die memory system. In Figure 5, memory system 500 comprises stacked die package 510 and memory controller 520. Stacked die package 510 includes die stack 590, channel A interface 540a, channel B interface 540b, write strobe interface 513w, die #0 read strobe interface 513r0, die #1 read strobe interface 513rl , and die #2 read strobe interface 513r2. Die stack 590 includes a plurality of stacked memory dies 591-593. Controller 520 includes channel A interface 550a, channel B interface 550b, write strobe interface 523w, die #0 read strobe interface 523r0, die #1 read strobe interface 523rl, and die #2 read strobe interface 523r2.

[0057] Channel A interface 550a of controller 520 is operatively coupled to channel A interface 540a of stacked die package 510. Channel B interface 550b of controller 520 is operatively coupled to channel B interface 540b of stacked die package 510. Write strobe interface 523 w of controller 520 is operatively coupled to write strobe interface 513w of stacked die package 510. Die #0 read strobe interface 523r0 of controller 520 is operativelycoupled to die #0 read strobe interface 523r0 of stacked die package 510. Die #1 read strobe interface 523rl of controller 520 is operatively coupled to die #1 read strobe interface 523rl of stacked die package 510. Die #2 read strobe interface 523r2 of controller 520 is operatively coupled to die #2 read strobe interface 523r2 of stacked die package 510.

[0058] Write strobe interface 513w is operatively coupled to memory die #0 591, memory die #1 592, and memory die #2 593 of die stack 590 to share a write strobe signal transmitted by controller 520 with each of memory die #0 591, memory die #1 592, and memory die #2 593 of die stack 590. Die #0 read strobe interface 523r0 of stacked die package 510 is operatively coupled to memory die #0 591 of die stack 590. Die #0 read strobe interface 523r0 of stacked die package 510 is operatively coupled to memory die #0 591 of die stack 590 to transmit a read strobe (e.g., derived from a write strobe from controller 520) from memory die #0 591 to controller 520. Die #1 read strobe interface 523rl of stacked die package 510 is operatively coupled to memory die #1 592 of die stack 590. Die #1 read strobe interface 523rl of stacked die package 510 is operatively coupled to memory die #1 592 of die stack 590 to transmit a read strobe (e.g., derived from a write strobe from controller 520) from memory die #1 591 to controller 520. Die #2 read strobe interface 523r2 of stacked die package 510 is operatively coupled to memory die #1 593 of die stack 590 to transmit a read strobe (e.g., derived from a write strobe from controller 520) from memory die #3 593 to controller 520.

[0059] Memory dies 591-593 of stacked die packages may be, comprise, or be examples of, memory device 110, memory device 210, memory device 310, and / or memory device 410. Thus, it should be understood that when stacked with other memory dies, memory device 110, memory device 210, memory device 310, and / or memory device 410 may share a write strobe signal. It should be understood that when stacked with other memory dies, memory device 110, memory device 210, memory device 310, and / or memory device 410 may each transmit separate read strobe signals back to a controller (e.g., controller 520).

[0060] Figure 6 is a block diagram illustrating a dual-channel memory device. In Figure 6, memory device 600 comprises read data strobe driver 613r, write clock (e.g., strobe signal and / or clock signal) receiver 613w, control circuitry 615, channel A memory array(s) 630a, channel B memory array(s) 630b, channel A data (DQ) receivers 641a, channel B DQ receivers 641b, channel A data drivers 642a, channel B data drivers 642b, channel A data write circuitry 651a, channel B data write circuitry 651b, channel A data read circuitry 652a, channel B data read circuitry 652b, read clock gating circuitry 661, channel A read strobe gating circuitry 662a, channel B read strobe gating circuitry 662b, write clock gating circuitry663, channel A write strobe gating circuitry 664a, channel B write strobe gating circuitry 664b, and read strobe gating circuitry 665. Control circuitry 615 includes input / output (IO) signal training circuitry 616.

[0061] In an embodiment, control circuitry 615 receives, from a controller, a single set of command / address signals. In an embodiment, the single set of command / address signals are used to access channel A memory array 630a and channel B memory array 630b concurrently based on the same commands and addresses and in lockstep. In an embodiment, the single set of command / address signals are time-multiplexed between commands / addresses used to access channel A memory array 630a and channel B memory array 630b independently. In an embodiment, control circuitry 615 receives, from a controller, two sets of command / address signals that operate independently of each other and are respectively used to independently access channel A memory array 630a and channel B memory array 630b (illustrated in Figure 6 by the dotted line arrow going to control circuitry 615 from a controller).

[0062] The inputs of channel A data receivers 641a receive data signals communicated from the controller for write accesses of channel A memory array 630a. The outputs of channel A data drivers 642a transmit data signals to the controller for read accesses of channel A memory array 630a. Similarly, the inputs of channel B data receivers 641b receive data signals communicated from the controller for write accesses of channel B memory array 630b. The outputs of channel B data drivers 642b transmit data signals to the controller for read accesses of channel B memory array 630b.

[0063] The outputs of channel A data receivers 641a are provided to channel A data write circuitry 651a. Channel A data write circuitry 651a writes, under the control of control circuitry 615 (e.g., based on commands / addresses received from the controller), data received via channel A data receivers 641a to memory array 630a. The outputs of channel B data receivers 641b are provided to channel B data write circuitry 651b. Channel B data write circuitry 651b writes, under the control of control circuitry 615 (e.g., based on commands / addresses received from the controller), data received via channel B data receivers 641b to memory array 630b.

[0064] Channel A data read circuitry 652a, under the control or control circuitry 615, reads data from memory array 630a (e.g., based on commands / addresses received from the controller). The outputs of channel A data read circuitry 652a is provided to channel A data drivers 642a for transmission to the controller. Similarly, channel B data read circuitry 652b, under the control or control circuitry 615, reads data from memory array 630b (e.g., based oncommands / addresses received from the controller). The outputs of channel B data read circuitry 652b is provided to channel B data drivers 642b for transmission to the controller.

[0065] To time the sampling of data from the controller by channel A data receivers 641a and channel B data receivers 641b, and to time the transmission of data to the controller by channel A data drivers 642a and channel B data drivers 642b, a write clock (WCLK) or alternately a write strobe (WDS) signal is received from the controller at the input of write clock receiver 613w. Write clock WCLK and / or write strobe WDS should be understood to be examples of external timing reference signals that may provided to memory device 600. The output of write clock receiver 613w is provided to the input of read clock gating circuitry 661 and the input of write clock gating circuitry 663. Under the control of control circuitry 615 (e.g., based on commands from the controller that are directed to channel A and to commands that are directed to channel B), write clock gating circuitry 663 selectively generates an internal write clock signal (iWCK) that is provided to channel A write strobe gating circuitry 664a and channel B write strobe gating circuitry 664b. Under the control of control circuitry 615 (e.g., based on commands from the controller that are directed to channel A and commands that are directed to channel B), read clock gating circuitry 661 selectively generates an internal read clock signal (iRCK) that is provided to channel A read strobe gating circuitry 662a and channel B write strobe gating circuitry 662b.

[0066] Under the control of control circuitry 615 (e.g., based on commands from the controller directed to channel A), channel A write strobe gating circuitry 664a selectively generates an internal write strobe signal iWSA (a.k.a., timing reference signal) that is provided to time the sampling of data signals by channel A data receivers 641a. Similarly, under the control of control circuitry 615 (e.g., based on commands from the controller directed to channel B), channel B write strobe gating circuitry 664b selectively generates an internal write strobe signal iWSB (a.k.a., timing reference signal) that is provided to time the sampling of data signals by channel B data receivers 641b.

[0067] Under the control of control circuitry 615 (e.g., based on commands from the controller directed to channel A), channel A read strobe gating circuitry 662a selectively generates an internal read strobe signal iRSA (a.k.a., timing reference signal) that is provided to time the transmission of data signals by channel A data drivers 642a. Similarly, under the control of control circuitry 615 (e.g., based on commands from the controller directed to channel B), channel B read strobe gating circuitry 662b selectively generates an internal read strobe signal iRSB (a.k.a., timing reference signal) that is provided to time the transmission of data signals by channel B data drivers 642b.

[0068] Internal read clock signal iRCK is also provided to read strobe gating circuitry 665. Under the control of control circuitry 615 (e.g., based on commands from the controller that are directed to channel A and commands that are directed to channel B), read strobe gating circuitry 665 selectively generates read strobe signal that is provided to the input of read data strobe driver 613r. Based on the signal from read strobe gating circuitry 665, read data strobe driver 613r transmits an external read timing reference signal RDQS to the controller to time the communication of data from either, or both, of channel A data drivers 642a and channel B data drivers 642b to the controller. The operation of memory device 600 is further illustrated by Figures 7A-7B.

[0069] Figures 7A-7B are timing diagrams illustrating an example method of operating a memory device. The timings, signals, and functions illustrated in Figures 7A-7B may be examples used by one or more of system 100, system 200, system 300, system 400, system 500, and / or memory device 600, and / or their components.

[0070] In Figures 7A-7B, a toggling clock signal CLK is illustrated. The sequence illustrated begins with two read commands (e.g., from a controller) on the command / address (CA) bus (e.g., received by control circuitry 615): a read command directed to channel A (RAI) followed immediately by a read command (RBI) directed to channel B (RBI). Based on the read command RAI and after a read access delay, data DAI is output on the channel A DQ (DQA) signal lines (e.g., by channel A data drivers 642a). This is illustrated in Figure 7B by arrow 701 running from the RAI command on the CA bus to the DAI data on the DQA bus. Based on the read command RBI and after a read access delay, and overlapping in part with the DAI data on the DQA bus, data DB 1 is output on the channel B DQ (DQB) signal lines (e.g., by channel A data drivers 642a). This is illustrated in Figure 7B by arrow 702 running from the RBI command on the CA bus to the DB1 data on the DQB bus.

[0071] To time the transfers of the DAI data on the DQA bus and the DB1 data on the DQB bus, an external read data strobe (RDQS) signal is output (e.g., by read data strobe driver 613r) and toggled during the time starting with the beginning of the DAI data on the DQA bus and ending with the end of the DB1 data on the DQB bus. This is illustrated in Figure 7B by arrow 703 running from the start of the toggling of RDQS to the start of the DAI data and arrow 704 running from the end of the toggling of RDQS to the end of the DB1 data.

[0072] The external read data strobe RDQS may be generated from (i.e., based on) an internal read strobe iRCK (e.g., by read data strobe driver 613r). This is illustrated in Figure 7B by arrow 705 running from the start of the toggling of internal read strobe iRCK to thestart of the toggling of external read strobe RDQS and arrow 706 running from the end of the toggling of iRCK to the end of the toggling of external read strobe RDQS.

[0073] To time the transmission of the DAI data on the DQA bus, an internal read strobe iRSA (e.g., clock input to channel A data drivers 642a) that is based on the internal read strobe iRCK, is toggled for the duration of the transmission of the DAI data. This is illustrated in Figure 7B by arrow 709 running from the first rising edge of iRCK (which aligns with the start of DAI data on the DQA bus) to the first rising edge of iRSA and by arrow 710 running from the eighth (8th) falling edge of iRCK (which aligns with the end of the DAI data on the DQA bus) to the last falling edge of iRSA. To time the transmission of the DB1 data on the DQB bus, an internal read strobe iRSB (e.g., clock input to channel B data drivers 642b) that is based on the internal read strobe iRCK, is toggled for the duration of the transmission of the DB1 data. This is illustrated in Figure 7B by arrow 711 running from the fourth rising edge of iRCK (which aligns with the start of DB1 data on the DQB bus) to the first rising edge of iRSB and by arrow 712 running from the last falling edge of iRCK (which aligns with the end of the DAI data on the DQA bus) to the last falling edge of iRSB.

[0074] In Figures 7A-7B, during the transmission of DAI on the DQA bus a second read command directed to channel A (RA2) is illustrated. Based on the second read command RAI directed to channel A, and after a read access delay, data DA2 is output on the channel A DQ (DQA) signal lines (e.g., by channel A data drivers 642a). Following the transmission of DB1 on the DQB bus, a write command directed to channel B (WB2) immediately followed by a third read command directed to channel A (RA3) are illustrated. To time the transmission of DA2 data on the DQA bus, RDQS, iRCK, and iRSA are illustrated as toggling for eight cycles during the transmission of DA2.

[0075] To time the reception of the write data DB2 from the controller, an internal write clock iWCLK (based on external write clock WCLK) and an internal write strobe iWSB (e.g., clock input to channel B data receivers 641b) toggle for eight cycles beginning with the start of the write data DB2 from the controller on the DQB bus. This is illustrated in Figure 7B by arrow 713 running from a rising edge of WCLK to the first rising edge of iWCLK and arrow 714 running from the first rising edge of iWSB to the start of the write data DB2 on the DQB bus.

[0076] To time the transfers of the DA3 data on the DQA bus, the external read data strobe (RDQS) signal is output (e.g., by read data strobe driver 613r) and toggled for eight cycles during the time starting with the beginning of the DA3 data on the DQA bus andending with the end of the DA3 data on the DQA bus. This is illustrated in Figure 7B by arrow 715 running from the start of the toggling of RDQS to the start of the DA3 data and arrow 716 running from the end of the toggling of RDQS to the end of the DA3 data.

[0077] Figure 8 is a block diagram illustrating a co-packaged memory die memory system. In Figure 8, memory system 800 comprises packaged multi-die memory device 850 and memory controller 820. Multi-die memory device 850 includes co-packaged memory device (die) 810a and memory device (die) 810b.

[0078] Memory device 810a includes command / address (CA) interface 811a, read data strobe interface 813ar, write clock interface 813aw, datapath circuitry 814a, control circuitry 815a, memory array(s) 830a, data (DQ) interface 812a, and timing signal interface 813a. CA interface 81 la is operatively coupled with control circuitry 815a. DQ interface 812a of memory device 810a is operatively coupled with datapath circuitry 814a and control circuitry 815a. Datapath circuitry 814a is operatively coupled with memory array 830a and control circuitry 815a. Memory array 830a is also operatively coupled with control circuitry 815a. Control circuitry 815a of memory device 810a is also operatively coupled with read data strobe interface 813ar, write clock interface 813aw, and control circuitry 815a. Control circuitry 815a is operatively coupled with timing signal interface 813a. Thus, it should be understood that one or more timing signals communicated via read data strobe interface 813ar and / or write clock interface 813aw may be communicated via control circuitry 815a and timing signal interface 813a.

[0079] Memory device 810b includes CA interface 811b, read strobe interface 813br, write strobe interface 813bw, datapath circuitry 814b, control circuitry 815b, memory array(s) 830b, DQ interface 812b, and timing signal interface 813b. CA interface 811b is operatively coupled with control circuitry 815b. DQ interface 812b of memory device 810b is operatively coupled with datapath circuitry 814b and control circuitry 815b. Datapath circuitry 814b is operatively coupled with memory array 830b and control circuitry 815b. Memory array 830b is also operatively coupled with control circuitry 815b. Control circuitry 815b of memory device 810b is also operatively coupled with read strobe interface 813br, write strobe interface 813bw, and control circuitry 815b. Control circuitry 815b is operatively coupled with timing signal interface 813b. Thus, it should be understood that one or more timing signals communicated via read strobe interface 813br and / or write strobe interface 813bw may be communicated via control circuitry 815b and timing signal interface 813b.

[0080] Controller 820, memory device 810a, and memory device 810b may be integrated circuit type devices, such as are commonly referred to as “chips”. A memory controller, such as controller 820, manages the flow of data going to and from memory devices and / or memory modules. Memory device 850 may be a standalone device, or may be a component of a memory module such as a DIMM module used in servers. In an embodiment, memory device 850 may be a device that adheres to, or is compatible with, a dynamic random access memory (DRAM) specification. In an embodiment, memory device 850 may be, or comprise, a device that is or includes other memory device technologies and / or specifications. A memory controller can be a separate, standalone chip, or integrated into another chip. For example, a memory controller 820 may be included on a single die with a microprocessor, included as a chip co-packaged with one or more microprocessor chips, included as part of a more complex integrated circuit system such as a block of a system on a chip (SOC), or be remotely coupled to one or more microprocessors via a fabric interconnect or other type of interconnect.

[0081] Controller 820 includes shared CA interface 821, read strobe interface 823r, write clock interface 823w, channel A datapath circuitry 824a, channel B datapath circuitry 824b, control circuitry 825, channel A DQ interface 822a, and channel B DQ interface 822b.Shared CA interface 821 is operatively coupled with control circuitry 825. Channel A DQ interface 822a of controller 820 is operatively coupled with channel A datapath circuitry 824a and control circuitry 825. Channel A datapath circuitry 824a is also operatively coupled with control circuitry 815. Memory array 830a is also operatively coupled with control circuitry 815. Channel B DQ interface 822b of controller 820 is operatively coupled with channel B datapath circuitry 824b and control circuitry 825. Channel B datapath circuitry 814b is also operatively coupled with control circuitry 825. Control circuitry 825 of controller 820 is also operatively coupled with read strobe interface 823r and write clock interface 823w.

[0082] Controller 820 is operatively coupled to CA interface 81 la of memory device 810a via CA interface 821 via connections internal to memory device 850. Controller 820 is operatively coupled to CA interface 81 lb of memory device 810b via CA interface 821 via connections internal to memory device 850. Memory device 810a is also operatively coupled to memory device 810b via timing signal interface 813a and timing signal interface 813b using connections internal to memory device 850.

[0083] Controller 820 is operatively coupled to DQ interface 812a of memory device 810a via channel A DQ interface 822a. Controller 820 is operatively coupled to DQ interface 812b of memory device 810b via channel B DQ interface 822b. Controller 820 is operativelycoupled to read data strobe interface 813ar of memory device 810a via read strobe interface 823r. Controller 820 is operatively coupled to write clock interface 813aw of memory device 810a via write strobe interface 823 aw.

[0084] CA interface 811a includes command and address functions for accessing memory array 830a. CA interface 811b includes command and address functions for accessing memory array 830b. DQ interface 812a includes data transfer functions for accessing memory array 830a of memory device 810a. DQ interface 812a and datapath circuitry 814a, under the control of control circuitry 815a, transfer data to / from memory array 830a.

[0085] CA interface 811b includes command and address functions for accessing memory array 830b. DQ interface 812b includes data transfer functions for accessing memory array 830b of memory device 810b. DQ interface 812b and channel A datapath circuitry 814b, under the control of control circuitry 815, transfer data to / from memory array 830b.

[0086] In an embodiment, DQ interface 812a is operated, with the exception of the time multiplexing of commands directed to CA interface 811a and CA interface 811b, to access memory array 830a independent of the accesses of memory array 830b via DQ interface 812b. Likewise, in this embodiment, DQ interface 812b is operated, with the exception of the time multiplexing of commands directed to CA interface 811a and CA interface 811b, to access memory array 830b independent of the accesses of memory array 830a via channel A DQ interface 812a. In an embodiment, commands communicated via communicated to CA interface 811a and CA interface 811b access both memory array 830a and memory array 830b in lockstep and are therefore not independent of the accesses to the other memory array 830a-430b.

[0087] In an embodiment, read data strobe interface 813ar and read strobe interface 823r communicate a timing reference signal (e.g., read data strobe) that is used to synchronize data transfers from memory device 810a to controller 820 via DQ interface 812a (and thus also channel A DQ interface 822a). Another timing reference signal (e.g., read data strobe) may be provided by memory device 810b via timing signal interface 813a, timing signal interface 813b, and read data strobe interface 813ar to read strobe interface 823r in order to synchronize data transfers from memory device 810b to controller 820 via DQ interface 812b (and thus also channel B DQ interface 822b).

[0088] Similarly, in an embodiment, write clock interface 813aw and write clock interface 823w communicate a timing reference signal (e.g., write data strobe or write clock) that is used to synchronize data transfers from controller 820 to memory device 810a via DQinterface 812a (and thus also channel A DQ interface 822a). A version of this timing reference signal (e.g., internal write data strobe or internal write clock) may be provided to memory device 810b via timing signal interface 813a, timing signal interface 813b in order to synchronize data transfers from controller 820 to memory device 810b via DQ interface 812b (and thus also channel B DQ interface 822b).

[0089] Figure 9 is a flowchart illustrating a method of operating a memory device. One or more steps illustrated in Figure 9 may be performed by, for example, system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and / or their components. A first memory array and a second memory array are accessed independent of accessing the other of the first memory array and the second memory array (902). For example, memory device 110 may access memory array 130a based on commands, addresses, and data transfers communicated via channel A interface 140a independent of the commands, addresses, and data transfers communicated via channel B interface 140b, and vice versa.

[0090] A first timing reference signal is received (904). For example, memory device 110 may receive, via write strobe interface 113w, a toggling write clock signal from controller 120. A second timing reference signal is transmitted (906). For example, during data communication from memory device 110 to controller 120 via either, or both, of channel A interface 140a and channel B interface 140b, memory device 110 may transmit, via read data strobe interface 113r, a data strobe signal to time the data communication.

[0091] Via a first data interface and synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array is received (908). For example, memory device 110 may receive, from controller 120 and synchronized by the write strobe signal from controller 120 (e.g., WCLK) received via write strobe interface 113w, first data via channel A interface 140a that is to be stored in memory array 130a (independent of any accesses to memory array 130b via channel B interface 140b). Via the first data interface and synchronously with respect to the second external timing reference signal, second data retrieved from the first memory array is transmitted (910). For example, memory device 110 may transmit, via channel A interface 140a, to controller 120, and synchronized by the read data strobe signal transmitted by memory device 110 (e.g., RDQS) via read data strobe interface 113r, second data retrieved from memory array 130a (independent of any accesses to memory array 130b via channel B interface 140b).

[0092] Via a second data interface and synchronously with respect to the first external timing reference signal, third data to be stored in the second memory array is received (912).For example, memory device 110 may receive, from controller 120 and synchronized by the write strobe signal from controller 120 (e.g., WCLK) received via write strobe interface 113w, third data via channel B interface 140b that is to be stored in memory array 130b (independent of any accesses to memory array 130a via channel A interface 140a). Via the second data interface and synchronously with respect to the second external timing reference signal, fourth data retrieved from the second memory array is transmitted (914). For example, memory device 110 may transmit, via channel B interface 140b, to controller 120, and synchronized by the read data strobe signal transmitted by memory device 110 (e.g., RDQS) via read data strobe interface 113r, fourth data retrieved from memory array 130a (independent of any accesses to memory array 130a via channel A interface 140a).

[0093] Figure 10 is a flowchart illustrating a method of operating a controller. One or more steps illustrated in Figure 10 may be performed by, for example, system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and / or their components. A first memory array of a memory device and a second memory array of the memory device are accessed independent of accessing the other of the first memory array and the second memory array (1002). For example, controller 120 may access memory array 130a based on commands, addresses, and data transfers communicated via channel A interface 150a independent of the commands, addresses, and data transfers communicated via channel B interface 150b, and vice versa.

[0094] A first timing reference signal is transmitted (1004). For example, controller 120 may transmit, via write strobe interface 123w, a toggling write clock signal to memory device 110. A second timing reference signal is received (1006). For example, during data communication from memory device 110 to controller 120 via either, or both, of channel A interface 150a and channel B interface 150b, controller 120 may receive, via read data strobe interface 123r, a data strobe signal to time the data communication from memory device 110.

[0095] Via a first data interface and synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array is transmitted (1008). For example, controller 120 may transmit, via channel A interface 150a, to memory device 110, and synchronized by the write strobe signal (e.g., WCLK) transmitted via write strobe interface 123w, first data that is to be stored in memory array 130a (independent of any accesses to memory array 130b via channel B interface 150b). Via the first data interface and synchronously with respect to the second external timing reference signal, second data retrieved from the first memory array is received (1010). For example, controller 120 may receive, via channel A interface 150a, from memory device 110, and synchronized by theread data strobe signal received from memory device 110 (e.g., RDQS) via read data strobe interface 123r, second data retrieved from memory array 130a (independent of any accesses to memory array 130b via channel B interface 150b).

[0096] Via a second data interface and synchronously with respect to the first external timing reference signal, third data to be stored in the second memory array is transmitted (1012). For example, controller 120 may transmit, via channel B interface 150b, to memory device 110, and synchronized by the write strobe signal (e.g., WCLK) transmitted via write strobe interface 123w, third data that is to be stored in memory array 130b (independent of any accesses to memory array 130a via channel A interface 150a). Via the second data interface and synchronously with respect to the second external timing reference signal, fourth data retrieved from the second memory array is received (1014). For example, controller 120 may receive, via channel B interface 150b, from memory device 110, and synchronized by the read data strobe signal received from memory device 110 (e.g., RDQS) via read data strobe interface 123r, fourth data retrieved from memory array 130b (independent of any accesses to memory array 130a via channel A interface 150a).

[0097] Figure 11 is a flowchart illustrating a method of transmitting data retrieved from memory arrays. One or more steps illustrated in Figure 11 may be performed by, for example, system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and / or their components. From a controller and via a command / address (CA) interface, a first command to read a first memory array and a second command to read a second memory array are received (1102). For example, memory device 210 may receive, via CA interface 211 and from controller 220, a first command to read data from memory array 230a and a second command to read data from memory array 230b.

[0098] From the controller and via a first timing signal interface, a first external timing reference signal is received (1104). For example, from controller 220 and via write strobe interface 213w, memory device 210 may receive a write clock signal. To the controller and via a second external timing reference signal interface, a second external timing reference signal that is based on the first external timing reference signal, the first command, and the second command, is transmitted (1106). For example, memory device 210 may transmit, via read data strobe interface 213r, a read data strobe signal derived from the write clock signal that toggles during the transmission of data associated with either, or both, of the first command and the second command.

[0099] Based on the first command, via a first data signal interface, and synchronously with respect to the second external timing reference signal, first data retrieved from the firstmemory array is transmitted (1108). For example, based on the first command to read data from memory array 230a, memory device 210 may transmit, via channel A data interface 212a and timed by the read data strobe signal transmitted via read data strobe interface 213r, data associated with the first command that was retrieved from memory array 230a. Based on the second command, via a second data signal interface, and synchronously with respect to the second external timing reference signal, second data retrieved from the second memory array is transmitted (1110). For example, based on the second command to read data from memory array 230b, memory device 210 may transmit, via channel B data interface 212b and timed by the read data strobe signal transmitted via read data strobe interface 213r, data associated with the second command that was retrieved from memory array 230b.

[0100] Figure 12 is a flowchart illustrating a method of receiving data retrieved from memory arrays. One or more steps illustrated in Figure 12 may be performed by, for example, system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and / or their components. To a memory device and via a command / address (CA) interface, a first command to read a first memory array of the memory device and a second command to read a second memory array of the memory device are transmitted (1202). For example, controller 220 may transmit, via CA interface 221 and to memory device 210, a first command to read data from memory array 230a and a second command to read data from memory array 230b.

[0101] To the memory device and via a first timing signal interface, a first external timing reference signal is transmitted (1204). For example, to memory device 210 and via write strobe interface 223 w, controller 220 may transmit a write clock signal. From the memory device and via a second external timing reference signal interface, a second external timing reference signal that is generated by the memory device based on the first external timing reference signal, the first command, and the second command, is received (1206). For example, controller 220 may receive, and memory device 210 may transmit via read data strobe interface 213r, a read data strobe signal derived from the write clock signal that toggles during the transmission of data associated with either, or both, of the first command and the second command.

[0102] Via a first data signal interface and synchronously with respect to the second external timing reference signal, first data retrieved from the first memory array based on the first command is received (1208). For example, based on the first command to read data from memory array 230a, memory device 210 may transmit, and controller 220 receive, via channel A data interface 222a and timed by the read data strobe signal received via read datastrobe interface 223r, data associated with the first command that was retrieved from memory array 230a. Via a second data signal interface and synchronously with respect to the second external timing reference signal, second data retrieved from the second memory array based on the second command is received (1210). For example, based on the second command to read data from memory array 230b, memory device 210 may transmit, and controller 220 receive, via channel B data interface 222b and timed by the read data strobe signal received via read data strobe interface 223r, data associated with the second command that was retrieved from memory array 230b.

[0103] Figure 13 is a flowchart illustrating a method of sharing timing signals. One or more steps illustrated in Figure 13 may be performed by, for example, system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and / or their components. From a controller and via a first command / address interface of a first memory device co-packaged with a second memory device, a first command to read a first memory array of the first memory device is received (1302). For example, memory device 810a (which is co-packaged in the package of multi-die memory device 850 with memory device 810b) may receive, from controller 820 and via CA interface 811a, a first command to read memory array 830a. From a controller and via a second command / address interface of the second memory device, a second command to read a second memory array of the second memory device is received (1304). For example, memory device 810b may receive, from controller 820 and via CA interface 81 lb, a second command to read memory array 830b.

[0104] By the first memory device, from the controller, and via a first timing signal interface, a first external timing reference signal is received (1306). For example, memory device 810a may receive, from controller 820 and via write clock interface 823 w and write clock interface 813aw, an external write clock signal. By the second memory device, from the first memory device, and via a second timing signal interface, a first timing reference signal generated by the first memory device based on the first external timing reference signal is received (1308). For example, memory device 810b may receive, from memory device 810a, via timing signal interface 813a and timing signal interface 813b, a write clock signal that is based on the external write clock signal received by memory device 810a from controller 820.

[0105] By the second memory device, to the first memory device, and via the second timing signal interface, a second timing reference signal that is based on the first timing reference signal and the second command is transmitted (1310). For example, memory device 810b may transmit, to memory device 810a via timing signal interface 813b andtiming signal interface 813a, a first read data strobe signal derived from the write clock signal received from memory device 810a that toggles during the transmission, by memory device 810b, of data associated with the second command. By the first memory device and via the first timing signal interface, a second external timing reference signal that is based on the first command and the second timing reference signal is transmitted (1312). For example, memory device 810a may transmit, to controller 820 via read data strobe interface 813ar, an external data strobe signal that is based on the first read data strobe signal from memory device 810b and the first command (and may be further based on the first external timing reference signal) that toggles during the transmission of data associated with either, or both, of the first command and the second command.

[0106] By the first memory device, based on the first command, via a first data signal interface, and synchronously with respect to the second external timing reference signal, first data retrieved from the first memory array is transmitted (1314). For example, based on the first command to read data from memory array 830a, memory device 810a may transmit, and controller 820 receive, via data interface 812a and timed by the external read data strobe signal transmitted via read data strobe interface 813ar, data associated with the first command that was retrieved from memory array 830a. By the second memory device, based on the second command, via a second data signal interface, and synchronously with respect to the second external timing reference signal, second data retrieved from the second memory array is transmitted (1316). For example, based on the second command to read data from memory array 830b, memory device 810b may transmit, and controller 820 receive, via data interface 812b and timed by the external read data strobe signal transmitted via read data strobe interface 8 Bar, data associated with the second command that was retrieved from memory array 830b.

[0107] The methods, systems and devices described above may be implemented in computer systems, or stored by computer systems. The methods described above may also be stored on a non-transitory computer readable medium. Devices, circuits, and systems described herein may be implemented using computer-aided design tools available in the art, and embodied by computer-readable files containing software descriptions of such circuits. This includes, but is not limited to one or more elements of system 100, system 200, system 300, system 400, system 500, memory device 600, and / or system 800, and their components. These software descriptions may be: behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, the software descriptions may be stored on storage media or communicated by carrier waves.

[0108] Data formats in which such descriptions may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email. Note that physical files may be implemented on machine-readable media such as: 4 mm magnetic tape, 8 mm magnetic tape, 3-1 / 2 inch floppy media, CDs, DVDs, and so on.

[0109] Figure 14 is a block diagram illustrating one embodiment of a processing system 1400 for including, processing, or generating, a representation of a circuit component 1420. Processing system 1400 includes one or more processors 1402, a memory 1404, and one or more communications devices 1406. Processors 1402, memory 1404, and communications devices 1406 communicate using any suitable type, number, and / or configuration of wired and / or wireless connections 1408.

[0110] Processors 1402 execute instructions of one or more processes 1412 stored in a memory 1404 to process and / or generate circuit component 1420 responsive to user inputs 1414 and parameters 1416. Processes 1412 may be any suitable electronic design automation (EDA) tool or portion thereof used to design, simulate, analyze, and / or verify electronic circuitry and / or generate photomasks for electronic circuitry. Representation 1420 includes data that describes all or portions of system 100, system 200, system 300, system 400, system 500, memory device 600, system 800, and their components, as shown in the Figures.

[0111] Representation 1420 may include one or more of behavioral, register transfer, logic component, transistor, and layout geometry-level descriptions. Moreover, representation 1420 may be stored on storage media or communicated by carrier waves.

[0112] Data formats in which representation 1420 may be implemented include, but are not limited to: formats supporting behavioral languages like C, formats supporting register transfer level (RTL) languages like Verilog and VHDL, formats supporting geometry description languages (such as GDSII, GDSIII, GDSIV, CIF, and MEBES), and other suitable formats and languages. Moreover, data transfers of such files on machine-readable media may be done electronically over the diverse media on the Internet or, for example, via email.

[0113] User inputs 1414 may comprise input parameters from a keyboard, mouse, voice recognition interface, microphone and speakers, graphical display, touch screen, or other type of user interface device. This user interface may be distributed among multiple interfacedevices. Parameters 1416 may include specifications and / or characteristics that are input to help define representation 1420. For example, parameters 1416 may include information that defines device types (e.g., NFET, PFET, etc.), topology (e.g., block diagrams, circuit descriptions, schematics, etc.), and / or device descriptions (e.g., device properties, device dimensions, power supply voltages, simulation temperatures, simulation models, etc.).

[0114] Memory 1404 includes any suitable type, number, and / or configuration of non- transitory computer-readable storage media that stores processes 1412, user inputs 1414, parameters 1416, and circuit component 1420.

[0115] Communications devices 1406 include any suitable type, number, and / or configuration of wired and / or wireless devices that transmit information from processing system 1400 to another processing or storage system (not shown) and / or receive information from another processing or storage system (not shown). For example, communications devices 1406 may transmit circuit component 1420 to another system. Communications devices 1406 may receive processes 1412, user inputs 1414, parameters 1416, and / or circuit component 1420 and cause processes 1412, user inputs 1414, parameters 1416, and / or circuit component 1420 to be stored in memory 1404.

[0116] Implementations discussed herein include, but are not limited to, the following examples:

[0117] Example 1: A dynamic random access memory (DRAM) integrated circuit device, comprising: a first memory array having first command, address, and data transfer functions; a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array; a first interface to receive a first external timing reference signal; a second interface to transmit a second external timing reference signal; a first data signal interface to receive, synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array, the first data signal interface also to, synchronously with respect to the second external timing reference signal, transmit second data retrieved from the first memory array; and a second data signal interface to receive, synchronously with respect to the first external timing reference signal, third data to be stored in the second memory array, the second data signal interface also to, synchronously with respect to the second external timing reference signal, transmit fourth data retrieved from the second memory array.

[0118] Example 2: The DRAM integrated circuit device of example 1, further comprising: a command / address (CA) interface to receive first commands interspersed withsecond commands, the first commands and addresses to access the first memory array and the second commands and addresses to access the second memory array.

[0119] Example 3: The DRAM integrated circuit device of example 1, further comprising:

[0120] a first command / address (CA) interface to receive first commands and addresses to access the first memory array; and a second command / address (CA) interface to receive second commands and addresses to access the second memory array.

[0121] Example 4: The DRAM integrated circuit device of example 1, wherein the second external timing reference signal is based on the first external timing reference signal.

[0122] Example 5: The DRAM integrated circuit device of example 1, wherein the first memory array is on a first integrated circuit die and the second memory array is on a second integrated circuit die.

[0123] Example 6: The DRAM integrated circuit device of example 5, wherein, based on a first mode, the first integrated circuit die is to transmit at least one internal timing reference signal to the second integrated circuit die.

[0124] Example 7: The DRAM integrated circuit device of example 5, wherein the first integrated circuit die is stacked with the second integrated circuit die.

[0125] Example 8: A dynamic random access memory (DRAM) integrated circuit, comprising: a first interface to receive a first external timing reference signal; a second interface to transmit a second external timing reference signal; a first memory array having first command, address, and data transfer functions; a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array; a first bidirectional data signal interface to receive, synchronized by the first external timing reference signal, first data to be stored in the first memory array, the first bidirectional data signal interface also to, synchronized by the second external timing reference signal, transmit second data retrieved from the first memory array; and a second bidirectional data signal interface to receive, synchronized by the first external timing reference signal, third data to be stored in the second memory array, the second bidirectional data signal interface also to synchronized by the second external timing reference signal, transmit fourth data retrieved from the second memory array.

[0126] Example 9: The DRAM integrated circuit of example 8, further comprising: training control circuitry to adjust first phase relationships between the first external timing reference signal and a first sampling of the first bidirectional data signal interface, and toadjust second phase relationships between the first external timing reference signal and a second sampling of the second bidirectional data signal interface.

[0127] Example 10: The DRAM integrated circuit of example 8, wherein the second external timing reference signal is based on the first external timing reference signal.

[0128] Example 11 : The DRAM integrated circuit of example 10, further comprising: training control circuitry to adjust a phase relationship between the first external timing reference signal and the second external timing reference signal.

[0129] Example 12: The DRAM integrated circuit of example 8, further comprising: a command / address (CA) interface to receive first access commands and addresses directed to the first memory array and second access commands and addresses to directed to the second memory array.

[0130] Example 13: The DRAM integrated circuit of example 8, further comprising: a first command / address (CA) interface to receive first access commands and addresses directed to the first memory array; and a second command / address (CA) interface to receive second access commands and addresses directed to the second memory array.

[0131] Example 14: The DRAM integrated circuit of example 8, further comprising: gating circuitry to selectively transmit a first internal version of the first external timing reference signal to the first bidirectional data signal interface, and to selectively transmit a second internal version of the first external timing reference signal to the second bidirectional data signal interface.

[0132] Example 15: The DRAM integrated circuit of example 8, further comprising: gating circuitry to, based on the first external timing reference signal, selectively generate an internal version of the second external timing reference signal.

[0133] Example 16: A method of operating a dynamic random access memory (DRAM) integrated circuit device, comprising: accessing a first memory array having first command, address, and data transfer functions; accessing a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array;; receiving a first external timing reference signal; transmitting a second external timing reference signal; receiving, via a first data signal interface and synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array; transmitting, via the first data signal interface and synchronously with respect to the second external timing reference signal, second data retrieved from the first memory array; receiving, via a second data signal interface and synchronously with respect to the first external timing referencesignal, third data to be stored in the second memory array; and transmitting, via the second data signal interface and synchronously with respect to the second external timing reference signal, fourth data retrieved from the second memory array.

[0134] Example 17: The method of example 16, further comprising: receiving, via a command / address (CA) interface, first commands and addresses interspersed with second commands and addresses, the first commands and addresses to access the first memory array and second commands and addresses to access the second memory array.

[0135] Example 18: The method of example 16, further comprising: receiving, via a first command / address (CA) interface, first commands and addresses to access the first memory array; and receiving, via a second command / address (CA) interface, second commands and addresses to access the second memory array.

[0136] Example 19: The method of example 16, further comprising: generating the second external timing reference signal based on the first external timing reference signal.

[0137] Example 20: The method of example 16, wherein the first memory array is on a first integrated circuit die and the second memory array is on a second integrated circuit die.

[0138] The foregoing description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.

Claims

1. CLAIMSWhat is claimed is:

1. A dynamic random access memory (DRAM) integrated circuit device, comprising: a first memory array having first command, address, and data transfer functions; a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array; a first interface to receive a first external timing reference signal; a second interface to transmit a second external timing reference signal; a first data signal interface to receive, synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array, the first data signal interface also to, synchronously with respect to the second external timing reference signal, transmit second data retrieved from the first memory array; and a second data signal interface to receive, synchronously with respect to the first external timing reference signal, third data to be stored in the second memory array, the second data signal interface also to, synchronously with respect to the second external timing reference signal, transmit fourth data retrieved from the second memory array.

2. The DRAM integrated circuit device of claim 1, further comprising: a command / address (CA) interface to receive first commands interspersed with second commands, the first commands and addresses to access the first memory array and the second commands and addresses to access the second memory array.

3. The DRAM integrated circuit device of claim 1, further comprising: a first command / address (CA) interface to receive first commands and addresses to access the first memory array; and a second command / address (CA) interface to receive second commands and addresses to access the second memory array.

4. The DRAM integrated circuit device of claim 1, wherein the second external timing reference signal is based on the first external timing reference signal.

5. The DRAM integrated circuit device of claim 1, wherein the first memory array is on a first integrated circuit die and the second memory array is on a second integrated circuit die.

6. The DRAM integrated circuit device of claim 5, wherein, based on a first mode, the first integrated circuit die is to transmit at least one internal timing reference signal to the second integrated circuit die.

7. The DRAM integrated circuit device of claim 5, wherein the first integrated circuit die is stacked with the second integrated circuit die.

8. A dynamic random access memory (DRAM) integrated circuit, comprising: a first interface to receive a first external timing reference signal; a second interface to transmit a second external timing reference signal; a first memory array having first command, address, and data transfer functions; a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array; a first bidirectional data signal interface to receive, synchronized by the first external timing reference signal, first data to be stored in the first memory array, the first bidirectional data signal interface also to, synchronized by the second external timing reference signal, transmit second data retrieved from the first memory array; and a second bidirectional data signal interface to receive, synchronized by the first external timing reference signal, third data to be stored in the second memory array, the second bidirectional data signal interface also to synchronized by the second external timing reference signal, transmit fourth data retrieved from the second memory array.

9. The DRAM integrated circuit of claim 8, further comprising: training control circuitry to adjust first phase relationships between the first external timing reference signal and a first sampling of the first bidirectional datasignal interface, and to adjust second phase relationships between the first external timing reference signal and a second sampling of the second bidirectional data signal interface.

10. The DRAM integrated circuit of claim 8, wherein the second external timing reference signal is based on the first external timing reference signal.

11. The DRAM integrated circuit of claim 10, further comprising: training control circuitry to adjust a phase relationship between the first external timing reference signal and the second external timing reference signal.

12. The DRAM integrated circuit of claim 8, further comprising: a command / address (CA) interface to receive first access commands and addresses directed to the first memory array and second access commands and addresses to directed to the second memory array.

13. The DRAM integrated circuit of claim 8, further comprising: a first command / address (CA) interface to receive first access commands and addresses directed to the first memory array; and a second command / address (CA) interface to receive second access commands and addresses directed to the second memory array.

14. The DRAM integrated circuit of claim 8, further comprising: gating circuitry to selectively transmit a first internal version of the first external timing reference signal to the first bidirectional data signal interface, and to selectively transmit a second internal version of the first external timing reference signal to the second bidirectional data signal interface.

15. The DRAM integrated circuit of claim 8, further comprising: gating circuitry to, based on the first external timing reference signal, selectively generate an internal version of the second external timing reference signal.

16. A method of operating a dynamic random access memory (DRAM) integrated circuit device, comprising:accessing a first memory array having first command, address, and data transfer functions; accessing a second memory array having second command, address, and data transfer functions that operate independently of the first command, address, and data transfer functions of the first memory array; receiving a first external timing reference signal; transmitting a second external timing reference signal; receiving, via a first data signal interface and synchronously with respect to the first external timing reference signal, first data to be stored in the first memory array; transmitting, via the first data signal interface and synchronously with respect to the second external timing reference signal, second data retrieved from the first memory array; receiving, via a second data signal interface and synchronously with respect to the first external timing reference signal, third data to be stored in the second memory array; and transmitting, via the second data signal interface and synchronously with respect to the second external timing reference signal, fourth data retrieved from the second memory array.

17. The method of claim 16, further comprising: receiving, via a command / address (CA) interface, first commands and addresses interspersed with second commands and addresses, the first commands and addresses to access the first memory array and second commands and addresses to access the second memory array.

18. The method of claim 16, further comprising: receiving, via a first command / address (CA) interface, first commands and addresses to access the first memory array; and receiving, via a second command / address (CA) interface, second commands and addresses to access the second memory array.

19. The method of claim 16, further comprising:generating the second external timing reference signal based on the first external timing reference signal.

20. The method of claim 16, wherein the first memory array is on a first integrated circuit die and the second memory array is on a second integrated circuit die.

Images