Closed-loop autotuning of resonant switched-capacitor converters for soft switching operation

Abstract

Closed-loop control techniques which modulate the switching frequency and duty cycle of resonant switched-capacitor (ReSC) converters to achieve soft-switching operation including zero current switching (ZCS), zero voltage switching (ZVS) and merged ZCS / ZVS operation. During phase (switching state) transitions or deadtimes, incomplete soft switching conditions are detected by sensing one or more voltage node(s): such as at the inductor switch node(s). Using this feedback control loop, the duration of each phase is independently tuned until one or more of the inductor switch node voltage(s) indicates complete soft switching conditions have been met.

Description

CLOSED-LOOP AUTOTUNING OF RESONANT SWITCH ED-CAPACITOR CONVERTERS FOR SOFT SWITCHING OPERATIONCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to, and the benefit of, U.S. provisional patent application serial number 63 / 664,051 filed on June 25, 2024, incorporated herein by reference in its entirety.STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

[0002] Not ApplicableNOTICE OF MATERIAL SUBJECT TO COPYRIGHT PROTECTION

[0003] A portion of the material in this patent document may be subject to copyright protection under the copyright laws of the United States and of other countries. The owner of the copyright rights has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the United States Patent and Trademark Office publicly available file or records, but otherwise reserves all copyright rights whatsoever. The copyright owner does not hereby waive any of its rights to have this patent document maintained in secrecy, including without limitation its rights pursuant to 37 C. F. R. § 1.14.BACKGROUND

[0004] 1. Technical Field

[0005] The technology of this disclosure pertains generally to switched- capacitor converters, and more particularly to closed-loop or adaptive tuning of resonant switched-capacitor converters for soft-switching operation.

[0006] 2. Background Discussion

[0007] By leveraging energy dense capacitors and soft-charging capabilities, hybrid and resonant switched-capacitor converters have achieved state-of-the-art power densities and efficiencies in applications ranging from data center power delivery, grid-tied systems and electric transportation.Moreover, many resonant switched-capacitor (ReSC) converter topologies have inherent soft-switching capabilities through which switching losses are significantly reduced. Switching losses are commonly the dominating loss mechanism at high switching frequencies and under light load operation, and can significantly decrease the efficiency of power electronic converters and switched-mode power supplies (SMPS).

[0008] With Zero Current Switching (ZCS), the Voltage-Current (V-l) overlap losses can be eliminated. Theoretically, the only requirement to obtain ZCS in a ReSC converter is to set each phase duration to half the resonant period of the LC tank formed within each phase. In practice, however, the reality of non-ideal circuit elements which provide finite input and output filtering capacitances, passive component tolerance, derating and aging effects, can render ZCS timing challenging to estimate with a desired level of precision.

[0009] In addition to the elimination of V-l overlap losses, Zero Voltage Switching (ZVS) allows for the recovery of the charge (Qoss) stored in the output capacitance (Coss) of the transistor during switching transitions. Due to this property, ZVS can often enable higher efficiency levels under light-load conditions than ZCS in ReSC converters. In addition to the previously mentioned non-ideal operating realities, ZVS phase timings are noticeably dependent on load current and can be more challenging to estimate than ZCS phase timings.BRIEF SUMMARY

[0010] This disclosure describes closed-loop control techniques which modulate both the switching frequency and duty cycle of fixed-ratio Resonant Switched-Capacitor (ReSC) converters to achieve soft-switching operation including Zero Current Switching (ZCS), Zero Voltage Switching (ZVS) and merged ZCS / ZVS operation. During phase (switching state) transitions or deadtimes, incomplete soft switching conditions are detected by sensing the voltage at the inductor switch node(s). With a feedback control loop, the duration of each phase is independently tuned until the inductor switch nodevoltage indicates complete soft switching conditions.

[0011] In ReSC converters, ZCS and ZVS operation can require large inductor RMS currents resulting in higher conduction losses and lowered heavy-load efficiencies. By achieving ZCS on a portion of the switches and ZVS on the remaining ones, a “merged” soft-switching operation with reduced inductor RMS current can be realized to increase the heavy-load efficiency without significantly compromising light-load performance.

[0012] To mitigate the challenge of maintaining precise soft-switching operation across passive component, line and load variations, the present disclosure presents various closed-loop control techniques which modulate the switching frequency and duty cycle of ReSC converters to achieve complete ZCS, ZVS, or merged ZCS / ZVS operation. During phase (or switching state) transitions or deadtimes, incomplete soft switching conditions are detected by sensing one or more voltage node(s), specifically the inductor switch node(s). With a feedback control loop, the duration of each phase is independently tuned until the inductor switch node voltage indicates that complete soft switching conditions have been met.

[0013] Various aspects of this technology of this disclosure may include, but are not limited to, the following: (1) It can be applied to input and output inductor based ReSC converters of various families and conversion ratios.(2) It can be applied to systems containing one or more input or output inductor based ReSC converter(s). (3) It can be applied to systems containing cascaded or series-connected ReSC converter units wherein the output of one unit is fed into the input of a subsequent unit to obtain an overall higher conversion ratio. (4) It can be applied to systems containing paralleled, or interleaved, ReSC converter units wherein multiple units are running in parallel, with or without phase-shifting. (5) It eliminates the need to estimate or manually tune phase timings which are highly sensitive to real world circuit variations, such as temperature changes, passive component tolerance, derating, aging, and similar. (6) It allows for the detection of incomplete soft switching conditions and the establishment of complete soft switching conditions by sensing one or more inductor switch node(s). (7) It can increase the efficiency of ReSC converters compared with conventionalcontrol techniques.

[0014] Additionally, the technology of this disclosure may have use in applications which include, but are not limited to, the following: (a) Hybrid and resonant switched capacitor converters; (b) Intermediate bus converters in data center power delivery networks; (c) Power converters for automotive applications; and (d) Renewable energy applications and microinverters.

[0015] Further aspects of the technology described herein will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the technology without placing limitations thereon.BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The technology described herein will be more fully understood by reference to the following drawings which are for illustrative purposes only:

[0017] FIG. 1 is a block diagram of a single inductor ReSC topology.

[0018] FIG. 2 is a block diagram of a split-inductor ReSC topology.

[0019] FIG. 3 is a block diagram of a switched-capacitor unit which performs2-to-1 step-down or step-up conversion, with the transistor modeled as an ideal switch with an anti-parallel diode (body diode).

[0020] FIG. 4A through FIG. 4G are block diagrams of various switch node voltage sensing circuits to detect incomplete soft-switching conditions, according to embodiments of the present disclosure.

[0021] FIG. 5 is a block diagram of sensing and control circuitry interfaced with the single inductor ReSC converter of FIG. 1 , according to at least one embodiment of the present disclosure.

[0022] FIG. 6 is a waveform diagram of complete ZCS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0023] FIG. 7 is a waveform diagram of incomplete ZCS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0024] FIG. 8 is a waveform diagram of complete ZVS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0025] FIG. 9 is a waveform diagram of incomplete ZVS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0026] FIG. 10 is a waveform diagram of complete merged ZCS / ZVS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0027] FIG. 11 is a waveform diagram of incomplete merged ZCS / ZVS operation in a 2-to-1 single inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0028] FIG. 12 is a block diagram of the sensing and control circuitry interfaced with the split-inductor ReSC converter, based on sensed feedback of top inductor switch node vswt, according to at least one embodiment of the present disclosure.

[0029] FIG. 13 is a block diagram of the sensing and control circuitry interfaced with the split-inductor ReSC converter, based on sensed feedback of the bottom inductor switch node vswb, according to at least one embodiment of the present disclosure.

[0030] FIG. 14 is a waveform diagram of complete ZCS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0031] FIG. 15 is a waveform diagram of incomplete ZCS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0032] FIG. 16 is a waveform diagram of complete ZVS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0033] FIG. 17 is a waveform diagram of incomplete ZVS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0034] FIG. 18 is a waveform diagram of complete merged ZCS / ZVS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0035] FIG. 19 is a waveform diagram of incomplete merged ZCS / ZVS operation in a 2-to-1 split-inductor ReSC converter, according to at least one embodiment of the present disclosure.

[0036] FIG. 20 is a flow diagram of a first example of a control scheme to sense and dynamically maintain complete ZCS, according to at least one embodiment of the present disclosure.

[0037] FIG. 21 is a flow diagram of a second example of a control scheme to sense and dynamically maintain complete ZCS, according to at least one embodiment of the present disclosure.

[0038] FIG. 22 is a flow diagram of a first example of the control scheme to sense and dynamically maintain complete ZVS, according to at least one embodiment of the present disclosure.

[0039] FIG. 23 is a flow diagram of a second example of the control scheme to sense and dynamically maintain complete ZVS, according to at least one embodiment of the present disclosure.

[0040] FIG. 24 is a flow diagram of a first example of the control scheme to sense and dynamically maintain complete merged ZCS / ZVS, according to at least one embodiment of the present disclosure.

[0041] FIG. 25 is a flow diagram of a second example of the control scheme to sense and dynamically maintain complete merged ZCS / ZVS, according to at least one embodiment of the present disclosure.DETAILED DESCRIPTION

[0042] 1. Introduction

[0043] A ReSC converter generally comprises one or more pure Switched- Capacitor (SC) converter units interfaced with one or more inductors. The technology of the present disclosure applies to inductor-based ReSC converter topologies; including topologies in which the inductor is located between the pure SC unit(s) and the output node or the input node, respectively.

[0044] The inductor node that is connected to the SC circuit is referred to as the “inductor switch node” or simply, the “switch node”. Some ReSC topologies operate with split-inductors in which case one inductor is placed between the SC unit(s) and the output or input of the converter, and the other is placed between the SC unit(s) and ground. In this case, the ReSC converter will possess two switch nodes.

[0045] 1.1. ReSC Converters

[0046] For a system containing cascaded or series-connected ReSC converters, one or more of the inductor(s) may be placed between the output of the first-stage pure SC unit(s) and the input of the subsequent second- stage SC unit(s).

[0047] FIG. 1 illustrates a simplified schematic 10 of a ReSC converter, shown with VHI 12 (input voltage) connected to the SC unit 14 with switched voltage Vsw 16 through a single inductor 18 to VLO 20 (output voltage).

[0048] FIG. 2 illustrates a simplified schematic 50 of a ReSC converter with split-inductors. VHI 52 (input voltage) is connected through split inductors 54a, 54b to each side of capacitor 56, showing voltages of Vswt, Vswb (top, bottom) to the SC unit 60 which supplies VLO 62 (output voltage).

[0049] For both FIG. 1 and FIG. 2, when operating in voltage step-down mode, VHI represents the input voltage and VLO represents the output voltage which would feed the load. When operating in voltage step-up mode, VLO represents the input voltage and VHI represents the output voltage which would supply the load. The polarity of the inductor current in FIG. 1 and FIG.2 corresponds to the case of voltage step-down. In the case of voltage step- up, the inductor currents would flow in the opposite direction.

[0050] Embodiments of the disclosed technology utilize sensing at one or more inductor switch node(s) to detect incomplete soft switching conditions and the use of a feedback control loop to tune phase timings accordingly and restore complete soft switching. For single inductor ReSC topologies, the sensed node is Vsw, as shown in FIG. 1 . For split-inductor ReSC topologies, either vswt or vSWb, as shown in FIG. 2, can be sensed.

[0051] Depending on the type and voltage conversion ratio, a ReSC convertermay have a specific number of switches and capacitors and their interconnections.

[0052] 1 .2. Switching in an ReSC Converter

[0053] FIG. 3 illustrates that for a 2-to-1 conversion ratio, all SC converters converge to this fundamental circuit, showing a first pair of switches 72a, 72b on a first side of a flying capacitor 74, and a second pair of switches 76a, 76b on the second side of the flying capacitor. The transistors in these example are modeled as an ideal switch with an anti-parallel (body) diode.

[0054] Therefore, this circuit is an excellent basis to analyze incomplete and complete soft switching conditions to extend the control scheme to the largest number of ReSC converters.

[0055] It should be noted that while the figures and waveforms in this document are based on the operation of the fundamental 2-to-1 unit, the presented analyses and techniques can be extended to ReSC converters of various conversion ratios and families including, but not limited to, the Dickson, Series-Parallel, Fibonacci or Ladder topologies.

[0056] Incomplete soft switching conditions during switching transitions typically indicate one of two cases: (1 ) the duration of the previous phase was too short or (2) the duration of the previous phase was too long. In various ReSC converter topologies, both case (1 ) and case (2) can be sensed, differentiated, identified, and rectified.

[0057] 2.0. Example Voltage Sensing Circuits

[0058] To sense the switch node, a voltage sensing circuit can be utilized.Numerous forms of these sensors can be utilized, such as simple standalone voltage comparators, or their equivalents.

[0059] FIG. 4A through FIG. 4G illustrate examples of voltage sensing circuits, shown by way of example and not limitation.

[0060] In FIG. 4A is shown a non-inverting input voltage comparator 110, shown with switch node connection 112 through a ladder of impedances (voltage divider) 116a, 116b terminating at a reference voltage exemplified as ground, with a voltage Vsw.div split off to the comparator 118, while the other input of the comparator receives a threshold voltage Vth setting the basis of the comparison, whereby the output 120 is either high or low. In this examplethe voltage Vsw.div is directed to the non-inverting input of the comparator. The remaining examples provide similar thresholding functionality.

[0061] In FIG. 4B is shown an inverting input voltage comparator 130 circuit with comparator 132 receiving the same input as in FIG. 4A, but the inputs are reversed, wherein this is an inverting input comparator.

[0062] In FIG. 4C is shown another inverting input voltage comparator 150 with hysteresis. Voltage Vsw.div to be sensed is connected to the inverting input of comparator 152. The non-inverting input receives the threshold signal Vth through impedance 156, and is connected to a feedback impedance 158 coupled to the output. Thus, the feedback from the output 120 will skew the threshold trigger points based on the current output state thus introducing hysteresis to the transfer functions.

[0063] In FIG. 4D is shown a voltage sensing circuit 170 using a voltage amplifier 172 (operational amplifier (op-amp)), in a feedback arrangement in which Voltage Vsw.div to be sensed is connected to non-inverting input of amplifier 172, while the inverting input receives its signal through a voltage divider using impedances 178, 176 between the output 120 and back to a reference (ground) 174.

[0064] In FIG. 4E is shown an inverting input op-amp circuit 190 using op-amp 192. In this example Voltage Vsw.div to be sensed through impedance 194 to the inverting input of op-amp 192, while the non-inverting input of the op-amp is connected to a Vbias voltage. Another impedance 196 is shown coupled between the inverting input of the op-amp and the output 120 of the op-amp, thus providing negative feedback, as the combination of impedances 194, 196 form a voltage divider.

[0065] In FIG. 4F is shown a non-inverting input slope (^) detection circuit 210 which detects changes in voltage with respect to time. This circuit can use the same voltage divider with impedances 116a, 116b to provide voltage Vsw.div to be sensed at the non-inverting input of a voltage amplifier 212. A feedback circuit is shown with impedances 220, 218 in a voltage divider between the output of the amplifier and a reference 216 (e.g., ground), whereby a portion of the output signal influences the inverting input.

[0066] Output from voltage amplifier 212 is directed through a capacitance Cdi 222 to the inverting input of a voltage differentiator using amplifier 214. Feedback is directed between the output 120 and the inverting input of this amplifier through impedance (resistor Rdi) 224. The non-inverting input of the amplifier is connected to receive a controlling bias voltage Vbias 226.

[0067] The input capacitance at the last stage is configured for passing along a signal to this last amplifier stage in response to changes in the output signal from voltage amplifier 212. It should be appreciated that many such circuits and variations can be designed, without departing from the teachings of the present disclosure, to selectively generate an output which is based on the activity / state of switch node vsw.

[0068] In FIG. 4G is shown an inverting example 230 of an input slope (^) detection circuit. The circuit is much the same as FIG. 4F, aside from the voltage amplifier 232 having its inverting and non-inverting inputs reversed. Sensed voltage Vsw,div is connected through impedance 236 to the inverting input of amplifier 232, with a bias voltage Vbiasi 240 connecting to the noninverting input. A feedback impedance 238 is coupled between the output of the voltage amplifier and its inverting input. Output from the voltage amplifiers is coupled through capacitor Cdi 242 to the inverting input of amplifier 234. A feedback resistance (impedance) is connected between the output 120 of amplifier 234 and its inverting input. The non-inverting input of this second amplifier is connected to a bias voltage Vbias2 246.

[0069] It should be appreciated that these circuits may utilize other circuitry, for example more elaborate analog circuits such as differential amplifiers, differentiators, or integrators. It is also possible to use conversion / digital circuitry to register the switch node voltage and generate a desired response for controlling soft switching conditions.

[0070] Depending on the desired controller implementation, the example circuits of FIG. 4A through FIG. 4G may be used individually for sensing, or they can be cascaded / series-connected for a multi-stage approach, or utilized with other circuitry as desired. Moreover, these circuits may be interfaced with one or more Analog-to-Digital Converters (ADC) before feeding into thecontroller. The controller processes the output of the sensing circuit to identify incomplete soft switching conditions and tune phase timings accordingly. Alternatively, the controller can be implemented as a Microcontroller Unit (MCU), a field programmable gate array (FPGA), or a combination of analog, digital and / or mixed-signal blocks.

[0071] 3.0. Single Inductor ReSC Converter

[0072] FIG. 5 illustrates 310 sensing and control circuitry interfaced with the single inductor ReSC converter. An ReSC converter 314 is shown with inputs 312. The signal vSw 316 from converter 314 is received by a sensing circuit 318 which processes the signal and generates a signal to controller 324, which outputs the phase control signals 325 (e.g., phase 1 (<|>1 ) through phase n (<|>n)) to control the ReSC 314. Thus, the controller outputs control signals for the switches in the switched-capacitor unit to maintain soft-switching operations based on the sensed feedback of the inductor switch node vsw. Signal Vsw 316 is also coupled through inductance 320 to VLO 322.

[0073] For simplicity, the figures in the following subsections consider a 2-to-1 ReSC converter with standard two-phase operation and identical resonant tanks in both phases. However, it will be evident to one of ordinary skill in the art that the analysis and concepts described herein can be utilized with ReSC converters having different voltage conversion ratios, more than two phases or multi-resonant operation (different resonant tanks across phases).

[0074] 3.1. Zero Current Switching (ZCS)

[0075] Complete and incomplete ZCS operation of single inductor ReSC converters are characterized in this section. In the case of input-to-output voltage step up, the inductor current would flow in the opposite direction. The deadtime is a negligible portion of the total switching cycle but is expanded in FIG. 6 and FIG. 7 for improved visibility.

[0076] FIG. 6 illustrates the case 350 of complete ZCS at the end of a phase, at which time the switch node voltage remains constant during the following deadtime. The figure showing signals 01 ,3 352, 2,4 354, IL 356, and Vsw 358, and indicating Phase 1 360, Phase 2 362, and deadtimes 364.

[0077] FIG. 7 illustrates 370 the same waveforms, phases and deadtimes.However, it is seen that if a phase is too short and the turn off inductor current is positive during the deadtime, the switch node voltage will decrease 372 below its nominal value during the following deadtime. If a phase is too long and the turn off inductor current is negative, the switch node voltage will increase 374 above its nominal value during the following deadtime. Therefore, if a phase is too short, the switch node voltage will have a negative slope during the following deadtime whereas if a phase is too long, the switch node voltage will have a positive slope during the following deadtime.

[0078] 3.2. Zero Voltage Switching (ZVS)

[0079] Complete and incomplete ZVS operation of single inductor ReSC converters are characterized in this section. In the case of input-to-output voltage step up, the inductor current would flow in the opposite direction.

[0080] FIG. 8 and FIG. 9 illustrate 390, 410 ZVS operation showing time durations Tdi and Td2, indicate the time intervals for Coss discharge, representing a negligible portion of the total switching cycle, and are expanded in these figures for improved visibility. It should be noted that Tdi and Td2 are short time durations during which the parasitic capacitance (Coss) of the switches are being softly charged / discharged to eliminate related losses. These delays are similar to the deadtime in that they are also short (typically on the order of tens of nanoseconds) and they do not participate in the main input-to-output voltage conversion. Yet, they are dissimilar to the deadtime in the sense that not all switches are turned off. In a Tegular” deadtime, all the switches are turned off; whereas during Tdi and Td2 a reduced number of switches will typically remain on.

[0081] Both figures show signals 1 392, 2 394, 03 396, 04 398, L 400, and vsw402, while indicating Phase 1 404 and Phase 2 406, as well as durations Tdi 408 and Td2 409.

[0082] As shown in FIG. 8, provided the duration of Tdi and Td2 are well estimated, in the case of complete ZVS at the end of a phase, the switch node voltage would be equal to 0 V at the end of Tdi , as seen in this figure.

[0083] In FIG. 9, however, it is seen that if a phase is too long, the switch node voltage would be larger 411 than 0 V at the end of Tdi . And if a phase is too short, the switch node voltage would be smaller 412 than 0 V (slightlynegative) at the end of Tdi. When a phase is too short, the slope of the switch node voltage during the following Tdi will have a larger magnitude than when the phase is too long.

[0084] 3.3. Merged ZCS / ZVS

[0085] In a merged ZCS / ZVS operation, ZVS is achieved on a portion of the switches and ZCS on the remaining ones. Complete and incomplete merged ZCS / ZVS operations within single inductor ReSC converters are characterized in this section.

[0086] FIG. 10 and FIG. 11 illustrate 430, 450, a merged ZCS / ZVS operation with Tdi 432 and the deadtime 434 representing a negligible portion of the total switching cycle and are shown expanded in the figures for improved visibility. Both figures show signals 1 392, 2 394, 03 396, 04 398, IL 400, and Vsw 402, while indicating Phase 1 404 and Phase 2 406, as well as durations Tdi 432 and deadtime 434.

[0087] In FIG. 10 is shown an example in which the duration of Tdi has been properly estimated, in the case represents a complete merged ZCS / ZVS at the end of a phase, the switch node voltage would be equal to 0 V at the end of Tdi 432 plus the deadtime 434.

[0088] In FIG. 11 , however, it is shown that if a phase is too long, the switch node voltage would exceed 436 0 V at the end of the Tdi 432 plus deadtime 434. And if a phase is too short, the switch node voltage would be less than 438 0 V (slightly negative) at the end of Tdi 432 plus deadtime 434. When a phase is too short, the slope of the switch node voltage during the following Tdi plus deadtime will be smaller (more negative) than when the phase is too long.

[0089] 4. Split-Inductor ReSC Converter

[0090] FIG. 12 is a block diagram 510 of the described sensing 520 (at top inductor 514a) and control circuitry 522 interfaced with a split-inductor ReSC converter 524, shown receiving input VHI 512, through inductors 514a, 514b to both sides of capacitor Ci 516, across which voltage 518 is shown across Vswt to Vswb. In at least one case, based on sensed feedback of the top inductor switch node Vswt, the controller outputs control signals 526, such asexemplified with 01, 02, 03, ...0n for the switches in the switched-capacitor unit to maintain soft-switching operation, and maintaining output VLO 528.

[0091] FIG. 13 illustrates 550 sensing and control circuitry interfaced with the split-inductor ReSC converter. Based on sensed feedback of the bottom inductor switch node Vswb, the controller outputs control signals for the switches in the switched-capacitor unit to maintain soft-switching operation.

[0092] Specifically, the circuit depicts sensing 552 at the bottom inductor 514b, and control circuitry 554 interfaced with a split-inductor ReSC converter 558, shown receiving input VHI 512, through inductors 514a, 514b to both sides of capacitor Ci 516, across which voltage Vswb 518 is shown. Based on sensed feedback of the bottom inductor switch node Vswb, the controller outputs control signals 556, such as exemplified with 01, 02, 03, ...0n for the switches in the switched-capacitor unit to maintain soft-switching operation, and maintaining output VLO 560.

[0093] For simplicity, the figures in the following subsections (4.1 , 4.2 and 4.3) consider a 2-to-1 ReSC converter with standard two-phase operation and which utilize identical resonant tanks in both phases. However, it should be appreciated that the analysis and concepts can be extended to ReSC converters with higher voltage conversion ratios, more than two phases or multi-resonant operation (different resonant tanks across phases).

[0094] 4.1. Zero Current Switching (ZCS)

[0095] Complete and incomplete ZCS operation of split-inductor ReSC converters are characterized in this section. In the case of input-to-output voltage step up, the inductor currents would flow in the opposite direction.

[0096] FIG. 14 and FIG. 15 illustrate complete and incomplete ZCS operations 570, 590, in which since the deadtime is a negligible portion of the total switching cycle, it has been shown expanded in these figures to improve visibility. Both figures depict signals 01 ,3 572, 02,4 574, it 576, ib 578, Vswt 580, and Vswb 582, and indicating Phase 1 584, Phase 2 586, and deadtimes 588.

[0097] In FIG. 14, the case of complete ZCS is shown, wherein at the end of a phase, the switch node voltages remain constant during the following deadtime 588.

[0098] In FIG. 15, it is shown, however, that when a phase is too short and the turn off inductor current is positive, the switch node voltages will increase above their nominal values during the following deadtime. If a phase is too long and the turn off inductor current is negative, the switch node voltages will decrease below their nominal values during the following deadtime.Therefore, if a phase is too short, the switch node voltages will have a positive slope during the following deadtime whereas if a phase is too long, the switch node voltages will have a negative slope during the following deadtime.

[0099] 4.2. Zero Voltage Switching (ZVS)

[0100] Complete and incomplete ZVS operation of split-inductor ReSC converters are characterized in this section. In the case of input-to-output voltage step up, the inductor current would flow in the opposite direction.

[0101] FIG. 16 and FIG. 17 illustrate 610, 650 Tdi and Td2, which represent a negligible portion of the total switching cycle but are expanded in these figures to improve visibility. Both figures show signals 01 612, 4 614, 3 616, 02 618, it 620, ib 622, Vt 624, and Vb 626, while indicating Phase 1 628 and Phase 2 630, as well as durations Tdi 612 and Td2 614.

[0102] In FIG. 16 is shown the case when the durations of Tdi 612 and Td2 614 are well estimated, in the case of complete ZVS at the end of a phase, the switch node voltages would increase by VDS 616 at the end of Tdi 612. VDS is the blocking voltage of the discharged switch in the previous phase.

[0103] In FIG. 17, however, is shown the case of a phase being excessive in length, wherein the switch node voltages would have an insufficient increase 618 (by less than VDS) at the end of Tdi . And if a phase is too short, the switch node voltages increase by slightly more 620 than VDS at the end of Tdi. When a phase is too short, the slope of the switch node voltages during the following Tdi will be larger (more positive) than when the phase is too long.

[0104] 4.3. Merged ZCS / ZVS

[0105] In merged ZCS / ZVS operation, ZVS is achieved on a portion of the switches and ZCS on the remaining ones. Complete and incomplete merged ZCS / ZVS operation of split-inductor ReSC converters are characterized in this section. As duration Tdi and deadtime duration represent a negligible portion of the total switching cycle they have been accentuated in these figures forimproved visibility.

[0106] FIG. 18 and FIG. 19 illustrate Merged ZCS / ZVS operation 650, 670 in relation to durations Tdi and deadtime. As durations Tdi and deadtime represent a negligible portion of the total switching time they are accentuated to improve visibility.

[0107] Again, both figures show signals 1 612, 4614, 03 616, 02 618, it 620, ib 622, Vt 624, and Vb 626, while indicating Phase 1 628 and Phase 2 630, as well as durations Tdi 652 and deadtime 654.

[0108] In FIG. 18 a case is shown in which the duration of Tdi and the deadtime have been properly estimated, resulting in a completely merged ZCS / ZVS at the end of a phase, the switch node voltages would increase by VDS 616 at the end of Tdi 652 and deadtime 654. VDS is the blocking voltage of the discharged switch in the previous phase.

[0109] In FIG. 19, however, a case is shown when phase duration is overly long, whereby the switch node voltages would increase by less than 672 VDS at the end of Tdi and deadtime. And if a phase duration is too short, the switch node voltages increase by slightly more 674 than VDS at the end of Tdi and deadtime durations. When a phase duration is too short, the slope of the switch node voltages during the following Tdi interval will be larger (more positive) than when the phase is too long.

[0110] 5. Control Scheme and Flowcharts

[0111] In this subsection, flowcharts summarizing the disclosed control schemes are shown. For each soft switching technique (ZCS, ZVS and merged ZCS / ZVS) two examples are shown. Depending on the selected sensing circuit and topology, one of the two control scheme examples, or a combination of both (e.g., using the scheme of example 1 after a phase and the scheme of example 2 after another), can be implemented with a controller to actively tune phase durations and maintain soft switching operation. Overall, the control schemes shown in the following flowcharts work as follows: the output of the analog sensing circuit for the switch node voltage is compared with a voltage reference or threshold: Vthi after phase 1 and Vth2 after phase 2. If there are more than two phases, there can be more than two voltage references (for n phases, there can be up to n different thresholds).Under certain embodiments / cases, one single threshold can serve for multiple phases, e.g., Vthi = Vth2. Depending on the sensed switch node voltage during a switching transition or deadtime (higher or lower than the threshold(s)), an incomplete soft condition is deduced, and the controller adjusts the corresponding phase duration accordingly for the upcoming switching cycles.

[0112] 5.1. Zero Current Switching (ZCS)

[0113] Example 1 : FIG. 20 illustrates a flowchart 710 of the control scheme to sense and dynamically maintain complete ZCS. There are four phases depicted with Phase 1 712, deadtime 714, Phase 2 716 and deadtime 718, which returns 720 back to Phase 1 to repeat the sequence.

[0114] In the following figures, two types of lines are shown. The solid lines and oval shapes represent a sequence in the time domain; whereas the dashed lines are intended to represent control related decisions in the “logic” of the controller, and how it changes the durations of phases 1 and 2.

[0115] At the first deadtime 714 a decision tree is shown. The first side of the tree depicts determining that vSw is less than Vthi 722a, and L is greater than 0 Amps 724a, wherein with these conditions met, at block 726a the duration of Phase 1 is increased in the next switching cycle. The second side of the tree depicts determining that vSw is greater than Vthi 722b, and II is less than 0 Amps 724b, wherein at block 726b as the conditions are met the block is executed which decreases the duration of Phase 1 in the next switching cycle. If neither sets of conditions are met, then the present settings remain. In either case, the controller proceeds to Phase 2 718.

[0116] At the second deadtime 718, a similar decision tree is shown. The first side of the tree depicts determining that vSw is less than Vth2 732a, and II is greater than 0 Amps 734a, wherein at block 736a the duration of Phase 2 is increased in the next switching cycle. The second side of the tree depicts determining that vSw is greater than Vth2 732b, and II is less than 0 Amps 734b, wherein at block 736b is executed which decreases the duration of Phase 2 in the next switching cycle. If neither set of conditions are met, then the present settings remain. In either case, the controller returns back toPhase 1 712.

[0117] Example 2: FIG. 21 is a flowchart 750 of the control scheme to sense and dynamically maintain complete ZCS, this is very similar to FIG. 20, with the exception of the decision directions. There are four phases depicted with Phase 1 752, deadtime 754, Phase 2 756 and deadtime 758, which returns back 760 to Phase 1 .

[0118] Beneath the first deadtime 754 a decision tree is shown. The first side of the tree depicts determining that vSw is greater than Vthi 762a, and II is greater than 0 Amps 764a, wherein at block 766a the duration of Phase 1 is increased in the next switching cycle.

[0119] The second side of the tree depicts determining that vSw is less than Vthi 762b, and II is less than 0 Amps 764b, wherein block 766b is executed which decreases the duration of Phase 1 in the next switching cycle. If neither set of conditions are met, then the present settings remain the same. In either case, the controller proceeds to Phase 2 756.

[0120] At the second deadtime 758, we see a similar decision tree. The first side of the tree depicts determining that vSw is greater than Vth2 772a, and II is greater than 0 Amps 774a, wherein at block 776a the duration of Phase 2 is increased in the next switching cycle.

[0121] The second side of the tree depicts determining that vSw is less than Vth2 772b, and II is less than 0 Amps 774b, wherein block 776b is executed which decreases the duration of Phase 2 in the next switching cycle. If neither set of conditions are met, then the present settings remain in effect. In either case, the controller returns to Phase 1 752.

[0122] 5.2. Zero Voltage Switching (ZVS)

[0123] Example 1 : FIG. 22 is a flowchart of the control scheme to sense and dynamically maintain complete ZVS. There are six phases depicted with Phase 1 812, Tdi 814, Td2 816, Phase 2 820 and Tdi 822, Td2 824 with return 826 back to Phase 1 .

[0124] At the first Tdi 814, a decision tree is seen. The first side of the tree depicts determining that vSw is greater than Vthi 830a, and that there is no Zero-Voltage Switching (ZVS) on switch S4 832a, wherein at block 834a theduration of Phase 1 is decreased in the next switching cycle.

[0125] The second side of the tree depicts determining that vSw is less than Vthi 830b, and that there is no ZVS on switch S4 832b, wherein block 834b is executed which increases the duration of Phase 1 in the next switching cycle. If neither set of conditions are met, then the present settings remain. In either case, the controller proceeds to Td2 816 and then Phase 2 820.

[0126] At the second Tdi 822, a decision tree is seen. The first side of the tree depicts determining that vSw is greater than Vth2 840a, and that there is no ZVS on switch S3 842a, wherein at block 844a the duration of Phase 2 is decreased in the next switching cycle.

[0127] The second side of the tree depicts determining that vSw is less than Vthi 840b, and that there is no ZVS on switch Si 842b, wherein block 844b is executed which increases the duration of Phase 2. If neither set of conditions are met, then the present settings remain. In either case the controller proceeds to Td2 824 and then returns to Phase 1 812.

[0128] Example 2: FIG. 23 is a flowchart of the control scheme to sense and dynamically maintain complete ZVS, and is similar to FIG. 22, except for the threshold conditions. There are six phases depicted with Phase 1 852, Tdi 854, Td2 856, Phase 2 858 and Tdi 860, and Td2 862 with return 864 back to Phase 1 852.

[0129] At the first Tdi 854, a decision tree is seen. The first side of the tree depicts determining that vSw is less than Vthi 870a, and that there is no ZVS on switch S4872a, wherein with these conditions met, at block 874a the duration of Phase 1 is decreased in the next switching cycle.

[0130] The second side of the tree depicts determining that vSw is greater than Vthi 870b, and that there is no ZVS on switch S4 872b, wherein block 874b is executed which increases the duration of Phase 1 in the next switching cycle. If neither set of conditions are met, then the present settings remain. In either case the controller proceeds to Td2 856 and then proceeds to Phase 2 858.

[0131] At the second Tdi 860, a decision tree is seen. The first side of the tree depicts determining that vSw is less than Vth2 880a, and that there is no ZVS on switch S3 882a, wherein at block 884a the duration of Phase 2 isdecreased in the next switching cycle.

[0132] The second side of the tree depicts determining that vSw is greater than Vth2 880b, and that there is no ZVS on switch Si 882b, wherein block 884b is executed which increases the duration of Phase 2 in the next switching cycle. If neither set of conditions are met, then the present settings remain. In either case the controller proceeds to Td2 862 and then returns to Phase 1 852.

[0133] 5.3 Merged ZCS / ZVS

[0134] Example 1 : FIG. 24 is a flowchart of the control scheme to sense and dynamically maintain a complete merged ZCS / ZVS. There are four phases depicted with Phase 1 912, Tdi or deadtime 914, Phase 2 916, then Tdi or deadtime 918, and a return 919 back to Phase 1 912.

[0135] At the first Tdi or deadtime 914, a decision tree is shown. The first side of the tree depicts determining that vSw is greater than Vthi 920a, and there is no ZVS on switch S4 922a, wherein at block 924a the duration of Phase 1 is decreased in the next switching cycle.

[0136] The second side of the tree depicts determining that vswis less than Vthi 920b, and that there is no ZCS (it should be noted that this threshold was ZVS in the first side of the tree) on switch S2 922b, wherein block 924b is executed which increases 924b the duration of Phase 1 in the next switching cycle. If neither set of conditions are met, then the present settings remain. In either case, the controller proceeds to Phase 2 916

[0137] At the second Tdi or deadtime 918, a similar decision tree is shown.The first side of the tree depicts determining that vswis greater than Vth2 930a, and that there is no ZVS on switch S3 932a, wherein at block 934a the duration of Phase 2 is decreased in the next switching cycle.

[0138] The second side of this tree depicts determining that vswis less than Vth2 930b and there is no ZCS on switch Si 932b, wherein block 934b is executed which increases the duration of Phase 2 in the next switching cycle. If neither set of conditions are met, then the present settings are retained. In either case, the controller returns to Phase 1 912.

[0139] Example 2: FIG. 25 is a flowchart of the control scheme to sense and dynamically maintain complete merged ZCS / ZVS, and is similar to FIG. 24,except for the threshold conditions.

[0140] There are four phases depicted with Phase 1 952, Tdi or deadtime 954, Phase 2 956 and Tdi or deadtime 958, and a return 959 back to Phase 1 952.

[0141] At the first Tdi or deadtime 954, a decision tree is shown. The first side of the tree depicts determining that vSw is less than Vthi 960a, and that there is no ZVS on switch S4 962a, wherein at block 964a the duration of Phase 1 is decreased in the next switching cycle.

[0142] The second side of this tree depicts determining that vSw is greater than Vthi 960b, and that there is no ZCS on switch S2 962b, wherein block 964b is executed which increases the duration of Phase 1 in the next switching cycle. If neither set of conditions are met, then the present settings are maintained. In either case the controller proceeds to Phase 2 956.

[0143] At the second Tdi or deadtime 958, a decision tree is shown. The first side of the tree depicts determining that vSw is less than Vth2 970a, and that there is no ZVS on switch S3 972a, wherein at block 974a the duration of Phase 1 is decreased in the next switching cycle.

[0144] The second side of this same tree depicts determining that vSw is greater than Vth2 970b, and that there is no ZCS on switch Si 972b, wherein block 974b is executed which increases the duration of Phase 2 in the next switching cycle. If neither set of conditions are met, then the present settings are retained. In either case the controller returns to Phase 1 952.

[0145] 6. General Implementations

[0146] From the description herein, it will be appreciated that the present disclosure encompasses multiple implementations of the technology which include, but are not limited to, the following:

[0147] A feedback control technique that utilizes sensing at the inductor switch node to detect incomplete ZCS operation. The feedback controller tunes phase timings to achieve ZCS operation in single inductor resonant switched- capacitor converters.

[0148] A feedback control technique that utilizes sensing at one or more inductor switch node(s) to detect incomplete ZCS operation. The feedback controller tunes phase timings to achieve ZCS operation in split-inductorresonant switched-capacitor converters.

[0149] A feedback control technique that utilizes sensing at the inductor switch node to detect incomplete ZVS operation. The feedback controller tunes phase timings to achieve ZVS operation in single inductor resonant switched- capacitor converters.

[0150] A feedback control technique that utilizes sensing at one or more inductor switch node(s) to detect incomplete ZVS operation. The feedback controller tunes phase timings to achieve ZVS operation in split-inductor resonant switched-capacitor converters.

[0151] A “merged ZCS / ZVS” switching scheme at the intersection of ZCS and ZVS that achieves ZVS on certain switches and ZCS on the others while maintaining a unidirectional inductor current in single inductor resonant switched-capacitor converters.

[0152] A “merged ZCS / ZVS” switching scheme at the intersection of ZCS and ZVS that achieves ZVS on certain switches and ZCS on the others while maintaining unidirectional inductor currents in split-inductor resonant switched-capacitor converters.

[0153] A feedback control technique that utilizes sensing at the inductor switch node to detect incomplete merged ZCS / ZVS operation. The feedback controller tunes phase timings to achieve merged ZCS / ZVS operation in single inductor resonant switched-capacitor converters.

[0154] A feedback control technique that utilizes sensing at one or more inductor switch node(s) to detect incomplete merged ZCS / ZVS operation. The feedback controller tunes phase timings to achieve merged ZCS / ZVS operation in split-inductor resonant switched-capacitor converters.

[0155] 7. General Scope of Embodiments

[0156] Embodiments of the technology of this disclosure may be described herein with reference to flowchart illustrations of methods and systems according to embodiments of the technology. Embodiments of the technology of this disclosure may also be described with reference to procedures, algorithms, steps, operations, formulae, or other computational depictions, which may be included within the flowchart illustrations or otherwise described herein. It will be appreciated that any of the foregoingmay also be implemented as computer program instructions. In this regard, each block or step of a flowchart, and combinations of blocks (and / or steps) in a flowchart, as well as any procedure, algorithm, step, operation, formula, or computational depiction can be implemented by various means, such as hardware, firmware, and / or software including one or more computer program instructions embodied in computer-readable program code. As will be appreciated, any such computer program instructions may be executed by one or more computer processors, including without limitation a general purpose computer or special purpose computer, or other programmable processing apparatus to produce a machine, such that the computer program instructions which execute on the computer processor(s) or other programmable processing apparatus create means for implementing the function(s) specified.

[0157] Accordingly, blocks of the flowcharts, and procedures, algorithms, steps, operations, formulae, or computational depictions described herein support combinations of means for performing the specified function(s), combinations of steps for performing the specified function(s), and computer program instructions, such as embodied in computer-readable program code logic means, for performing the specified function(s). It will also be understood that each block of the flowchart illustrations, as well as any procedures, algorithms, steps, operations, formulae, or computational depictions and combinations thereof described herein, can be implemented by special purpose hardware-based computer systems which perform the specified function(s) or step(s), or combinations of special purpose hardware and computer-readable program code.

[0158] Furthermore, these computer program instructions, such as embodied in computer-readable program code, may also be stored in one or more computer-readable memory or memory devices that can direct a computer processor or other programmable processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory or memory devices produce an article of manufacture including instruction means which implement the function specified in the block(s) of the flowchart(s). The computer program instructions may also be executed by acomputer processor or other programmable processing apparatus to cause a series of operational steps to be performed on the computer processor or other programmable processing apparatus to produce a computer- implemented process such that the instructions which execute on the computer processor or other programmable processing apparatus provide steps for implementing the functions specified in the block(s) of the flowchart(s), procedure (s) algorithm(s), step(s), operation(s), formula(e), or computational depiction(s).

[0159] It will further be appreciated that the terms "programming" or "program executable" as used herein refer to one or more instructions that can be executed by one or more computer processors to perform one or more functions as described herein. The instructions can be embodied in software, in firmware, or in a combination of software and firmware. The instructions can be stored local to the device in non-transitory media, or can be stored remotely such as on a server, or all or a portion of the instructions can be stored locally and remotely. Instructions stored remotely can be downloaded (pushed) to the device by user initiation, or automatically based on one or more factors.

[0160] It will further be appreciated that as used herein, the terms controller, microcontroller, processor, microprocessor, hardware processor, computer processor, central processing unit (CPU), and computer are used synonymously to denote a device capable of executing the instructions and communicating with input / output interfaces and / or peripheral devices, and that the terms controller, microcontroller, processor, microprocessor, hardware processor, computer processor, CPU, and computer are intended to encompass single or multiple devices, single core and multicore devices, and variations thereof.

[0161] From the description herein, it will be appreciated that the present disclosure encompasses multiple implementations of the technology which include, but are not limited to, the following:

[0162] A switched capacitor converter apparatus, comprising: (a) a resonant switched capacitor (ReSC) converter having an inductor switch node; (b) a control circuit configured for generating phase signals to said ReSC converterto control the operation of switches within said ReSC converter; (c) a sensing circuit coupled to said inductor switch node of said ReSC converter; (d) wherein said sensing circuit is configured for determining conditions for soft- switching of the ReSC converter; and (e) wherein said control circuit receives soft-switching information from said sensing circuit, and when the soft- switching information indicates when the ReSC converter is not operating at a complete soft-switching condition, said control circuit adjusts phase durations being sent to the ReSC converter to provide closed-loop autotuning of the ReSC converter to attain a complete soft-switching condition.

[0163] A switched capacitor converter apparatus, comprising: (a) a resonant switched capacitor (ReSC) converter, configured for up-conversion or downconversion, and having an inductor switch node; (b) a control circuit configured for generating phase signals to said ReSC converter to control the operation of switches within said ReSC converter; (c) a sensing circuit coupled to said inductor switch node of said ReSC converter, which comprises either an input inductor based, or an output inductor based, ReSC converter; (d) wherein said sensing circuit is configured for determining conditions for soft-switching of the ReSC converter; (e) wherein said control circuit receives soft-switching information from said sensing circuit, and when the soft-switching information indicates when the ReSC converter is not operating at a complete soft-switching condition, wherein said control circuit adjusts phase durations being sent to the ReSC converter to provide closed- loop autotuning of the ReSC converter to attain a complete soft-switching condition; (f) wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to as be between a first set of thresholds and a second set of thresholds, which provide a lower and upper bound on what is considered the complete soft- switching condition; and (g) wherein said apparatus overcomes the need for manual phase tuning that is sensitive to ambient conditions and circuit variations.

[0164] A feedback control method that utilizes sensing at the inductor switch node to detect incomplete ZCS operation. The feedback controller tunes phase timings to achieve ZCS operation in single inductor resonant switched-capacitor converters.

[0165] A feedback control method that utilizes sensing at a single inductor switch node to detect incomplete ZCS operation. The feedback controller tunes phase timings to achieve ZCS operation in split-inductor resonant switched-capacitor converters.

[0166] A feedback control method that utilizes sensing at the inductor switch node to detect incomplete ZVS operation. The feedback controller tunes phase timings to achieve ZVS operation in single inductor resonant switched- capacitor converters.

[0167] A feedback control method that utilizes sensing at a single inductor switch node to detect incomplete ZVS operation. The feedback controller tunes phase timings to achieve ZVS operation in split-inductor resonant switched-capacitor converters.

[0168] A “merged ZCS / ZVS” switching method at the intersection of ZCS and ZVS that achieves ZVS on certain switches and ZCS on the others while maintaining a unidirectional inductor current in single inductor resonant switched-capacitor converters.

[0169] A “merged ZCS / ZVS” switching method at the intersection of ZCS and ZVS that achieves ZVS on certain switches and ZCS on the others while maintaining unidirectional inductor currents in split-inductor resonant switched-capacitor converters.

[0170] A feedback control method that utilizes sensing at the inductor switch node to detect incomplete merged ZCS / ZVS operation. The feedback controller tunes phase timings to achieve merged ZCS / ZVS operation in single inductor resonant switched-capacitor converters.

[0171] A feedback control method that utilizes sensing at a single inductor switch node to detect incomplete merged ZCS / ZVS operation. The feedback controller tunes phase timings to achieve merged ZCS / ZVS operation in splitinductor resonant switched-capacitor converters.

[0172] The apparatus or method of any preceding implementation, wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to be within at least one set of thresholds.

[0173] The apparatus or method of any preceding implementation, wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to be between a first set of thresholds and a second set of thresholds, which provide a lower and upper bound on what is considered the complete soft-switching condition.

[0174] The apparatus or method of any preceding implementation, wherein said sensing circuit is operating in combination with said control circuit and said ReSC converter to perform detection and correction of incomplete soft switching conditions to ensure maintaining complete soft switching conditions.

[0175] The apparatus or method of any preceding implementation, wherein said apparatus overcomes requirements for manual phase tuning which is sensitive to ambient conditions and circuit variations.

[0176] The apparatus or method of any preceding implementation, wherein said ambient conditions comprise temperature.

[0177] The apparatus or method of any preceding implementation, wherein said circuit variations comprise component tolerance, derating, and aging.

[0178] The apparatus or method of any preceding implementation, wherein said ReSC converter is configured for voltage step-up-conversion or voltage step-down-conversion.

[0179] The apparatus or method of any preceding implementation, wherein said ReSC converter comprises a series of connected ReSC converters to obtain an overall higher up-conversion or down-conversion ratio.

[0180] The apparatus or method of any preceding implementation, wherein said ReSC converter comprises paralleled, or interleaved, ReSC converters wherein multiple units are operating in parallel.

[0181] The apparatus or method of any preceding implementation, wherein said ReSC converter comprises an ReSC converter which is either an input inductor based, or output inductor based, ReSC converter.

[0182] The apparatus or method of any preceding implementation, wherein said apparatus is configured for being utilized in converter applications, selected from the group of converter application consisting of: (a) hybrid and resonant switched capacitor converters; (b) intermediate bus converters; (c) power converters for automotive applications; and (d) renewable energyapplications and microinverters.

[0183] The apparatus or method of any preceding implementation, wherein said ReSC converter comprises a single inductor converter, or a split inductor ReSC.

[0184] The apparatus or method of any preceding implementation, wherein said ReSC converter maintains unidirectional inductor current for both single inductor, and split inductor, ReSC converters.

[0185] The apparatus or method of any preceding implementation, wherein said conditions for soft-switching of the ReSC converter are based on detecting incomplete zero-current switching (ZCS), whereby said control circuit tunes phase timings to achieve ZCS operation in the ReSC.

[0186] The apparatus or method of any preceding implementation, wherein said conditions for soft-switching of the ReSC converter are based on detecting incomplete zero-voltage switching (ZVS), whereby said control circuit tunes phase timings to achieve ZVS operation in the ReSC.

[0187] The apparatus or method of any preceding implementation, wherein said conditions for soft-switching of the ReSC converter are based on a merged zero-current switching (ZCS), zero-voltage switching (ZVS) for achieving ZVS on select switches and ZCS on other switches.

[0188] As used herein, the term "implementation" is intended to include, without limitation, embodiments, examples, or other forms of practicing the technology described herein.

[0189] As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. Reference to an object in the singular is not intended to mean "one and only one" unless explicitly so stated, but rather "one or more."

[0190] Phrasing constructs, such as “A, B and / or C”, within the present disclosure describe where either A, B, or C can be present, or any combination of items A, B and C. Phrasing constructs indicating, such as “at least one of” followed by listing a group of elements, indicates that at least one of these groups of elements is present, which includes any possible combination of the listed elements as applicable.

[0191] References in this disclosure referring to “an embodiment”, “at leastone embodiment” or similar embodiment wording indicates that a particular feature, structure, or characteristic described in connection with a described embodiment is included in at least one embodiment of the present disclosure. Thus, these various embodiment phrases are not necessarily all referring to the same embodiment, or to a specific embodiment which differs from all the other embodiments being described. The embodiment phrasing should be construed to mean that the particular features, structures, or characteristics of a given embodiment may be combined in any suitable manner in one or more embodiments of the disclosed apparatus, system, or method.

[0192] As used herein, the term "set" refers to a collection of one or more objects. Thus, for example, a set of objects can include a single object or multiple objects.

[0193] Relational terms such as first and second, top and bottom, upper and lower, left and right, topside and underside, front and back, proximal and distal, leading and trailing, and the like, may be used solely to distinguish one entity, action, or orientation from another entity, action, or orientation without necessarily requiring or implying any actual such relationship or order between such entities, actions, or orientations. Such terms are not intended to be terms of limitation read into the claims.

[0194] The terms "comprises," "comprising," "has", "having," "includes", "including," "contains", "containing" or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, apparatus, or system, that comprises, has, includes, or contains a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, apparatus, or system. An element proceeded by "comprises . . . a", "has . . . a", "includes . . . a", "contains . . . a" does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, apparatus, or system, that comprises, has, includes, contains the element.

[0195] As used herein, the terms "approximately", "approximate", "substantially", "substantial", "essentially", and "about", or any other version thereof, are used to describe and account for small variations. When used inconjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. When used in conjunction with a numerical value, the terms can refer to a range of variation of less than or equal to ± 10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1 %, less than or equal to ±0.5%, less than or equal to ±0.1 %, or less than or equal to ±0.05%. For example, "substantially" aligned can refer to a range of angular variation of less than or equal to ±10°, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1 °, less than or equal to ±0.5°, less than or equal to ±0.1 °, or less than or equal to ±0.05°.

[0196] Additionally, amounts, ratios, and other numerical values may sometimes be presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified. For example, a ratio in the range of about 1 to about 200 should be understood to include the explicitly recited limits of about 1 and about 200, but also to include individual ratios such as about 2, about 3, and about 4, and sub-ranges such as about 10 to about 50, about 20 to about 100, and so forth.

[0197] The term "coupled" as used herein is defined as connected, although not necessarily directly and not necessarily mechanically. A device or structure that is "configured" in a certain way is configured in at least that way, but may also be configured in ways that are not listed.

[0198] Benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of the technology described herein or any or all the claims.

[0199] In addition, in the foregoing disclosure various features may begrouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Inventive subject matter can lie in less than all features of a single disclosed embodiment.

[0200] The abstract of the disclosure is provided to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

[0201] It will be appreciated that the practice of some jurisdictions may require deletion of one or more portions of the disclosure after the application is filed. Accordingly, the reader should consult the application as filed for the original content of the disclosure. Any deletion of content of the disclosure should not be construed as a disclaimer, forfeiture, or dedication to the public of any subject matter of the application as originally filed.

[0202] All text in a drawing figure is hereby incorporated into the disclosure and is to be treated as part of the written description of the drawing figure.

[0203] The following claims are hereby incorporated into the disclosure, with each claim standing on its own as a separately claimed subject matter.

[0204] Although the description herein contains many details, these should not be construed as limiting the scope of the disclosure, but as merely providing illustrations of some of the presently preferred embodiments. Therefore, it will be appreciated that the scope of the disclosure fully encompasses other embodiments which may become obvious to those skilled in the art.

[0205] All structural and functional equivalents to the elements of the disclosed embodiments that are known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the present claims. Furthermore, no element, component, or method step in the present disclosure is intended to be dedicated to the public regardless of whether the element, component, or method step is explicitly recited in the claims. No claim element herein is to be construed as a "means plus function" element unless the element is expressly recited using the phrase "means for". No claim element herein is to be construed as a"step plus function" element unless the element is expressly recited using the phrase "step for".

Claims

CLAIMSWhat is claimed is:1 . A switched capacitor converter apparatus, comprising: a resonant switched capacitor (ReSC) converter having an inductor switch node; a control circuit configured for generating phase signals to said ReSC converter to control the operation of switches within said ReSC converter; a sensing circuit coupled to said inductor switch node of said ReSC converter; wherein said sensing circuit is configured for determining conditions for soft- switching of the ReSC converter; and wherein said control circuit receives soft-switching information from said sensing circuit, and when the soft-switching information indicates when the ReSC converter is not operating at a complete soft-switching condition, said control circuit adjusts phase durations being sent to the ReSC converter to provide closed-loop autotuning of the ReSC converter to attain a complete soft-switching condition.

2. The apparatus of claim 1 , wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to be within at least one set of thresholds.

3. The apparatus of claim 1 , wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to be between a first set of thresholds and a second set of thresholds, which provide a lower and upper bound on what is considered the complete soft- switching condition.

4. The apparatus of claim 1 , wherein said sensing circuit is operating in combination with said control circuit and said ReSC converter to perform detection and correction of incomplete soft switching conditions to ensure maintaining complete soft switching conditions.

5. The apparatus of claim 1 , wherein said apparatus overcomes requirements for manual phase tuning which is sensitive to ambient conditions and circuit variations.

6. The apparatus of claim 5, wherein said ambient conditions comprise temperature.

7. The apparatus of claim 5, wherein said circuit variations comprise component tolerance, derating, and aging.

8. The apparatus of claim 1 , wherein said ReSC converter is configured for voltage step-up-conversion or voltage step-down-conversion.

9. The apparatus of claim 1 , wherein said ReSC converter comprises a series of connected ReSC converters to obtain an overall higher up-conversion or down-conversion ratio.

10. The apparatus of claim 1 , wherein said ReSC converter comprises paralleled, or interleaved, ReSC converters wherein multiple units are operating in parallel.11 . The apparatus of claim 1 , wherein said ReSC converter comprises an ReSC converter which is either an input inductor based, or output inductor based, ReSC converter.

12. The apparatus of claim 1 , wherein said apparatus is configured for being utilized in converter applications, selected from the group of converter application consisting of: (a) hybrid and resonant switched capacitor converters; (b) intermediate bus converters; (c) power converters for automotive applications; and (d) renewable energy applications and microinverters.

13. The apparatus of claim 1 , wherein said ReSC converter comprises a single inductor converter, or a split inductor ReSC.

14. The apparatus of claim 13, wherein said ReSC converter maintains unidirectional inductor current for both single inductor, and split inductor, ReSC converters.

15. The apparatus of claim 1 , wherein said conditions for soft-switching of the ReSC converter are based on detecting incomplete zero-current switching (ZCS), whereby said control circuit tunes phase timings to achieve ZCS operation in the ReSC.

16. The apparatus of claim 1 , wherein said conditions for soft-switching of the ReSC converter are based on detecting incomplete zero-voltage switching (ZVS), whereby said control circuit tunes phase timings to achieve ZVS operation in the ReSC.

17. The apparatus of claim 1 , wherein said conditions for soft-switching of the ReSC converter are based on a merged zero-current switching (ZCS), zerovoltage switching (ZVS) for achieving ZVS on select switches and ZCS on other switches.

18. A switched capacitor converter apparatus, comprising: a resonant switched capacitor (ReSC) converter, configured for up-conversion or down-conversion, and having an inductor switch node; a control circuit configured for generating phase signals to said ReSC converter to control the operation of switches within said ReSC converter; a sensing circuit coupled to said inductor switch node of said ReSC converter, which comprises either an input inductor based, or an output inductor based, ReSC converter; wherein said sensing circuit is configured for determining conditions for soft- switching of the ReSC converter; wherein said control circuit receives soft-switching information from said sensing circuit, and when the soft-switching information indicates when the ReSC converter is not operating at a complete soft-switching condition, wherein saidcontrol circuit adjusts phase durations being sent to the ReSC converter to provide closed-loop autotuning of the ReSC converter to attain a complete soft-switching condition; wherein said complete soft-switching condition is met when the soft-switching information from said sensing circuit is determined to as be between a first set of thresholds and a second set of thresholds, which provide a lower and upper bound on what is considered the complete soft-switching condition; and wherein said apparatus overcomes the need for manual phase tuning that is sensitive to ambient conditions and circuit variations.

19. The apparatus of claim 18, wherein said ReSC converter comprises a series of connected ReSC converters to obtain an overall higher up-conversion or down-conversion ratio, or paralleled I interleaved, ReSC converters wherein multiple units are running in parallel.

20. The apparatus of claim 18, wherein said apparatus is configured for being utilized in converter applications, selected from the group of converter application consisting of: (a) hybrid and resonant switched capacitor converters; (b) intermediate bus converters; (c) power converters for automotive applications; and (d) renewable energy applications and microinverters.

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