Wafer, wafer surface nanotopography prediction method and apparatus, device, and medium

Abstract

The present disclosure belongs to the technical field of semiconductor manufacturing. Provided are a wafer, a wafer surface nanotopography prediction method and apparatus, a device, and a medium. The method comprises: during the processing of a wafer, using a step-type design filter to perform filtering and data processing on acquired surface topography measurement data of the wafer, so as to obtain a measured nanotopography value nt of the wafer; and on the basis of a prediction function f(nt)=NT and the measured nanotopography value nt of the wafer, performing prediction to obtain a predicted nanotopography value NT of the wafer after subsequent processing procedures.

Description

Wafer and surface nanotopography prediction method, device, equipment and medium thereof

[0001] Cross-reference to Related Applications

[0002] The present disclosure claims priority from Chinese Patent Application No. 202410895811.6 filed on July 5, 2024 in China, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor manufacturing, and in particular, to a wafer and surface nanotopography prediction method, device, equipment and medium thereof. BACKGROUND

[0004] In the wafer manufacturing process, after a single crystal silicon rod is prepared by the Czochralski method, the single crystal silicon rod is sequentially subjected to wire cutting, grinding, etching, grinding and chemical mechanical polishing (CMP) and other processing procedures, and finally a single crystal silicon wafer is obtained. For a single crystal silicon wafer, the surface topography is a key parameter for measuring its quality. The nanotopography (NT) of the wafer is an important quality parameter in the wafer surface topography parameters.

[0005] In related solutions, the NT detection of the wafer is usually set after the last surface processing procedure, i.e. the CMP procedure. However, for nanotopography, a short-wave related quality parameter, it is largely determined by the processing procedure before chemical mechanical polishing. That is, in the implementation process of the related solution, when there is a problem in the processing procedure before CMP, it can only be found after the CMP procedure. As a result, the wafer with a problem in the processing before CMP still undergoes the complete wafer manufacturing process, which is a waste of production resources. SUMMARY

[0006] Therefore, the present disclosure aims to provide a wafer and surface nanotopography prediction method, device, equipment and medium thereof, which can predict the predicted nanotopography value of the wafer after completing the subsequent procedure according to the measured nanotopography value of the wafer after completing the current processing procedure. This allows the use of the predicted nanotopography data to monitor the product performance of the front-end processing procedure, avoiding the flow of poor wafers from the front-end processing procedure into the subsequent processing procedure, and avoiding the waste of production resources.

[0007] The technical solution of the present disclosure is implemented as follows:

[0008] In a first aspect, the present disclosure provides a wafer surface nanotopography prediction method, comprising:

[0009] In the processing of the wafer, the surface topography measurement data of the wafer obtained is filtered and data processed by using a step design filter to obtain the measured nanotopography value nt of the wafer.

[0010] Based on the prediction function f(nt)=NT, the predicted nanotopography value NT of the wafer after the subsequent processing procedure is predicted according to the measured nanotopography value nt of the wafer.

[0011] In a second aspect, the present disclosure provides a wafer surface nanotopography prediction device, comprising a filtering part and a prediction part, wherein,

[0012] The filtering part is configured to filter and data process the surface topography measurement data of the wafer obtained in the processing of the wafer by using a step design filter to obtain the measured nanotopography value nt of the wafer.

[0013] The prediction part is configured to predict the predicted nanotopography value NT of the wafer after the subsequent processing procedure based on the prediction function f(nt)=NT according to the measured nanotopography value nt of the wafer.

[0014] In a third aspect, the present disclosure provides a computing device, comprising a processor and a memory, wherein the processor is configured to execute instructions stored in the memory to implement the wafer surface nanotopography prediction method of the first aspect.

[0015] In a fourth aspect, the present disclosure provides a computer readable storage medium, which stores at least one instruction for being executed by a processor to implement the wafer surface nanotopography prediction method of the first aspect.

[0016] In a fifth aspect, the present disclosure provides a wafer, wherein the predicted nanotopography value of the wafer is less than 5nm in a 2mm*2mm specification and / or less than 10nm in a 10mm*10mm specification, and the final wafer has a nanotopography value of less than 5nm in a 2mm*2mm specification and less than 10nm in a 10mm*10mm specification.

[0017] The present disclosure provides a wafer and a method for predicting the surface nanotopography of the wafer, a device, an apparatus and a medium. The method uses a prediction function and the measured nanotopography value of the wafer after a current processing procedure to predict the predicted nanotopography value of the wafer after a subsequent processing procedure. The predicted nanotopography value can be used to monitor each processing procedure to ensure the stability and consistency of the processing equipment used in the processing procedure, and to monitor the product of each processing procedure to ensure that the qualified product enters the next processing procedure, improve the microtopography quality of the wafer surface, avoid subsequent processing procedures to process products with low future qualification possibility, thereby reducing the processing cost, and the predicted nanotopography value can also be used to determine whether the process of the completed procedure has a problem to assist process adjustment. BRIEF DESCRIPTION OF DRAWINGS

[0018] Fig. 1 is a flowchart of a method for predicting the nanotopography of a wafer surface according to the present disclosure;

[0019] Fig. 2 is a linear correlation diagram of the predicted NT value and the actually measured NT value obtained based on the sampling data of 100 wafers according to the present disclosure;

[0020] Fig. 3 is a schematic diagram of a device for predicting the nanotopography of a wafer surface according to the present disclosure;

[0021] Fig. 4 is a schematic diagram of another device for predicting the nanotopography of a wafer surface according to the present disclosure;

[0022] Fig. 5 is a schematic diagram of a computing device according to the present disclosure. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present disclosure.

[0024] In related solutions, the wafer surface after a CMP procedure is divided into analysis regions according to a set size, the peak-to-valley values in the filtered measurement data at each sampling point in each analysis region are arranged in ascending order, and a value at a corresponding position in the ascending order according to a set percentile (for example, 99.5%) is selected as the nanotopography (NT) value of the wafer.

[0025] From the wafer surface, the filtered measurement data at each sampling point in each region will show fluctuations in the measurement data of each sampling point as a whole. The present disclosure considers this fluctuation phenomenon as being caused by the superposition of wave signals of different wavelengths from the perspective of waves. Different wavelengths can correspond to the size of the region where the wave phenomenon occurs, that is, the smaller the wavelength of the wave signal, the smaller the size of the region where the measurement data fluctuation phenomenon occurs; the larger the wavelength of the wave signal, the larger the size of the region where the measurement data fluctuation phenomenon occurs. In the fluctuation phenomenon presented by the measurement data, signal data with longer wavelengths can include parameters such as Bow, Warp, etc. These parameters are roughly shaped after the line cutting process, and subsequent processing processes have little effect on them. For signal data with shorter wavelengths, such as nanotopography values, all front-end processing processes before the CMP process will affect them. The NT value of the wafer obtained by the related scheme is the NT value of the wafer after the CMP process. This data can only represent the performance of the entire wafer processing process, and cannot evaluate the performance of each processing process in the processing process. Moreover, as the requirements for the microtopography of the wafer surface become increasingly stringent, each processing process needs to be monitored to ensure the stability and consistency of the processing equipment used in the processing process, and the products of each processing process are monitored to ensure that qualified products enter the next processing process, thereby improving the microtopography quality of the wafer surface.

[0026] Based on this, the present disclosure provides a wafer surface nanotopography prediction method, which comprises steps S101 to S102.

[0027] In step S101, in the processing process of the wafer, the acquired surface topography measurement data of the wafer is filtered and data processed by using a stepwise designed filter, and the measurement nanotopography value nt of the wafer is obtained.

[0028] In the present disclosure, the measurement nanotopography value of the wafer is obtained after any process in the wafer processing process is completed. In some examples, after any processing process (such as line cutting) is completed, the surface height of the sampling point on the wafer surface after line cutting can be measured by a single-point measurement scheme to obtain the surface topography measurement data of the wafer.

[0029] In the above example, the single measurement scheme is a scheme in which only one sampling point is measured in one measurement process. For example, a contact measurement scheme can be used, such as using a probe to contact the wafer surface to be measured and moving horizontally on the wafer surface. As the horizontal movement, the height difference of the wafer surface to be measured will cause the probe to produce a longitudinal displacement, which is sensed by a displacement sensor and converted into height data of the wafer surface to be measured, i.e. historical measurement data about the historical wafer surface height. For example, a non-contact measurement scheme such as capacitive measurement, laser focusing measurement, etc. can also be used.

[0030] Of course, in some examples, the surface topography measurement data of the wafer after completing the current processing procedure can also be obtained by only one measurement process, such as a scheme using optical means (such as Fizeau interference, differential interference, etc.) for measurement. The present disclosure does not repeat the details here.

[0031] Specifically, the sampling interval used when performing measurement can be determined by the accuracy of the device performing measurement and the specific recipe. For example, for an optical measurement device, the sampling interval can be as low as 0.2 mm, and for some low-precision capacitive measurement devices, the sampling interval can be increased to 4 mm.

[0032] In the present disclosure, the surface topography measurement data of all sampling points can be regarded as a three-dimensional fluctuation phenomenon from the entire wafer surface. This fluctuation phenomenon can be formed by superimposing wave signals of different wavelengths. For the NT value, the corresponding wavelength range is 22 microns to 20 millimeters. In some examples, the surface topography measurement data is filtered by a filter to obtain a filtered value in the wavelength range from 22 microns to 20 millimeters.

[0033] In some examples, the present disclosure does not use a filter of a fixed size to filter the surface topography measurement data of all sampling points on the wafer surface. The size of the filter changes with the position of the sampling point. For example, the filter is a step design filter, and the size of the step design filter can be designed according to the target wavelength range, the sampling interval, and the position of the sampling point of the wafer surface topography measurement data.

[0034] In the present disclosure, taking the target wavelength range of 22 microns to 20 millimeters as an example, after obtaining the filtered value in the wavelength range from 22 microns to 20 millimeters, a plurality of analysis regions can be divided on the wafer surface, the Peak to valley (PV) value of the filtered value in each analysis region is obtained, and after arranging all the PV values of the analysis regions in ascending order, the PV value selected according to the set percentile is taken as the measurement nanotopography value of the wafer after completing the line cutting.

[0035] In step S102, a predicted nanotopography value NT of the wafer after a subsequent processing procedure is predicted based on a prediction function f(nt) = NT according to a measured nanotopography value nt of the wafer.

[0036] In the present disclosure, the subsequent processing procedure refers to a processing procedure after the procedure of obtaining the surface topography measurement data of the wafer in step S101 in the wafer processing process. For example, if the surface topography measurement data of the wafer after the wire sawing procedure is obtained in step S101, the subsequent processing procedure in step S102 can be a procedure after the wire sawing procedure in the wafer processing process, such as a grinding procedure, an etching procedure, a lapping procedure, a CMP procedure, etc.

[0037] For example, taking the wire sawing procedure as an example, it is assumed that a normal distribution of the wafer NT value is formed after the wire sawing procedure, and based on the assumption, it can be considered that there is a fixed functional relationship between the nanotopography value of the wafer after the wire sawing procedure and the nanotopography value of the wafer after the subsequent processing procedure, which is represented by NT = f(nt) in the present disclosure, wherein NT represents the predicted nanotopography value of the wafer after the subsequent processing procedure, nt represents the measured nanotopography value of the wafer obtained in step S101, and f() represents the expression of the prediction function.

[0038] In the present disclosure, after obtaining the predicted nanotopography value of the wafer, the currently completed processing procedure can be evaluated.

[0039] In some examples, the working state of the equipment performing the currently completed processing procedure can be determined according to the statistics of the predicted nanotopography value of the wafer, so as to ensure the stability and consistency of the equipment and avoid machine difference. For example, the NT predicted value of all products processed by each equipment per day is monitored, and if the NT predicted value is discrete, too many outliers appear, the mean value is too large, etc., it indicates that the equipment is unstable and needs to be stopped for maintenance.

[0040] In some examples, whether the wafer continues to perform the subsequent processing procedure can be determined according to the comparison result of the predicted nanotopography value of the wafer and the set evaluation index, so as to screen qualified products for delivery and avoid processing products with low possibility of being qualified in the subsequent processing procedure, thereby reducing the processing cost.

[0041] In some examples, the process parameters of the currently completed processing procedure are adjusted according to the predicted nanotopography value of the wafer. For example, whether the process of the completed procedure has a problem is judged according to the predicted nanotopography value of the product of each processing procedure, so as to assist process adjustment and be more targeted. In the process adjustment, the process parameters of the processing procedure can also be fed back and adjusted by referring to the predicted nanotopography value.

[0042] By the technical solution shown in FIG. 1, the predicted function and the measured nanotopography value of the wafer after completing the current processing procedure are used to predict the predicted nanotopography value of the wafer after completing the subsequent processing procedure. The predicted nanotopography value can not only monitor each processing procedure to ensure the stability and consistency of the processing equipment used in the processing procedure, but also monitor the product of each processing procedure to ensure that the qualified product enters the next processing procedure, improve the microtopography quality of the wafer surface, avoid the processing of the subsequent processing procedure to produce products with low future qualification possibility, thereby reducing the processing cost, and can also be used to judge whether the process of the completed procedure has a problem to assist process adjustment.

[0043] For the technical solution shown in FIG. 1, in some possible implementation manners, the size of the stepwise design filter in step S101 can be designed according to the target wavelength range, the sampling pitch, and the sampling point position of the wafer surface topography measurement data. The specific design process can include:

[0044] determining the filter by using a double-Gaussian low-pass filter function based on the target wavelength range;

[0045] determining the critical size of the filter according to the upper limit of the wavelength of the target wavelength range;

[0046] performing edge shrinkage processing according to the sampling point position;

[0047] when the distance between the sampling point position and the wafer surface center is less than or equal to the critical size, determining the radius of the stepwise design filter as a first radius; or

[0048] when the distance between the sampling point position and the wafer surface center is greater than the critical size, determining the radius of the stepwise design filter as a second radius; wherein the first radius is greater than the second radius.

[0049] For the above example, the target wavelength range can be 22 microns to 20 millimeters corresponding to the NT value. In the present disclosure, the filter can be a circular filter and composed of a double-Gaussian low-pass filter function. Specifically, the determination of the filter by using a double-Gaussian low-pass filter function based on the target wavelength range includes:

[0050] determining a first Gaussian low-pass filter function with a low-pass filter range covering the upper limit of the target wavelength range;

[0051] determining a second Gaussian low-pass filter function with a low-pass filter range covering the lower limit of the target wavelength range;

[0052] determining the radius of the stepwise design filter according to the first Gaussian low-pass filter function G LP1G LP2 The function G used to describe the filter is obtained according to the following formula DHP : G DHP = G LP1 (1-G LP2 ).

[0053] For example, the relationship between the cutoff wavelength and the standard deviation is defined as λ c = 6σ, and the Gaussian low-pass filter functions are where λ represents the parameter of the function as the wavelength. It should be noted that the standard deviations σ of the first Gaussian low-pass filter function and the second Gaussian low-pass filter function are different, so that signals in different wavelength ranges can be preserved.

[0054] After obtaining the circular filter through the above specific scheme, the action range of the filter needs to be set according to the sampling point position of the filtering calculation. Specifically, since the closer to the edge of the wafer surface, the more dramatic the topography changes, in order to accurately capture the dramatic topography changes and effectively capture the surface topography features of different scales, when the sampling point is close to the edge of the wafer surface, the action range of the corresponding circular filter should be smaller than that of the sampling point close to the center of the wafer surface, that is, as the sampling point gradually moves away from the center of the wafer surface, the action range of the corresponding filter should decrease, or be called edge shrinkage. In the present disclosure, the edge shrinkage is stepwise, that is, a critical size is set to determine whether the sampling point is close to the center of the wafer surface or close to the edge of the wafer surface. Compared to the sampling point close to the center of the wafer surface, when the sampling point is close to the edge of the wafer surface, the action range of the filter should be shrunk (k is the edge processing coefficient when the shrinkage is performed), and when the distance between the sampling point and the center of the wafer surface is greater than the critical size, the second radius is fixedly set to a value smaller than the first radius. Taking a 12-inch wafer as an example, the radius R = 150 mm, the edge removal amount (EE) is usually 3 mm during measurement, and the upper limit w of the target wavelength range is 20 mm. The critical size a can be calculated according to the following formula: a = R - EE - 0.5 * w

[0055] In the present disclosure, the stepwise radius of the filter according to the critical size is shown in Table 1.

[0056] Table 1

[0057] In some examples, when the distance between the sampling point and the center of the wafer surface is greater than the critical size, the second radius is not only set to be smaller than the first radius, but also set to decrease, for example, linearly decrease, with the increase of the distance between the sampling point and the center of the wafer surface, instead of being set to a fixed value.

[0058] Based on the above implementation, after obtaining the circular filter and the radius of its action range according to the above scheme, the surface topography measurement data of the wafer can be filtered using the filter to obtain the measurement nanotopography value of the wafer. Specifically, obtaining the measurement nanotopography value of the wafer can include:

[0059] After filtering the surface topography measurement data of the wafer using the step filter, the filtered value of each sampling point position is obtained.

[0060] All sampling points are divided into at least one analysis region according to the set size.

[0061] The maximum and minimum filtered values in each analysis region are obtained to obtain the peak-to-valley (PV) value of each analysis region.

[0062] After arranging the PV values of all analysis regions in ascending order, the selected PV value according to the set percentile is taken as the measurement nanotopography value of the wafer.

[0063] In the above example, when the sampling point is near the edge of the wafer, and the action range of the filter exceeds the edge range of the wafer surface, during the filtering process, the part of the action range of the filter that exceeds the edge range of the wafer surface can be supplemented with interpolation filling method, or can not be filled. The interpolation filling method can be linear extrapolation, symmetric interpolation, cubic spline interpolation, etc., which is not described in detail in the present disclosure.

[0064] In the above example, the division of the analysis region can be determined according to the specific surface topography measurement and analysis requirements. In the present disclosure, the analysis region is obtained by uniform grid division, that is, the data is divided into several uniform small grids on the wafer surface, each grid is an analysis region and the size of each grid is a square of 10*10 microns or 20*20 microns.

[0065] In the above example, after arranging the PV values of each analysis region in ascending order, the PV value in the Nth order can be selected as the measurement nanotopography value of the wafer according to a specific percentile, such as 99%, 99.5%, etc.

[0066] For the technical scheme shown in FIG. 1, in some possible implementation, the method further includes a process of obtaining a prediction function, specifically, the process can include:

[0067] According to the mathematical modeling and fitting of the measurement nanotopography value of the historical wafer after completing the current processing procedure and the measurement nanotopography value of the historical wafer after completing the subsequent processing procedure, the prediction function is obtained by linear fitting or polynomial fitting.

[0068] For the above implementation, in detail, whether the measured nanotopography value after completing the current processing procedure or the measured nanotopography value after completing the subsequent processing procedure, the measured nanotopography value of the historical wafer can be obtained by filtering and data processing on the surface topography measurement data of the historical wafer using the step design filter. In the specific implementation process, the specific acquisition process of the measured nanotopography value of the wafer is the same as that in the foregoing scheme, and the disclosure does not repeat it here.

[0069] For the present implementation, in some examples, the specific implementation details of the prediction function obtained by linear fitting or polynomial fitting can include:

[0070] First, the measured nanotopography value of the historical wafer after completing the current processing procedure and the nanotopography value of the historical wafer after completing the subsequent processing procedure are arranged into a data set, such as stored in the form of a matrix, each row in the matrix corresponding to a sample.

[0071] Next, according to the actual situation, a suitable prediction function f(nt) = NT is selected, such as a linear function, a polynomial function, an exponential function, a logarithmic function, etc. Taking the selection of polynomial fitting as an example, for polynomial fitting, the least squares method is usually used to fit the data, that is, by minimizing the sum of squares of residuals between the actual observed value NT and the fitted value (f(nt) value) to determine the parameters of the prediction function f(nt), and finally obtain the prediction function that can be applied in actual production.

[0072] Based on the foregoing technical scheme, the disclosure is described in a specific embodiment, in which, taking 100 bare wafers with a radius of 150 mm after wire cutting as an example, after removing the edge of each bare wafer according to the edge removal amount (EE) of 4 mm, the height data of the surface of each bare wafer is measured by using the capacitance method to obtain the surface topography measurement data of each bare wafer. For example, according to uniform sampling in the polar coordinate system with the center of the wafer surface as the pole, that is, measuring one diameter direction every 45°, and the sampling interval on each diameter direction is 4 mm, in the polar coordinate system, the surface topography measurement data of 8*37 sampling points can be obtained. From the whole wafer surface, each sampling point can be regarded as a pixel point.

[0073] Next, after filtering the surface topography measurement data of each sampling point by the filter of the foregoing technical solution, the filtered values of all sampling points after filtering are divided into analysis regions according to the size of 10 mm*10 mm, and for each analysis region, the PV value of the analysis region is determined according to the filtered value of each pixel point (sampling point). After arranging the PV values of all analysis regions in ascending order, the PV value in the Nth order is selected as the measurement nanotopography value of the wafer after line cutting according to a specific percentile, such as 99%, 99.5%, etc.

[0074] Then, the measurement nanotopography values of all 100 wafers after line cutting are calculated into the predicted nanotopography values of the 100 wafers by a fitting function, and in this embodiment, the fitting function is obtained by linear fitting of the data of historical wafers, as shown by the dashed straight line in FIG. 2. In this embodiment, the prediction function is NT=1.9785*nt+5.9023. Wherein, nt represents the measurement nanotopography value after line cutting, and NT represents the predicted nanotopography value.

[0075] Finally, taking the CMP as an example of the subsequent processing procedure, whether there is a correlation between the actual nanotopography value and the predicted nanotopography value of the 100 wafers after CMP is analyzed, and continuing to refer to FIG. 2, the predicted nanotopography value and the actual nanotopography value of the 100 wafers selected by the disclosure are shown as points in FIG. 2, taking the predicted nanotopography value after line cutting and the actual nanotopography value after CMP as coordinates. In order to verify whether the predicted nanotopography value (predicted NT value) and the actual nanotopography value (actual NT value) have a correlation, the residual between the fitting curve and the actual data or the R 2 value of the fitting curve is calculated according to the predicted NT value and the actually measured NT value. For the 100 wafers selected in this embodiment, the correlation between the predicted NT value and the actual NT value is shown in Table 2.

[0076] Table 2

[0077] It can be seen from Table 2 that the predicted NT value and the actual NT value have a correlation.

[0078] Based on the prediction method of wafer surface nanotopography provided by the foregoing technical solution, when the predicted nanotopography value of the wafer is less than 5 nm in the specification of 2 mm*2 mm and / or less than 10 nm in the specification of 10 mm*10 mm, the nanotopography value of the wafer is less than 5 nm in the specification of 2 mm*2 mm and less than 10 nm in the specification of 10 mm*10 mm.

[0079] It should be noted that the processing procedure for obtaining the predicted nanotopography value is prior to obtaining the nanotopography value of the wafer. For example, the predicted nanotopography value can be obtained after the on-line cutting procedure, and the nanotopography value in the wafer can be obtained after the CMP procedure. Alternatively, the predicted nanotopography value can be obtained after the CMP procedure, and the nanotopography value in the wafer can be obtained when the wafer flows into the back-end semiconductor manufacturing process, which is not described in detail in the present disclosure.

[0080] Based on the same inventive concept of the foregoing technical solutions, referring to FIG. 3, a wafer surface nanotopography prediction device 30 provided by the present disclosure is shown, which comprises a filtering part 301 and a prediction part 302; wherein,

[0081] The filtering part 301 is configured to filter and process the obtained surface topography measurement data of the wafer by using a step design filter during the processing of the wafer, to obtain the measurement nanotopography value nt of the wafer;

[0082] The prediction part 302 is configured to predict the predicted nanotopography value NT of the wafer after the subsequent processing procedure according to the measurement nanotopography value nt of the wafer based on the prediction function f(nt) = NT.

[0083] In some examples, the step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface topography measurement data of the wafer. Accordingly, the filtering part 301 is configured to:

[0084] Based on the target wavelength range, a double Gaussian low-pass filter function is used to determine the filter;

[0085] The upper limit of the wavelength of the target wavelength range is used to determine the critical size of the filter;

[0086] The edge shrinkage processing is performed according to the sampling point position;

[0087] When the distance between the sampling point position and the wafer surface center is less than or equal to the critical size, the radius of the step design filter is determined as a first radius; or

[0088] When the distance between the sampling point position and the wafer surface center is greater than the critical size, the radius of the step design filter is determined as a second radius; wherein the first radius is greater than the second radius.

[0089] In some examples, the filtering part 301 is configured to:

[0090] The first Gaussian low-pass filter function is determined, wherein the low-pass filter range covers the upper limit of the target wavelength range;

[0091] determining a low-pass filter range covering the second Gaussian low-pass filter function according to a lower limit of the target wavelength range;

[0092] according to the first Gaussian low-pass filter function G LP1 and the second Gaussian low-pass filter function G LP2 a function G DHP for describing the filter is obtained according to the following formula: DHP G LP1 (1-G LP2 ).

[0093] In some examples, the filtering part 301 is configured to:

[0094] After filtering the wafer surface topography measurement data by using the step design filter, a filtered value of each sampling point position is obtained;

[0095] Divide all sampling points into at least one to-be-analyzed region according to a set size;

[0096] Obtain the peak-valley PV value of each to-be-analyzed region by taking the maximum filtered value and the minimum filtered value in each to-be-analyzed region;

[0097] After arranging the PV values of all to-be-analyzed regions in ascending order, select a PV value according to a set percentile as the measurement nanotopography value of the wafer.

[0098] Referring to FIG. 4, the device 30 further comprises: the fitting part 303, which is configured to: perform mathematical modeling and fitting according to the measurement nanotopography value of a historical wafer after completing a current processing procedure and the measurement nanotopography value of the historical wafer after completing a subsequent processing procedure, and obtain the prediction function by linear fitting or polynomial fitting.

[0099] In some examples, the filtering part 301 is further configured to obtain the measurement nanotopography value of the historical wafer by filtering the surface topography measurement data of the historical wafer by using the step design filter and data processing.

[0100] In some examples, referring to FIG. 4, the device 30 further comprises: the feedback part 304, which is configured to:

[0101] determine the working state of a device performing a current completed front-end processing procedure according to the statistical quantity of the predicted nanotopography value of the wafer; or

[0102] determine whether the wafer continues to perform a subsequent processing procedure according to a comparison result of the predicted nanotopography value of the wafer and a set evaluation index; or

[0103] adjusting the process parameters of the current finished processing procedure according to the predicted nanotopography value of the wafer.

[0104] It should be noted that for the above device, the specific implementation of the functions configured by each "part" can refer to the implementation manner and examples of the corresponding steps in the aforementioned wafer surface nanotopography prediction method, which will not be described here.

[0105] Please refer to FIG. 5, which shows the structural block diagram of a computing device provided by an exemplary embodiment of the present disclosure. In some examples, the computing device 50 can be at least one of a smart phone, a smart watch, a desktop computer, a laptop computer, a virtual reality terminal, an augmented reality terminal, a wireless terminal, and a laptop computer. The computing device 50 has a communication function and can access a wired network or a wireless network. The computing device 50 can generally refer to one of a plurality of terminals, and those skilled in the art can know that the number of terminals can be more or less. In some examples, the computing device 50 can receive data based on the accessed wired network or wireless network. It can be understood that the computing device 50 undertakes the calculation and processing work of the technical solutions of the present disclosure, which are not limited by the present disclosure.

[0106] As shown in FIG. 5, the computing device in the present disclosure can include one or more of the following components: a processor 510 and a memory 520.

[0107] Optionally, the processor 510 utilizes various interfaces and lines to connect various parts within the entire computing device, performs various functions of the computing device and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 520, and calling data stored in the memory 520. Optionally, the processor 510 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA). The processor 510 can be integrated with a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), a neural-network processing unit (NPU), and a baseband chip. Among them, the CPU is mainly used to process operating systems, user interfaces, and application programs; the GPU is used to render and draw the content to be displayed on the touch display screen; the NPU is used to implement artificial intelligence (AI) functions; and the baseband chip is used to process wireless communication. It can be understood that the above baseband chip can also not be integrated into the processor 510, but be implemented by a separate chip.

[0108] The memory 520 can include a random access memory (RAM) and can also include a read-only memory (ROM). Optionally, the memory 520 includes a non-transitory computer-readable storage medium. The memory 520 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 520 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above various method embodiments, etc.; and the data storage area can store data created according to the use of the computing device, etc.

[0109] In addition, those skilled in the art can understand that the structure of the computing device shown in the above-mentioned drawings does not constitute a limitation on the computing device, and the computing device can include more or fewer components than the diagram, or combine certain components, or different component arrangements. For example, the computing device also includes a display screen, a camera assembly, a microphone, a speaker, a radio frequency circuit, an input unit, a sensor (such as an acceleration sensor, an angular velocity sensor, a light sensor, etc.), an audio circuit, a WiFi module, a power supply, a Bluetooth module, and the like, which will not be described here.

[0110] The present disclosure also provides a computer-readable storage medium storing at least one instruction for being executed by a processor to implement the wafer surface nanotopography prediction method according to any of the above embodiments.

[0111] The present disclosure also provides a computer program product including computer instructions stored in a computer-readable storage medium; a processor of a computing device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to cause the computing device to perform the wafer surface nanotopography prediction method according to any of the above embodiments.

[0112] The present disclosure also provides a wafer, wherein the wafer has a final nanotopography value of less than 5 nm within a 2mm*2mm size and less than 10 nm within a 10mm*10mm size, when the wafer surface nanotopography prediction method according to any of the above embodiments is used to obtain a predicted nanotopography value of less than 5 nm within a 2mm*2mm size and less than 10 nm within a 10mm*10mm size.

[0113] Those skilled in the art should be aware that, in the above one or more examples, the functions described in the embodiments of the present disclosure can be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, the functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. The computer-readable medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transfer of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0114] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0115] The above merely provides the specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for predicting a wafer surface nanotopography, the method comprising: filtering and data processing, using a step design filter, surface profile measurement data of a wafer obtained during a wafer processing procedure, to obtain a measured nanotopography value nt of the wafer; and predicting, based on a prediction function f (nt) = NT, a predicted nanotopography value NT of the wafer after a subsequent processing procedure according to the measured nanotopography value nt of the wafer. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius.

2. The method of claim 1, wherein, The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius.

3. The method of claim 2, wherein, The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is less than or equal to the critical size; or determining a second radius of the step design filter when the distance between the sampling point position and the wafer surface center is greater than the critical size, wherein the first radius is greater than the second radius. According to the first Gaussian low-pass filter function G LP1 With the second Gaussian low-pass filter function G LP2 The function G for describing the filter is obtained according to DHP : G DHP = G LP1 (1 - G LP2 ).

4. The method of claim 2, wherein, The step design filter size is designed according to a target wavelength range, a sampling pitch, and a sampling point position of the surface profile measurement data of the wafer, and accordingly, the method comprises: determining, based on the target wavelength range, a filter using a double Gaussian low-pass filter function; determining a critical size of the filter according to an upper limit of the target wavelength range; performing edge shrinkage processing according to the sampling point position; determining a first radius of the step design filter when a distance between the sampling point position and a wafer surface center is ​ ​ ​ ​ 5. The method of claim 1, wherein, ​ ​ 6. The method of claim 5, wherein, ​ ​ 7. An apparatus for predicting a nanotopography of a wafer surface, the apparatus comprising: ​ ​ The prediction unit is configured to predict a predicted nanotopography value NT of the wafer after a subsequent processing step based on a prediction function f(nt)=NT from a measured nanotopography value nt of the wafer.

8. A computing device comprising: a processor and a memory; The processor is configured to execute instructions stored in the memory to implement the method of predicting nanotopography of a wafer surface according to any one of claims 1 to 6. 9.A computer readable storage medium storing at least one instruction for execution by a processor to implement the method of predicting nanotopography of a wafer surface according to any one of claims 1 to 6. 10.A wafer, wherein a nanotopography value of the wafer is less than 5nm in a 2mm*2mm specification and / or less than 10nm in a 10mm*10mm specification, and a predicted nanotopography value NT of the wafer is less than 5nm in a 2mm*2mm specification and / or less than 10nm in a 10mm*10mm specification.

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