Memory expansion system, memory access method, device, medium and computer program product

Abstract

The present application relates to the technical field of computers, and discloses a memory expansion system, a memory access method, a device, a medium, and a computer-readable instruction product. The memory expansion system comprises N graphics processing units and N field programmable gate array modules. Memory expansion modules are mounted on the field programmable gate array modules. The N graphics processing units are connected in a ring shape. The N field programmable gate array modules are connected in a ring shape. Each graphics processing unit is connected to k field programmable gate array modules. The field programmable gate array modules are used for receiving memory access requests, wherein the memory access requests include memory access requests sent by processors and / or graphics processing units connected to the field programmable gate array modules, and / or other field programmable gate array modules. The memory expansion modules are used for responding to the memory access requests. The present application realizes memory expansion of graphics processing units, and improves the processing performance of the graphics processing units.

Description

Memory expansion system, access method and device, medium and computer program product

[0001] Cross-reference to related applications

[0002] The present application claims priority from the Chinese patent application No. 202410889277.8 filed on July 04, 2024, and entitled "Memory expansion system, access method and device, medium and computer program product", the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application relates to the technical field of computers, more specifically, to a memory expansion system, access method and device, medium and computer program product. BACKGROUND

[0004] With the development of AI (Artificial Intelligence) and its large model related technologies, more and more GPU (Graphics Processing Unit) servers and data are needed to train iterative large models. Early GPU functions and resources are very single, only used for graphics image processing, and are currently widely used in the field of AI artificial intelligence computing, which is an important data center computing chip.

[0005] The inventor realizes that the GPU is usually plugged as a PCIe (Peripheral Component Interconnect Express) device on the server slot, and the memory relied on by the GPU chip calculation is usually on-chip HBM (High Bandwidth Memory), and the memory cannot be effectively shared between GPU cards, which causes performance bottleneck.

[0006] Therefore, how to realize the memory expansion of the GPU and improve the processing performance of the GPU is a technical problem to be solved by those skilled in the art. SUMMARY

[0007] The present application provides a memory access method, device and equipment, storage medium and computer program product, which realizes the memory expansion of the GPU and improves the processing performance of the GPU.

[0008] Specifically, the application provides a memory expansion system, comprising N graphic processors and N field programmable gate array modules, a memory expansion module being mounted on the field programmable gate array module, the N graphic processors being connected in a ring shape, the N field programmable gate array modules being connected in a ring shape, each graphic processor being connected with k field programmable gate array modules, the nth graphic processor being connected with the mth field programmable gate array module, 2≤k≤N, 1≤n≤N, when n≥k, the value range of m is [n-k+1, n], when n<k, the value range of m is [1, n]∪[N+n-k+1, N];

[0009] The field programmable gate array module is used for receiving a memory access request, analyzing the memory access request to obtain an analysis result, and sending the memory access request to the memory expansion module mounted on the field programmable gate array module according to the analysis result; wherein the memory access request comprises a memory access request sent by a processor and / or a graphic processor and / or other field programmable gate array module connected with the field programmable gate array module;

[0010] The memory expansion module is used for responding to the memory access request.

[0011] The memory expansion module comprises a first memory area and a second memory area, the nth graphic processor reads data from the first memory area in the memory expansion module mounted on the nth field programmable gate array module and the second memory area in the memory expansion module mounted on other field programmable gate array modules connected with the nth graphic processor, and stores the processed data to the second memory area in the memory expansion module mounted on the nth field programmable gate array module.

[0012] The field programmable gate array module mounts the memory expansion module through an open memory interface, and the field programmable gate array module sends the memory access request to the mounted memory expansion module through the open memory interface according to the analysis result.

[0013] And / or, the field programmable gate array module mounts a double data rate synchronous random access memory, the double data rate synchronous random access memory is mounted on the field programmable gate array module in the form of a dual in-line module, and the field programmable gate array module sends the memory access request to the double data rate synchronous random access memory according to the analysis result, so that the double data rate synchronous random access memory responds to the memory access request.

[0014] The memory expansion system is deployed in the target node, and the field programmable gate array module is specifically configured to: receive a first memory access request sent by a processor in the target node, parse the first memory access request to determine a requested destination memory page table, determine whether an attribute of the destination memory page table meets a preset condition, if yes, lock the destination memory page table, and send the first memory access request to a memory expansion module mounted by the field programmable gate array module; and unlock the destination memory page table after the memory expansion module responds to the first memory access request.

[0015] The field programmable gate array module includes a compute express link interface or a peripheral component interconnect express bus interface, a compute express link and a direct memory access controller, and a page table enabling module.

[0016] The compute express link interface or the peripheral component interconnect express bus interface is configured to receive a first memory access request sent by a processor in the target node.

[0017] The compute express link and the direct memory access controller are configured to parse the first memory access request to determine a requested destination memory page table.

[0018] The page table enabling module is configured to determine whether an attribute of the destination memory page table meets a preset condition, and if yes, lock the destination memory page table.

[0019] The compute express link and the direct memory access controller are further configured to send the first memory access request to a memory expansion module mounted by the field programmable gate array module.

[0020] The page table enabling module is further configured to unlock the destination memory page table after the memory expansion module responds to the first memory access request.

[0021] The memory expansion system is deployed in the target node, and the field programmable gate array module is specifically configured to: receive a second memory access request sent by a graphics processor and / or other field programmable gate array modules in the target node, parse the second memory access request, convert an address of a destination memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request, parse the converted second memory access request to determine the requested destination memory page table, determine whether an attribute of the destination memory page table meets a preset condition, if yes, lock the destination memory page table, and send the converted second memory access request to a memory expansion module mounted by the field programmable gate array module; receive response data of the memory expansion module in response to the converted second memory access request, construct a response data packet conforming to a format corresponding to the destination memory page table based on the response data, return the response data packet to a sender of the second memory access request, and unlock the destination memory page table.

[0022] The graphics processor comprises a high-speed channelized chip-to-chip interface, the field programmable gate array module comprises the high-speed channelized chip-to-chip interface, an inter-card memory access request analysis module, a page table conversion module, a compute express link and direct memory access controller, a page table enabling module and an inter-card memory access response packet assembling module; the high-speed channelized chip-to-chip interfaces are connected between different graphics processors, between different field programmable gate array modules and between the field programmable gate array module and the graphics processor;

[0023] The high-speed channelized chip-to-chip interface in the field programmable gate array module is configured to receive a second memory access request sent by a graphics processor and / or other field programmable gate array module in a target node;

[0024] The inter-card memory access request analysis module is configured to analyze the second memory access request;

[0025] The page table conversion module is configured to convert an address of a target memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request;

[0026] The compute express link and direct memory access controller is configured to analyze the converted second memory access request to determine the target memory page table requested;

[0027] The page table enabling module is configured to determine whether an attribute of the target memory page table meets a preset condition, and if so, lock the target memory page table;

[0028] The compute express link and direct memory access controller is further configured to send the converted second memory access request to a memory expansion module mounted by the field programmable gate array module;

[0029] The inter-card memory access response packet assembling module is configured to receive response data of the memory expansion module in response to the converted second memory access request, and construct a response data packet in a format corresponding to the target memory page table based on the response data;

[0030] The high-speed channelized chip-to-chip interface in the field programmable gate array module is further configured to return the response data packet to a sender of the second memory access request;

[0031] The page table enabling module is further configured to unlock the target memory page table.

[0032] The memory expansion system is deployed in the target node, and the field programmable gate array module is specifically configured to: receive a third memory access request sent by a device in another node, parse the third memory access request to determine a requested destination memory page table, determine whether an attribute of the destination memory page table meets a preset condition, and if so, lock the destination memory page table and send the memory access request to a memory expansion module mounted by the field programmable gate array module; and unlock the destination memory page table after the memory expansion module responds to the third memory access request; wherein the device in the other node includes a processor and / or a field programmable gate array module and / or a graphics processor in the other node.

[0033] The field programmable gate array module includes a network optical module, an Ethernet-based remote direct memory access protocol stack, a compute express link and a direct memory access controller, and a page table enabling module.

[0034] The network optical module is configured to receive a third memory access request sent by a device in another node.

[0035] The Ethernet-based remote direct memory access protocol stack, the compute express link and the direct memory access controller are configured to parse the third memory access request to determine a requested destination memory page table.

[0036] The page table enabling module is configured to determine whether an attribute of the destination memory page table meets a preset condition, and if so, lock the destination memory page table.

[0037] The compute express link and the direct memory access controller are further configured to send the third memory access request to a memory expansion module mounted by the field programmable gate array module.

[0038] The page table enabling module is further configured to unlock the destination memory page table after the memory expansion module responds to the third memory access request.

[0039] The graphics processor includes a high-bandwidth memory.

[0040] The memory expansion system is applied to model training, and training data is divided into N training sub-data stored in first memory areas of N memory expansion modules mounted by field programmable gate array modules.

[0041] The nth graphics processor reads target training data from a first memory area of a memory expansion module mounted by the nth field programmable gate array module and a second memory area of a memory expansion module mounted by another field programmable gate array module connected to the nth graphics processor, performs model training based on the target training data, and stores processed data to the second memory area of the memory expansion module mounted by the nth field programmable gate array module.

[0042] The N training sub-data are respectively stored into first memory areas in N memory expansion modules mounted by field programmable gate array modules through peripheral component interconnect express bus interfaces or network optical modules.

[0043] The data transmission is performed between the field programmable gate array module and the graphic processor through a DMA controller.

[0044] The N graphic processors share high-bandwidth memories in the graphic processors through ring connection.

[0045] The application further provides a memory access method applied to the field programmable gate array module in the memory expansion system.

[0046] The memory access request is received, wherein the memory access request comprises a memory access request sent by a processor and / or a graphic processor and / or another field programmable gate array module connected with the field programmable gate array module.

[0047] The memory access request is parsed to obtain a parsing result, and the memory access request is sent to the memory expansion module mounted by the field programmable gate array module according to the parsing result, so that the memory expansion module responds to the memory access request.

[0048] The memory expansion system is deployed in a target node, and the memory access request is received, comprising:

[0049] The first memory access request sent by the processor in the target node is received.

[0050] Correspondingly, the memory access request is parsed to obtain a parsing result, and the memory access request is sent to the memory expansion module mounted by the field programmable gate array module according to the parsing result, comprising:

[0051] The first memory access request is parsed to determine a requested destination memory page table, it is judged whether the attribute of the destination memory page table satisfies a preset condition, if yes, the destination memory page table is locked, and the first memory access request is sent to the memory expansion module mounted by the field programmable gate array module;

[0052] Correspondingly, after the memory expansion module responds to the first memory access request, further comprising:

[0053] The destination memory page table is unlocked.

[0054] The memory expansion system is deployed in a target node, and the memory access request is received, comprising:

[0055] The second memory access request sent by the graphic processor and / or another field programmable gate array module in the target node is received.

[0056] Correspondingly, the memory access request is parsed to obtain a parsing result, and the memory access request is sent to a memory expansion module mounted by the field programmable gate array module according to the parsing result, including:

[0057] The second memory access request is parsed, and an address of a target memory page table requested in the second memory access request is converted into a memory physical address to obtain a converted second memory access request;

[0058] The converted second memory access request is parsed to determine the target memory page table, and it is determined whether an attribute of the target memory page table meets a preset condition, if yes, the target memory page table is locked, and the converted second memory access request is sent to the memory expansion module mounted by the field programmable gate array module;

[0059] Correspondingly, after the memory expansion module responds to the second memory access request, the method further includes:

[0060] Response data of the memory expansion module responding to the converted second memory access request is received, response data packets conforming to a format corresponding to the target memory page table are constructed based on the response data, the response data packets are returned to a sender of the second memory access request, and the target memory page table is unlocked.

[0061] The memory expansion system is deployed in the target node, and the memory access request is received, including:

[0062] The third memory access request sent by a device in another node is received, and the device in the another node includes a processor and / or a field programmable gate array module and / or a graphics processing unit in the another node;

[0063] Correspondingly, the memory access request is parsed to obtain a parsing result, and the memory access request is sent to a memory expansion module mounted by the field programmable gate array module according to the parsing result, including:

[0064] The third memory access request is parsed to determine the target memory page table, and it is determined whether an attribute of the target memory page table meets a preset condition, if yes, the target memory page table is locked, and the third memory access request is sent to the memory expansion module mounted by the field programmable gate array module;

[0065] Correspondingly, after the memory expansion module responds to the third memory access request, the method further includes:

[0066] The target memory page table is unlocked.

[0067] The application further provides an electronic device, including:

[0068] A memory is configured to store computer readable instructions;

[0069] A processor for implementing the steps of the memory access method as described above when executing computer readable instructions.

[0070] To achieve the above object, the present application provides a non-volatile storage medium, which stores computer readable instructions, and the computer readable instructions implement the steps of the memory access method as described above when executed by a processor.

[0071] To achieve the above object, the present application provides a computer readable instruction product, which includes computer readable instructions, and the computer readable instructions implement the steps of the memory access method as described above when executed by a processor.

[0072] It can be known from the above scheme that the memory expansion system provided by the present application includes N graphic processors and N field programmable gate array modules, the memory expansion module is mounted on the field programmable gate array module, the N graphic processors are connected in a ring shape, the N field programmable gate array modules are connected in a ring shape, each graphic processor is connected with k field programmable gate array modules, the nth graphic processor is connected with the mth field programmable gate array module, 2≤k≤N, 1≤n≤N, when n≥k, the value range of m is [n-k+1, n], when n<k, the value range of m is [1, n]∪[N+n-k+1, N]; the field programmable gate array module is used for receiving a memory access request, analyzing the memory access request to obtain an analysis result, and sending the memory access request to the memory expansion module mounted on the field programmable gate array module according to the analysis result; wherein the memory access request includes a memory access request sent by a processor and / or a graphic processor and / or other field programmable gate array module connected with the field programmable gate array module; the memory expansion module is used for responding to the memory access request; the memory expansion module includes a first memory area and a second memory area, the nth graphic processor reads data from the first memory area in the memory expansion module mounted on the nth field programmable gate array module and the second memory area in the memory expansion module mounted on the other field programmable gate array module connected with the nth graphic processor, and stores the processed data to the second memory area in the memory expansion module mounted on the nth field programmable gate array module.

[0073] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0074] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description only are some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without creative work based on these drawings also belong to the protection scope of the present application. In addition, in some embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence.

[0075] Fig. 1 is a structural diagram of a memory access system according to some embodiments;

[0076] Fig. 2 is a structural diagram of an FPGA module according to some embodiments;

[0077] Fig. 3 is a data flow diagram of various functional modules in an FPGA module according to some embodiments;

[0078] Fig. 4 is a flowchart of a first memory access method according to some embodiments;

[0079] Fig. 5 is a flowchart of a second memory access method according to some embodiments;

[0080] Fig. 6 is a flowchart of a third memory access method according to some embodiments;

[0081] Fig. 7 is a flowchart of a fourth memory access method according to some embodiments;

[0082] Fig. 8 is a structural diagram of an electronic device according to some embodiments. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present application. In addition, in some embodiments of the present application, "first", "second", etc. are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence.

[0084] Some embodiments of the present application disclose a memory expansion system, comprising N graphic processors and N field programmable gate array modules, a memory expansion module being mounted on each field programmable gate array module, the N graphic processors being connected in a ring, the N field programmable gate array modules being connected in a ring, each graphic processor being connected with k field programmable gate array modules, the nth graphic processor being connected with the mth field programmable gate array module, 2≤k≤N, 1≤n≤N, when n≥k, the value range of m is [n-k+1, n], when n<k, the value range of m is [1, n]∪[N+n-k+1, N];

[0085] The field programmable gate array module is configured to receive a memory access request, analyze the memory access request to obtain an analysis result, and send the memory access request to the memory expansion module mounted on the field programmable gate array module according to the analysis result; wherein the memory access request comprises a memory access request sent by a processor and / or a graphic processor and / or another field programmable gate array module connected with the field programmable gate array module.

[0086] The memory expansion module is configured to respond to the memory access request.

[0087] The memory expansion system in some embodiments can be applied to a server, the server comprising a plurality of nodes, each node deploying a set of memory expansion systems. The memory expansion system comprises N GPUs and N FPGA modules, the GPU comprising a HBM (High Bandwidth Memory), and each FPGA module mounting a memory expansion module.

[0088] The memory expansion system provided by the present application has the advantages that: the memory expansion system provided by the present application forms a multi-path ring network communication topology between GPUs and FPGA (Field Programmable Gate Array) modules, the GPU can directly access the memory expansion module mounted on the FPGA module connected with the GPU, in addition, the processor and other FPGA modules can also access the memory expansion module mounted on the current FPGA module, thereby effectively expanding the GPU computing memory, reducing the communication bottleneck, increasing the GPU computing resource utilization, and improving the processing performance of the GPU. Further, each GPU realizes processing of data stored in the memory expansion module in the link ring composed of the circulating processing FPGA modules, can fully utilize the interconnection between the GPU and the FPGA to process data, expand the local memory of a single GPU, improve the data amount processed by a single GPU, and further improve the processing performance of multiple GPUs. The present application also discloses a memory access device, an electronic equipment, a nonvolatile storage medium and a computer program product, which can also achieve the above technical effects.

[0089] In some embodiments, the FPGA module mounts the memory expansion module through an open memory interface, and the FPGA module sends a memory access request to the mounted memory expansion module through the open memory interface according to the analysis result; and / or, the FPGA module mounts a DDR SDRAM, the DDR SDRAM is mounted on the FPGA module in the form of a DIMM, and the FPGA module sends a memory access request to the DDR SDRAM according to the analysis result, so that the DDR SDRAM responds to the memory access request.

[0090] In some embodiments, the memory expansion module can include a memory expansion module connected with the FPGA module through an OMI, a DDR SDRAM, etc. The DDR is a memory particle that can transmit data twice per clock cycle, i.e., the rising edge and the falling edge are sampled respectively, and is usually in the form of a DIMM, i.e., a plurality of memory particles are concentrated on a circuit board, and an address, data and control bus is applied in a server host or various acceleration cards. The OMI is an open-source memory bus interface using a high-speed serial transmission link, and only the physical layer specification is defined, and the link protocol layer is not within the scope. Usually, a high-speed serial-parallel conversion controller and a buffer are integrated on the circuit board where the memory particle is located. The OMI memory expansion module is connected with the FPGA module using the OMI interface, uses a high-speed differential link, has strong anti-interference performance, stable signal transmission, and high transmission signal frequency, data rate, and total bandwidth. The single channel of the expansion memory module can reach up to GHz, the data rate can reach 25.6 GB / s, or even higher, a plurality of memory controller channels are supported, the expansion memory has a high total bandwidth, the total memory is larger, the single OMI memory expansion module can reach 256 GB, and a plurality of OMI memory expansion modules are used to form a multi-channel expansion memory, and the total capacity can easily reach a TB level.

[0091] In some embodiments, the GPUs are interconnected with the left and right adjacent GPUs, that is, N GPU ring connection, the FPGA modules are interconnected with the left and right adjacent FPGA modules, that is, N FPGA module ring connection, each graphics processor is connected with k field programmable gate array modules, the nth graphics processor is connected with the mth field programmable gate array module, 2≤k≤N, 1≤n≤N, when n≥k, the value range of m is [n-k+1, n], when n<k, the value range of m is [1, n]∪[N+n-k+1, N]. Taking k=2 as an example, the GPU is interconnected with the front and rear adjacent two FPGA modules, that is, the first GPU is connected with the first FPGA module and the last FPGA module, the nth GPU is connected with the nth FPGA module and the n-1th FPGA module, and the connection topology diagram is shown in Figure 1.

[0092] The GPU and the FPGA module each support multiple high-speed interlaken interfaces, Compute Express Link (CXL) interfaces or Peripheral Component Interconnect Express (PCIE) interfaces, different GPUs, different FPGA modules and the FPGA module and the GPU are connected through interlaken. The GPU in a node can not only access the memory of the GPU connected therewith, but also access the memory expansion module mounted by the FPGA module connected therewith, and further access the memory expansion module mounted by the FPGA module in another node, that is, the memory accessible by a single GPU is increased, and the computing efficiency of the single GPU is improved. The FPGA module can offload the work load of DMA (Direct Memory Access) data migration of the GPU, and reduce the occupation of the GPU computing scheduling resources.

[0093] The structure diagram of the FPGA module is shown in Figure 2, which includes a field programmable gate array chip, a network optical module, a Compute Express Link interface or a Peripheral Component Interconnect Express interface, a multi-channel high-speed interlaken interface, an MCU (Microcontroller Unit), a memory expansion module connected through an open memory interface, a double-rate static random access memory and a power module. The MCU is used for detecting the voltage, temperature and other state of the entire field programmable gate array module, and sending an alarm information when any state index exceeds the standard.

[0094] The memory expansion module comprises a first memory region and a second memory region, the nth GPU reads data from the first memory region of the memory expansion module mounted by the nth FPGA module and the second memory region of the memory expansion module mounted by other FPGA module connected with the nth GPU, and stores the processed data to the second memory region of the memory expansion module mounted by the nth FPGA module.

[0095] Taking the second GPU as an example, k=2, the data flow is shown by the dashed line in FIG. 1, the second GPU reads the data processed by the first GPU in the second memory region of the memory expansion module mounted by the first FPGA module and the data in the first memory region of the memory expansion module mounted by the second FPGA module, processes the data in the two memory regions simultaneously, and writes the processed data to the second memory region of the memory expansion module mounted by the second FPGA module, and the same processing is repeated for the data stored in the link ring.

[0096] The data flow diagram of each functional module in the FPGA module is shown in FIG. 3, the compute express link interface or peripheral component interconnect express bus interface is used to send and receive TLP (Transaction Layer Packet) messages interacting with the CPU (Central Processing Unit) in the node, the compute express link and the direct memory access controller can be mounted with an extended multi-channel memory controller, the DMA controller can realize data transfer between the CPU and the FPGA module and between the FPGA modules, the Ethernet-based RDMA (Remote Direct Memory Access) protocol stack is responsible for processing DMA requests for accessing the extended memory from the network, the multi-channel Interlaken IP connects each Interlaken interface, which is used to receive and send Interlaken-based protocol data packets, the inter-card memory access request parsing module is responsible for parsing the read and write command requests for the extended memory, the inter-card memory access response packet assembling module is responsible for assembling and sending the response data returned by the read request, the page table conversion module is responsible for converting the page table ID and the corresponding 64-bit address bus of the extended memory in the system. The page table enabling module is responsible for monitoring and enabling the read and write state permissions of the page table block, the network optical module can be a 400G network optical module, and is responsible for receiving and sending data packets for remotely accessing the local extended memory.

[0097] After the system is powered on, the FPGA module automatically runs the extended memory self-checking program, uploads the self-checking result through the MCU, the host CPU allocates address space for the extended memory, registers the extended memory as an independent NUMA (Non-Uniform Memory Access) node, and initializes the page table ID attribute table.

[0098] The page table conversion module and the page table enable module divide the page table in a preset unit (for example, 4 KB) according to the allocated physical address of the corresponding extended memory when the system is powered on and initialized, and each block of the page table has a read, write, enable, lock and other states and operations. These information can be stored in an 8-bit dual-port RAM with the page table ID as the address, that is, the page table ID attribute table, which is defined in detail as shown in Table 1.

[0099] Table 1

[0100] The communication frame type between the FPGAs, the GPU and the FPGA through the Interlaken interface can include the source ID and the destination ID of the board, the request / response frame type, the request page table ID, the packet sequence number and the payload data, and the like. Taking the request frame as an example, the specific format is shown in Table 2.

[0101] Table 2

[0102] In some embodiments, the memory expansion system is deployed in a target node, and the field programmable gate array module is specifically configured to: receive a first memory access request sent by a processor in the target node, parse the first memory access request to determine a requested destination memory page table, lock the destination memory page table when an attribute of the destination memory page table meets a preset condition, and send the first memory access request to a memory expansion module mounted by the field programmable gate array module; and unlock the destination memory page table after the memory expansion module responds to the first memory access request.

[0103] In some embodiments, the processor in the target node sends the first memory access request to the FPGA module through a CXL interface or a PCIE interface, determines an attribute of a requested destination memory page table after being parsed by a computing express link and a direct memory access controller, locks a page table update state when the destination memory page table is enabled and the attribute meets a non-locking state, sends a read / write memory operation command to the memory expansion module, returns response data to the processor in the original path, and unlocks the page table update state.

[0104] Referring to FIG. 3, the field programmable gate array module includes a compute express link interface or peripheral component interconnect express bus interface, a compute express link and direct memory access controller, and a page table enabling module. The compute express link interface or peripheral component interconnect express bus interface is configured to receive a first memory access request sent by a processor in a target node. The compute express link and direct memory access controller is configured to parse the first memory access request to determine a requested destination memory page table. The page table enabling module is configured to lock the destination memory page table when a property of the destination memory page table satisfies a preset condition. The compute express link and direct memory access controller is further configured to send the first memory access request to a memory expansion module mounted on the field programmable gate array module. The page table enabling module is further configured to unlock the destination memory page table after the memory expansion module responds to the first memory access request. The data flow of the processor in the node accessing the FPGA module is 1, 10, 11, 10, 2, 1, 10, 11 in FIG. 3 in sequence.

[0105] In some embodiments, the memory expansion system is deployed in a target node, and the field programmable gate array module is specifically configured to: receive a second memory access request sent by a graphics processing unit and / or another field programmable gate array module in the target node, parse the second memory access request, convert an address of a destination memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request, parse the converted second memory access request to determine the destination memory page table, lock the destination memory page table when a property of the destination memory page table satisfies a preset condition, and send the converted second memory access request to a memory expansion module mounted on the field programmable gate array module; receive response data of the memory expansion module in response to the converted second memory access request, construct a response data packet conforming to a format corresponding to the destination memory page table based on the response data, return the response data packet to a sender of the second memory access request, and unlock the destination memory page table.

[0106] In some embodiments, when a GPU or another FPGA module connected through an Interlaken interface accesses a memory expansion module mounted on the current FPGA module, the multi-channel Interlaken interface first receives the second memory access request, parses the specific command through an inter-card memory access request parsing module, converts the physical address of the corresponding destination memory page table according to a page table conversion module, sends the converted second memory access request to the compute express link and direct memory access controller for parsing, locks the update page table state when the destination memory page table is enabled and the property satisfies the non-locking state, initiates the access to the memory expansion module, returns the read response data to the inter-card memory access response packet module after the DMA controller reads, converts the response data packet conforming to the format corresponding to the destination memory page table, sends the response data packet to the Interlaken interface to return to the sender, and unlocks the page table update state.

[0107] Referring to FIG. 3, the high-speed channelized chip-to-chip interface in the FPGA module is configured to receive a second memory access request sent by a GPU and / or other FPGA module in a target node; the inter-card memory access request parsing module is configured to parse the second memory access request; the page table conversion module is configured to convert an address of a target memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request; the compute express link and direct memory access controller is configured to parse the converted second memory access request to determine the target memory page table requested; the page table enabling module is configured to lock the target memory page table when an attribute of the target memory page table meets a preset condition; the compute express link and direct memory access controller is further configured to send the converted second memory access request to a memory expansion module mounted on the FPGA module; the inter-card memory access response packet building module is configured to receive response data of the memory expansion module in response to the converted second memory access request, and build a response data packet in a format corresponding to the target memory page table based on the response data; the high-speed channelized chip-to-chip interface in the FPGA module is further configured to return the response data packet to a sender of the second memory access request; and the page table enabling module is further configured to unlock the target memory page table. The data flow of the GPU or other FPGA module in the node accessing the current FPGA module is sequentially 3, 4, 5, 10, 11, 10, 2, 6, 7, 8, 10, 11 in FIG. 3.

[0108] In some embodiments, the memory expansion system is deployed in a target node, and the FPGA module is specifically configured to: receive a third memory access request sent by a device in another node, parse the third memory access request to determine a target memory page table requested, lock the target memory page table when an attribute of the target memory page table meets a preset condition, and send the memory access request to a memory expansion module mounted on the FPGA module; and unlock the target memory page table after the memory expansion module responds to the third memory access request; wherein the device in the other node includes a processor and / or an FPGA module and / or a GPU in the other node.

[0109] In some embodiments, a device outside the node sends a third memory access request to the FPGA module in the target node through a network optical module, determines an attribute of a target memory page table after the third memory access request is parsed by an Ethernet-based remote direct memory access protocol stack and a compute express link and direct memory access controller, locks a page table update state when the target memory page table is enabled and the attribute meets a non-locked state, sends a read / write memory operation command to the memory expansion module, returns response data to the device outside the node along the original route, and unlocks the page table update state.

[0110] Referring to FIG. 3, the field programmable gate array module includes a network optical module, an Ethernet-based remote direct memory access protocol stack, a compute express link and a direct memory access controller, and a page table enabling module. The network optical module is configured to receive a third memory access request sent by a device in another node. The Ethernet-based remote direct memory access protocol stack, the compute express link and the direct memory access controller are configured to parse the third memory access request to determine a requested destination memory page table. The page table enabling module is configured to lock the destination memory page table when an attribute of the destination memory page table meets a preset condition. The compute express link and the direct memory access controller are further configured to send the third memory access request to a memory expansion module mounted on the field programmable gate array module. The page table enabling module is further configured to unlock the destination memory page table after the memory expansion module responds to the third memory access request. The data flow of the device outside the node (including a processor outside the node, a GPU outside the node, and an FPGA module outside the node) accessing the current FPGA module is 9, 4, 10, 11, 10, 2, 4, 9, 10, and 11 in FIG. 3.

[0111] The FPGA module in some embodiments can access a RoCEv2 (RDMA over Converged Ethernet version 2) network or a standard Ethernet through the network optical module to communicate with other computing nodes or storage nodes. The GPU can communicate with resources outside the node through the directly connected FPGA without the need for a traditional scheme to connect the RDMA network card through the PCIe switch, thereby improving the data transmission efficiency between nodes.

[0112] The memory expansion system provided by some embodiments of the present application forms a multi-path ring network communication topology between the GPU and the FPGA module. The GPU can directly access the memory expansion module mounted on the FPGA module connected thereto. In addition, the processor and other FPGA modules can also access the memory expansion module mounted on the current FPGA module, thereby effectively expanding the GPU computing memory, reducing the communication bottleneck, increasing the utilization rate of GPU computing resources, and improving the processing performance of the GPU. Further, each GPU realizes processing of data stored in the memory expansion module in the link ring composed of the loop processing FPGA module, can fully utilize the interconnection between the GPU and the FPGA to process data, expand the local memory of a single GPU, increase the amount of data processed by a single GPU, and further improve the processing performance of multiple GPUs.

[0113] The memory expansion system provided by the above embodiments can be applied to model training. Training data is divided into N training sub-data, which are respectively stored in first memory areas of N memory expansion modules mounted on field programmable gate array modules.

[0114] In some embodiments, the N training sub-data are respectively stored into the first memory area in the memory expansion module mounted by the N FPGA modules through the peripheral component interconnect express bus interface or the network optical module.

[0115] In some embodiments, the N GPUs share the high-bandwidth memory in the GPUs through a ring connection. In some embodiments, when the GPU local memory is sufficient, multiple GPUs access the local memory, and the inter-GPU interconnection ring channel can still be used for data transmission, and the internal control logic and the DMA controller are responsible for memory read and write and data migration in each node. That is, the Ring Allreduce algorithm can be used for communication between multiple GPUs, and only the limited HBM memory between adjacent GPU cards is directly shared by the GPUs.

[0116] In some embodiments, the data transmission between the FPGA module and the GPU is performed through the DMA controller. In some embodiments, when the GPU local memory is insufficient, the GPU accesses the memory expansion module mounted by the FPGA module connected thereto, and the FPGA module can receive the data migration descriptor information (including source address, destination address, and length information) from the GPU, and actively perform memory data transmission between the FPGA module and the GPU by using the DMA controller, so as to release the GPU computing and control resources, and enable the GPU to more concentrate on data computation processing.

[0117] The FPGA modules can also receive the commands sent by the host CPU in the node or the host CPU outside the node through the PCIe, and initiate the transmission of the extended memory data between the FPGA modules according to the source address, destination address, and length information in the descriptor command according to the control logic in FIG. 3, and the transmission path is shown in (9, 4), 10, 7, and 8 in FIG. 3.

[0118] The nth GPU reads target training data from the first memory area in the memory expansion module mounted by the nth FPGA module and the second memory area in the memory expansion module mounted by the other FPGA module connected to the nth GPU, performs model training based on the target training data, and stores the processed data into the second memory area in the memory expansion module mounted by the nth FPGA module.

[0119] In some embodiments, taking k = 2, GPU2 as an example, the data in the second memory area in the memory expansion module mounted by the FPGA1 module processed by GPU1 and the data in the first memory area in the memory expansion module mounted by the FPGA2 module are read at the same time, and after the data in the two memory areas are processed at the same time, the data are written into the second memory area in the memory expansion module mounted by the FPGA2 module, and the like is sequentially deduced, and the data stored on the link ring are processed in a loop, so that the Interlaken channel flow processing data between cards can be fully utilized.

[0120] As can be seen, by expanding the local memory of the GPU through the memory expansion system, the amount of data processed by a single GPU can be increased, thereby reducing the number of GPUs required for the entire model training, thereby reducing the total communication time and the total amount of communication, and improving the model training efficiency.

[0121] In some embodiments, a memory access method is disclosed. Referring to FIG. 4, a flowchart of a first memory access method according to some embodiments is shown in FIG. 4, which includes the following steps:

[0122] S101: receiving a memory access request; wherein the memory access request includes a memory access request sent by a processor and / or a graphics processing unit and / or other field programmable gate array module connected to the field programmable gate array module;

[0123] S102: obtaining a parsing result by parsing the memory access request, and sending the memory access request to a memory expansion module mounted by the field programmable gate array module according to the parsing result, so that the memory expansion module responds to the memory access request.

[0124] In some embodiments, the execution subject is the field programmable gate array module in the memory expansion system. In some embodiments, the field programmable gate array module is located in a target node, and the processor, graphics processing unit, and other field programmable gate array module connected to the field programmable gate array module in the target node can access the memory expansion module mounted by the field programmable gate array module, and the processor, graphics processing unit, and field programmable gate array module in other nodes can also access the memory expansion module mounted by the field programmable gate array module.

[0125] As can be seen, in some embodiments, the GPU can directly access the memory expansion module mounted by the FPGA module connected thereto, and in addition, the processor and other FPGA modules can also access the memory expansion module mounted by the current FPGA module, thereby effectively expanding the GPU computing memory, reducing the communication bottleneck, increasing the GPU computing resource utilization, and improving the processing performance of the GPU.

[0126] In some embodiments, a memory access method is disclosed, referring to FIG. 5, a flowchart of a second memory access method according to some embodiments, as shown in FIG. 5, comprising:

[0127] S201: receiving a first memory access request sent by a processor in a target node;

[0128] S202: parsing the first memory access request to determine a requested destination memory page table, when the attributes of the destination memory page table meet preset conditions, locking the destination memory page table, and sending the first memory access request to a memory expansion module mounted by the field programmable gate array module, so that the memory expansion module responds to the first memory access request;

[0129] S203: after the memory expansion module responds to the first memory access request, unlocking the destination memory page table.

[0130] In some embodiments, the processor in the target node sends the first memory access request to the FPGA module through the CXL interface or the PCIE interface, and after being parsed by the compute express link and direct memory access controller, determines the attributes of the requested destination memory page table, when the destination memory page table is enabled and the attributes meet the non-locked state, locks the page table update state, sends the read / write memory operation command to the memory expansion module, returns the read response data to the processor via the original path, and unlocks the page table update state.

[0131] In some embodiments, a memory access method is disclosed, referring to FIG. 6, a flowchart of a third memory access method according to some embodiments, as shown in FIG. 6, comprising:

[0132] S301: receiving a second memory access request sent by a graphics processor and / or other field programmable gate array module in a target node;

[0133] S302: parsing the second memory access request, converting the address of the requested destination memory page table in the second memory access request into a memory physical address to obtain a converted second memory access request;

[0134] S303: parsing the converted second memory access request to determine the requested destination memory page table, when the attributes of the destination memory page table meet preset conditions, locking the destination memory page table, and sending the converted second memory access request to a memory expansion module mounted by the field programmable gate array module, so that the memory expansion module responds to the second memory access request;

[0135] S304: After the memory expansion module responds to the second memory access request, receiving response data of the memory expansion module responding to the converted second memory access request, constructing a response data packet in a format corresponding to the target memory page table based on the response data, returning the response data packet to the sender of the second memory access request, and unlocking the target memory page table.

[0136] In some embodiments, when a GPU or other FPGA module connected through an Interlaken interface accesses a memory expansion module mounted by the current FPGA module, the multi-channel Interlaken interface first receives a second memory access request, parses the specific command through the inter-card memory access request parsing module, converts the corresponding physical address of the target memory page table according to the page table conversion module, sends the converted second memory access request to the compute express link and direct memory access controller to determine the target memory page table enablement and state, when the target memory page table is enabled and the attribute meets the non-locking state, lock the update page table state, initiate access to the memory expansion module, the DMA controller reads and returns the read response data to the inter-card memory access response packet module, converts the response data packet in a format corresponding to the target memory page table, sends it to the Interlaken interface to return to the sender, and unlocks the page table update state.

[0137] In some embodiments, a memory access method is disclosed, as shown in FIG. 7, according to the flowchart of the fourth memory access method shown in some embodiments, as shown in FIG. 7, including:

[0138] S401: Receiving a third memory access request sent by a device in another node; wherein the device in the other node includes a processor and / or a field programmable gate array module and / or a graphics processor in the other node;

[0139] S402: Parsing the third memory access request to determine the requested target memory page table, locking the target memory page table when the attribute of the target memory page table meets the preset condition, and sending the third memory access request to the memory expansion module mounted by the field programmable gate array module, so that the memory expansion module responds to the third memory access request;

[0140] S403: After the memory expansion module responds to the third memory access request, unlocking the target memory page table.

[0141] In some embodiments, the device outside the node sends a third memory access request to the FPGA module in the target node through the network optical module, and after being parsed by an Ethernet-based remote direct memory access protocol stack, a compute express link and a direct memory access controller, attributes of a requested destination memory page table are determined. When the destination memory page table is enabled and the attributes meet the non-locking state, the page table update state is locked, a read / write memory operation command is sent to the memory expansion module, and the read response data is returned to the device outside the node that requests the device. The page table update state is unlocked.

[0142] Based on the hardware implementation of the above program module, and in order to implement the memory access method of the present application, some embodiments of the present application also provide an electronic device, including a memory and one or more processors, the memory stores computer readable instructions, and the computer readable instructions are executed by the one or more processors, so that the one or more processors execute the memory access method provided by one or more technical solutions.

[0143] In one or some embodiments, the computer device can be a server, and its internal structure diagram can be as shown in FIG. 8. The computer device includes a processor, a memory and a network interface connected by a system bus. Among them, the processor of the computer device is used to provide computing and control capability. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and computer readable instructions. The internal memory provides an environment for the operation of the operating system and computer readable instructions in the non-volatile storage medium. The network interface of the computer device is used to communicate with the external terminal through the network connection. The computer readable instructions are executed by the processor to implement a memory access method.

[0144] In one or more embodiments, the present application also provides a non-transitory computer readable storage medium, and the non-transitory computer readable storage medium stores computer readable instructions, and the computer readable instructions are executed to implement the memory access method provided by one or more technical solutions.

[0145] The computer readable storage medium can be the computer readable storage medium in the computer device shown in FIG. 8.

[0146] In some embodiments, some embodiments of the present application also provide a computer readable instruction product, including computer readable instructions, which are executed by a processor to complete the steps of the foregoing memory access method.

[0147] Those skilled in the art can understand that all or part of the steps of the foregoing method embodiments can be completed by relevant hardware instructed by computer readable instructions. The foregoing computer readable instructions can be stored in a nonvolatile storage medium, and when executed, perform steps including the foregoing method embodiments. Alternatively, when the foregoing integrated units are implemented in the form of software function modules and sold or used as independent products, they can also be stored in a nonvolatile storage medium. Based on this understanding, the technical solutions of some embodiments of the present application can be embodied in the form of software products, and the computer software products are stored in a nonvolatile storage medium, including a number of instructions to make an electronic device (which can be a personal computer, a server, a network device, etc.) execute all or part of the method embodiments of the present application.

[0148] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application.

Claims

1. A memory extension system, characterized by, The memory expansion system comprises N graphic processors and N field programmable gate array modules, the field programmable gate array modules are mounted with memory expansion modules, the N graphic processors are connected in a ring, the N field programmable gate array modules are connected in a ring, each graphic processor is connected with k field programmable gate array modules, the nth graphic processor is connected with the mth field programmable gate array module, 2≤k≤N, 1≤n≤N, when n≥k, the value range of m is [n-k+1, n], when n The field programmable gate array module is used for receiving a memory access request, analyzing the memory access request to obtain an analysis result, and sending the memory access request to the memory expansion module mounted on the field programmable gate array module according to the analysis result; wherein the memory access request comprises a memory access request sent by a processor and / or a graphic processor and / or other field programmable gate array modules connected with the field programmable gate array module; The memory expansion module is used for responding to the memory access request; and The memory expansion module comprises a first memory area and a second memory area, the nth graphic processor reads data from the first memory area in the memory expansion module mounted on the nth field programmable gate array module and the second memory area in the memory expansion module mounted on the other field programmable gate array module connected with the nth graphic processor, and stores the processed data to the second memory area in the memory expansion module mounted on the nth field programmable gate array module.

2. The memory extension system of claim 1, wherein, The field programmable gate array module mounts the memory expansion module through an open memory interface, and the field programmable gate array module sends the memory access request to the mounted memory expansion module through the open memory interface according to the analysis result; And / or, the field programmable gate array module mounts a double data rate synchronous random access memory, the double data rate synchronous random access memory is mounted on the field programmable gate array module in the form of a dual in-line module, and the field programmable gate array module sends the memory access request to the double data rate synchronous random access memory according to the analysis result, so that the double data rate synchronous random access memory responds to the memory access request.

3. The memory extension system of claim 1, wherein, The memory expansion system is deployed in a target node, and the field programmable gate array module is specifically used for receiving a first memory access request sent by a processor in the target node, analyzing the first memory access request to determine a requested destination memory page table, locking the destination memory page table when the attribute of the destination memory page table meets a preset condition, and sending the first memory access request to the memory expansion module mounted on the field programmable gate array module; The destination memory page table is unlocked after the memory expansion module responds to the first memory access request.

4. The memory extension system of claim 3, wherein, The field programmable gate array module comprises a compute express link interface or a peripheral component interconnect express bus interface and a compute express link and direct memory access controller; The computing quick link interface or peripheral component interconnect express bus interface is configured to receive a first memory access request sent by a processor in the target node; The computing quick link and direct memory access controller is configured to parse the first memory access request to determine a requested destination memory page table; The field programmable gate array module is further configured to lock the destination memory page table when a property of the destination memory page table meets a preset condition; The computing quick link and direct memory access controller is further configured to send the first memory access request to a memory expansion module mounted by the field programmable gate array module; And The field programmable gate array module is further configured to unlock the destination memory page table after the memory expansion module responds to the first memory access request.

5. The memory extension system of claim 1, wherein, The memory expansion system is deployed in a target node, and the field programmable gate array module is specifically configured to: receive a second memory access request sent by a graphics processor and / or another field programmable gate array module in the target node, parse the second memory access request, convert an address of a destination memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request, parse the converted second memory access request to determine a requested destination memory page table, lock the destination memory page table when a property of the destination memory page table meets a preset condition, and send the converted second memory access request to a memory expansion module mounted by the field programmable gate array module; receive response data of the memory expansion module in response to the converted second memory access request, construct response data packets conforming to a format corresponding to the destination memory page table based on the response data, return the response data packets to a sender of the second memory access request, and unlock the destination memory page table.

6. The memory extension system of claim 5, wherein, The graphics processor includes a high-speed channelized chip-to-chip interface, and the field programmable gate array module includes a high-speed channelized chip-to-chip interface and a computing quick link and direct memory access controller; different graphics processors, different field programmable gate array modules, and field programmable gate array modules and graphics processors are connected through the high-speed channelized chip-to-chip interface; The high-speed channelized chip-to-chip interface in the field programmable gate array module is configured to receive a second memory access request sent by a graphics processor and / or another field programmable gate array module in the target node; The field programmable gate array module is further configured to parse the second memory access request; The field programmable gate array module is further configured to convert an address of a destination memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request; The computing quick link and direct memory access controller is configured to parse the converted second memory access request to determine a requested destination memory page table; The field programmable gate array module is further configured to lock the destination memory page table when a property of the destination memory page table meets a preset condition; The computing fast link and direct memory access controller is further configured to send the converted second memory access request to a memory expansion module mounted on the field programmable gate array module. The field programmable gate array module is further configured to receive response data of the memory expansion module in response to the converted second memory access request, and construct a response data packet in a format corresponding to the target memory page table based on the response data. The high-speed channelized chip-to-chip interface in the field programmable gate array module is further configured to return the response data packet to a sender of the second memory access request. And The field programmable gate array module is further configured to unlock the target memory page table.

7. The memory extension system of claim 1, wherein, The memory expansion system is deployed in a target node, and the field programmable gate array module is specifically configured to: receive a third memory access request sent by a device in another node, parse the third memory access request to determine a target memory page table, lock the target memory page table when an attribute of the target memory page table meets a preset condition, and send the memory access request to a memory expansion module mounted on the field programmable gate array module. The target memory page table is unlocked after the memory expansion module responds to the third memory access request; wherein the device in another node includes a processor and / or a field programmable gate array module and / or a graphics processor in another node.

8. The memory extension system of claim 7, wherein, The field programmable gate array module includes an Ethernet-based remote direct memory access protocol stack, a computing fast link and direct memory access controller; The field programmable gate array module is further configured to receive a third memory access request sent by a device in another node. The Ethernet-based remote direct memory access protocol stack and the computing fast link and direct memory access controller are configured to parse the third memory access request to determine a target memory page table. The field programmable gate array module is further configured to lock the target memory page table when an attribute of the target memory page table meets a preset condition. The computing fast link and direct memory access controller is further configured to send the third memory access request to a memory expansion module mounted on the field programmable gate array module. And The field programmable gate array module is further configured to unlock the target memory page table after the memory expansion module responds to the third memory access request.

9. The memory extension system of claim 1, wherein, The graphics processor includes a high-bandwidth memory.

10. The memory extension system of claim 1, wherein, The memory expansion system is applied to model training, and training data is divided into N training sub-data and stored in first memory areas of N memory expansion modules mounted on field programmable gate array modules. And The nth graphics processor reads target training data from a first memory area of an nth memory expansion module mounted on an nth field programmable gate array module and a second memory area of a memory expansion module mounted on another field programmable gate array module connected to the nth graphics processor, and stores processed data to a second memory area of the nth memory expansion module mounted on the nth field programmable gate array module after model training based on the target training data.

11. The memory extension system of claim 10, wherein, N portions of training sub-data are respectively stored into first memory areas in N memory expansion modules mounted by N field programmable gate array modules through peripheral component interconnect express bus interfaces.

12. The memory extension system of claim 10, wherein, Data transmission is performed between the field programmable gate array module and the graphics processor through a DMA controller.

13. The memory extension system of claim 10, wherein, The N graphics processors share high-bandwidth memories in the graphics processors through ring connection.

14. A memory access method, comprising: The method applied to the field programmable gate array module in the memory expansion system in any one of claims 1 to 13, the method comprises: receiving a memory access request; wherein the memory access request comprises a memory access request sent by a processor and / or a graphics processor and / or another field programmable gate array module connected with the field programmable gate array module; and parsing the memory access request to obtain a parsing result, and sending the memory access request to a memory expansion module mounted by the field programmable gate array module according to the parsing result, so that the memory expansion module responds to the memory access request.

15. The memory access method of claim 14, wherein, The memory expansion system is deployed in a target node, and the receiving of the memory access request comprises: receiving a first memory access request sent by a processor in the target node; The parsing of the memory access request to obtain a parsing result, and sending the memory access request to a memory expansion module mounted by the field programmable gate array module according to the parsing result, comprises: parsing the first memory access request to determine a requested destination memory page table, locking the destination memory page table when an attribute of the destination memory page table meets a preset condition, and sending the first memory access request to the memory expansion module mounted by the field programmable gate array module; After the memory expansion module responds to the first memory access request, the method further comprises: unlocking the destination memory page table.

16. The memory access method of claim 14, wherein, The memory expansion system is deployed in a target node, and the receiving of the memory access request comprises: receiving a second memory access request sent by a graphics processor and / or another field programmable gate array module in the target node; The parsing of the memory access request to obtain a parsing result, and sending the memory access request to a memory expansion module mounted by the field programmable gate array module according to the parsing result, comprises: parsing the second memory access request, converting an address of a destination memory page table requested in the second memory access request into a memory physical address to obtain a converted second memory access request; parsing the converted second memory access request to determine a requested destination memory page table, locking the destination memory page table when an attribute of the destination memory page table meets a preset condition, and sending the converted second memory access request to the memory expansion module mounted by the field programmable gate array module; and After the memory expansion module responds to the second memory access request, the method further comprises: receiving response data of the memory expansion module in response to the converted second memory access request, constructing a response data packet conforming to a format corresponding to the destination memory page table based on the response data, returning the response data packet to a sender of the second memory access request, and unlocking the destination memory page table.

17. The memory access method of claim 14, wherein, The memory expansion system is deployed in the target node, and the receiving the memory access request comprises: receiving a third memory access request sent by a device in another node; wherein the device in the other node comprises a processor and / or a field programmable gate array module and / or a graphics processor in the other node; The analyzing the memory access request to obtain an analysis result, and sending the memory access request to a memory expansion module mounted by the field programmable gate array module according to the analysis result, comprises: analyzing the third memory access request to determine a requested destination memory page table, locking the destination memory page table when an attribute of the destination memory page table meets a preset condition, and sending the third memory access request to the memory expansion module mounted by the field programmable gate array module; and After the memory expansion module responds to the third memory access request, further comprising: unlocking the destination memory page table.

18. An electronic device, comprising: The memory and one or more processors, the memory stores computer readable instructions, the computer readable instructions are executed by one or more processors, so that one or more processors execute the steps of any one of claims 14 to 17.

19. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium stores computer readable instructions, the computer readable instructions are executed to implement the steps of the memory access method of any one of claims 14 to 17.

20. A computer readable instruction product, characterized in that, The computer readable instructions are executed by the processor to implement the steps of the memory access method of any one of claims 14 to 17.

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