Three-dimensional optoelectronic integrated packaging structure and forming method therefor

Abstract

The present invention relates to a three-dimensional optoelectronic integrated package structure and a forming method therefor. The forming method comprises: arranging an optical chip and a protective structure right-side-up on a carrier, a gap being present between the protective structure and the optical chip, an edge of a front surface of the optical chip being provided with an optical port, and the optical port being opposite to the protective structure; providing an electrical chip on the optical chip in a flip-chipped manner, a part of the electrical chip extending past the gap and being located above the protective structure; forming a thin film layer covering the protective structure, the optical chip, and the electrical chip; forming a plastic packaging layer, the plastic packaging layer integrally plastically packaging the protective structure, the optical chip, and the electrical chip, and then thinning the plastic packaging layer and the thin film layer on the electrical chip to expose the electrical chip; removing the carrier, and cutting the electrical chip along the gap between the protective structure and the optical chip to expose the optical port; and coupling an optical fiber to the optical port of the optical chip. According to the present invention, a cavity is formed by means of vacuum lamination for optical port protection without occupying the area of an active region of the chip, and the area ratio of the electrical chip to the optical chip can be greatly increased.

Description

A three-dimensional optoelectronic integrated packaging structure and a forming method thereof TECHNICAL FIELD

[0001] The present application relates to the technical field of chip packaging, and in particular to a three-dimensional optoelectronic integrated packaging structure and a forming method thereof. BACKGROUND

[0002] With the development of information technology, higher and higher requirements are put forward for the transmission rate, time delay, energy efficiency and the like of an optical module, and a CPO (Chip Photo Optics) structure in which an optical chip and an electrical chip are packaged in the same package has been more and more widely applied. In the CPO structure, a through silicon via is made on the optical chip or the electrical chip, and then the through silicon via is vertically stacked with a matching electrical chip / optical chip, so that the three-dimensional optoelectronic integrated packaging formed has the advantages of high interconnection density and small parasitic parameters, and is an important development direction of high-speed optical interconnection.

[0003] Due to the thin thickness of the silicon adapter plate, the warping after the plate is large, which makes the subsequent C2C mounting more difficult, and it is best to vertically stack the optical chip and the electrical chip, and then to package the whole as one whole before the plate is mounted. However, the optical port of the optical chip is easy to be contaminated or damaged in the packaging process, so a special protection structure needs to be arranged at the optical port, or the optical port can be covered by die bonding adhesive DA. The optical port protection structure will limit the area of the electrical chip and affect the improvement of the overall performance of the optical module. If the die bonding adhesive DA is used, the die bonding adhesive DA is difficult to be cleaned completely, which will bring the risk of optical port contamination.

[0004] Chinese patent CN112034567B discloses an optoelectronic chip packaging structure and a packaging method thereof. An electrical chip is arranged on an optical chip, a protection structure is mounted on the optical chip before packaging to protect the optical port area, the protection structure has a groove, and a closed cavity is formed after mounting. After packaging, the back of the optical chip is thinned to expose the conductive plug, the re-wiring is made and the solder balls are arranged, and finally the wafer is cut to expose the optical port. The mounting of the protection structure will reduce the space on the surface of the optical chip, which will limit the area of the electrical chip. Moreover, the protection structure usually uses adhesive, such as die bonding adhesive DA, but there will be a situation of adhesive overflow, which will further reduce the available space on the optical chip and further limit the area of the electrical chip. In addition, a closed cavity is formed in the protection structure after packaging, and after the optical chip is thinned and the conductive plug is exposed, the thickness of the optical chip containing the conductive plug is relatively thin, and there is a risk of silicon explosion caused by the pressure difference between the inside and outside of the cavity in the subsequent solder ball arrangement process. SUMMARY

[0005] To solve at least part of the above problems in the prior art, the present application provides a forming method of a three-dimensional optoelectronic integrated packaging structure, comprising:

[0006] The optical chip and the protection structure are arranged on the carrier in a normal way, wherein a gap exists between the protection structure and the optical chip, the edge of the front surface of the optical chip has an optical port, and the optical port is opposite to the protection structure;

[0007] The electrical chip is arranged on the optical chip in a reversed way, and a part of the electrical chip extends over the gap and is located above the protection structure;

[0008] The film layer covering the protection structure, the optical chip and the electrical chip is formed;

[0009] The plastic sealing layer is formed, the protection structure, the optical chip and the electrical chip are integrally sealed by the plastic sealing layer, then the plastic sealing layer and the film layer above the electrical chip are thinned to expose the electrical chip;

[0010] The carrier is removed, and the electrical chip is cut along the gap between the protection structure and the optical chip to expose the optical port; and

[0011] The optical fiber is coupled with the optical port of the optical chip.

[0012] Further, after the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier form a closed space;

[0013] The part of the electrical chip extending out has no transistor and circuit;

[0014] The front surface and the back surface of the optical chip have a redistribution layer (RDL), and the optical chip has a through silicon via, which is electrically connected with the redistribution layer (RDL).

[0015] Further, the method further comprises:

[0016] After the electrical chip is cut, the solder balls are arranged on the redistribution layer surface of the back surface of the optical chip; and

[0017] The structure in which the optical chip and the electrical chip are packaged together is attached on the substrate.

[0018] The application also provides a forming method of a three-dimensional optoelectronic integrated packaging structure, comprising:

[0019] The electrical chip and the protection structure are arranged on the carrier in a normal way, wherein a gap exists between the protection structure and the electrical chip;

[0020] The optical chip is arranged on the electrical chip in a reversed way, and a part of the optical chip extends over the gap and is located above the protection structure, wherein the front surface of the optical chip has an optical port, the optical port is 0.08-0.3 mm away from the edge of the optical chip, and the optical port is located above the protection structure;

[0021] The film layer covering the protection structure, the electrical chip and the optical chip is formed;

[0022] forming a plastic sealing layer, the plastic sealing layer integrally sealing the protection structure, the optical chip and the electrical chip, thinning the plastic sealing layer and the film layer above the optical chip to expose the optical chip, and removing the carrier sheet;

[0023] cutting the structure after the thinning, the cutting line passing through the optical port to expose the side surface of the optical waveguide of the optical port; and

[0024] coupling the optical fiber with the optical port of the optical chip.

[0025] The application further provides a forming method of a three-dimensional optoelectronic integrated packaging structure, comprising:

[0026] arranging the electrical chip and the protection structure in a normal direction on the carrier sheet, wherein a gap exists between the protection structure and the electrical chip;

[0027] arranging the optical chip in a reverse direction on the electrical chip, and a part of the optical chip protrudes above the protection structure beyond the gap, wherein the front surface of the optical chip has an optical port, and the optical port is above the gap;

[0028] forming a film layer covering the protection structure, the electrical chip and the optical chip;

[0029] forming a plastic sealing layer, the plastic sealing layer integrally sealing the protection structure, the optical chip and the electrical chip, thinning the plastic sealing layer and the film layer above the optical chip to expose the optical chip, and removing the carrier sheet;

[0030] cutting the protection structure; and

[0031] coupling the optical fiber with the optical port of the optical chip.

[0032] Further, the part of the plastic sealing layer and the film layer above the protection structure are reserved after the cutting, and the space surrounded by the protection structure, the electrical chip, the optical chip, the plastic sealing layer and the film layer can only be accessed through the gap between the protection structure and the electrical chip.

[0033] Further, after the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier sheet surround a closed space;

[0034] The front surface and the back surface of the electrical chip have a redistribution layer (RDL), and the electrical chip has a through silicon via, which is electrically connected with the RDL.

[0035] The application further provides a three-dimensional optoelectronic integrated packaging structure, comprising:

[0036] an optical chip, the front surface of the optical chip having an optical port;

[0037] an electrical chip, which is electrically connected with the electrical chip;

[0038] an optical fiber, which is coupled with the optical port of the optical chip.

[0039] Further, the front surface of the electric chip is opposite to the front surface of the optical chip, and the optical port is located at the edge of the optical chip, and the optical fiber is coupled with the optical port of the optical chip from the side surface;

[0040] The optical chip or the electric chip has a through silicon via and a redistribution layer (RDL) on the front surface and the back surface, and the through silicon via is electrically connected with the redistribution layer (RDL).

[0041] Further, a protection structure is further arranged in parallel with the electric chip, and a gap is formed between the electric chip and the protection structure.

[0042] Further, the optical chip is flip-chip arranged on the electric chip, and a part of the optical chip extends over the gap and is located above the protection structure, and the optical port is located above the gap.

[0043] The optical fiber extends into the gap and is coupled with the optical port of the optical chip.

[0044] The present application has at least the following advantages: (1) the present application arranges the protection structure in parallel with the chip with a through silicon via on the carrier, and a gap is formed between the protection structure and the chip, and a sealed cavity is formed after vacuum lamination, the gap is used for air pressure balance, and the risk of silicon explosion in the subsequent solder ball process is eliminated after debonding; (2) the present application forms a cavity for optical port protection by vacuum lamination, and the area of the active region of the chip is not occupied, and the area ratio of the electric chip and the optical chip can be greatly improved. BRIEF DESCRIPTION OF DRAWINGS

[0045] In order to further illustrate the above and other advantages and features of the embodiments of the present application, more detailed description of the embodiments of the present application will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present application, and therefore should not be considered as limiting the scope thereof. In the drawings, for the sake of clarity and conciseness, the same or corresponding parts will be denoted by the same or similar reference numerals.

[0046] FIGS. 1 to 10 show schematic diagrams of a process of forming a three-dimensional optoelectronic integrated packaging structure according to an embodiment of the present application.

[0047] FIG. 11 shows a schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to an embodiment of the present application.

[0048] FIGS. 12 to 21 show schematic diagrams of a process of forming a three-dimensional optoelectronic integrated packaging structure according to another embodiment of the present application.

[0049] FIG. 22 shows a schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber edge coupling according to another embodiment of the present application.

[0050] FIG. 23 shows a schematic diagram of a three-dimensional optoelectronic integrated packaging structure with fiber vertical coupling according to an embodiment of the present application. DETAILED DESCRIPTION

[0051] It should be noted that the components in the various figures can be shown exaggerated in size for illustrative purposes and are not necessarily drawn to scale.

[0052] In the present application, each embodiment is merely intended to illustrate the scheme of the present application and should not be understood as limiting.

[0053] In the present application, unless specifically indicated, the quantifier "one" does not exclude the scenario of multiple elements.

[0054] It should also be noted herein that, for the sake of clarity and simplicity, only a part of the components or assemblies can be shown in the embodiments of the present application, but those skilled in the art can understand that, under the teaching of the present application, the required components or assemblies can be added according to the specific scene needs.

[0055] It should also be noted herein that, within the scope of the present application, the phrases "same", "equal", "equal to" and the like do not mean that the numerical values of the two are absolutely equal, but allow a certain reasonable error, that is, the phrases also cover "substantially the same", "substantially equal", "substantially equal".

[0056] It should also be noted herein that, in the description of the present application, the orientations or positional relationships indicated by the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and are not meant to imply or suggest that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for description purposes and cannot be understood as implying or suggesting relative importance.

[0057] In addition, the embodiments of the present application describe the process steps in a specific order, however this is only for the convenience of distinguishing the steps and is not limited to the order of the steps, and in different embodiments of the present application, the order of the steps can be adjusted according to the adjustment of the process.

[0058] Figures 1 to 10 show schematic diagrams of the process of forming a three-dimensional optoelectronic integrated packaging structure according to an embodiment of the present application.

[0059] When the optical chip is used as a conversion board, the method for forming a three-dimensional optoelectronic integrated packaging structure comprises:

[0060] Step 1, as shown in Figure 1, a temporary bonding glue layer 102 is coated on a slide 101.

[0061] Step 2, as shown in FIG. 2, a protective structure 103 and an optical chip 104 are attached on the temporary bonding layer 102 with a certain interval. There is a gap between the protective structure 103 and the optical chip 104. The optical chip 104 has completed the through-silicon via and the front / back surface redistribution layer (RDL) fabrication. The optical port 1041 is located at the edge of the front surface of the optical chip 104, and the optical port is opposite to the protective structure 103. The optical chip 104 is attached on the carrier wafer 101 with the front surface upward. The protective structure can be a plate-like or block-like structure with the same thickness as the optical chip, such as a dummy die.

[0062] Step 3, as shown in FIG. 3, an electrical chip 105 is flip-chip mounted on the optical chip 104, and the underfill is performed between the optical chip 104 and the electrical chip 105. A part of the electrical chip 105 extends over the protective structure 103 beyond the gap, and the extended part of the electrical chip is free of transistors and lines.

[0063] Step 4, as shown in FIGS. 4 and 5, a film layer 106 is formed by a vacuum film pressing process to cover the protective structure 103, the optical chip 104 and the electrical chip 105. The gap under the electrical chip 105 is shielded and not filled with the film. The protective structure 103, the optical chip 104, the electrical chip 105, the film layer 106 and the carrier wafer 101 form a closed space to protect the optical port 1041.

[0064] Step 5, as shown in FIGS. 6 and 7, a plastic encapsulation layer 107 is formed, and the plastic encapsulation layer 107 and the film layer 106 above the electrical chip 105 are thinned to expose the electrical chip 105. The plastic encapsulation layer 107 integrally encapsulates the protective structure 103, the optical chip 104 and the electrical chip 105. The thinning process includes chemical mechanical polishing, etching process or mechanical polishing process.

[0065] Step 6, as shown in FIGS. 8 and 9, the carrier wafer 101 and the temporary bonding layer 102 are removed, and the electrical chip 105 is cut along the gap between the protective structure 103 and the optical chip 104 to expose the optical port, and then the solder balls are arranged on the redistribution layer (RDL) surface of the back surface of the optical chip 104.

[0066] Step 7, as shown in FIG. 10, the structure in which the optical chip 104 and the electrical chip 105 are packaged together is attached on a substrate 108, and an optical fiber 109 is coupled with the optical port 1041 of the optical chip 104.

[0067] FIG. 11 shows a schematic diagram of a three-dimensional optoelectronic integrated packaging structure of fiber edge coupling according to an embodiment of the present application.

[0068] As shown in FIG. 11, the three-dimensional optoelectronic integrated packaging structure formed by the above embodiment includes an optical chip 201, an electrical chip 202, an optical fiber 203 and a substrate 204.

[0069] The front and back surfaces of the optical chip 201 have a redistribution layer (RDL), and the optical chip 201 has through-silicon vias (TSVs) that are electrically connected to the RDL. The edge of the front surface of the optical chip 201 has an optical port 2021. Solder balls are disposed on the RDL surface of the back surface of the optical chip 201.

[0070] The optical chip 201 is disposed on the substrate 204 in a face-up manner.

[0071] The electrical chip 202 is disposed on the optical chip 201 in a flip-chip manner, and the two are filled with underfill glue. The electrical chip 202 is electrically connected to the optical chip 201.

[0072] The optical fiber 203 is coupled to the optical port 2021 of the optical chip 201 from the side.

[0073] FIGS. 12 to 21 show schematic diagrams of a process of forming a three-dimensional optoelectronic integrated package structure according to another embodiment of the present application.

[0074] When the electrical chip is used as a board, the method for forming the three-dimensional optoelectronic integrated package structure includes the following steps:

[0075] Step 1: As shown in FIG. 12, a temporary bonding glue layer 302 is coated on a wafer 301.

[0076] Step 2: As shown in FIG. 13, a protective structure 303 and an electrical chip 304 are attached on the temporary bonding glue layer 302 at a certain interval. There is a gap between the protective structure 303 and the electrical chip 304. The electrical chip 304 has been fabricated with through-silicon vias and redistribution layers (RDLs) on the front and back surfaces. The electrical chip 304 is attached on the wafer 101 in a face-up manner. The protective structure can be a plate-shaped or block-shaped structure with the same thickness as the electrical chip, such as a dummy die.

[0077] Step 3: As shown in FIGS. 14 and 15, an optical chip 305 is disposed on the electrical chip 304 in a flip-chip manner, and underfill is performed between the optical chip 305 and the electrical chip 304. A part of the optical chip 305 protrudes above the protective structure 303 beyond the gap.

[0078] In one embodiment of the present application, the front surface of the optical chip 305 has an optical port 3051, the optical port 3051 is 0.08-0.3 mm away from the edge of the optical chip, and the optical port 3051 is located above the protective structure 303, corresponding to the edge coupling case, as shown in FIG. 14.

[0079] In another embodiment of the present application, the front surface of the optical chip 305 has an optical port 3051, the optical port 3051 is greater than 0.2 mm away from the edge of the optical chip, and the optical port 3051 of the optical chip 305 is located above the gap, corresponding to the vertical coupling case, as shown in FIG. 15.

[0080] Step 4. Form a thin film layer covering the protection structure 303, the electrical chip 304 and the optical chip 305 by a vacuum lamination process. The gap under the optical chip 305 is shielded and not filled by the film. The protection structure 303, the electrical chip 304, the optical chip 305, the thin film layer and the carrier wafer form a closed space to protect the optical port.

[0081] Step 5. As shown in FIGS. 16 and 17, a plastic encapsulation layer 306 is formed. The plastic encapsulation layer 306 and the thin film layer above the optical chip 305 are thinned to expose the optical chip 305, and then the carrier wafer 301 and the temporary bonding layer 302 are removed. The plastic encapsulation layer 306 integrally encapsulates the protection structure 303, the electrical chip 304 and the optical chip 305. The thinning process includes chemical mechanical polishing, etching or mechanical polishing.

[0082] Step 6. As shown in FIGS. 16 and 18, for the structure in which the optical port is above the protection structure 303, the thinned structure is cut, and the cutting line passes through the optical port to expose the side of the optical waveguide of the optical port 3051.

[0083] The cutting line passes through the optical port area in FIG. 16 because the mounted optical chip 305 is a chip that is not cut to expose the side of the optical port waveguide in advance. To prevent the flow of the film material from polluting the optical port area during the vacuum lamination, a certain width of silicon (without transistors and lines, width 0.08-0.3 mm) needs to be reserved between the optical port area and the edge of the optical chip during the lamination. When cutting after the debonding, the cutting line needs to pass through the optical port area to cut out the side of the waveguide for the subsequent edge coupling with the optical fiber. In contrast, the optical port area is far from the film material in FIG. 8, and a cut optical chip can be used, and the optical port area is not cut during the cutting.

[0084] In another embodiment of the present application, as shown in FIGS. 17 and 19, for the structure in which the optical port is above the gap, the protection structure 303 is cut. The cut structure retains part of the plastic encapsulation layer and the thin film layer above the protection structure 303. The space surrounded by the protection structure 303, the electrical chip 304, the optical chip 305, the plastic encapsulation layer and the thin film layer can only be accessed through the gap between the protection structure 303 and the electrical chip 304.

[0085] Step 7. As shown in FIGS. 18 and 19, solder balls are arranged on the surface of the redistribution layer (RDL) on the back of the electrical chip 304.

[0086] Step 8. As shown in FIGS. 20 and 21, the structure in which the optical chip 305 and the electrical chip 304 are packaged together is mounted on a substrate 307, and an optical fiber 308 is coupled with the optical port of the optical chip 305. For the edge coupling case, the optical fiber is connected with the optical port from the side. For the vertical coupling case, the optical fiber extends into the gap between the protection structure 303 and the electrical chip 304 and is connected with the optical port.

[0087] In FIG. 20, the side of the film-plastic encapsulant connected remaining protective structure and other parts in the package is integrated, and the remaining protective structure does not fall off because of no support below.

[0088] For the case of sufficient area of the electrical chip (such as the integration of DSP in the electrical chip), the process route of growing TSV on the electrical chip and then mounting the optical chip on it can also be used. At this time, the air pressure balance gap (the gap between the electrical chip and the protective structure) can also be used to insert the optical fiber to achieve vertical coupling.

[0089] FIG. 22 shows a schematic diagram of a three-dimensional optoelectronic integrated package structure of optical fiber edge coupling according to another embodiment of the present application.

[0090] As shown in FIG. 22, the three-dimensional optoelectronic integrated package structure formed by the above embodiment includes a substrate 401, an electrical chip 402, an optical chip 403, and an optical fiber 404.

[0091] The electrical chip 402 is disposed on the substrate 401.

[0092] The front and back surfaces of the electrical chip 402 have a redistribution layer (RDL), and the electrical chip 402 has a through silicon via (TSV) electrically connected to the RDL. Solder balls are disposed on the surface of the RDL on the back surface of the electrical chip 402.

[0093] The optical chip 403 is flip-chip disposed on the electrical chip 402, and the two are filled with underfill glue. The electrical chip 402 is electrically connected to the optical chip 403. The edge of the front surface of the optical chip 403 has an optical port 4031.

[0094] The optical fiber 404 is coupled to the optical port of the optical chip 403 from the side.

[0095] FIG. 23 shows a schematic diagram of a three-dimensional optoelectronic integrated package structure of optical fiber vertical coupling according to an embodiment of the present application.

[0096] As shown in FIG. 23, the three-dimensional optoelectronic integrated package structure formed by the above embodiment includes a substrate 501, an electrical chip 502, an optical chip 503, an optical fiber 504, and a protective structure 505.

[0097] The electrical chip 502 and the protective structure 505 are disposed side by side on the substrate 501, and there is a gap between them.

[0098] The front and back surfaces of the electrical chip 502 have a redistribution layer (RDL), and the electrical chip 502 has a through silicon via (TSV) electrically connected to the RDL. Solder balls are disposed on the surface of the RDL on the back surface of the electrical chip 502.

[0099] The optical chip 503 is flip-chip mounted on the electrical chip 502, and the two are filled with underfill glue. The electrical chip 502 is electrically connected to the optical chip 503. The front surface of the optical chip 503 has a light port 5031. A part of the optical chip 503 extends over the gap above the protection structure, and the light port is located above the gap.

[0100] The optical fiber 404 extends from the gap to couple with the light port of the optical chip 403.

[0101] The three-dimensional optoelectronic integrated packaging structure further includes a film layer covering the left and right sides of the optical chip 503, the upper surface of the protection structure 505, and the right side of the electrical chip 502.

[0102] It further includes a plastic sealing layer that seals the part covered by the film layer.

[0103] Although some embodiments of the present application have been described in the present application, those skilled in the art can understand that these embodiments are only shown as examples. Those skilled in the art can think of numerous variations, alternatives and improvements under the teaching of the present application without departing from the scope of the present application. The appended claims are intended to define the scope of the present application and thereby cover the methods and structures within the scope of the claims themselves and their equivalent transformations.

Claims

1. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: The method comprises the following steps: arranging an optical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the optical chip, the edge of the front surface of the optical chip has an optical port, and the optical port is opposite to the protection structure; arranging an electrical chip on the optical chip in a reverse direction, and a part of the electrical chip extends over the gap to the top of the protection structure; forming a film layer covering the protection structure, the optical chip and the electrical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, then thinning the plastic encapsulation layer and the film layer above the electrical chip to expose the electrical chip; removing the carrier, and cutting the electrical chip along the gap between the protection structure and the optical chip to expose the optical port; and coupling an optical fiber with the optical port of the optical chip. After the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier form a closed space; 2. The method of claim 1, wherein, the part of the electrical chip extending out has no transistor and circuit; the front surface and the back surface of the optical chip have a redistribution layer (RDL), and the optical chip has a through silicon via (TSV) which is electrically connected with the RDL. The method further comprises the following steps:

3. The method of claim 1, wherein, arranging solder balls on the surface of the RDL on the back surface of the optical chip after the electrical chip is cut; and attaching the structure in which the optical chip and the electrical chip are encapsulated together to a substrate. The method comprises the following steps: arranging an electrical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the electrical chip; 4. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: arranging an optical chip on the electrical chip in a reverse direction, and a part of the optical chip extends over the gap to the top of the protection structure, wherein the front surface of the optical chip has an optical port, the distance between the optical port and the edge of the optical chip is 0.08-0.3 mm, and the optical port is above the protection structure; forming a film layer covering the protection structure, the electrical chip and the optical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, thinning the plastic encapsulation layer and the film layer above the optical chip to expose the optical chip, and removing the carrier; cutting the structure after the plastic encapsulation layer is thinned, the cutting line passes through the optical port, and the side surface of the optical waveguide of the optical port is exposed; and coupling an optical fiber with the optical port of the optical chip. The method comprises the following steps: arranging an electrical chip and a protection structure on a carrier in a normal direction, wherein a gap exists between the protection structure and the electrical chip; 5. A method of forming a three-dimensional optoelectronic integrated package structure, comprising: arranging an optical chip on the electrical chip in a reverse direction, and a part of the optical chip extends over the gap to the top of the protection structure, wherein the front surface of the optical chip has an optical port, and the optical port is above the gap; forming a film layer covering the protection structure, the electrical chip and the optical chip; forming a plastic encapsulation layer, and integrally encapsulating the protection structure, the optical chip and the electrical chip, thinning the plastic encapsulation layer and the film layer above the optical chip to expose the optical chip, and removing the carrier; cutting the protection structure; and coupling an optical fiber with the optical port of the optical chip from the gap. After cutting, the part of the plastic encapsulation layer and the film layer above the protection structure is reserved, and the space surrounded by the protection structure, the electrical chip, the optical chip, the plastic encapsulation layer and the film layer can only be accessed through the gap between the protection structure and the electrical chip. After the film layer is formed, the protection structure, the optical chip, the electrical chip, the film layer and the carrier form a closed space; the front surface and the back surface of the electrical chip have a redistribution layer (RDL), and the electrical chip has a through silicon via (TSV) which is electrically connected with the RDL.

6. The method of claim 5, wherein, The method comprises the following steps:

7. The method according to claim 4 or 5, characterized in that, arranging an optical chip, the front surface of which has an optical port; arranging an electrical chip which is electrically connected with the electrical chip; 8. A three-dimensional optoelectronic integrated package structure, characterized by, arranging an optical fiber which is coupled with the optical port of the optical chip. ​ ​ ​ 9. The structure of claim 8, wherein The front surface of the electric chip is opposite to the front surface of the optical chip, and the light port is located at the edge of the optical chip, and the optical fiber is coupled with the light port of the optical chip from the side surface; The optical chip or the electric chip has a through silicon via and a redistribution layer (RDL) on the front surface and the back surface, and the through silicon via is electrically connected with the redistribution layer (RDL).

10. The structure of claim 8, wherein A protection structure is further included, which is arranged side by side with the electric chip, and a gap is formed between the electric chip and the protection structure.

11. The structure of claim 10, wherein The optical chip is flip-chip mounted on the electric chip, and a part of the optical chip extends over the gap to be located above the protection structure, and the light port is located above the gap; The optical fiber extends into the gap to be coupled with the light port of the optical chip.

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