Power unit, three-phase full-bridge power module, power supply system, and vehicle

Abstract

The present application discloses a power unit, a three-phase full-bridge power module, a power supply system, and a vehicle. The power unit comprises an upper bridge power chip and a lower bridge power chip, a second pole of the upper bridge power chip and a first pole of the lower bridge power chip both being electrically connected to an alternating-current output conductive circuit of the power unit, and a first pole of the upper bridge power chip and a second pole of the lower bridge power chip being electrically connected to two different conductive layers, respectively. The two different conductive layers are at least partially stacked, and are a direct-current input conductive circuit of the power unit.

Description

Power unit, three-phase full-bridge power module, power supply system and vehicle

[0001] Priority information

[0002] The present application claims priority to and the benefit of the filing date of the Chinese Patent Application No. 202421589611.X filed on July 5, 2024 with the China National Intellectual Property Office, and incorporates herein by reference in its entirety. TECHNICAL FIELD

[0003] The present application belongs to the technical field of power supply, and particularly relates to a power unit, a three-phase full-bridge power module, a power supply system and a vehicle. BACKGROUND

[0004] The three-phase full-bridge power module is an important component in power electronic equipment, which is widely used in many fields, for example, it can be applied to new energy vehicles, and can convert the direct current output by the battery into alternating current to drive the devices that need alternating current drive, such as electric motors.

[0005] The power unit is a component of the three-phase full-bridge power module, and a general power unit includes a single-layer ceramic substrate, and a half-bridge unit or a full-bridge unit arranged on the surface of the single-layer ceramic substrate, and the full-bridge unit is also composed of two half-bridge units; for each half-bridge unit, it can include an upper bridge power chip, a lower bridge power chip, and a commutation loop connected with the upper bridge power chip and the lower bridge power chip. In the prior art, there is a problem of too high parasitic inductance in the packaging structure of the power unit, and such too high parasitic inductance usually causes a series of problems such as turn-off overvoltage, voltage and current oscillation, mis-switching and electromagnetic interference in the switching process of the power unit. With the application of SiC and GaN devices in the power unit, although they have the advantages of high switching speed, which can reduce switching loss, but they are more sensitive to parasitic inductance. Therefore, how to reduce the parasitic inductance in the packaging structure of the power unit is a technical problem to be solved. SUMMARY

[0006] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes a power unit, a three-phase full-bridge power module, a power supply system and a vehicle, which can reduce the parasitic inductance in the packaging structure of the power unit.

[0007] In a first aspect, the application provides a power unit, comprising a first substrate, and at least one half-bridge unit formed on the first substrate, the half-bridge unit comprising an upper bridge power chip and a lower bridge power chip, a second pole of the upper bridge power chip and a first pole of the lower bridge power chip are electrically connected with an alternating current output conductive path of the power unit, a first pole of the upper bridge power chip and a second pole of the lower bridge power chip are respectively electrically connected with two different conductive layers, the two different conductive layers are at least partially laminated, and are direct current input conductive paths of the power unit.

[0008] In some embodiments, a first conductive layer and a second conductive layer are formed on the upper surface of the first substrate;

[0009] The upper bridge power chip is arranged on the first conductive layer, and a first pole of the upper bridge power chip is electrically connected with the first conductive layer;

[0010] The lower bridge power chip is arranged on the second conductive layer, and a second pole of the upper bridge power chip and a first pole of the lower bridge power chip are electrically connected with the second conductive layer, and the second conductive layer is an alternating current output conductive path of the power unit;

[0011] The power unit further comprises:

[0012] The second substrate is arranged on the first conductive layer, and a third conductive layer is formed on the upper surface of the second substrate, the third conductive layer and the first conductive layer are at least partially laminated, and a second pole of the lower bridge power chip is electrically connected with the third conductive layer;

[0013] The first conductive layer and the third conductive layer are direct current input conductive paths of the power unit.

[0014] In some embodiments, the upper bridge power chip and / or the lower bridge power chip is a MOSFET, the first pole is a drain, the second pole is a source, the first conductive layer is a direct current positive input conductive path of the power unit, and the third conductive layer is a direct current negative input conductive path of the power unit.

[0015] In some embodiments, the upper bridge power chip and / or the lower bridge power chip is an IGBT, the first pole is a collector, the second pole is an emitter, the first conductive layer is a direct current positive input conductive path of the power unit, and the third conductive layer is a direct current negative input conductive path of the power unit.

[0016] In some embodiments, a fourth conductive layer is further formed on the upper surface of the first substrate, and the fourth conductive layer is electrically connected with a control pole of the upper bridge power chip;

[0017] A fifth conductive layer is further formed on the upper surface of the first substrate, and the fifth conductive layer is electrically connected with a control pole of the lower bridge power chip.

[0018] In some embodiments, the number of the upper bridge power chips and the lower bridge power chips is at least two, and the at least two upper bridge power chips and the at least two lower bridge power chips extend along the length direction of the first substrate, and the fourth conductive layer, the first conductive layer, the second conductive layer and the fifth conductive layer of the half-bridge unit are sequentially arranged in the width direction of the first substrate.

[0019] In some embodiments, the second pole includes a power second pole and a driving second pole, and the upper surface of the first substrate further forms a sixth conductive layer and a seventh conductive layer.

[0020] The power second pole of the upper bridge power chip is electrically connected with the second conductive layer, and the driving second pole of the upper bridge power chip is electrically connected with the sixth conductive layer, thereby constituting a Kelvin connection.

[0021] The power second pole of the lower bridge power chip is electrically connected with the third conductive layer, and the driving second pole of the lower bridge power chip is electrically connected with the seventh conductive layer, thereby constituting a Kelvin connection.

[0022] In some embodiments, the upper bridge power chip, the lower bridge power chip and the second substrate are fixed on the upper surface of the first substrate through a connecting layer.

[0023] In some embodiments, the second substrate is fixed on the first conductive layer on the side adjacent to the second conductive layer through a connecting layer, and the upper bridge power chip is located on the side of the first conductive layer away from the second conductive layer.

[0024] In some embodiments, the second pole of the upper bridge power chip is electrically connected with the second conductive layer through a first connecting line, and the first connecting line crosses the second substrate.

[0025] The second pole of the lower bridge power chip is electrically connected with the third conductive layer through a second connecting line.

[0026] In some embodiments, the first connecting line is one of a bonding wire or a copper sheet; and the second connecting line is one of a bonding wire or a copper sheet.

[0027] In some embodiments, the first substrate includes a first insulating substrate, a first copper layer on the upper surface of the first insulating substrate and a second copper layer on the lower surface of the first insulating substrate, and the first copper layer is etched to obtain at least one of the first conductive layer, the second conductive layer, the fourth conductive layer, the fifth conductive layer, the sixth conductive layer and the seventh conductive layer.

[0028] The second substrate includes a second insulating substrate and a third copper layer on the upper surface of the second insulating substrate, and the third copper layer serves as the third conductive layer.

[0029] In some embodiments, at least one of the following is further included:

[0030] a direct current positive input terminal and a direct current negative input terminal, respectively electrically connected with one of the first conductive layer and the third conductive layer;

[0031] an alternating current output terminal electrically connected with the second conductive layer;

[0032] a first upper bridge driving terminal electrically connected with the fourth conductive layer;

[0033] a first lower bridge driving terminal electrically connected with the fifth conductive layer;

[0034] a second upper bridge driving terminal electrically connected with the sixth conductive layer;

[0035] a second lower bridge driving terminal electrically connected with the seventh conductive layer.

[0036] In some embodiments, the direct current positive input terminal and the direct current negative input terminal are arranged at a first end of the first substrate along the length direction, and are at least partially stacked;

[0037] The alternating current output terminal is arranged at a second end of the first substrate along the length direction.

[0038] In some embodiments, the direct current positive input terminal, the direct current negative input terminal and the alternating current output terminal are all arranged at a middle section of the first substrate along the length direction, and the direct current positive input terminal and the direct current negative input terminal are arranged adjacently.

[0039] In some embodiments, two half-bridge units are formed on the first substrate, which are a first half-bridge unit and a second half-bridge unit;

[0040] The second conductive layer of the first half-bridge unit and the second conductive layer of the second half-bridge unit are integrally arranged, and the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are respectively arranged at the outer side of the integrally arranged second conductive layer along the width direction.

[0041] In some embodiments, the first conductive layer of the first half-bridge unit and the first conductive layer of the second half-bridge unit are electrically connected.

[0042] In some embodiments, the fourth conductive layer and / or the sixth conductive layer are arranged at the outer side of the first conductive layer along the width direction;

[0043] The fifth conductive layer and the seventh conductive layer are arranged in the hollowed-out region of the middle part of the second conductive layer, and the lower bridge power chip of the first half-bridge unit and the lower bridge power chip of the second half-bridge unit are respectively arranged at the two sides of the hollowed-out region.

[0044] In some embodiments, the hollowed region comprises a plurality of sub-hollowed regions, the fifth conductive layer and the seventh conductive layer comprise a plurality of sub-conductive layers respectively arranged in the sub-hollowed regions, the plurality of sub-conductive layers of the fifth conductive layer are electrically connected to each other, the plurality of sub-conductive layers of the seventh conductive layer are electrically connected to each other, and the control poles of the lower bridge power chips are respectively connected to the adjacent sub-conductive layers of the fifth conductive layer, and the driving electrodes of the lower bridge power chips are respectively connected to the adjacent sub-conductive layers of the seventh conductive layer.

[0045] In some embodiments, a conductive connection layer is arranged in the hollowed region at the edge of the first substrate, the fourth conductive layer of the first half-bridge unit and the fourth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer, and / or the sixth conductive layer of the first half-bridge unit and the sixth conductive layer of the second half-bridge unit are electrically connected through the conductive connection layer.

[0046] In a second aspect, the present application provides a three-phase full-bridge power module, comprising three power units as described in any of the above, a heat dissipation plate and a housing;

[0047] The lower surfaces of the first substrates in the three power units are fixed on the heat dissipation plate, and the housing covers the three power units.

[0048] In a third aspect, the present application further provides a power supply system, comprising a battery and the three-phase full-bridge power module as described above.

[0049] In a fourth aspect, the present application further provides a vehicle, comprising the power supply system as described above.

[0050] In the technical scheme provided by the embodiments of the present application, the half-bridge unit comprises a first substrate, and an upper bridge power chip and a lower bridge power chip formed on the first substrate, and the second pole of the upper bridge power chip and the first pole of the lower bridge power chip as the alternating current output end are electrically connected with the alternating current output conductive path of the power unit; the first pole of the upper bridge power chip and the second pole of the lower bridge power chip as the direct current input end are respectively electrically connected with two different conductive layers, the two different conductive layers are at least partially laminated, and the two different conductive layers are the direct current input conductive path of the power unit. The current flow directions of the two different conductive layers are opposite, and the mutual inductance is negative, forming a mutual inductance cancellation effect to reduce the total parasitic inductance in the power unit, and the two conductive layers in the embodiments of the present application are at least partially laminated to form a laminated structure, so that the distance between the two conductive planes is extremely small, and the mutual inductance cancellation effect is better when the distance is closer, which helps to reduce the parasitic inductance inside the power unit.

[0051] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and / or can be learned by practice of the application. Attached Figure Description

[0052] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, wherein:

[0053] Figure 1 is a schematic diagram of the structure of a power chip in an embodiment of this application;

[0054] Figure 2 is a schematic cross-sectional view of a power unit in an embodiment of this application;

[0055] Figure 3 is a top view of a power unit in an embodiment of this application;

[0056] Figure 4 is a top view of the upper surface of the first substrate in an embodiment of this application;

[0057] Figure 5 is a schematic diagram of the connection of the power unit in an embodiment of this application;

[0058] Figure 6 is a second schematic diagram of the connection of the power unit in an embodiment of this application;

[0059] Figure 7 is a schematic diagram of the power unit with connection terminals in an embodiment of this application;

[0060] Figure 8 is a schematic diagram of the power unit with connection terminals in an embodiment of this application;

[0061] Figure 9 is an equivalent circuit diagram of the power unit in the embodiment shown in Figure 7;

[0062] Figure 10 is a top view of another power unit in an embodiment of this application;

[0063] Figure 11 is a top view of the first substrate in the embodiment shown in Figure 10;

[0064] Figure 12 is a top view of the second substrate in the embodiment shown in Figure 10;

[0065] Figure 13 is a schematic diagram of the connection of the power unit in the embodiment shown in Figure 10;

[0066] Figure 14 is a schematic diagram of the structure of the power unit with connection terminals in an embodiment of this application;

[0067] Figure 15 is a schematic diagram of the structure of the three-phase full-bridge power module in an embodiment of this application;

[0068] Figure 16 is a schematic diagram of the structure of the three-phase full-bridge power module in an embodiment of this application;

[0069] Figure 17 is a schematic diagram of a power supply system according to an embodiment of this application;

[0070] Figure 18 is a schematic diagram of a vehicle according to an embodiment of this application;

[0071] FIG. 19 is a schematic view of another vehicle in embodiments of the present application. DETAILED DESCRIPTION

[0072] Embodiments of the present application are described in detail below with reference to the attached drawing figures, wherein the same or like reference numerals are used throughout the drawing figures to refer to the same or like elements or elements having the same or similar functionality. The embodiments described below are exemplary and are merely intended to explain the present application, and are not to be understood as limiting the present application.

[0073] As described in the background, there is a problem of excessive parasitic inductance in the power unit packaging structure in the prior art, and the excessive parasitic inductance usually causes a series of problems such as turn-off overvoltage, voltage current oscillation, mis-switching and electromagnetic interference in the switching process of the power unit. Moreover, with the application of SiC and GaN devices in the power unit, although they have the advantages of high switching speed and can reduce switching loss, they are more sensitive to parasitic inductance. Therefore, how to reduce the parasitic inductance in the power unit packaging structure is a technical problem to be solved. It is found in the implementation process of the technical scheme of the present application that the commutation inductance inside the commutation unit is the main source of the parasitic inductance in the power unit packaging structure. This is mainly because the commutation loop connected between the upper bridge power chip and the lower bridge power chip is arranged in the same plane and has a large distance in the prior art, which will result in a large commutation inductance inside the power unit. The technical scheme provided in the embodiments of the present application provides a targeted solution to the above problems.

[0074] The embodiments of the present application provide a power unit, a three-phase full-bridge power module comprising the power unit, and a power supply system and a vehicle, to solve the above technical problems. The half-bridge unit in the power unit provided in the embodiments of the present application comprises a first substrate, and an upper bridge power chip and a lower bridge power chip formed on the first substrate, and the second pole of the upper bridge power chip and the first pole of the lower bridge power chip as the alternating current output end are electrically connected with the alternating current output conduction path of the power unit. The first pole of the upper bridge power chip and the second pole of the lower bridge power chip as the direct current input end are respectively electrically connected with two different conduction layers, the two different conduction layers are at least partially laminated, and the two different conduction layers are the direct current input conduction path of the power unit. The current flow directions in the two different conduction layers are opposite, have negative mutual inductance, form mutual inductance cancellation effect to reduce the total parasitic inductance in the power unit, and the two conduction layers in the embodiments of the present application are at least partially laminated to form a laminated structure, so that the distance between the conduction planes formed by the two conduction layers is extremely small, and the closer the distance, the better the mutual inductance cancellation effect, because the embodiments of the present application help to reduce the parasitic inductance inside the power unit.

[0075] Specifically, for the power unit provided in the embodiments of the present application, the two conductive layers serving as the direct current input conductive paths can be at least partially arranged in a stacked manner in various ways, for example, the two conductive layers are arranged on different surfaces of the first substrate, or more substrates are added, and the two conductive layers are arranged on different substrates.

[0076] In an embodiment, the power unit can be as shown in FIGS. 1-7, which includes a first substrate 2 and at least one half-bridge unit formed on the first substrate 2. For each half-bridge unit, it can include a first conductive layer 21 and a second conductive layer 22 formed on the upper surface of the first substrate 2; an upper bridge power chip 101 is arranged on the first conductive layer 21, and the first pole of the upper bridge power chip 101 is electrically connected to the first conductive layer 21; a lower bridge power chip 102 is arranged on the second conductive layer 22, and the second pole of the upper bridge power chip 101 and the first pole of the lower bridge power chip 102 are both electrically connected to the second conductive layer 22, and the second conductive layer 22 serves as an alternating current output conductive path of the power unit.

[0077] Further, the power unit further includes a second substrate 3 arranged on the first conductive layer 21, and the upper surface of the second substrate 3 is formed with a third conductive layer 31, and the third conductive layer 31 and the first conductive layer 21 are at least partially arranged in a stacked manner, and the second pole of the lower bridge power chip 102 is electrically connected to the third conductive layer 31.

[0078] In the above embodiments of the present application, the first conductive layer 21 and the third conductive layer 31 serve as the direct current input conductive paths of the power unit, and specifically, the first conductive layer 21 can serve as a direct current positive input conductive path, and the third conductive layer 31 can serve as a direct current negative input conductive path, or the first conductive layer 21 can serve as a direct current negative input conductive path, and the third conductive layer 31 can serve as a direct current positive input conductive path.

[0079] In the above embodiments of the present application, the third conductive layer 31 and the first conductive layer 21 are at least partially arranged in a stacked manner, forming a 3D multi-layer circuit structure, and the current directions of the direct current positive input conductive path and the direct current negative input conductive path are opposite, which can form good coupling to reduce inductance, and the above stacked structure makes the distance between the two smaller, further enhancing the mutual inductance cancellation effect, and achieving extremely low parasitic inductance in the power unit.

[0080] The upper bridge power chip 101 and the lower bridge power chip 102 in the above embodiments of the present application can be power chips of the same type and structure, or power chips of different types and structures. FIG. 1 is a structural schematic diagram of a power chip in an embodiment of the present application. As shown in FIG. 1, the power chip described above can be a power chip of vertical structure, which includes a first pole 11 on the bottom surface, a second pole 12 on the top surface, and a control pole 13. In FIG. 1, the top surface of the power chip is mainly shown, and the bottom surface is on the opposite surface. For some types of power chips, for example, in the case of MOSFET, the second pole 12 is a source pole. In this case, the second pole 12 can be divided into a power second pole 121 and a driving second pole 122, so as to be connected to an external power loop and a driving loop respectively, but the two are in communication inside the chip and have equal potentials. Or in some cases, the second pole 12 is not divided, and the second pole 12 can be connected to the power loop and the driving loop at the same time. The above two types of power chips are not different in function, and both can be applied to the technical solution of the present application. In the embodiments of the present application, the types of the power chip include but are not limited to MOSFET, IGBT, and other types of vertical structure chips.

[0081] Specifically, if the upper bridge power chip 101 and / or the lower bridge power chip 102 described above is a MOSFET, the first pole 11 is a drain pole, the second pole 12 is a source pole, and the control pole 13 is a gate pole. In this case, the first conductive layer 21 is a direct current positive pole input conductive path of the power unit, and the third conductive layer 31 is a direct current negative pole input conductive path of the power unit. Or, the first pole 11 is a source pole, the second pole 12 is a drain pole, and the control pole 13 is a gate pole. In this case, the first conductive layer 21 is a direct current negative pole input conductive path of the power unit, and the third conductive layer 31 is a direct current positive pole input conductive path of the power unit.

[0082] In some other cases, when the upper bridge power chip 101 and / or the lower bridge power chip 102 is an IGBT, the first pole 11 is a collector pole, the second pole 12 is an emitter pole, and the control pole 13 is a gate pole. In this case, the first conductive layer 21 is a direct current positive pole input conductive path of the power unit, and the third conductive layer 31 is a direct current negative pole input conductive path of the power unit. Or, the first pole 11 is an emitter pole, the second pole 12 is a collector pole, and the control pole 13 is a gate pole. In this case, the first conductive layer 21 is a direct current negative pole input conductive path of the power unit, and the third conductive layer 31 is a direct current positive pole input conductive path of the power unit.

[0083] In specific embodiments, there can be a case that both the upper bridge power chip 101 and the lower bridge power chip 102 are MOSFETs, or both are IGBTs, or the upper bridge power chip 101 is MOSFET and the lower bridge power chip 102 is IGBT, or the upper bridge power chip 101 is IGBT and the lower bridge power chip 102 is MOSFET, but the electrode types and connection relationships of the power chips are all referred to the above description.

[0084] In subsequent embodiments of the present application, MOSFETs are taken as an example to illustrate the upper bridge power chip 101 and the lower bridge power chip 102, and the first electrode is the drain electrode and the second electrode is the source electrode.

[0085] FIG. 2 is a schematic diagram of the cross-sectional structure of a power unit in an embodiment of the present application. As shown in FIG. 2, the power unit includes a first substrate 2 and a half-bridge unit on the first substrate. The half-bridge unit can specifically include a second substrate 3, an upper bridge power chip 101, and a lower bridge power chip 102. The second substrate 3 is arranged on the upper surface of the first substrate 2 to form a laminated substrate, and the upper bridge power chip 101 and the lower bridge power chip 102 are also arranged on the upper surface of the first substrate 2.

[0086] Specifically, the first substrate 2 can be a double-sided copper-clad ceramic substrate, such as an AMB substrate or a DBC substrate. The ceramic substrate is a first insulating substrate 20, which mainly functions as support, insulation, and heat conduction. The upper surface and the lower surface of the ceramic substrate can be provided with a copper layer. For example, a first copper layer is arranged on the upper surface, and a second copper layer is arranged on the lower surface. The first copper layer on the upper surface mainly functions as conduction and can be etched to obtain a desired pattern, such as the first conductive layer 21 and the second conductive layer 22 described above. The second copper layer mainly functions as heat conduction and can be connected to a heat dissipation substrate.

[0087] The second substrate 3 has less demand for heat conduction, and can have various structures. For example, the second substrate 3 can also be double-sided copper-clad, with a second insulating substrate 30 in the middle, such as a ceramic substrate, for example, an AMB substrate or a DBC substrate, or a thick copper PCB board or a FPC flexible substrate. In this case, the second substrate 3 can be connected to the first substrate 2 through a connecting layer 4, and the second insulating substrate 30 mainly functions as support and insulation. The second substrate 3 can also be provided with a third copper layer on the upper surface as the third conductive layer 31. In this case, the second insulating substrate 30 can additionally have adhesion capability, and the third copper layer is adhered to the upper surface of the first substrate 2 through the second insulating substrate 30.

[0088] In the embodiments of the present application, copper layers are used to prepare the conductive layers, and other materials with conductive properties can also be used to prepare the conductive layers.

[0089] In some embodiments, as shown in FIG. 2, the upper bridge power chip 101 and the lower bridge power chip 102 can also be connected to the upper surface of the first substrate 2 through a connection layer 4, which has good conductivity and heat conduction performance. Optionally, the connection layer 4 can be a sintered silver layer or a solder layer, and the corresponding connection process can be sintering or welding.

[0090] In the above embodiments of the present application, the first copper layer on the upper surface of the first substrate 2 and the third copper layer on the upper surface of the second substrate 3 constitute a laminated conductive plane. Generally speaking, for two adjacent conductors, when the current directions are opposite, there is a negative mutual inductance, forming a mutual inductance cancellation effect to reduce the total parasitic inductance in the power unit, and the closer the distance between the conductors, the better the mutual inductance cancellation effect. Therefore, compared with the traditional power unit, the first copper layer and the third copper layer in the embodiments of the present application have a laminated structure, so that the distance between the conductive planes formed by the two is extremely small, which helps to achieve extremely low parasitic inductance.

[0091] FIG. 3 is a top view of a power unit in an embodiment of the present application. As described in the above embodiments, when the first copper layer is provided on the upper surface of the first substrate 2, the first conductive layer 21 and the second conductive layer 22 can be obtained by etching process. In addition, a fourth conductive layer 23 can be formed on the upper surface of the first substrate 2, which is electrically connected to the gate electrode 13 of the upper bridge power chip 101; and a fifth conductive layer 26 can also be formed on the upper surface of the first substrate 2, which is electrically connected to the gate electrode 13 of the lower bridge power chip 102. For MOSFET, the gate electrode 13 is the gate electrode, and for IGBT, the gate electrode 13 is the gate electrode.

[0092] In some embodiments, as described above, when the second electrode 12 of the upper bridge power chip 101 and the lower bridge power chip 102 can be divided into a power second electrode 121 and a driving second electrode 122, a sixth conductive layer 24 and a seventh conductive layer 25 can also be formed on the upper surface of the first substrate 2. At this time, the power second electrode 121 of the upper bridge power chip 101 is electrically connected to the second conductive layer 22, and the driving second electrode 122 of the upper bridge power chip 102 is electrically connected to the sixth conductive layer 24, forming a Kelvin connection. At the same time, the power second electrode 121 of the lower bridge power chip 102 is electrically connected to the third conductive layer 31, and the driving second electrode 122 of the upper bridge power chip 102 is electrically connected to the seventh conductive layer 25, forming a Kelvin connection.

[0093] For the MOSFET, the above-mentioned driving second electrode 122 is a driving source electrode. In addition, as can be seen from FIG. 3, the number of the upper bridge power chip 101 and the lower bridge power chip 102 is at least two, and the above-mentioned at least two upper bridge power chips 101 and at least two lower bridge power chips 102 extend along the length direction of the first substrate 2, i.e. the A direction, while the respective conductive layers are arranged along the B direction. Among them, for the number of the upper bridge power chip 101 and the lower bridge power chip 102 in the half-bridge unit, more can also be more, and can continue to extend along the length direction A.

[0094] FIG. 4 is a schematic top view of the upper surface of the first substrate in the embodiment of the present application. As shown in FIG. 4, in the width direction of the first substrate, the fourth conductive layer 23, the first conductive layer 21, the second conductive layer 22 and the fifth conductive layer 26 of the half-bridge unit are sequentially arranged. In addition to the above, if necessary, a sixth conductive layer 24 can be formed between the fourth conductive layer 23 and the first conductive layer 21, and a seventh conductive layer 25 can be formed between the second conductive layer 22 and the fifth conductive layer 26.

[0095] In some cases, for example, when the upper bridge power chip 101 and the lower bridge power chip 102 do not separately provide the driving second electrode 122, the sixth conductive layer 24 and the seventh conductive layer 25 do not need to be formed on the upper surface of the first substrate 2. For the specific positions of the sixth conductive layer 24 and the seventh conductive layer 25, as well as the fourth conductive layer 23 and the fifth conductive layer 26, the sixth conductive layer 24 and the seventh conductive layer 25 can be arranged on the outer side.

[0096] In addition, in the embodiment of the present application, the second substrate 3 can be fixed to the first conductive layer 21 adjacent to the second conductive layer 22 on one side, and the upper bridge power chip 101 is located on the first conductive layer 21 away from the second conductive layer 22 on the other side.

[0097] FIGS. 5 and 6 are schematic connection diagrams of the power unit in the embodiment of the present application. As shown in FIGS. 5 and 6, and referring to the structure of the upper bridge power chip 101 and the lower bridge power chip 102 shown in FIG. 1, the second electrode 12 of the upper bridge power chip 101 can be electrically connected to the second conductive layer 22 through a first connecting line, and the first connecting line crosses the second substrate 3. Among them, the above-mentioned first connecting line can be the first bonding wire 51 in the example shown in FIG. 5, or the first copper sheet 62 in the embodiment shown in FIG. 6.

[0098] The second electrode 12 of the lower bridge power chip 102 can be electrically connected to the third conductive layer 31 through a second connecting line. Among them, the above-mentioned second connecting line can be the second bonding wire 52 in the example shown in FIG. 5, or the second copper sheet 61 in the embodiment shown in FIG. 6.

[0099] In addition, the control poles 13 of the upper bridge power chip 101 and the lower bridge power chip 102 can be respectively electrically connected with the fourth conductive layer 23 and the fifth conductive layer 26 through third connecting lines, and the third connecting lines can be third bonding wires 53. In the case where the second poles 12 of the upper bridge power chip 101 and the lower bridge power chip 102 are divided into power second poles 121 and driving second poles 122, the power second poles 121 can be respectively electrically connected with the second conductive layer 22 through first connecting lines and electrically connected with the third conductive layer 31 through second connecting lines, and the driving second poles 122 of the upper bridge power chip 101 and the lower bridge power chip 102 can be respectively electrically connected with the sixth conductive layer 24 and the seventh conductive layer 25 through fourth connecting lines, and the fourth connecting lines can be fourth bonding wires 54. In the embodiments shown in FIGS. 5 and 6, whether the first connecting lines and the second connecting lines are selected bonding wires or copper sheets, in the case of using copper sheets 61, the copper sheets 61 can be connected with the second poles 12 of the power chip, such as the power second poles 121, and the second conductive layer 22 and the third conductive layer 31 by welding or sintering. The third connecting lines and the fourth connecting lines can generally be implemented by bonding wires.

[0100] FIGS. 7 and 8 are structural schematic diagrams of connection terminals of a power unit in the embodiments of the present application. As shown in FIGS. 7 and 8, the embodiments of the present application provide corresponding connection terminals for each conductive layer of the power unit, such as a direct current positive input terminal 71 and a direct current negative input terminal 72, which can be respectively electrically connected with one of the first conductive layer 21 and the third conductive layer 31. For example, as shown in FIGS. 7 and 8, the direct current positive input terminal 71 is electrically connected with the first conductive layer 21, and the direct current negative input terminal 72 is electrically connected with the third conductive layer 31. At this time, the first poles 11 of the upper bridge power chip 101 and the lower bridge power chip 102 can be drains, the second poles 12 can be sources, the first conductive layer 21 can be a direct current positive circuit of the power unit, and the third conductive layer 31 can be a direct current negative input conductive path of the power unit. In other embodiments, the direct current positive input terminal 71 can be electrically connected with the third conductive layer 31, and the direct current negative input terminal 72 can be electrically connected with the first conductive layer 21.

[0101] Further, an alternating current output terminal 73 can be electrically connected with the second conductive layer 22, and the power unit can output alternating current through the alternating current output terminal 73.

[0102] Further, the power unit can further include:

[0103] a first upper bridge driving terminal 74 electrically connected with the fourth conductive layer 23;

[0104] The first lower bridge driving terminal 75 is electrically connected with the fifth conductive layer 26.

[0105] The second upper bridge driving terminal 76 is electrically connected with the sixth conductive layer 24.

[0106] The second lower bridge driving terminal 77 is electrically connected with the seventh conductive layer 25.

[0107] The terminals are set according to actual needs, including one or more of them. For specific settings, different embodiments are given in FIG. 7 and FIG. 8.

[0108] As shown in FIG. 7, the DC positive input terminal 71 and the DC negative input terminal 72 are arranged at the first end of the first substrate 2 along the length direction, and have a certain insulation distance, and are at least partially stacked, and the stacked arrangement can reduce the parasitic inductance introduced by the DC positive input terminal 71 and the DC negative input terminal 72; at the same time, the AC output terminal 73 is arranged at the second end of the first substrate along the length direction; the AC output terminal 73 is arranged at the other end of the length direction, which is convenient for the layout of the external circuit. For each driving terminal, it can be arranged at the first end or the second end.

[0109] In the embodiments of the present application, each terminal can be connected with the corresponding conductive layer by ultrasonic welding, welding and sintering.

[0110] In addition, as shown in FIG. 8, the DC positive input terminal 71, the DC negative input terminal 72 and the AC output terminal 73 can also be arranged at the middle section of the first substrate 2 along the length direction, and the DC positive input terminal 71 and the DC negative input terminal 72 are arranged adjacent to each other, which can reduce the parasitic inductance introduced by the terminals. And each of the above terminals is vertically upward. As shown in FIG. 8, the upper bridge power chip 101 is divided into two groups, which are respectively located on both sides of the DC positive input terminal 71, and the lower bridge power chip 102 is divided into two groups, which are respectively located on both sides of the AC output terminal 73. The terminal setting method can further reduce the parasitic inductance introduced by the conductors inside the power unit, and can effectively improve the dynamic current sharing.

[0111] Figure 9 is an equivalent circuit diagram of the power unit in the embodiment shown in Figure 7, in which the overall commutation loop is as follows: the positive pole of the DC current is connected to the first conductive layer 21 through the DC positive input terminal 71, the first conductive layer 21 is connected to the first pole of the upper bridge power chip 101, which is the drain, the power second pole of the upper bridge power chip 101, i.e. the power source, is connected to the second conductive layer 22, the second conductive layer 22 is connected to the first pole of the lower bridge power chip 102, the power second pole of the lower bridge power chip 102, i.e. the power source, is connected to the third conductive layer 31, the third conductive layer 31 is connected to the DC negative input terminal 72, and finally the DC negative input terminal 72 is connected to the negative pole of the DC power supply; the second conductive layer 22 is electrically connected to the AC output terminal 73, and then connected to the external output load.

[0112] For the power unit in the embodiment of the present application, the parasitic inductance is introduced by each conductor in the overall commutation loop, in which the inductance introduced by the first conductive layer 21 and the third conductive layer 31 usually accounts for the dominant part. As shown in Figure 9, the main inductance is segmented by taking the connection position of each power chip as a node, and the parasitic inductance introduced by the conductive layer between adjacent two power chips is marked, the self-inductance of each conductive layer on the first conductive layer 21 is L1, the self-inductance of each conductive layer on the third conductive layer 31 is L2, and the mutual inductance between them is M, the total inductance of the commutation loop acted on by the first conductive layer 21 and the third conductive layer 31 is L = L1 + L2 + 2*M.

[0113] The inductance L above is the main component of the inductance of the power unit, and is also the main factor causing dynamic uneven current, which needs to be reduced as much as possible. When the positive pole and the negative pole of the direct power supply are connected respectively, the mutual inductance M above is negative, so the total inductance of the loop can be reduced by strengthening the coupling between the first conductive layer 21 and the third conductive layer 31; the coupling coefficient is related to the distance between the two conductive layers, the smaller the distance, the greater the coupling coefficient, and the smaller the total parasitic inductance.

[0114] Compared with the planar structure of the traditional layout, the stacked structure provided in the embodiments of the present application can greatly reduce the overall distance between the first conductive layer 21 and the third conductive layer 31, so that the coupling coefficient is higher, and very low parasitic inductance can be achieved. Through simulation of the technical solutions provided in the embodiments of the present application, the simulation results show that the coupling coefficient between each first conductive layer 21 and the third conductive layer 31 in the embodiment shown in FIG. 7 reaches -0.85, while the coupling coefficient between the planar commutation loops in the traditional power unit is about -0.05 to -0.5. The inductance introduced by the commutation loop inside the power unit (including the AMB substrate, the connection lines between the power chips) shown in FIG. 7 is only about 1-2 nH, which is much lower than the 5-10 nH of the traditional power unit. Therefore, the technical solutions provided in the embodiments of the present application can effectively reduce the parasitic inductance introduced by the conductive path inside the power unit, and effectively improve the dynamic current sharing.

[0115] In the above embodiments of the present application, the first substrate can be expanded in the width direction to expand more half-bridge units, and the expanded half-bridge units can be arranged in parallel to form a half-bridge module with greater current-carrying capacity. The specific number of expansions can be set according to actual needs, for example, one more half-bridge unit can be expanded. FIG. 10 is a top view of another power unit in an embodiment of the present application. As shown in FIG. 10, the power unit includes a first substrate 2, and two half-bridge units formed on the first substrate 2, i.e., a first half-bridge unit 1001 and a second half-bridge unit 1002. The first half-bridge unit 1001 and the second half-bridge unit 1002 can have the structural features described in the above embodiments, respectively.

[0116] In addition, FIG. 11 is a top view of the first substrate in the embodiment shown in FIG. 10, FIG. 12 is a top view of the second substrate in the embodiment shown in FIG. 10, and FIG. 13 is a connection diagram of the power unit in the embodiment shown in FIG. 10. Referring to the above FIGS. 10-13, the conductive layers with close positions and the same functions in the first half-bridge unit 1001 and the second half-bridge unit 1002 on the first substrate 2 can be merged or connected, so as to optimize the layout, improve the integration and improve the performance, for example, the second conductive layers 22 of the first half-bridge unit 1001 and the second half-bridge unit 1002 are connected to each other to form an integrated structure. The first conductive layer 21 of the first half-bridge unit 1001 and the first conductive layer 21 of the second half-bridge unit 1002 can be arranged outside the integrated second conductive layer 22 in the width direction, respectively.

[0117] In some embodiments, as shown in FIG. 11, the connection structure can also be increased so that the first conductive layer 21 of the two half-bridge units is also electrically connected to form an integrated structure. Specifically, the electrical connection can be achieved by bonding wires, copper sheets, or the like, or as shown in FIG. 11, an interconnection conductive layer 29 is formed on the upper surface of the first substrate to communicate with the first conductive layers on both sides to form a whole first conductive layer.

[0118] On the basis of the above embodiments, at least one of the fourth conductive layer 23 electrically connected to the control electrode of the upper bridge power chip 101 of the two half-bridge units and the sixth conductive layer 24 electrically connected to the driving second electrode of the upper bridge power chip 101 of the two half-bridge units can be arranged outside the first conductive layer 21 in the width direction. At least one of the fifth conductive layer 25 electrically connected to the control electrode of the lower bridge power chip 102 of the two half-bridge units and the seventh conductive layer 26 electrically connected to the driving second electrode of the lower bridge power chip 102 of the two half-bridge units can be arranged in the hollow area 27 in the middle of the second conductive layer 22. The lower bridge power chip 102 of the first half-bridge unit 1001 and the lower bridge power chip 102 of the second half-bridge unit 1002 are arranged on both sides of the hollow area 27, respectively.

[0119] Specifically, referring to the embodiments shown in FIGS. 11 and 13, the hollow area 27 includes a plurality of sub-hollow areas, and the fifth conductive layer 25 and the seventh conductive layer 26 can include a plurality of sub-conductive layers arranged in the different sub-hollow areas, respectively. The plurality of sub-conductive layers of the fifth conductive layer 25 can be electrically connected to each other, and the plurality of sub-conductive layers of the seventh conductive layer 26 can also be electrically connected to each other. The control electrode of the lower bridge power chip 102 is connected to the adjacent sub-conductive layer of the fifth conductive layer 25, and the driving electrode of the lower bridge power chip 102 is connected to the adjacent sub-conductive layer of the seventh conductive layer 26.

[0120] In some embodiments, still referring to the embodiments shown in FIGS. 11 and 13, when the hollow area 27 is arranged, a conductive connection layer 28 can be arranged in the hollow area 27 at the edge of the first substrate 2. The fourth conductive layer 23 of the first half-bridge unit 1001 and the fourth conductive layer 23 of the second half-bridge unit 1002 are electrically connected by the conductive connection layer 28, and / or the sixth conductive layer 24 of the first half-bridge unit 1001 and the sixth conductive layer 24 of the second half-bridge unit 1002 can also be electrically connected by the conductive connection layer 28.

[0121] As shown in FIG. 13, which is an example of electrical connection by bonding wires. In which the second poles of the upper bridge power chips 101 of the two half-bridge units can be electrically connected to the second conductive layer 22 by the first bonding wires 51, and the first bonding wires 51 cross the second substrate 3. In some embodiments, the second poles 12 of the lower bridge power chips 102 of the two half-bridge units can be electrically connected to the third conductive layer 31 by the second bonding wires 52. The first bonding wires 51 and the second bonding wires 52 described above can both be replaced by copper sheets.

[0122] In addition, the control poles 13 of the upper bridge power chips 101 and the lower bridge power chips 102 can be respectively electrically connected to the fourth conductive layer 23 and the fifth conductive layer 26 described above by the third bonding wires 53 respectively. And in the case where the second poles 12 of the upper bridge power chips 101 and the lower bridge power chips 102 described above can be divided into power second poles and driving second poles, the power second poles 121 described above can be respectively electrically connected to the second conductive layer 22 by the first bonding wires 51, and electrically connected to the third conductive layer 31 by the second bonding wires 52; while the driving second poles 122 of the upper bridge power chips 101 and the lower bridge power chips 102 can be respectively electrically connected to the sixth conductive layer 24 and the seventh conductive layer 25 by the fourth bonding wires 54.

[0123] And for the two fourth conductive layers 23 arranged outside the second conductive layer 22, they can be respectively connected to the conductive connection layer 28 of the hollow area by the third bonding wires 53, and for the two sixth conductive layers 24 arranged outside the second conductive layer 22, they can be connected to the conductive connection layer 28 of the hollow area by the fourth bonding wires 54.

[0124] FIG. 14 is a structure diagram of the connection terminal of the power unit in the embodiment of the application, as shown in FIG. 14, in which the direct current positive connection terminal 71 is electrically connected to the first conductive layer 21, the direct current negative connection terminal 72 is electrically connected to the third conductive layer 31, and the direct current positive connection terminal 71 and the direct current negative connection terminal 72 are both arranged at the first end of the first substrate, and are at least partially stacked, which can effectively reduce the parasitic inductance. In addition, the alternating current output terminal 73 can be arranged at the second end of the first substrate, and further comprising:

[0125] The first upper bridge driving terminal 74 is electrically connected to the fourth conductive layer 23 described above;

[0126] The first lower bridge driving terminal 75 is electrically connected to the fifth conductive layer 26 described above;

[0127] The second upper bridge driving terminal 76 is electrically connected to the sixth conductive layer 24 described above;

[0128] The second lower bridge driving terminal 77 is electrically connected to the seventh conductive layer 25 described above.

[0129] In the embodiments of the present application, the number of required half-bridge units can be selected according to the power requirement to obtain different power ranges, which can be extended in structure according to the manner described in the above embodiments to be applicable to an extremely wide power range.

[0130] The three-phase full-bridge power module according to the embodiments of the present application also includes three power units shown in any one of FIGS. 1-14, a heat sink 8, and an outer shell 9. The lower surfaces of the first substrates 2 in the three power units are fixed on the heat sink 8, and the outer shell 9 covers the three power units. Specifically, the outer shell 9 can be provided with openings to expose at least one of the DC positive input terminals, the DC negative input terminals, the AC output terminals, the first upper bridge driving terminals, the second upper bridge driving terminals, the first lower bridge driving terminals, and the second lower bridge driving terminals of the power units.

[0131] The heat sink 8 can play a role in mechanical fixation and heat conduction, and as described in the above embodiments, the first substrate 2 can be provided with copper layers on the upper and lower surfaces. The copper layer on the upper surface has been etched into the conductive layers in the power unit, while the copper layer on the lower surface mainly plays a role in heat conduction and can be connected to the heat sink 8 to play a good role in heat dissipation. In addition, the outer shell 9 mainly plays a role in protection and insulation.

[0132] The three-phase full-bridge power module according to the embodiments of the present application includes the power unit shown in any one of FIGS. 1-14. In the power unit, the first conductive layer 21 and the third conductive layer 31 are stacked, and the first conductive layer 21 and the third conductive layer 31 are connected to the DC positive input terminal and the DC negative input terminal, respectively, so that the current directions of the first conductive layer 21 and the third conductive layer 31 are opposite, resulting in a negative mutual inductance, a mutual inductance cancellation effect, a reduction in the total parasitic inductance in the power unit, and an effective improvement in dynamic current sharing.

[0133] FIG. 17 is a structural schematic diagram of a power supply system according to an embodiment of the present application. As shown in FIG. 17, the power supply system includes a battery 171 and the three-phase full-bridge power module 172. The battery 171 can output DC power, which can be converted into AC power by the three-phase full-bridge power module 172 and further output to an electrical device that needs to operate using AC power. The power supply system according to the embodiments of the present application has the technical features and effects described in the above embodiments, and will not be described herein.

[0134] Fig. 18 is a schematic view of a vehicle according to an embodiment of the present application. As shown in Fig. 18, the vehicle includes the power supply system 18 described above, which can supply power to various electrical devices on the vehicle. For example, for some electrical devices using alternating current, the three-phase full-bridge power module in the power supply system 18 can be used to convert direct current into alternating current. The embodiment has the corresponding technical features and effects described in the above embodiments, and will not be described here. The structure of the vehicle can also refer to Fig. 19.

[0135] The terms "first", "second", and the like in the description and claims of the present application are used to distinguish similar objects, and are not used to describe a particular order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally a class, not limited to the number of objects, for example, the first object can be one or more. In addition, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0136] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0137] In the description of the present application, "first feature" and "second feature" can include one or more features.

[0138] In the description of the present application, "a plurality of" means two or more.

[0139] In the description of the present application, "above" or "below" the first feature of the second feature can include direct contact between the first and second features, or indirect contact between the first and second features through another feature therebetween.

[0140] In the description of the present application, "above", "above" and "above" of the first feature of the second feature include the first feature directly above and obliquely above the second feature, or only indicate that the first feature is higher than the second feature in horizontal height.

[0141] In the description of the application, reference has been made to descriptive terms such as "one embodiment", "some embodiments", "an embodiment", "example", "specific example" or "some examples" etc. It is emphasized that each of these terms refers to a specific feature, structure, material or characteristic described in connection with a particular embodiment or example. The descriptive terms are not necessarily referring to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0142] While the embodiments of the application have been shown and described, it is to be understood that the embodiments described are only by way of example and that various changes, modifications, substitutions and alterations can be made thereto without departing from the spirit and scope of the application as set forth in the claims and their equivalents.

Claims

1. A power unit, wherein, The application relates to a power unit, comprising a first substrate (2) and at least one half-bridge unit formed on the first substrate (2), wherein the half-bridge unit comprises an upper bridge power chip (101) and a lower bridge power chip (102), the second pole (12) of the upper bridge power chip (101) and the first pole (11) of the lower bridge power chip (102) are electrically connected with an alternating current output conduction path of the power unit, the first pole (11) of the upper bridge power chip (101) and the second pole (12) of the lower bridge power chip (102) are respectively electrically connected with two different conduction layers, the two different conduction layers are at least partially laminated, and the two different conduction layers are respectively direct current input conduction paths of the power unit.

2. The power unit of claim 1, wherein, The upper surface of the first substrate (2) is formed with a first conduction layer (21) and a second conduction layer (22); The upper bridge power chip (101) is arranged on the first conduction layer (21), and the first pole (11) of the upper bridge power chip (101) is electrically connected with the first conduction layer (21); The lower bridge power chip (102) is arranged on the second conduction layer (22), the second pole (12) of the upper bridge power chip (101) and the first pole (11) of the lower bridge power chip (102) are electrically connected with the second conduction layer (22), and the second conduction layer (22) is an alternating current output conduction path of the power unit; The power unit further comprises: The second substrate (3) is arranged on the first conduction layer (21), and the upper surface of the second substrate (3) is formed with a third conduction layer (31), the third conduction layer (31) and the first conduction layer (21) are at least partially laminated, and the second pole (12) of the lower bridge power chip (102) is electrically connected with the third conduction layer (31); The first conduction layer (21) and the third conduction layer (31) are direct current input conduction paths of the power unit.

3. The power unit of claim 2, wherein, The upper bridge power chip (101) or the lower bridge power chip (102) is a MOSFET, or the upper bridge power chip (101) and the lower bridge power chip (102) are MOSFETs, the first pole (11) is a drain, the second pole (12) is a source, the first conduction layer (21) is a direct current positive input conduction path of the power unit, and the third conduction layer (31) is a direct current negative input conduction path of the power unit.

4. The power unit of claim 2, wherein, The upper bridge power chip (101) or the lower bridge power chip (102) is an IGBT, or the upper bridge power chip (101) and the lower bridge power chip (102) are IGBTs, the first pole (11) is a collector, the second pole (12) is an emitter, the first conduction layer (21) is a direct current positive input conduction path of the power unit, and the third conduction layer (31) is a direct current negative input conduction path of the power unit.

5. The power unit according to any of claims 2-4, wherein, A fourth conductive layer (23) is further formed on the upper surface of the first substrate (2), and the fourth conductive layer (23) is electrically connected with the control electrode (13) of the upper bridge power chip (101). A fifth conductive layer (26) is further formed on the upper surface of the first substrate (2), and the fifth conductive layer (26) is electrically connected with the control electrode (13) of the lower bridge power chip (102).

6. The power unit of claim 5, wherein, The number of the upper bridge power chip (101) and the lower bridge power chip (102) is at least two, and the at least two upper bridge power chips (101) and the at least two lower bridge power chips (102) extend along the length direction of the first substrate (2), and the fourth conductive layer (23), the first conductive layer (21), the second conductive layer (22) and the fifth conductive layer (26) of the half-bridge unit are sequentially arranged in the width direction of the first substrate (2).

7. The power unit of claim 5, wherein, The second electrode (12) includes a power second electrode (121) and a driving second electrode (122), and the upper surface of the first substrate (2) further forms a sixth conductive layer (24) and a seventh conductive layer (25). The power second electrode (121) of the upper bridge power chip (101) is electrically connected with the second conductive layer (22), and the driving second electrode (122) of the upper bridge power chip (101) is electrically connected with the sixth conductive layer (24), thereby forming a Kelvin connection. The power second electrode (121) of the lower bridge power chip (102) is electrically connected with the third conductive layer (31), and the driving second electrode (122) of the lower bridge power chip (102) is electrically connected with the seventh conductive layer (25), thereby forming a Kelvin connection.

8. The power unit of claim 7, wherein, The upper bridge power chip (101), the lower bridge power chip (102) and the second substrate (3) are fixed on the upper surface of the first substrate (2) through a connecting layer.

9. The power unit of claim 8, wherein, The second substrate (3) is fixed on one side of the first conductive layer (21) adjacent to the second conductive layer (22) through a connecting layer, and the upper bridge power chip (101) is located on the other side of the first conductive layer (21) away from the second conductive layer (22).

10. The power unit of claim 9, wherein, The second electrode (12) of the upper bridge power chip (101) is electrically connected with the second conductive layer (22) through a first connecting line, and the first connecting line crosses the second substrate (3). The second electrode (12) of the lower bridge power chip (102) is electrically connected with the third conductive layer (31) through a second connecting line.

11. The power unit of claim 10, wherein, The first connecting line is one of a bonding wire or a copper sheet, and the second connecting line is one of a bonding wire or a copper sheet.

12. The power unit of claim 7, wherein, The first substrate (2) includes a first insulating substrate (20), a first copper layer on the upper surface of the first insulating substrate (20) and a second copper layer on the lower surface of the first insulating substrate (20), and at least one of the first conductive layer (21), the second conductive layer (22), the fourth conductive layer (23), the fifth conductive layer (26), the sixth conductive layer (24) and the seventh conductive layer (25) is obtained by etching the first copper layer. The second substrate (3) comprises a second insulating substrate (30), and a third copper layer on the upper surface of the second insulating substrate (30), which serves as the third conductive layer (31).

13. The power unit according to claim 7, further comprising at least one of: a direct current positive input terminal (71) and a direct current negative input terminal (72) electrically connected with one of the first conductive layer (21) and the third conductive layer (31) respectively; an alternating current output terminal (73) electrically connected with the second conductive layer (22); a first upper bridge driving terminal (74) electrically connected with the fourth conductive layer (23); a first lower bridge driving terminal (75) electrically connected with the fifth conductive layer (26); a second upper bridge driving terminal (76) electrically connected with the sixth conductive layer (24); and a second lower bridge driving terminal (77) electrically connected with the seventh conductive layer (25). The direct current positive input terminal (71) and the direct current negative input terminal (72) are arranged at a first end of the first substrate (2) in the length direction, and are at least partially stacked. The alternating current output terminal (73) is arranged at a second end of the first substrate (2) in the length direction. The direct current positive input terminal (71), the direct current negative input terminal (72) and the alternating current output terminal (73) are arranged at a middle section of the first substrate (2) in the length direction, and the direct current positive input terminal (71) and the direct current negative input terminal (72) are arranged adjacent to each other.

16. The power unit according to claim 13, wherein two half-bridge units are formed on the first substrate (2), which are a first half-bridge unit (1001) and a second half-bridge unit (1002) respectively. The second conductive layer (22) of the first half-bridge unit (1001) and the second conductive layer (22) of the second half-bridge unit (1002) are integrally arranged, and the first conductive layer (21) of the first half-bridge unit (1001) and the first conductive layer (21) of the second half-bridge unit (1002) are arranged on the outer sides of the integrally arranged second conductive layer (22) in the width direction respectively. The first conductive layer (21) of the first half-bridge unit (1001) and the first conductive layer (21) of the second half-bridge unit (1002) are electrically connected through an interconnection conductive layer (29).

14. The power unit of claim 13, wherein, The fourth conductive layer (23) and the sixth conductive layer (24) are arranged on the outer sides of the first conductive layer (21) in the width direction. The fifth conductive layer (26) and the seventh conductive layer (25) are arranged in the hollowed-out area (27) of the middle part of the second conductive layer (22), and the lower bridge power chip (102) of the first half-bridge unit (1001) and the lower bridge power chip (102) of the second half-bridge unit (1002) are arranged on the two sides of the hollowed-out area (27) respectively.

15. The power unit of claim 13, wherein, ​ ​ ​ 17. The power unit of claim 16, wherein, ​ 18. The power unit of claim 17, wherein, ​ ​ 19. The power unit of claim 18, wherein, The fifth conductive layer (26) and the seventh conductive layer (25) comprise a plurality of sub-conductive layers respectively arranged in the sub-hollowed areas, the plurality of sub-conductive layers of the fifth conductive layer (26) are electrically connected to each other, the plurality of sub-conductive layers of the seventh conductive layer (25) are electrically connected to each other, and the control electrode (13) of the lower bridge power chip (102) is respectively connected to the adjacent sub-conductive layer of the fifth conductive layer (26), and the driving second electrode (122) of the lower bridge power chip (102) is respectively connected to the adjacent sub-conductive layer of the seventh conductive layer (25).

20. The power unit of claim 19, wherein, The conductive connection layer (28) is arranged in the hollowed area (27) at the edge (20) of the first substrate (2), the fourth conductive layer (23) of the first half-bridge unit (1001) and the fourth conductive layer (23) of the second half-bridge unit (1002) are electrically connected through the conductive connection layer (28), or the sixth conductive layer (24) of the first half-bridge unit (1001) and the sixth conductive layer (24) of the second half-bridge unit (1002) are electrically connected through the conductive connection layer (28), or the fourth conductive layer (23) of the first half-bridge unit (1001) and the fourth conductive layer (23) of the second half-bridge unit (1002) are electrically connected through the conductive connection layer (28), and the sixth conductive layer (24) of the first half-bridge unit (1001) and the sixth conductive layer (24) of the second half-bridge unit (1002) are electrically connected through the conductive connection layer (28).

21. A three-phase full-bridge power module, wherein, The three power units as claimed in any one of claims 1-20, a heat sink (8) and a housing (9) are included. The lower surface of the first substrate (2) in the three power units is fixed on the heat sink (8), and the housing (9) covers the three power units.

22. A power supply system, wherein, The three-phase full-bridge power module (172) as claimed in claim 21 and a battery (171) are included.

23. A vehicle, wherein, The power supply system (18) as claimed in claim 22 is included. The power supply system (18) as claimed in claim 22 is included.

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