Storage device

Abstract

Provided is a storage device with a novel configuration. A sense circuit, a first sense amplifier section, a second sense amplifier section, a word-line–side drive circuit section, a sense amplifier drive circuit section, and a controller section are included. A sense amplifier drive block control signal is a signal for setting a state in which a plurality of sense amplifier drive blocks control sense amplifier blocks. A word-line–side drive block control signal is a signal for setting a state in which a plurality of word-line–side drive blocks output a word signal to a memory cell connected to the first sense amplifier blocks and output a sense circuit control signal to the sense circuit connected to the memory cell. The memory cell and the sense circuit each have a first transistor. The first transistor has a first semiconductor layer having an oxide semiconductor in a channel formation region.

Description

storage device

[0001] This specification describes storage devices and the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, an imaging device, a display device, a light-emitting device, a power storage device, a memory device, a display system, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, efforts to combat global warming have become increasingly important. Energy consumption continues to increase, and carbon dioxide emissions, one of the causes of global warming, have yet to be reduced. Simply reducing energy consumption may actually result in a loss of convenience. To reduce energy consumption without sacrificing convenience, low-power consumption technologies are becoming extremely important.

[0004] As a technology for reducing power consumption, for example, a memory device that stores data using a transistor including an oxide semiconductor (also referred to as an OS transistor) is known (see, for example, Patent Document 1). The memory device described in Patent Document 1 can reduce the frequency of refresh operations and achieve low power consumption by utilizing the characteristics of an OS transistor, which flows very little current in an off state, for data storage.

[0005] US Patent Publication No. 2015 / 0294710

[0006] Takashi Koida, "High Mobility Transparent Conductive Film," National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Report 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0007] In the memory device described in Patent Document 1, a memory cell using an OS transistor requires a longer time for writing and reading than a transistor using silicon (Si transistor) such as a DRAM. In order to increase the memory bandwidth in this configuration, the time required for writing and reading can be shortened by increasing the number of activated sense amplifiers (sense amplifiers that enable writing and reading).

[0008] However, as the number of simultaneously activated sense amplifiers increases, the amount of current flowing through the memory device increases, which may result in a voltage drop in the power supply lines that supply power to the sense amplifiers.In addition, when data read by activated sense amplifiers is output to an external device, it may be necessary to output the data as data according to the external bus width.

[0009] In a memory cell structure in which element layers each containing memory cells are stacked, reducing the height of each element layer is effective in increasing the number of memory cells per unit area. Therefore, it is preferable that the capacitors in the memory cells be parallel plate or shallow trench types. In this case, it may be difficult for the sense amplifier to read the potential based on the charge stored in the capacitor.

[0010] An object of one embodiment of the present invention is to provide a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a miniaturized memory device. Another object of one embodiment of the present invention is to provide a memory device in which the time required for writing and reading can be shortened. Another object of one embodiment of the present invention is to provide a memory device in which a voltage drop in a power supply line that supplies power to a sense amplifier can be suppressed. Another object of one embodiment of the present invention is to provide a memory device that can output data according to an external bus width. Another object of one embodiment of the present invention is to provide a memory device with excellent data reliability. Another object of one embodiment of the present invention is to provide a memory device with a novel structure.

[0011] Note that one embodiment of the present invention does not necessarily have to solve all of the above problems, but it is sufficient that it can solve at least one of the problems. Furthermore, the description of the above problems does not preclude the existence of other problems. Problems other than these will become apparent from the description in the specification, claims, drawings, etc., and other problems can be extracted from the description in the specification, claims, drawings, etc.

[0012] one embodiment of the present invention is a memory device including: a sense circuit electrically connected to a memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via a second bit line; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier block via a third bit line; a word line side driver circuit unit having a plurality of word line side driver blocks that output word signals to memory cells and sense circuit control signals to the sense circuit; a sense amplifier driver circuit unit having a plurality of sense amplifier drive blocks that drive the first sense amplifier block; and a controller unit that outputs sense amplifier drive block control signals that control the sense amplifier drive blocks and word line side driver block control signals that control the word line side driver blocks;

[0013] One aspect of the present invention is a memory cell array including: a sense circuit electrically connected to a memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via a second bit line; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier blocks via a third bit line; a word line side driver circuit unit having a plurality of word line side driver blocks that output word signals to the memory cells and sense circuit control signals to the sense circuit; a sense amplifier driver circuit unit having a plurality of sense amplifier driver blocks that drive the first sense amplifier blocks; a sense amplifier driver block control signal that controls the sense amplifier driver block; and a controller unit that outputs a word line side driver block control signal and a second sense amplifier control signal that controls a second sense amplifier block, wherein the sense amplifier drive block control signal is a signal that causes a state in which a plurality of sense amplifier drive blocks control a first sense amplifier block, the word line side driver block control signal is a signal that causes a state in which a plurality of word line side driver blocks output word signals to memory cells connected to the first sense amplifier block and output sense circuit control signals to sense circuits connected to the memory cells, and the second sense amplifier control signal is a signal that causes a state in which one second sense amplifier block accesses data read out to the first sense amplifier block via a third bit line.

[0014] one embodiment of the present invention is a memory device including: a sense circuit electrically connected to a memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via a second bit line; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier block via a third bit line; a word line side driver circuit unit having a plurality of word line side driver blocks that output word signals to memory cells and sense circuit control signals to the sense circuit; a sense amplifier drive circuit unit having a plurality of sense amplifier drive blocks that drive the first sense amplifier block; and a controller unit that outputs sense amplifier drive block control signals that control the sense amplifier drive blocks and word line side driver block control signals that control the word line side driver blocks,

[0015] In one embodiment of the present invention, the memory cell and the sense circuit preferably each include a first transistor, the first transistor including a first semiconductor layer, and the first semiconductor layer including an oxide semiconductor in a channel formation region.

[0016] In one aspect of the present invention, a memory device preferably has a switching circuit electrically connected to a sense circuit and a first sense amplifier block, the memory cell has a first transistor, the sense circuit and the switching circuit each have a second transistor, the first transistor has a first semiconductor layer, the second transistor has a second semiconductor layer, the first semiconductor layer has an oxide semiconductor in a channel formation region, and the second semiconductor layer has indium oxide in a channel formation region.

[0017] In one aspect of the present invention, the controller unit preferably has a function of outputting a second sense amplifier control signal for controlling the second sense amplifier block, and the second sense amplifier control signal is a signal that puts one second sense amplifier block into a state in which it can access data read out to the first sense amplifier block via a third bit line.

[0018] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0019] One embodiment of the present invention can provide a memory device with low power consumption. Another embodiment of the present invention can provide a miniaturized memory device. Another embodiment of the present invention can provide a memory device in which the time required for writing and reading can be shortened. Another embodiment of the present invention can provide a memory device in which a voltage drop in a power supply line that supplies power to a sense amplifier can be suppressed. Another embodiment of the present invention can provide a memory device that can output data according to an external bus width. Another embodiment of the present invention can provide a memory device with excellent data reliability. Another embodiment of the present invention can provide a memory device with a novel structure.

[0020] The description of multiple effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the exemplified effects. Furthermore, problems, effects, and novel features of one embodiment of the present invention other than those described above will become apparent from the description and drawings of this specification.

[0021] FIG. 1 is a diagram illustrating an example of the configuration of a storage device. FIG. 2 is a diagram illustrating an example of the configuration of a storage device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a storage device. FIGS. 4A and 4B are diagrams illustrating an example of the configuration of a storage device. FIGS. 5A and 5B are diagrams illustrating an example of the configuration of a storage device. FIGS. 6A to 6C are diagrams illustrating an example of the configuration of a storage device. FIGS. 7A and 7B are diagrams illustrating an example of the configuration of a storage device. FIGS. 8A and 8B are diagrams illustrating an example of the configuration of a storage device. FIGS. 9A and 9B are diagrams illustrating an example of the configuration of a storage device. FIGS. 10A and 10B are diagrams illustrating an example of the configuration of a storage device. FIGS. 11A and 11B are diagrams illustrating an example of the configuration of a storage device. FIGS. 12A to 12C are diagrams illustrating an example of the configuration of a storage device. FIGS. 13A to 13G are diagrams illustrating an example of the configuration of a storage device. FIGS. 14A and 14B are diagrams illustrating an example of the configuration of a storage device. FIGS. 15A to 15C are diagrams illustrating an example of the configuration of a storage device. FIGS. 16A to 16C are diagrams illustrating an example of the configuration of a storage device. FIG. 17 is a diagram illustrating an example of the configuration of a memory device. FIG. 18 is a diagram illustrating an example of the configuration of a memory device. FIGS. 19A and 19B are diagrams illustrating an example of the configuration of a memory device. FIG. 20 is a diagram illustrating an example of the configuration of a memory device. FIG. 21 is a diagram illustrating an example of the configuration of a memory device. FIGS. 22A and 22B are cross-sectional views illustrating an example of the configuration of a transistor included in a memory device. FIG. 23A is a plan view illustrating an example of the configuration of a transistor included in a memory device. FIGS. 23B to 23D are cross-sectional views illustrating an example of the configuration of a transistor included in a memory device. FIG. 24A is a plan view illustrating an example of the configuration of a transistor included in a memory device. FIGS. 24B to 24D are cross-sectional views illustrating an example of the configuration of a transistor included in a memory device. FIG. 25A is a diagram illustrating an example of the configuration of a transistor included in a memory device. FIG. 25B is a diagram illustrating an equivalent circuit of a memory cell. FIG. 26 is a cross-sectional view illustrating an example of the configuration of a memory device. FIG. 27A is a diagram illustrating an example of the configuration of a transistor included in a memory device. FIG. 27B is a diagram illustrating an equivalent circuit of a memory cell.28A and 28B are plan views showing an example of the configuration of a transistor included in a memory device, and FIG. 28C is a cross-sectional view showing an example of the configuration of a transistor included in a memory device. FIG. 29A is a cross-sectional view showing an example of the configuration of a transistor included in a memory device, and FIG. 29B is a plan view showing an example of the configuration of a transistor included in a memory device. FIGS. 30A and 30B are diagrams explaining the carrier concentration dependence of Hall mobility. FIG. 30C is a cross-sectional view explaining an indium oxide film. FIG. 31 is a diagram showing various memory devices by layer. FIGS. 32A and 32B are diagrams showing an example of an electronic component. FIGS. 33A to 33D are diagrams explaining an example of an electronic component. FIGS. 34A and 34B are diagrams showing an example of an electronic device. FIGS. 35A to 35C are diagrams showing an example of an electronic device. FIG. 36 is a diagram showing an example of a mainframe computer.

[0022] The following describes an embodiment of the present invention. However, one embodiment of the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be interpreted as being limited to the description of the embodiment shown below.

[0023] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0024] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated description thereof may be omitted.

[0025] In this specification, for example, the power supply potential VDD may be abbreviated as potential VDD, VDD, etc. This also applies to other components (for example, signals, voltages, circuits, elements, electrodes, wiring, etc.).

[0026] Furthermore, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "_2", "[n]", or "[m, n]" may be added to the reference numeral. For example, the second wiring GL is described as wiring GL[2].

[0027] Embodiment 1 A structure, operation, and the like of a storage device according to one embodiment of the present invention will be described.

[0028] In this specification and the like, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0029] (Configuration Example of Storage Device 100) FIG. 1 is a schematic diagram illustrating a storage device 100 according to one embodiment of the present invention.

[0030] The memory device 100 includes an element layer 10, an element layer 20 provided to overlap the element layer 10, and an element layer 40 provided to overlap the element layer 20. In the schematic diagram shown in Figure 1, the element layer 10, the element layer 20, and the element layer 40 are shown separated from each other to make it easier to understand the arrangement of each element constituting the memory device 100. Note that the element layer is a layer in which a semiconductor element such as a transistor or a capacitor is provided.

[0031] The element layer 10 has a global sense amplifier section 11 in which multiple global sense amplifier blocks GSAB are arranged, as well as a data sense amplifier section 12, a global sense amplifier drive circuit section 13, a column line drive circuit section 14, a word line side drive circuit section 15, and a controller section 16. The global sense amplifier section 11 may be referred to as a first sense amplifier section. The global sense amplifier block GSAB may be referred to as a first sense amplifier block. The global sense amplifier drive circuit section 13 may be referred to as a first sense amplifier drive circuit section. The data sense amplifier section 12 may be referred to as a second sense amplifier section.

[0032] 1, in order to explain the arrangement of each component, the Z-axis direction is defined as a direction perpendicular or approximately perpendicular to the surface of the element layer 10 (for example, a surface on which an interlayer insulating layer is provided). For ease of understanding, the Z-axis direction may be referred to as a direction perpendicular to the surface of the element layer 10 in the specification. Note that "approximately perpendicular" refers to a state in which the elements are arranged at an angle of 85 degrees or more and 95 degrees or less.

[0033] In this specification and drawings, the X direction, Y direction, and Z direction may be defined to explain the arrangement of each element. For example, in the schematic diagram shown in Figure 1, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the storage device 100. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other.

[0034] The element layer 10 has a transistor having silicon (Si transistor) in a semiconductor layer having a channel formation region. The element layer 10 is an element layer in which a semiconductor layer having a channel formation region is provided in a silicon substrate, or an element layer in which a silicon semiconductor layer having a channel formation region is bonded to a silicon substrate.

[0035] Although the substrate provided in the element layer 10 is described as a silicon substrate, this embodiment is not limited to this. The silicon substrate refers to a substrate using silicon as a semiconductor material, for example, a single-crystal silicon substrate. The substrate is not limited to silicon, and may be made of materials such as Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), and GaAlAs (gallium aluminum arsenide).

[0036] The Si transistors included in the element layer 10 are made of highly crystalline silicon, such as monocrystalline silicon or polycrystalline silicon. The highly crystalline silicon in the element layer 10 allows for high field-effect mobility and faster operation. Therefore, the element layer 10 can be provided with a global sense amplifier unit 11, a data sense amplifier unit 12, a global sense amplifier driver circuit unit 13, a column line driver circuit unit 14, a word line driver circuit unit 15, and a controller unit 16, all integrated together.

[0037] The element layer 20 includes a sense circuit portion 22 having a plurality of sense circuits 21. The element layer 20 includes a transistor including an oxide semiconductor in a semiconductor layer having a channel formation region (OS transistor).

[0038] The sense circuit 21 is a sense circuit having an OS transistor. The sense circuit 21 has a function of converting a change in the potential of a bit line connected to a selected memory cell 41 into the potential of a bit line connected to a global sense amplifier block GSAB and reading it out. The sense circuit 21 also has a function of writing the potential of the bit line connected to the global sense amplifier block GSAB to the selected memory cell 41 via the sense circuit 21. The sense circuit 21 is sometimes called a local sense amplifier.

[0039] As the oxide semiconductor used in the OS transistor, for example, an In—Ga—Zn oxide or an indium oxide (In oxide or indium oxide) can be used. Examples of the atomic ratio of metal elements in In—Ga—Zn oxide include a composition in which In:Ga:Zn=1:1:1 or thereabouts, a composition in which In:Ga:Zn=1:1:1.2 or thereabouts, a composition in which In:Ga:Zn=2:1:3 or thereabouts, a composition in which In:Ga:Zn=3:1:2 or thereabouts, a composition in which In:Ga:Zn=4:2:3 or thereabouts, a composition in which In:Ga:Zn=4:2:4.1 or thereabouts, a composition in which In:Ga:Zn=5:1:3 or thereabouts, a composition in which In:Ga:Zn=5:1:6 or thereabouts, a composition in which In:Ga:Zn=5:1:7 or thereabouts, a composition in which In:Ga:Zn=5:1:8 or thereabouts, a composition in which In:Ga:Zn=6:1:6 or thereabouts, and a composition in which In:Ga:Zn=5:2:5 or thereabouts.

[0040] The element layer 20 including an OS transistor can be stacked over the element layer 10. By providing the element layer 20 over the element layer 10, the transistor density per unit area can be increased.

[0041] The element layer 40 includes a memory cell array 42 including a plurality of memory cells 41. The element layer 40 includes an OS transistor. The memory cell 41 is a memory cell including an OS transistor. A storage device including memory cells including OS transistors may also be referred to as an "OS memory."

[0042] The element layer 40 including an OS transistor can be stacked over the element layer 20. By providing the element layer 40 over the element layer 20, the transistor density per unit area can be increased.

[0043] FIG. 2 is a block diagram for explaining the global sense amplifier section 11 in which the global sense amplifier block GSAB is arranged, the data sense amplifier section 12, the global sense amplifier drive circuit section 13, the column line drive circuit section 14, the word line side drive circuit section 15, and the controller section 16.

[0044] A plurality of global sense amplifier blocks GSAB are arranged in the column direction in the global sense amplifier unit 11. Each global sense amplifier block GSAB has a plurality of global sense amplifiers GSA. The global sense amplifiers GSA may be referred to as first sense amplifiers.

[0045] The global sense amplifier GSA is connected to the memory cell 41 via a bit line GBL, a sense circuit 21, and a bit line LBL, which are arranged in the Z direction. The global sense amplifier GSA is also connected to the memory cell 41 via an inverted bit line GBLB, a sense circuit 21B, and an inverted bit line LBLB, which are also arranged in the Z direction.

[0046] The sense circuit 21 converts fluctuations in the potential of the bit line LBL, which changes depending on the charge held in the selected memory cell 41, into the potential of the bit line GBL (read operation). The sense circuit 21 also has the function of transmitting data held in the global sense amplifier GSA to the selected memory cell 41 via the bit line GBL, the sense circuit 21, and the bit line LBL (write operation). The sense circuit 21B has the same configuration as the sense circuit 21, and performs read and write operations between the global sense amplifier GSA and the selected memory cell 41 via the inverted bit line GBLB and the inverted bit line LBLB. The global sense amplifier GSA amplifies the potential difference between the bit line GBL and the inverted bit line GBLB and transmits the amplified potential to the bit line DBL and the inverted bit line DBLB (not shown).

[0047] The bit line GBL may be referred to as a global bit line, the inverted bit line GBLB as an inverted global bit line, the bit line LBL as a local bit line, and the inverted bit line LBLB as an inverted local bit line. The bit line LBL and the inverted bit line LBLB may be referred to as a bit line pair LBL-LBLB. The bit line LBL may be illustrated, and the inverted bit line LBLB may be omitted. The bit line GBL and the inverted bit line GBLB may be referred to as a bit line pair GBL-GBLB. The bit line GBL may be illustrated, and the inverted bit line GBLB may be omitted. The bit line LBL may be referred to as a first bit line. The bit line GBL may be referred to as a second bit line.

[0048] The configuration including the sense circuits 21 and 21B allows a slight change in the potential of the bit line LBL (inverted bit line LBLB) to be converted into the potential of the bit line GBL (inverted bit line GBLB) and transmitted to the global sense amplifier GSA. Therefore, the global sense amplifier GSA can read data by amplifying the potential difference between the pair of bit lines GBL and GBLB, thereby enabling the circuit to be miniaturized. Therefore, the memory device 100 according to one embodiment of the present invention can be miniaturized.

[0049] Furthermore, by including the sense circuits 21 and 21B in the memory device 100, the length of the wiring can be shortened compared to when the global sense amplifier GSA and the memory cell 41 are connected by bit lines. Specifically, since the bit line pair LBL-LBLB is connected to the sense circuits 21 and 21B in the element layer 20, the length of the wiring is shorter compared to when the bit line pair LBL-LBLB is connected to the global sense amplifier GSA in the element layer 10 below the element layer 20. This reduces the parasitic capacitance of the bit line LBL and the inverted bit line LBLB, allowing the memory cell 41 to operate even if the capacitance of the capacitor is reduced. In this case, the shape of the capacitor in the memory cell 41 can be a parallel plate type or a shallow trench type, allowing the height of each element layer 40 including the memory cell 41 to be reduced. This allows the number of stacked element layers 40 to be increased when the element layers 40 are stacked, thereby enabling the memory device to be miniaturized and have a higher capacity.

[0050] The data sense amplifier unit 12 has a plurality of data sense amplifier blocks DSAB. The data sense amplifier block DSAB amplifies the potential difference between the bit line DBL and the inverted bit line DBLB (not shown) according to input write data. The data sense amplifier block DSAB amplifies the potential difference between the bit line DBL and the inverted bit line DBLB (not shown) and outputs it as read data. The data sense amplifier block DSAB is sometimes referred to as a second sense amplifier block.

[0051] In FIG. 2, the global sense amplifier block GSAB is illustrated as a different block for each row of bit lines DBL, but the global sense amplifiers GSA connected to multiple rows, for example, two rows of bit lines DBL, may be grouped together as a global sense amplifier block GSAB.

[0052] The data sense amplifier block DSAB has a sense amplifier for each row, similar to the global sense amplifier block GSAB. The sense amplifier included in the data sense amplifier block DSAB may be called a second sense amplifier.

[0053] The bit line DBL and the inverted bit line DBLB may be referred to as a bit line pair DBL-DBLB. As shown in Figure 2, the bit line DBL may be illustrated, and the inverted bit line DBLB may be omitted. The bit line DBL may be referred to as a data bit line or a third bit line.

[0054] The bit line pair DBL-DBLB is a wiring for bidirectionally inputting and outputting data between the data sense amplifier block DSAB and the global sense amplifier block GSAB. Note that if the data inputted and outputted through the bit line pair DBL-DBLB is multi-bit, multiple wirings are also used.

[0055] The global sense amplifier drive circuit unit 13 has a plurality of sense amplifier drive blocks SADB. A sense amplifier drive block SADB is provided for each global sense amplifier block GSAB. The sense amplifier drive block SADB outputs a sense amplifier control signal SAEN to the global sense amplifier block GSAB. The sense amplifier control signal SAEN is a signal for controlling the global sense amplifier GSA included in the global sense amplifier block GSAB corresponding to the sense amplifier drive block SADB.

[0056] The column line driving circuit unit 14 supplies a column selection signal CSE to the global sense amplifiers GSA in the global sense amplifier blocks GSAB via the column lines CSEL. The column selection signal CSE is a signal that places the global sense amplifiers GSA in the global sense amplifier blocks GSAB in a selected or unselected state. The column lines CSEL are connected to the column line driving circuit unit 14. The column lines CSEL are also connected to the global sense amplifiers GSA in the global sense amplifier blocks GSAB.

[0057] The word line side driver circuit unit 15 has a plurality of word line side driver blocks WDB. A plurality of word line side driver blocks WDB is provided for each global sense amplifier block GSAB. The plurality of word line side driver blocks WDB output a sense circuit control signal SEN and a word signal SWL. The sense circuit control signal SEN is a signal that controls the operation of the sense circuits 21, 21B connected to the global sense amplifier GSA of the global sense amplifier block GSAB corresponding to the word line side driver block WDB. The word signal SWL is a word signal to the memory cell 41 connected to the global sense amplifier GSA of the global sense amplifier block GSAB corresponding to the word line side driver block WDB.

[0058] The global sense amplifier GSA is connected to the sense circuits 21 and 21B via a bit line GBL and an inverted bit line GBLB provided in the Z direction. The global sense amplifier GSA is controlled by a sense amplifier control signal SAEN and a column selection signal CSE.

[0059] The global sense amplifier GSA can perform write and read operations on the sense circuits 21, 21B connected to the global sense amplifier GSA and the memory cells 41 connected to the sense circuits 21, 21B using the sense circuit control signal SEN and word signal SWL from the word line side driver block WDB corresponding to the global sense amplifier block GSAB, and the sense amplifier control signal SAEN from the sense amplifier driver block SADB.

[0060] For example, the word line side driver block WDB of the word line side driver circuit unit 15 outputs a sense circuit control signal SEN and a word signal SWL to select the sense circuits 21 and 21B and the memory cell 41. Selecting the memory cell 41 causes a slight change in the potential of the bit line pair LBL-LBLB. Selecting the sense circuits 21 and 21B causes the potential of the bit line pair GBL-GBLB to change in response to the change in the potential of the bit line pair LBL-LBLB. The change in the potential of the bit line pair GBL-GBLB is detected by the sense amplifier control signal SAEN, which activates the global sense amplifier GSA, allowing data stored in the memory cell 41 to be read. Data is written to the selected memory cell 41 by transmitting the change in the potential of the bit line pair GBL-GBLB, which occurs when the global sense amplifier GSA is activated, to the bit line pair LBL-LBLB via the selected sense circuit 21 or 21B.

[0061] The global sense amplifier GSA can be activated by a sense amplifier control signal SAEN. Data to be written and read is input / output bidirectionally to / from the data sense amplifier block DSAB via the bit line DBL in response to a column selection signal CSE. Specifically, the global sense amplifier GSA selected by the column selection signal CSE can output data held in the memory cell 41 to the data sense amplifier block DSAB via the sense circuits 21 and 21B. Furthermore, the global sense amplifier GSA selected by the column selection signal CSE receives write data from the data sense amplifier block DSAB.

[0062] The controller unit 16 outputs a sense amplifier drive block control signal SADB_EN ​​for controlling the output of a sense amplifier control signal SAEN from a sense amplifier drive block SADB corresponding to a global sense amplifier block GSAB that writes or reads data.The controller unit 16 also outputs a word line side drive block control signal WDB_EN ​​for controlling the output of a sense circuit control signal SEN and a word signal SWL from a word line side drive block WDB corresponding to a global sense amplifier block GSAB that writes or reads data.The controller unit 16 also outputs a data sense amplifier block control signal DSAB_EN for writing and reading data in a data sense amplifier block DSAB corresponding to a global sense amplifier block GSAB that writes or reads data.

[0063] The word line side driver circuit unit 15 can simultaneously select the word lines of memory cells 41 connected to one or more global sense amplifier blocks GSAB and the sense circuits 21 and 21B using the word line side driver block control signal WDB_EN. The global sense amplifier driver circuit unit 13 can select one or more global sense amplifier blocks GSAB and activate the sense amplifiers included in the global sense amplifiers GSA using the sense amplifier driver block control signal SADB_EN. As a result, the global sense amplifiers GSA having the activated sense amplifiers can simultaneously read data from the selected memory cells 41 via the sense circuits 21 and 21B. The data sense amplifier unit 12 can activate the sense amplifiers included in one data sense amplifier block DSAB using the data sense amplifier block control signal DSAB_EN. As a result, the data sense amplifier block DSAB having the activated sense amplifier can access the data read out to the corresponding global sense amplifier block GSAB.

[0064] In an activated data sense amplifier block DSAB, the state in which data read out to the corresponding global sense amplifier block GSAB can be accessed refers to a state in which data can be read between the activated data sense amplifier block DSAB and the global sense amplifier GSA via the bit line DBL. For example, this refers to a state in which a signal from the global sense amplifier block GSAB is amplified and output by a data sense amplifier block control signal DSAB_EN that switches the data sense amplifier block DSAB between an active state and an inactive state. Alternatively, this refers to a state in which a switch is provided between the bit line pair DBL-DBLB and the data sense amplifier block DSAB and the switch is turned on by the data sense amplifier block control signal DSAB_EN.

[0065] The memory device 100 according to one embodiment of the present invention has a configuration in which a plurality of sense circuits 21 and 21B and a plurality of global sense amplifier blocks GSAB are arranged below the memory cell 41. Therefore, an increase in the circuit area can be suppressed, thereby achieving miniaturization and reduced power consumption.

[0066] Furthermore, the memory device 100 according to one embodiment of the present invention is configured to control the sense amplifier driver block SADB and the word line side driver block WDB so that one or more global sense amplifier blocks GSAB can be selected and data can be read. This allows the sense amplifiers included in the selected global sense amplifier blocks GSAB to be simultaneously activated, thereby increasing the memory bandwidth (also referred to as memory bandwidth). Furthermore, the data in the memory cells 41 selected by the activated sense amplifiers can be simultaneously read via the sense circuits 21 and 21B, thereby shortening the time required for writing and reading. Furthermore, by sequentially activating the global sense amplifier blocks GSAB, the amount of current flowing through the memory device due to an increase in the number of activated sense amplifiers can be adjusted, thereby reducing the voltage drop on the power supply line.

[0067] Furthermore, the memory device 100 according to one embodiment of the present invention can select one data sense amplifier block DSAB and access data read out to the global sense amplifier block GSAB. Therefore, data simultaneously read out to the global sense amplifiers GSA included in the global sense amplifier blocks GSAB can be output sequentially in accordance with the width of a bus external to the memory device 100. Furthermore, by sequentially activating the data sense amplifier blocks DSAB, the amount of current flowing through the memory device due to an increase in the number of activated sense amplifiers can be suppressed, and a voltage drop in the power supply line can be reduced.

[0068] 3A is a schematic diagram illustrating an example configuration of a memory cell 41, sense circuits 21 and 21B, and a global sense amplifier GSA. Fig. 3A illustrates a configuration in which an element layer 20 having sense circuits 21 and 21B and an element layer 40 having a memory cell 41 are provided above an area in which the global sense amplifier GSA and bit line pair DBL-DBLB described in Fig. 2 are provided. The memory cell 41 is connected to the sense circuits 21 and 21B via a bit line pair LBL-LBLB. The sense circuits 21 and 21B are also connected to the global sense amplifier GSA via a bit line pair GBL-GBLB.

[0069] 3B is a schematic diagram for explaining a transistor 51 provided in the element layers 20 and 40 and a transistor 53 provided in the element layer 10 in the schematic diagram in which the element layer 10, the element layer 20, and the element layer 40 are stacked as shown in FIG. 3B also illustrates the bit line pair LBL-LBLB, the sense circuits 21 and 21B, and the bit line pair GBL-GBLB shown in FIG.

[0070] The semiconductor layer 52 of the transistor 51 may be an oxide semiconductor (metal oxide), thereby forming the memory cell 41 and the sense circuits 21 and 21B including the OS transistor. The transistor 51 having an oxide semiconductor in the semiconductor layer 52 having a channel formation region may be referred to as a first transistor. The semiconductor layer 52 having an oxide semiconductor in the channel formation region may be referred to as a first semiconductor layer.

[0071] By using silicon for the semiconductor layer 54 of the transistor 53, it is possible to provide a global sense amplifier GSA in the element layer 10 configured with the above-described Si transistor.

[0072] By arranging the element layer 40 in which the memory cells 41 are provided and the element layer 20 in which the sense circuits 21 and 21B are provided on the element layer 10 in which the global sense amplifier GSA is provided, the storage capacity, i.e., the number of memory cells 41, can be increased compared to when the memory cells 41, the sense circuits 21 and 21B, and the global sense amplifier GSA are arranged on the same layer.

[0073] The memory device 100A shown in Fig. 4A is a modified example of the memory device 100 shown in Fig. 3A. The schematic diagram shown in Fig. 4A illustrates a case where the element layer 40 in Fig. 3A is provided by stacking a plurality of element layers 40_1 and 40_2.

[0074] 4A includes element layers 40_1 and 40_2 in which a plurality of memory cells 41 are arranged. This configuration allows a manufacturing process using the same photomask to be employed for the plurality of element layers 40_1 and 40_2. Therefore, the memory cells 41 can be manufactured using the same manufacturing process repeatedly in the vertical direction, thereby reducing manufacturing costs.

[0075] 4B is a schematic diagram illustrating element layers 40_1 to 40_n (n is an integer equal to or greater than 2) including element layers 40_1 and 40_2 shown in FIG. 4A. Also shown in FIG. 4B are the bit line pair LBL-LBLB, sense circuits 21 and 21B, and bit line pair GBL-GBLB shown in FIG. 4A. As shown in FIG. 4B, in the memory device 100A, multiple element layers 40_1 to 40_n are stacked vertically or approximately vertically relative to the surface of the element layer 10. This configuration allows the number of memory cells 41 arranged per unit area to be increased. This increases the memory density.

[0076] In the configuration of FIG. 4B , the bit line pair LBL-LBLB is connected to the sense circuits 21 and 21B in the element layer 20. Therefore, the wiring length of the bit line pair LBL-LBLB can be shorter than when the global sense amplifier GSA and the memory cell 41 are connected via the bit line pair LBL-LBLB. Since the parasitic capacitance generated in the bit line pair LBL-LBLB connected to the memory cell 41 can be reduced, the memory cell 41 can operate even if the capacitance of the capacitor provided therein is reduced. In this case, the shape of the capacitor provided in the memory cell 41 can be a parallel plate type or a shallow trench type, so the height of each element layer 40 including the memory cell 41 can be reduced. Therefore, the number of stacked layers when the element layers 40 are arranged in layers can be increased, thereby enabling the memory device to be miniaturized and have a high capacity.

[0077] FIG. 5A is a block diagram for explaining the sense amplifier drive block control signal SADB_EN, the word line side drive block control signal WDB_EN, and the data sense amplifier block control signal DSAB_EN output by the controller unit 16. As shown in FIG.

[0078] 5A, the global sense amplifier blocks GSAB included in the global sense amplifier unit 11 are, for example, eight blocks (global sense amplifier blocks GSAB[1] to GSAB[8]). Also in FIG. 5A, a sense circuit unit 22 is illustrated at a position overlapping with the global sense amplifier blocks GSAB[1] to GSAB[8]. Although not shown, the sense circuit unit 22 includes sense circuits 21 and 21B connected to the global sense amplifiers GSA included in the global sense amplifier blocks GSAB[1] to GSAB[8]. Also in FIG. 5A, a memory cell array 42 is illustrated at a position overlapping with the sense circuit unit 22. Although not shown, the memory cell array 42 includes memory cells 41 connected to the sense circuits 21 and 21B included in the sense circuit unit 22.

[0079] Furthermore, eight data sense amplifier blocks DSAB (in FIG. 5A, [1] to [8] are added) are illustrated as data sense amplifier blocks DSAB corresponding to global sense amplifier blocks GSAB[1] to GSAB[8]. A data sense amplifier block control signal DSAB_EN for selecting and controlling each block is provided to each of the eight data sense amplifier blocks DSAB by the controller unit 16.

[0080] Furthermore, eight sense amplifier driving blocks SADB (in FIG. 5A , [1] to [8] are added) corresponding to the global sense amplifier blocks GSAB[1] to GSAB[8] are illustrated as sense amplifier driving blocks SADB. A sense amplifier driving block control signal SADB_EN ​​for selecting and controlling each block is provided to each of the eight sense amplifier driving blocks SADB from the controller unit 16.

[0081] Furthermore, eight word line side driver blocks WDB (in FIG. 5A, [1] to [8] are added) corresponding to the global sense amplifier blocks GSAB[1] to GSAB[8] are illustrated as word line side driver blocks WDB. A word line side driver block control signal WDB_EN ​​for selecting and controlling each block is provided to each of the eight word line side driver blocks WDB by the controller unit 16.

[0082] In the above-mentioned data sense amplifier block DSAB, sense amplifier driving block SADB, and word line side driving block WDB, when selecting one or more blocks from multiple blocks, for example, as shown in Figure 5B, the control signal IN_EN and the control signal B_EN from the controller unit 16 are combined and input to the AND gate 17, and control is performed according to the resulting signal OUT_EN.

[0083] 6A illustrates a configuration in which, when selecting one or more of the data sense amplifier blocks DSAB[1] to DSAB[8], the input data sense amplifier control signal DSA_EN and the data sense amplifier block control signals DSAB_EN[1] to DSAB_EN[8] are input to and controlled by AND gates 17 provided for each of the data sense amplifier blocks DSAB[1] to DSAB[8]. The data sense amplifier control signal DSA_EN is a signal that puts the data sense amplifier block DSAB into a state in which it can access data read out to the global sense amplifier block GSAB. This configuration allows the data sense amplifier block DSAB selected by the data sense amplifier block control signals DSAB_EN[1] to DSAB_EN[8] to be put into a state in which it can access data read out to the global sense amplifier block GSAB.

[0084] 6B illustrates a configuration in which, when selecting one or more of the sense amplifier driving blocks SADB[1] to SADB[8], the input sense amplifier driving control signal SAD_EN and the sense amplifier driving block control signals SADB_EN[1] to SADB_EN[8] are input to and controlled by AND gates 17 provided for each of the sense amplifier driving blocks SADB[1] to SADB[8]. The sense amplifier driving control signal SAD_EN is a signal for outputting the sense amplifier control signal SAEN from the sense amplifier driving block SADB and activating the global sense amplifier GSA. With this configuration, the sense amplifier driving block SADB selected by the sense amplifier driving block control signals SADB_EN[1] to SADB_EN[8] can output the sense amplifier control signal SAEN and activate the global sense amplifier GSA of the corresponding global sense amplifier block GSAB.

[0085] 6C illustrates a configuration in which, when selecting one or more of the word line side driver blocks WDB[1] to WDB[8], the input word line drive control signal WD_EN and the word line side driver block control signals WDB_EN[1] to WDB_EN[8] are input to and controlled by AND gates 17 provided for each of the word line side driver blocks WDB[1] to WDB[8]. The word line drive control signal WD_EN is a signal for outputting the sense circuit control signal SEN and word signal SWL from the word line side driver block WDB to select the sense circuits 21, 21B and the memory cells 41. With this configuration, the word line side driving block WDB selected by the word line side driving block control signals WDB_EN[1] to WDB_EN[8] outputs a sense circuit control signal SEN and a word signal SWL, and the sense circuits 21, 21B and memory cells 41 connected to the global sense amplifier GSA of the corresponding global sense amplifier block GSAB can be selected.

[0086] (Operation example of memory device 100) Figures 7A to 11B will explain an operation example of the memory device 100 using the configuration examples explained in Figures 5A to 6C. Figures 7A, 8A, 9A, 10A, and 11A are diagrams showing blocks selected by the controller unit 16 in the block diagram shown in Figure 5A, and the selected blocks (those whose sense amplifiers are activated) are shown hatched.

[0087] 7B, 8B, 9B, 10B, and 11B are timing charts corresponding to the states shown in FIGS. 7A, 8A, 9A, 10A, and 11A, respectively. The timing charts shown in FIGS. 7B, 8B, 9B, 10B, and 11B show the data sense amplifier control signal DSA_EN, sense amplifier drive block control signals SADB_EN[1] to SADB_EN[8], word line drive control signal WD_EN, word line side drive block control signals WDB_EN[1] to WDB_EN[8], data sense amplifier control signal DSA_EN, and data sense amplifier block control signals DSAB_EN[1] to DSAB_EN[8], which are described with reference to FIGS. 6A to 6C. Note that the following description will be given assuming that each control signal is in a selected state at an H level and in a non-selected state at an L level.

[0088] 7A to 11B, the global sense amplifier blocks GSAB, sense amplifier driver blocks SADB, word line side driver blocks WDB, and data sense amplifier blocks DSAB are each described as eight blocks. Note that the number of blocks is not limited to eight, and is preferably two or more. By providing a plurality of global sense amplifier blocks GSAB, sense amplifier driver blocks SADB, word line side driver blocks WDB, and data sense amplifier blocks DSAB, the number of blocks controlled can be switched in accordance with each control signal output by the controller unit 16. The number of controlled blocks may be multiple or may be single.

[0089] 7A and 7B are operation and timing charts for selecting one global sense amplifier block, for example, global sense amplifier block GSAB[1]. When activating the sense amplifiers in global sense amplifier block GSAB[1] to read data, the control signals are set as shown in FIG. 7B. Specifically, the sense amplifier drive control signal SAD_EN, word line drive control signal WD_EN, and data sense amplifier control signal DSA_EN are set to H level, and the data sense amplifier control signal DSAB_EN[1], sense amplifier drive block control signal SADB_EN[1], and word line drive block control signal WDB_EN[1] corresponding to global sense amplifier block GSAB[1] are set to H level.

[0090] With this configuration, in the memory cell array 42, the sense circuits 21, 21B and memory cells 41 connected to the sense amplifiers of the global sense amplifier block GSAB[1] are selected by the sense circuit control signal SEN and word signal SWL output by the corresponding word line side driver block control signal WDB_EN[1]. Also, the sense amplifiers of the global sense amplifier block GSAB[1] are activated by the sense amplifier control signal SAEN output by the corresponding sense amplifier driver block SADB[1].

[0091] 7A and 7B, the data sense amplifier block control signal DSAB_EN[1] is set to the H level. With this configuration, the data sense amplifier block DSAB[1] is in an access state for the data read out by the sense amplifier included in the global sense amplifier block GSAB[1], and data can be read out from the sense amplifier included in the global sense amplifier block GSAB[1] selected by the column selection signal CSE.

[0092] 8A to 9B are timing charts showing the operation of two global sense amplifier blocks, for example, global sense amplifier blocks GSAB[1] and GSAB[2], when they are selected. When activating the sense amplifiers in the global sense amplifier blocks GSAB[1] and GSAB[2] to read data, the control signals are set as shown in FIGS. 8B and 9B. Specifically, the sense amplifier drive control signal SAD_EN, the word line drive control signal WD_EN, and the data sense amplifier control signal DSA_EN are set to H level, and the data sense amplifier control signals DSAB_EN[1] and DSAB_EN[2], the sense amplifier drive block control signals SADB_EN[1] and SADB_EN[2], and the word line side drive block control signals WDB_EN[1] and WDB_EN[2] corresponding to the global sense amplifier blocks GSAB[1] and GSAB[2] are set to H level.

[0093] With this configuration, in the memory cell array 42, the sense circuits 21, 21B and memory cells 41 connected to the sense amplifiers of the global sense amplifier blocks GSAB[1] and GSAB[2] are simultaneously selected by the sense circuit control signal SEN and word signal SWL output by the corresponding word line side driver block control signals WDB_EN[1] and WDB_EN[2]. Also, the sense amplifiers of the global sense amplifier blocks GSAB[1] and GSAB[2] are simultaneously activated by the sense amplifier control signal SAEN output by the corresponding sense amplifier driver blocks SADB[1] and SADB[2].

[0094] 8A and 8B, the data sense amplifier block control signal DSAB_EN[1] is set to the H level. With this configuration, the data sense amplifier block DSAB[1] is in an access state for the data read out by the sense amplifier included in the global sense amplifier block GSAB[1], and data can be read out from the sense amplifier included in the global sense amplifier block GSAB[1] selected by the column select signal CSE.

[0095] 9A and 9B, the data sense amplifier block control signal DSAB_EN[2] is set to level H. With this configuration, the data sense amplifier block DSAB[2] enters an access state for the data read out by the sense amplifier included in the global sense amplifier block GSAB[2], and data can be read out from the sense amplifier included in the global sense amplifier block GSAB[2] selected by the column select signal CSE.

[0096] 10A to 11B are operation and timing charts when all eight global sense amplifier blocks, for example, global sense amplifier blocks GSAB[1] and GSAB[8], are selected. When activating the sense amplifiers in the global sense amplifier blocks GSAB[1] to GSAB[8] to read data, the control signals are set as shown in FIGS. 10B and 11B. Specifically, the sense amplifier drive control signal SAD_EN, the word line drive control signal WD_EN, and the data sense amplifier control signal DSA_EN are set to H level, and the data sense amplifier control signals DSAB_EN[1] to DSAB_EN[8], the sense amplifier drive block control signals SADB_EN[1] to SADB_EN[8], and the word line side drive block control signals WDB_EN[1] to WDB_EN[8] corresponding to the global sense amplifier blocks GSAB[1] to GSAB[8] are set to H level.

[0097] With this configuration, in the memory cell array 42, the sense circuits 21, 21B and memory cells 41 connected to the sense amplifiers of the global sense amplifier blocks GSAB[1] to GSAB[8] are simultaneously selected by the sense circuit control signal SEN and word signal SWL output by the corresponding word line side driver block control signal WDB_EN[1] to WDB_EN[8]. Also, the sense amplifiers of the global sense amplifier blocks GSAB[1] to GSAB[8] are simultaneously activated by the sense amplifier control signal SAEN output by the corresponding sense amplifier driver blocks SADB[1] to SADB[8].

[0098] 10A and 10B, the data sense amplifier block control signal DSAB_EN[1] is set to level H. With this configuration, the data sense amplifier block DSAB[1] is in an access state for the data read out by the sense amplifier included in the global sense amplifier block GSAB[1], and data can be read out from the sense amplifier included in the global sense amplifier block GSAB[1] selected by the column select signal CSE.

[0099] Although not explained further, the data sense amplifier block control signals DSAB_EN[2] to DSAB_EN[7] are also sequentially set to H level (corresponding to periods T3-2 to T3-7). With this configuration, the data sense amplifier blocks DSAB[2] to DSAB[7] become sequentially accessible to the data read out by the sense amplifiers of the global sense amplifier blocks GSAB[2] to GSAB[7], and data can be sequentially read out from the sense amplifiers of the global sense amplifier blocks GSAB[2] to GSAB[7] selected by the column select signal CSE.

[0100] 11A and 11B, the data sense amplifier block control signal DSAB_EN[8] is set to H level. With this configuration, the data sense amplifier block DSAB[8] becomes accessible to the data read by the sense amplifier included in the global sense amplifier block GSAB[8], and data can be read from the sense amplifier included in the global sense amplifier block GSAB[8] selected by the column select signal CSE.

[0101] A memory device 100 according to one embodiment of the present invention is configured to control a sense amplifier driver block SADB and a word line side driver block WDB so that one or more global sense amplifier blocks GSAB can be selected and data can be read. This allows the sense amplifiers included in the selected global sense amplifier blocks GSAB to be simultaneously activated, thereby increasing the memory bandwidth (also referred to as memory bandwidth). Furthermore, by simultaneously reading data from selected memory cells 41 using the activated sense amplifiers, the time required for writing and reading can be shortened. Furthermore, by sequentially activating the global sense amplifier blocks GSAB, the amount of current flowing through the memory device due to an increase in the number of activated sense amplifiers can be adjusted, thereby reducing the voltage drop on the power supply line.

[0102] Furthermore, the memory device 100 according to one embodiment of the present invention can select one data sense amplifier block DSAB and access data read out to the global sense amplifier block GSAB. Therefore, data simultaneously read out to the global sense amplifiers GSA included in the global sense amplifier blocks GSAB can be output sequentially in accordance with the width of a bus external to the memory device 100. Furthermore, by sequentially activating the data sense amplifier blocks DSAB, the amount of current flowing through the memory device due to an increase in the number of activated sense amplifiers can be suppressed, and a voltage drop in the power supply line can be reduced.

[0103] (Configuration Example of Memory Cell 41) A circuit configuration of a memory cell that can be applied to the memory cell 41 will be described. Note that the memory cell 41 is a memory cell that includes an OS transistor. A memory that includes a memory cell that includes an OS transistor may also be referred to as an "OS memory."

[0104] The OS transistor has an extremely low off-state current. Therefore, charge corresponding to data written to the memory cell 41 can be held for a long time. That is, data once written can be held for a long time in the memory cell 41. Therefore, the frequency of data refresh can be reduced, and the power consumption of the storage device 100 of one embodiment of the present invention can be reduced.

[0105] 12A is a diagram illustrating a memory cell array 42 having a plurality of memory cells 41. In FIG. 12A, word lines WL_1 to WL_m and bit lines LBL_1 to LBL_n are illustrated, which are arranged in a matrix of m rows and n columns (m and n are natural numbers of 2 or greater). Also illustrated are memory cells 41 connected to each word line WL and bit line LBL.

[0106] 12B is a circuit diagram illustrating an example of a circuit configuration applicable to the memory cell 41. The memory cell 41 includes a transistor M1 and a capacitor C1 (also referred to as a capacitance element). The transistor M1 is connected to a word line WL, a bit line LBL, and the capacitor C1. The capacitor C1 is connected to a wiring PL that functions as a capacitance line. A ground potential GND, for example, is input to the wiring PL. FIG. 12C is a circuit block corresponding to the circuit diagram of FIG. 12B.

[0107] The memory cell 41 shown in FIG. 12B can be a 1T (transistor) 1C (capacitance) DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) memory cell. DOSRAM refers to a RAM having 1T1C type memory cells. DOSRAM is a DRAM formed using OS transistors, and is a memory that temporarily stores information sent from the outside. DOSRAM is a memory that utilizes the low off-state current of OS transistors. Because DOSRAM is a 1T1C type memory cell, a large storage capacity can be achieved in the memory cell array 42. Furthermore, by using OS transistors, the data retention period can be increased compared to DRAMs having Si transistors.

[0108] The circuit configuration applicable to the memory cell 41 is not limited to the 1T1C DOSRAM shown in FIG. 12B . For example, FIG. 13A shows another example configuration of a 1T1C memory cell applicable to a DOSRAM. The memory cell 41A shown in FIG. 13A differs from the memory cell 41 shown in FIG. 12B in that the transistor M1 is an OS transistor having a back gate, and the back gate is connected to a wiring BGL. The configuration including the wiring BGL allows the transistor M1 to have improved electrical characteristics.

[0109] The memory cell 41 having an OS transistor can be a nonvolatile oxide semiconductor random access memory (NOSRAM). The memory cell in an NOSRAM is a two-transistor (2T) or three-transistor (3T) gain cell. Since NOSRAM rewrites data by charging and discharging a capacitor, there is no theoretical limit to the number of rewrites and it requires low energy. Therefore, NOSRAM is a memory capable of high-speed operation, low power consumption, and high rewrite endurance. Furthermore, NOSRAM is suitable for long-term data retention because it can read written data nondestructively.

[0110] The memory cell 41B shown in FIG. 13B is a circuit equivalent to a 2T NOSRAM. The memory cell 41B includes a transistor M1, a transistor M2, and a capacitor C1. The transistors M1 and M2 are a write transistor and a read transistor, respectively. The transistors M1 and M2 may be OS transistors having semiconductor layers disposed in different layers or may be OS transistors having semiconductor layers disposed in the same layer. The memory cell 41B is illustrated as being connected to a write bit line WBL, a read bit line RBL, a write word line WWL, a read word line RWL, and a wiring SL.

[0111] 13C is a circuit equivalent to a 3T NOSRAM. The memory cell 41C includes transistors M1, M2, and M3, and a capacitor C1. The transistors M1, M2, and M3 are a write transistor, a read transistor, and a select transistor, respectively. The transistors M1, M2, and M3 may be OS transistors whose semiconductor layers are arranged in different layers or may be OS transistors whose semiconductor layers are arranged in the same layer.

[0112] Since the write transistor is an OS transistor, it can continue to hold charge corresponding to data by turning off the write transistor. Therefore, the memory cells 41B and 41C do not consume power to hold data. Therefore, the memory cells 41B and 41C can hold data for a long period of time and function as low-power memory cells. The gate of the read transistor functions as a node that holds charge corresponding to data. The read transistor is a transistor that has the function of passing a current corresponding to the potential of the node that holds charge corresponding to data. The select transistor is a transistor that controls the current flowing through the read transistor.

[0113] 13D shows another example of the configuration of a 2T gain cell. A memory cell 41D shown in FIG. 13D differs from the memory cell 41B shown in FIG. 13B in that the transistors M1 and M2 are OS transistors each having a back gate, and the back gates are connected to a wiring BGL. For example, a ground potential GND is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1 and M2 to have improved electrical characteristics.

[0114] 13E shows another example of the configuration of a 3T gain cell. A memory cell 41E shown in FIG. 13E differs from the memory cell 41C shown in FIG. 13C in that the transistors M1, M2, and M3 are OS transistors each having a back gate, and the back gates are connected to a wiring BGL. For example, a ground potential GND is input to the wiring BGL. The inclusion of the wiring BGL allows the transistors M1, M2, and M3 to have improved electrical characteristics.

[0115] Fig. 13F shows another example of the configuration of a 2T-type gain cell. The memory cell 41F shown in Fig. 13F differs from the memory cell 41B shown in Fig. 13B in that the capacitor C1 is omitted by using the gate capacitance of the read transistor, and the wiring PL is omitted.

[0116] The transistors M1 and M2 in the 2T gain cell shown in FIG. 13F are preferably vertical transistors in which the source electrode and the drain electrode are located at different heights. In a vertical transistor, current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. In other words, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel transistor, or a vertical transistor.

[0117] In a vertical transistor, the source region, the channel formation region, and the drain region can at least partially overlap each other in a top view, compared to a horizontal transistor (also called a planar structure or planar type) in which the source electrode and the drain electrode are located at the same height. This allows the vertical transistor to have a smaller occupied area (also called a footprint). Furthermore, the vertical transistor has a structure that allows the channel length to be short and the channel width to be wide, allowing the on-resistance to be small (the on-current to be large).

[0118] Fig. 13G shows another example of the configuration of a 3T gain cell. Memory cell 41G shown in Fig. 13G differs from memory cell 41C shown in Fig. 13C in that capacitor C1 is omitted by using the gate capacitance of the read transistor, and wiring PL is omitted. Transistors M1, M2, and M3 included in the 3T gain cell shown in Fig. 13G are vertical transistors in which the source electrode and drain electrode are located at different heights, thereby reducing the occupied area (also referred to as footprint) and reducing the on-resistance (increasing the on-current).

[0119] (Configuration Example of Global Sense Amplifier GSA) An example of the circuit configuration of the global sense amplifier GSA will be described. Fig. 14A is a circuit diagram of the global sense amplifier GSA. Fig. 14B shows a circuit block corresponding to the circuit diagram.

[0120] 14A includes a sense amplifier 61, a precharge circuit 62, a precharge circuit 63, and a switch circuit 64. The sense amplifier 61, the precharge circuit 62, the precharge circuit 63, and the switch circuit 64 are each connected to the bit line pair GBL-GBLB.

[0121] The sense amplifier 61 has a function of applying a predetermined potential to each of the wiring SAP and the wiring SAN to output a potential corresponding to one of the binary data values ​​to the bit line GBL and output a potential corresponding to the other of the binary data values ​​to the inverted bit line GBLB. The sense amplifier 61 includes transistors 61_1, 61_2, 61_3, and 61_4. The transistors 61_1 and 61_2 are p-channel transistors. The transistors 61_3 and 61_4 are n-channel transistors. The transistors 61_1 and 61_3 form an inverter circuit in which the inverted bit line GBLB is used as an input, the bit line GBL is used as an output, the wiring SAP is used as a high-potential power supply line, and the wiring SAN is used as a low-potential power supply line. The transistor 61_2 and the transistor 61_4 configure an inverter circuit in which the bit line GBL is used as an input, the inverted bit line GBLB is used as an output, the wiring SAP is used as a high-potential power supply line, and the wiring SAN is used as a low-potential power supply line.

[0122] The precharge circuit 62 has a function of precharging the bit line pair GBL-GBLB to a potential VPRE in response to a signal EQB. Specifically, the precharge circuit 62 includes transistors 62_1, 62_2, and 62_3. Each of the transistors 62_1, 62_2, and 62_3 is a p-channel transistor. The transistor 62_1 has a function of turning on or off the bit line pair GBL-GBLB in response to the signal EQB. The transistor 62_2 has a function of precharging the bit line GBL to a potential VPRE in response to the signal EQB. The transistor 62_3 has a function of precharging the inverted bit line GBLB to a potential VPRE in response to the signal EQB.

[0123] The precharge circuit 63 has a function of precharging the bit line pair GBL-GBLB to a potential VPRE in response to a signal EQ. Specifically, the precharge circuit 63 includes transistors 63_1, 63_2, and 63_3. Each of the transistors 63_1, 63_2, and 63_3 is an n-channel transistor. The transistor 63_1 has a function of turning on or off the bit line pair GBL-GBLB in response to the signal EQ. The transistor 63_2 has a function of precharging the bit line GBL to a potential VPRE in response to the signal EQ. The transistor 63_3 has a function of precharging the inverted bit line GBLB to a potential VPRE in response to the signal EQ.

[0124] The switch circuit 64 has a function of bringing the bit line pair GBL-GBLB and the bit line pair DBL-DBLB into a conductive state or a non-conductive state in response to a column selection signal CSE. Specifically, the switch circuit 64 includes a transistor 64_1 and a transistor 64_2. Each of the transistors 64_1 and 64_2 is an n-channel transistor. The transistor 64_1 has a function of bringing the bit line GBL and the bit line DBL into a conductive state or a non-conductive state in response to the column selection signal CSE. The transistor 64_2 has a function of bringing the bit line pair DBL-DBLB and the bit line pair GBL-GBLB into a conductive state or a non-conductive state in response to the column selection signal CSE.

[0125] FIG. 14B shows a circuit block corresponding to the circuit diagram of the global sense amplifier GSA described in FIG. 14A.

[0126] The signals EQ and EQB that control the global sense amplifier GSA correspond to the sense amplifier control signal SAEN. The sense amplifier control signal SAEN may also include switching of the potentials of the wirings SAP and SAN.

[0127] 14A and 14B, the potential difference between the bit line GBL and the inverted bit line GBLB, which varies depending on the charge held in the memory cell 41 when data is read from the memory cell 41, can be amplified and output to the bit line pair DBL-DBLB in accordance with the column selection signal CSE. Also, the configuration of the global sense amplifier GSA shown in FIG. 14A and 14B allows the potential difference between the bit line pair DBL-DBLB to be applied to the bit line pair GBL-GBLB in accordance with the column selection signal CSE, and the amplified potential difference can be written to the memory cell 41 via the sense circuits 21 and 21B connected to the bit line pair GBL-GBLB.

[0128] (Configuration Example of Data Sense Amplifier Block DSAB) An example of the circuit configuration of the data sense amplifier block DSAB will be described. Fig. 15A is a circuit diagram of the data sense amplifier block DSAB. Fig. 15B shows a circuit block corresponding to the circuit diagram. Fig. 15C illustrates a configuration example that combines the circuit block of the global sense amplifier GSA shown in Fig. 14B with the circuit block of the data sense amplifier block DSAB shown in Fig. 15B.

[0129] The data sense amplifier block DSAB shown in Figure 15A includes a precharge circuit 65, a sense amplifier 66, a switch circuit 67, a transistor 68, an AND gate 69, and a latch circuit 70. The data sense amplifier block DSAB shown in Figure 15A also includes the AND gate 17 shown in Figures 5B and 6A. The precharge circuit 65, the sense amplifier 66, and the switch circuit 67 are each connected to the bit line pair DBL-DBLB.

[0130] Although the AND gate 17 shown in FIG. 15A is provided at the gate of the transistor 68, other configurations are also possible. For example, the signals input to the precharge circuit 65, the sense amplifier 66, the switch circuit 67, the AND gate 69, and the latch circuit 70 may be controlled in response to a data sense amplifier block control signal DSAB_E provided to the AND gate 17. In this case, the data sense amplifier block DSAB can be more reliably deactivated, thereby reducing power consumption. Alternatively, a separate switch may be provided between the data sense amplifier block DSAB and the bit line pair DBL-DBLB, and the on / off state of the switch may be controlled in response to the data sense amplifier block control signal DSAB_E. In this case, the current flowing between the bit line pair DBL-DBLB and the data sense amplifier block DSAB can be more reliably reduced, thereby reducing power consumption.

[0131] The precharge circuit 65 has a function of precharging the bit line pair DBL-DBLB to the potential of the wiring DSAP in response to a signal DEQ_ENB. The wiring DSAP is a high-potential power supply line. Specifically, the precharge circuit 65 includes transistors 65_1, 65_2, and 65_3. Each of the transistors 65_1, 65_2, and 65_3 is a p-channel transistor. The transistor 65_1 has a function of turning on or off the bit line DBL and the inverted bit line DBLB in response to the signal DEQ_ENB. The transistor 65_2 has a function of precharging the bit line DBL to the potential of the wiring DSAP in response to the signal DEQ_ENB. The transistor 65_3 has a function of precharging the inverted bit line DBLB to the potential of the wiring DSAP in response to the signal DEQ_ENB.

[0132] The sense amplifier 66 has a function of applying a predetermined potential from each of the wirings DSAP and DSAN to output a potential corresponding to one of the binary data values ​​to the bit line DBL and outputting a potential corresponding to the other of the binary data values ​​to the inverted bit line DBLB. The sense amplifier 66 includes transistors 66_1, 66_2, 66_3, and 66_4. The transistors 66_1 and 66_2 are p-channel transistors. The transistors 66_3 and 66_4 are n-channel transistors. The transistors 66_1 and 66_3 form an inverter circuit in which the inverted bit line DBLB is used as an input, the bit line DBL is used as an output, the wiring DSAP is used as a high-potential power supply line, and the wiring DSAN is used as a low-potential power supply line. The transistor 66_2 and the transistor 66_4 configure an inverter circuit in which the bit line DBL is used as an input, the inverted bit line DBLB is used as an output, the wiring SAP is used as a high-potential power supply line, and the wiring SAN is used as a low-potential power supply line.

[0133] The supply of the potential of the wiring DSAN to the sense amplifier 66 is controlled by a data sense amplifier control signal DSA_EN supplied to a transistor 68. The data sense amplifier control signal DSA_EN is a signal that controls the state of the sense amplifier 66. When the data sense amplifier control signal DSA_EN turns the transistor 68 to a conductive state, the sense amplifier 66 is activated, and when the data sense amplifier control signal DSA_EN turns the transistor 68 to a non-conductive state, the sense amplifier 66 is deactivated.

[0134] The switch circuit 67 switches the write data W to the bit line pair DBL-DBLB in response to the write control signals WE and WEB. ＤＡＴＡ , W ＤＡＴＡ The write control signal WEB is an inverted signal of the write control signal WE. ＤＡＴＡ _B is the write data W ＤＡＴＡSpecifically, the switch circuit 67 includes transistors 67_1 to 67_4. The transistors 67_1 and 67_3 are n-channel transistors. The transistors 67_2 and 67_4 are p-channel transistors. The transistors 64_1 and 64_2 are used to transmit write data W to the inverted bit line DBLB. ＤＡＴＡ The transistors 64_3 and 64_4 function as analog switches that control the supply of write data W to the bit line DBL. ＤＡＴＡ It functions as an analog switch that controls the supply of

[0135] The AND gate 69 has a function of outputting the potential of the bit line DBL to the latch circuit 70 in response to the control of a signal RE. The signal RE is a read control signal. The latch circuit 70 also receives the output signal of the AND gate 69 in response to the latch signal DLAT, and outputs the read data R ＤＡＴＡ It has the function to output as

[0136] Fig. 15B shows a circuit block corresponding to the circuit diagram of the data sense amplifier block DSAB described in Fig. 15A. Fig. 15C shows a configuration example in which the circuit block of the data sense amplifier block DSAB shown in Fig. 15B is combined with the circuit block of the global sense amplifier GSA shown in Fig. 14B.

[0137] In the configuration of the data sense amplifier block DSAB shown in FIGS. 15A to 15C, the potential difference between the bit line pair DBL-DBLB, which varies under the control of the column selection signal CSE, is amplified, and the read data R is output in response to the signal RE and the latch signal DLAT. ＤＡＴＡ In the configuration of the data sense amplifier block DSAB shown in FIGS. 15A to 15C, write data W is input to the bit line pair DBL-DBLB under the control of the write control signals WE and WEB. ＤＡＴＡ , W ＤＡＴＡ The potential difference resulting from the supply of the signal .sub.B is amplified, and the potential of the bit line pair DBL-DBLB can be applied to the bit line pair GBL-GBLB by controlling the column selection signal CSE.

[0138] (Configuration Example of Sense Circuit 21) A circuit configuration example of the sense circuit 21 will be described. Fig. 16A is a circuit diagram of the sense circuit 21. Fig. 16B shows a circuit block corresponding to the circuit diagram. Fig. 16C illustrates a configuration example that combines the circuit block of the sense circuit 21 shown in Fig. 16B, the circuit block of the memory cell 41 shown in Fig. 12C, and the circuit block of the global sense amplifier GSA shown in Fig. 14B.

[0139] The sense circuit 21 shown in FIG. 16A includes transistors 31 to 34. One of the source or drain of the transistor 31 is connected to one of the source or drain of the transistor 33 and one of the source or drain of the transistor 34. The other of the source or drain of the transistor 31 is connected to one of the source or drain of the transistor 32. The gate of the transistor 31 is connected to the other of the source or drain of the transistor 33 and the bit line LBL. The other of the source or drain of the transistor 32 is connected to a wiring SL. The other of the source or drain of the transistor 34 is connected to a bit line GBL. The transistor 31 has a function of passing a current between its source and drain in accordance with the potential of the bit line LBL. The transistor 32 has a function of bringing the source and drain into a conductive state or a non-conductive state in accordance with a signal RE applied to its gate. The transistor 33 has a function of bringing the source and drain into a conductive state or a non-conductive state in accordance with a signal WSE applied to its gate. The transistor 34 has a function of bringing the source and drain into a conductive or non-conductive state in response to a signal MUX applied to the gate.

[0140] The signals RE, MUX, and WSE that control the sense circuit 21 correspond to the sense circuit control signal SEN described above. The signals RE, MUX, and WSE are controlled in accordance with the operations of writing and reading data to and from the memory cell 41.

[0141] The sense circuit 21 has a function of changing the potential of the bit line GBL by flowing a current corresponding to the potential of the bit line LBL from the bit line GBL to the wiring SL through the transistors 34, 31, and 32. The sense circuit 21 also has a function of transmitting the potential of the bit line GBL to the bit line LBL through the transistors 34 and 33. The sense circuit 21 also has a function of changing the potential of the gate of the transistor 31 to a potential corresponding to the threshold voltage of the transistor 31 by discharging charge accumulated in the gate of the transistor 31 to the wiring SL through the transistors 33, 31, and 32. This function enables the sense circuit 21 to make corrections to reduce the influence of the threshold voltage of the transistor 31.

[0142] The sense circuit 21 may include a capacitor. In this case, one terminal of the capacitor may be connected to the bit line LBL, and the other terminal of the capacitor may be connected to a wiring to which an arbitrary fixed potential is applied.

[0143] The transistors 31 to 34 are OS transistors, which allow the transistors 31 to 34 to have extremely low off-state current.

[0144] When writing data to the bit line LBL, the sense circuit 21 can apply a potential corresponding to the data from the bit line GBL to the bit line LBL by turning on the transistor 33. When reading data stored in the memory cell 41, the sense circuit 21 can read the data by applying a potential corresponding to the data to the gate of the transistor 31 via the bit line LBL, causing a current corresponding to the data to flow between the source and drain.

[0145] Fig. 16B shows a circuit block corresponding to the circuit diagram of the sense circuit 21 described in Fig. 16A. Fig. 16C shows a configuration example that combines the circuit block of the sense circuit 21 shown in Fig. 16B, the circuit configuration of the memory cell 41 described in Fig. 12B, and the circuit block of the global sense amplifier GSA shown in Fig. 14B.

[0146] 4B, the element layers 40_1 to 40_n, which can be stacked as described with reference to FIG. 4B, each include a plurality of memory cells 41. Each memory cell 41 includes the transistor M1 and the capacitor C1 described with reference to FIG. 12B.

[0147] The memory cell 41 can retain the charge stored in the capacitor C1 for a long period of time by turning off the transistor M1. The memory cell 41 can store binary data by, for example, corresponding the level of the potential of one electrode of the capacitor C1 to "1" or "0" depending on the amount of charge retained in the capacitor C1. When writing data, the memory cell 41 can apply a potential corresponding to the data from the bit line LBL to the capacitor C1 by turning on the transistor M1. When reading data, the memory cell 41 can extract the charge retained in the capacitor C1 to the bit line LBL by turning on the transistor M1.

[0148] When data is read from the memory cell 41, the charge held in the capacitor C1 is extracted to the bit line LBL, causing a change in the potential of the capacitor C1. In other words, when data is read from the memory cell 41, the stored data is destroyed. In other words, when data is read from the memory cell 41, a destructive read occurs. Therefore, after data is read from the memory cell 41, the data needs to be written back (refreshed).

[0149] The element layer 20 includes a sense circuit 21 and a sense circuit 21B. As shown in FIG. 16A , the sense circuit 21 includes transistors 32 to 34 in addition to a transistor M31 connected to a bit line LBL. The sense circuit 21 is connected to a global sense amplifier GSA via a bit line GBL. The sense circuit 21B has the same configuration as the sense circuit 21. In the description of the sense circuit 21B, the bit line GBL can be replaced with an inverted bit line GBLB, and the bit line LBL can be replaced with an inverted bit line LBLB.

[0150] It is preferable to provide a switching circuit between the global sense amplifier GSA and the sense circuit 21 and between the global sense amplifier GSA and the sense circuit 21B. In Fig. 16C, a switching circuit 24 is illustrated between the global sense amplifier GSA and the sense circuit 21 and between the global sense amplifier GSA and the sense circuit 21B. The switching circuit 24 switches the connection between the global sense amplifier GSA and the sense circuit 21 and between the global sense amplifier GSA and the sense circuit 21B during a data write-back operation. The switching circuit 24 can switch the path between the global sense amplifier GSA and the sense circuits 21 and 21B, allowing data with inverted logic to be written or read.

[0151] 17, an example of the operation of the memory device 100 having the sense circuit 21 will be described. Fig. 17 is a timing chart illustrating the operation of reading data stored in the memory cell 41 (the potential held in the capacitor C1) by the global sense amplifier GSA via the sense circuit 21.

[0152] In the following description of the operation example, as potentials corresponding to binary data, a potential corresponding to binary data "1" is a high power supply potential VDD (hereinafter may be abbreviated as VDD), and a potential corresponding to binary data "0" is a low power supply potential VSS (hereinafter may be abbreviated as VSS). VDD is a potential higher than VSS by at least a threshold voltage of a transistor. Note that VSS may be, for example, the ground potential GND. In the following description of the operation example, the potential of a signal is assumed to be an H level or an L level. The H level is a potential that, when applied to the gate of an n-channel transistor, turns the transistor conductive, and a potential that, when applied to the gate of a p-channel transistor, turns the transistor non-conductive. The L level is a potential that, when applied to the gate of an n-channel transistor, turns the transistor non-conductive, and a potential that, when applied to the gate of a p-channel transistor, turns the transistor conductive. The H level can be, for example, the same potential as VDD or a potential higher than VDD. The L level can be, for example, the same potential as VSS or a potential lower than VSS. In the following description of the operation example, for simplicity, the potential of all signals is described as being H level or L level, but the H levels of different signals can also be different potentials. The same applies to the description of the operation example in this embodiment (for example, FIGS. 17 and 20).

[0153] 17 shows the potentials (H level or L level) of the signal applied to the word line WL, the signal MUX, the signal WSE, the signal RE, the signal EQ, the signal EQB, and the column selection signal CSE at each time of operation. It also shows the potentials applied to the wiring SL, the wiring SAP, and the wiring SAN. It also shows the potential changes of the bit line LBL, the inverted bit line LBLB, the bit line GBL, and the inverted bit line GBLB when reading data "1" (Data 1) and when reading data "0" (Data 0).

[0154] The period from time T11 to time T13 is a period in which the threshold voltage is corrected. The period from time T13 to time T16 is a period in which data is read. The period from time T16 onwards is a period in which data is written back (refreshed).

[0155] Just before time T11, the signals MUX, WSE, and RE applied to the word line WL are all at L level. The potential of the line SL is a predetermined potential (e.g., VSS). The signal EQ is at H level, and the signal EQB is at L level. The column selection signal CSE is at L level. The potentials of the line SAP and the line SAN are both VDD. The potential VPRE is also VDD. At this time, the bit line GBL and the inverted bit line GBLB are each precharged to VDD. The bit line LBL and the inverted bit line LBLB are each floating and holding VDD or VSS. The capacitor C1 of the memory cell 41 is also held at VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of each operation from time T11 to time T16, unless otherwise specified, the potential of each wiring and each signal is maintained at the potential at the immediately preceding time.

[0156] At time T11, the signal MUX and the signal WSE go high. Then, the bit line GBL and the inverted bit line GBLB are precharged to VDD. Furthermore, the bit line LBL and the inverted bit line LBLB are precharged to VDD. The potential of the line SL becomes a predetermined potential between VDD and VSS. This predetermined potential affects the amount of current flowing through the transistor 31 in the operation at time T14, which will be described later. Therefore, the predetermined potential can be determined so that the amount of current becomes an appropriate value.

[0157] At time T12, the signal MUX goes low and the signal RE goes high, causing the potentials of the bit line LBL and the inverted bit line LBLB to drop to "the potential of the line SL plus the threshold voltage of the transistor 31" due to discharge to the line SL via the transistor 31 included in each of the sense circuits 21 and 21B.

[0158] At time T13, signals WSE and RE go low. This causes bit line LBL and inverted bit line LBLB to float. This causes potentials corresponding to the threshold voltages of transistors 31 included in sense circuit 21 and sense circuit 21B to be held on bit line LBL and inverted bit line LBLB, respectively. This allows the amount of current flowing through transistor 31 in the operation at time T14, which will be described later, to be corrected so that it is not affected by the threshold voltage of transistor 31. By performing such correction, the memory device 100 according to one embodiment of the present invention can improve the reliability of read data.

[0159] At time T13, the signal EQ goes low and the signal EQB goes high. Precharging of the bit line GBL and the inverted bit line GBLB stops. The bit line GBL and the inverted bit line GBLB each become floating.

[0160] Also, at time T13, the signal applied to the word line WL on the side of the memory cell 41 connected to the bit line LBL goes high. Then, charge sharing occurs between the bit line LBL and the capacitor C1. Therefore, the potential of the bit line LBL changes according to the data stored in the memory cell 41 (i.e., according to the potential held in the capacitor C1). This causes the potential of the bit line LBL and the potential of the capacitor C1 to become the same potential.

[0161] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1) (i.e., the potential held in the capacitor C1 is VDD), a signal applied to the word line WL goes high, causing the potential of the bit line LBL to rise and the potential of the capacitor C1 to fall. As a result, the potential of the bit line LBL and the potential of the capacitor C1 become the same potential. Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0) (i.e., the potential held in the capacitor C1 is VSS), a signal applied to the word line WL goes high, causing the potential of the bit line LBL to fall and the potential of the capacitor C1 to rise. As a result, the potential of the bit line LBL and the potential of the capacitor C1 become the same potential.

[0162] On the other hand, at time T13, the signal applied to the word line WL on the side of the memory cell 41 connected to the inverted bit line LBLB remains at the L level. That is, charge sharing is not performed on the inverted bit line LBLB. Therefore, the potential of the inverted bit line LBLB does not change.

[0163] Charge sharing changes the potential of the capacitor C1, which means that the data stored in the memory cell 41 is destroyed (destructive read). Therefore, the data is written back at time T16, which will be described later.

[0164] At time T14, signals MUX and RE go high. The potential of line SL goes high (e.g., VSS), the same as the potential immediately before time T11. Current flows through transistor 31 in sense circuit 21 and transistor 31 in sense circuit 21B in accordance with the potentials of bit line LBL and inverted bit line LBLB. This causes the potentials of bit line GBL and inverted bit line GBLB to gradually decrease. At this time, the difference between the potentials of bit line LBL and inverted bit line LBLB creates a difference between the amount of current flowing through transistor 31 in sense circuit 21 and the amount of current flowing through transistor 31 in sense circuit 21B. This difference in current amount corresponds to the potential of bit line LBL, which changes due to charge sharing in the operation at time T13 described above. In other words, the rate at which the potential of bit line GBL decreases varies depending on the potential of bit line LBL. Therefore, the potential of the bit line LBL can be converted into the potential difference between the bit line GBL and the inverted bit line GBLB.

[0165] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1), the amount of current flowing through the transistor 31 included in the sense circuit 21 is greater than the amount of current flowing through the transistor 31 included in the sense circuit 21B. Therefore, the rate at which the potential of the bit line GBL drops is faster than the rate at which the potential of the inverted bit line GBLB drops. The potential of the bit line GBL becomes lower than the potential of the inverted bit line GBLB.

[0166] Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0), the amount of current flowing through the transistor 31 included in the sense circuit 21 becomes smaller than the amount of current flowing through the transistor 31 included in the sense circuit 21B. Therefore, the rate at which the potential of the bit line GBL falls becomes slower than the rate at which the potential of the inverted bit line GBLB falls. As a result, the potential of the bit line GBL becomes higher than the potential of the inverted bit line GBLB.

[0167] At time T15, signal RE goes low. Furthermore, the potential of line SAN goes to VSS. Then, the global sense amplifier GSA operates, amplifying the potential difference between bit line GBL and inverted bit line GBLB, which occurred as a result of the operation at time T14 described above. This causes the potentials of bit line GBL and inverted bit line GBLB to be fixed at either VDD or VSS. In other words, reading of the data stored in memory cell 41 is completed.

[0168] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1), the potential of the bit line GBL becomes VSS and the potential of the inverted bit line GBLB becomes VDD. Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0), the potential of the bit line GBL becomes VDD and the potential of the inverted bit line GBLB becomes VSS.

[0169] At time T16, signal WSE goes high. Then, data is written back to memory cell 41 according to the data read from memory cell 41. In this case, it is preferable to use switching circuits 24 (FIG. 16B) provided between global sense amplifier GSA and sense circuit 21 and between global sense amplifier GSA and sense circuit 21B to switch the potentials of bit line GBL and bit line LBL to the same potential as the potential of inverted bit line GBLB established by the operation at time T15. This configuration allows the read potential to be written back to memory cell 41.

[0170] Specifically, for example, if the data stored in the memory cell 41 is "1" (data 1), the potential of the inverted bit line GBLB immediately before time T16 is VDD. Therefore, the potentials of the bit line GBL and the bit line LBL become VDD. Furthermore, VDD is written back to the memory cell 41. Alternatively, for example, if the data stored in the memory cell 41 is "0" (data 0), the potential of the inverted bit line GBLB immediately before time T16 is VSS. Therefore, the potentials of the bit line GBL and the bit line LBL become VSS. Furthermore, VSS is written back to the memory cell 41.

[0171] When writing data to the memory cell 41, the storage device 100 performs the same operation as the time T16 described above. For example, when writing data "1" to the memory cell 41, VDD is applied to the inverted bit line GBLB, as shown at time T16. Alternatively, when writing data "0" to the memory cell 41, VSS is applied to the inverted bit line GBLB, as shown at time T16.

[0172] (Configuration Example of Switching Circuit 24) FIG. 18 is a circuit diagram showing a specific example of the switching circuit 24 shown in FIG. 16C.

[0173] The switching circuit 24 is connected to the bit line GBL connected to the sense circuit 21, the bit line SA_GBL connected to the global sense amplifier GSA, the inverted bit line GBLB connected to the sense circuit 21B, and the inverted bit line SA_GBLB connected to the global sense amplifier GSA. The switching circuit 24 has a function of establishing a conductive state or a non-conductive state between the bit line GBL, the inverted bit line GBLB, the bit line SA_GBL, and the inverted bit line SA_GBLB. The switching circuit 24 also has a function of precharging each of the bit line GBL and the inverted bit line GBLB to a predetermined potential.

[0174] In the following description, the bit line GBL connected to the sense circuit 21 and the inverted bit line GBLB connected to the sense circuit 21B may be referred to as a bit line pair GBL-GBLB. Also, the bit line SA_GBL connected to the global sense amplifier GSA and the inverted bit line SA_GBLB may be referred to as a bit line pair SA_GBL-SA_GBLB.

[0175] The switching circuit 24 includes a transistor MT0, a transistor MT1, a transistor MT2, a transistor MT3, and a transistor MT4.

[0176] One of the source and drain of the transistor MT0 is connected to the bit line GBL. The other of the source and drain of the transistor MT0 is connected to the inverted bit line GBLB. The conductive state or non-conductive state of the transistor MT0 is controlled in response to a signal SW0.

[0177] One of the source and drain of the transistor MT1 is connected to the bit line GBL. The other of the source and drain of the transistor MT1 is connected to the bit line SA_GBL. The conductive state or non-conductive state of the transistor MT1 is controlled in response to a signal SW1.

[0178] One of the source and drain of the transistor MT2 is connected to the inverted bit line GBLB. The other of the source and drain of the transistor MT2 is connected to the inverted bit line SA_GBLB. The conductive state or non-conductive state of the transistor MT2 is controlled in response to a signal SW2.

[0179] One of the source and drain of the transistor MT3 is connected to the bit line GBL. The other of the source and drain of the transistor MT3 is connected to a terminal to which a potential VPRE2 is applied. The transistor MT3 has a function of precharging the bit line GBL to the potential VPRE2 in response to a signal SW3.

[0180] One of the source and drain of the transistor MT4 is connected to the inverted bit line GBLB. The other of the source and drain of the transistor MT4 is connected to a terminal to which a potential VPRE2 is applied. The transistor MT4 has a function of precharging the inverted bit line GBLB to the potential VPRE2 in response to a signal SW3.

[0181] 19A is a schematic diagram illustrating an example configuration of a memory cell 41, sense circuits 21 and 21B, a switching circuit 24, and a global sense amplifier GSA. In a memory device 100B shown in FIG. 19A , an element layer 20 having sense circuits 21 and 21B and a switching circuit 24, and an element layer 40 having a memory cell 41 are provided above an area where the global sense amplifier GSA and bit line pair DBL-DBLB described in FIGS. 2 and 18 are provided. The memory cell 41 is connected to the sense circuits 21 and 21B via a bit line pair LBL-LBLB. The sense circuits 21 and 21B are connected to the switching circuit 24 via a bit line pair GBL-GBLB. The switching circuit 24 is connected to the global sense amplifier GSA via a bit line pair SA_GBL-SA_GBLB.

[0182] 19B is a schematic diagram for explaining a transistor 51 provided in the element layer 40, a transistor 55 provided in the element layer 20, and a transistor 53 provided in the element layer 10 in the schematic diagram in which the element layer 10, the element layer 20, and the element layer 40 are stacked as shown in FIGS. 1, 19A, etc. Also shown in FIG. 19B are the bit line pair LBL-LBLB, sense circuits 21 and 21B, the bit line pair GBL-GBLB, the switching circuit 24, and the bit line pair SA_GBL-SA_GBLB shown in FIG.

[0183] The semiconductor layer 52 of the transistor 51 may be an oxide semiconductor (metal oxide), thereby forming the memory cell 41 including the OS transistor. The transistor 51 having an oxide semiconductor in the semiconductor layer 52 having a channel formation region may be referred to as a first transistor. The semiconductor layer 52 having an oxide semiconductor in the channel formation region may be referred to as a first semiconductor layer.

[0184] By using indium oxide for the semiconductor layer 56 of the transistor 55, the sense circuits 21 and 21B and the switching circuit 24 can have superior on-state current and frequency characteristics to those in the case where the above-described OS transistor is used. The transistor 55 having indium oxide in the semiconductor layer 56 having a channel formation region may be referred to as a second transistor. The semiconductor layer 56 having indium oxide in the channel formation region may be referred to as a second semiconductor layer.

[0185] By using silicon for the semiconductor layer 54 of the transistor 53, it is possible to provide a global sense amplifier GSA in the element layer 10 configured with the above-described Si transistor.

[0186] By arranging the element layer 40 in which the memory cells 41 are provided and the element layer 20 in which the sense circuits 21, 21B and the switching circuit 24 are provided on the element layer 10 in which the global sense amplifier GSA is provided, the storage capacity, i.e., the number of memory cells 41, can be increased compared to when the memory cells 41, the sense circuits 21, 21B, and the global sense amplifier GSA are arranged on the same layer.

[0187] 20, an example of the operation of the memory device 100B having the sense circuit 21 and the switching circuit 24 will be described. Fig. 20 is a timing chart illustrating the operation of reading data stored in the memory cell 41 (the potential held in the capacitor C1) by the global sense amplifier GSA via the sense circuit 21 and the switching circuit 24.

[0188] 20 shows the potentials (H level or L level) of the signal applied to the word line WL, the signal MUX, the signal WSE, the signal RE, the signal EQ, the signal EQB, and the column selection signal CSE at each time of operation. It also shows the potentials applied to the wiring SL, the wiring SAP, and the wiring SAN. It also shows the potential changes of the bit line LBL, the inverted bit line LBLB, the bit line GBL, and the inverted bit line GBLB when reading data "1" (Data 1) and when reading data "0" (Data 0).

[0189] The period from time T11 to time T13 is a period in which the threshold voltage is corrected. The period from time T13 to time T16 is a period in which data is read. The period from time T16 onwards is a period in which data is written back (refreshed). Note that the periods from time T11 to time T13 in which the threshold voltage is corrected may be omitted.

[0190] Immediately before time T11, the signals MUX, WSE, and RE applied to the word line WL are all set to the L level. The potential of the wiring SL is set to a predetermined potential (e.g., VSS). The signals SW0, SW1, SW2, and SW3 are all set to the L level. The signal EQ is set to the H level, and the signal EQB is set to the L level. The column selection signal CSE is set to the L level. The potentials of the wiring SAP and the wiring SAN are set to VDD. The potentials VPRE and VPRE2 are set to VDD. At this time, the bit line pair SA_GBL-SA_GBLB are precharged to VDD. The bit line pair GBL-GBLB is set to floating and is held at VDD or VSS. It is also assumed that the bit line pair LBL-LBLB is floating and holds VDD or VSS. It is also assumed that the capacitor C1 of the memory cell 41 holds VDD (a potential corresponding to data "1") or VSS (a potential corresponding to data "0"). In the description of the operations at time T11 to time T16, unless otherwise specified, it is assumed that the potentials of the wirings and signals at the immediately preceding time are maintained.

[0191] At time T11, signals SW1 and SW2 go high. Also at time T11, signals MUX and WSE go high. Then, the bit line GBL and the inverted bit line GBLB are precharged to VDD. Furthermore, the bit line LBL and the inverted bit line LBLB are precharged to VDD. The potential of the line SL becomes a predetermined potential between VDD and VSS. This predetermined potential affects the amount of current flowing through the transistor 31 in the operation at time T14, which will be described later. Therefore, the predetermined potential can be determined so that the amount of current becomes an appropriate value.

[0192] At time T12, the signal MUX goes low and the signal RE goes high, causing the potentials of the bit line LBL and the inverted bit line LBLB to drop to "the potential of the line SL plus the threshold voltage of the transistor 31" due to discharge to the line SL via the transistor 31 included in each of the sense circuits 21 and 21B.

[0193] At time T13, signals WSE and RE go low. This causes bit line LBL and inverted bit line LBLB to float. This causes potentials corresponding to the threshold voltages of transistors 31 included in sense circuit 21 and sense circuit 21B to be held on bit line LBL and inverted bit line LBLB, respectively. This allows the amount of current flowing through transistor 31 in the operation at time T14, which will be described later, to be corrected so that it is not affected by the threshold voltage of transistor 31. By performing such correction, the memory device 100 according to one embodiment of the present invention can improve the reliability of read data.

[0194] At time T13, the signal EQ goes low and the signal EQB goes high. Precharging of the bit lines SA_GBL and GBL and precharging of the inverted bit lines SA_GBLB and GBLB stop. The bit lines SA_GBL and GBL, and the inverted bit lines SA_GBLB and SA_GBLB become floating.

[0195] Also, at time T13, the signal applied to the word line WL on the side of the memory cell 41 connected to the bit line LBL goes high. Then, charge sharing occurs between the bit line LBL and the capacitor C1. Therefore, the potential of the bit line LBL changes according to the data stored in the memory cell 41 (i.e., according to the potential held in the capacitor C1). This causes the potential of the bit line LBL and the potential of the capacitor C1 to become the same potential.

[0196] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1) (i.e., the potential held in the capacitor C1 is VDD), a signal applied to the word line WL goes high, causing the potential of the bit line LBL to rise and the potential of the capacitor C1 to fall. As a result, the potential of the bit line LBL and the potential of the capacitor C1 become the same potential. Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0) (i.e., the potential held in the capacitor C1 is VSS), a signal applied to the word line WL goes high, causing the potential of the bit line LBL to fall and the potential of the capacitor C1 to rise. As a result, the potential of the bit line LBL and the potential of the capacitor C1 become the same potential.

[0197] On the other hand, at time T13, the signal applied to the word line WL on the side of the memory cell 41 connected to the inverted bit line LBLB remains at the L level. That is, charge sharing is not performed on the inverted bit line LBLB. Therefore, the potential of the inverted bit line LBLB does not change.

[0198] Charge sharing changes the potential of the capacitor C1, which means that the data stored in the memory cell 41 is destroyed (destructive read). Therefore, the data is written back at time T16, which will be described later.

[0199] At time T14, the signals MUX and RE go high. The potential of the line SL goes to the same potential (e.g., VSS) as the potential immediately before time T11. A current flows through the transistor 31 of the sense circuit 21 and the transistor 31 of the sense circuit 21B in accordance with the respective potentials of the bit line LBL and the inverted bit line LBLB. This causes the respective potentials of the bit line SA_GBL and the bit line GBL, and the inverted bit line SA_GBLB and the inverted bit line GBLB to gradually decrease. At this time, the difference between the potential of the bit line LBL and the inverted bit line LBLB causes a difference in the amount of current flowing through the transistor 31 of the sense circuit 21 and the amount of current flowing through the transistor 31 of the sense circuit 21B. This difference in current amount corresponds to the potential of the bit line LBL, which changes due to charge sharing in the operation at time T13 described above. That is, the speed at which the potentials of the bit lines SA_GBL and GBL drop varies depending on the potential of the bit line LBL. Therefore, the potential of the bit line LBL can be converted into a potential difference between the bit lines SA_GBL and GBL and the inverted bit lines SA_GBLB and GBLB.

[0200] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1), the amount of current flowing through the transistor 31 provided in the sense circuit 21 is greater than the amount of current flowing through the transistor 31 provided in the sense circuit 21B. Therefore, the rate at which the potential of the bit line SA_GBL drops is faster than the rate at which the potential of the inverted bit line SA_GBLB drops. The potential of the bit line SA_GBL becomes lower than the potential of the inverted bit line SA_GBLB.

[0201] Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0), the amount of current flowing through the transistor 31 included in the sense circuit 21 becomes smaller than the amount of current flowing through the transistor 31 included in the sense circuit 21B. Therefore, the rate at which the potentials of the bit line SA_GBL and the bit line GBL fall becomes slower than the rate at which the potentials of the inverted bit line SA_GBLB and the inverted bit line GBLB fall. As a result, the potentials of the bit line SA_GBL and the bit line GBL become higher than the potentials of the inverted bit line SA_GBLB and the inverted bit line GBLB.

[0202] At time T15, signal RE goes low. Furthermore, the potential of line SAN goes to VSS. Then, the global sense amplifier GSA operates, amplifying the potential difference between bit line SA_GBL and inverted bit line SA_GBLB, which occurred as a result of the operation at time T14 described above. This causes the potentials of bit line SA_GBL and inverted bit line SA_GBLB to be determined as either VDD or VSS. In other words, reading of the data stored in memory cell 41 is completed.

[0203] Specifically, for example, when the data stored in the memory cell 41 is "1" (data 1), the potential of the bit line SA_GBL becomes VSS and the potential of the inverted bit line SA_GBLB becomes VDD. Alternatively, for example, when the data stored in the memory cell 41 is "0" (data 0), the potential of the bit line SA_GBL becomes VDD and the potential of the inverted bit line SA_GBLB becomes VSS.

[0204] At time T16, signal SW0 goes high and signal SW1 goes low. Furthermore, signal WSE goes high. Then, an operation is performed to write data back to memory cell 41 in accordance with the data read from memory cell 41. That is, the potentials of bit line GBL and bit line LBL become the same as the potential of inverted bit line SA_GBLB established by the operation at time T15. Furthermore, this potential is written back to memory cell 41.

[0205] Specifically, for example, if the data stored in the memory cell 41 is "1" (data 1), the potential of the inverted bit line SA_GBLB immediately before time T16 is VDD. Therefore, the potentials of the bit line GBL and the bit line LBL become VDD. Furthermore, VDD is written back to the memory cell 41. Alternatively, for example, if the data stored in the memory cell 41 is "0" (data 0), the potential of the inverted bit line SA_GBLB immediately before time T16 is VSS. Therefore, the potentials of the bit line GBL and the bit line LBL become VSS. Furthermore, VSS is written back to the memory cell 41.

[0206] When writing data to the memory cell 41, the memory device 100B may do so in the same manner as the time T16 described above. For example, when writing data "1" to the memory cell 41, VDD may be applied to the inverted bit line SA_GBLB, as at time T16. Alternatively, when writing data "0" to the memory cell 41, VSS may be applied to the inverted bit line SA_GBLB, as at time T16.

[0207] As described above, a memory device according to one embodiment of the present invention controls the sense amplifier driver block and the word line side driver block to select one or more global sense amplifier blocks and read data. Therefore, the sense amplifiers included in the selected global sense amplifiers can be activated simultaneously or sequentially by switching between them. This allows output by switching the memory bandwidth (also called memory bandwidth).

[0208] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0209] In this embodiment, a cross-sectional structure example of an element layer including stacked OS transistors that can be applied to a memory device, etc. will be described. In this embodiment, an example of a cross-sectional schematic diagram that can be applied to a circuit configuration such as a NOSRAM or a DOSRAM will be described.

[0210] <Configuration Example of NOSRAM> Figure 21 shows a cross-sectional configuration example when a three-transistor NOSRAM circuit configuration is used. Figure 21 illustrates a case where an element layer MF is provided overlaid on an element layer LF, and element layers UF[1] and UF[2] are provided overlaid on the element layer MF. Figures 22A to 24D show examples of transistor structures applicable to OS transistors in the element layer MF or element layer LF. Figure 25A shows an example of the cross-sectional structure of an element layer UF[k]. Figure 25B shows an equivalent circuit diagram of Figure 25A.

[0211] The element layer LF is the element layer 10 described in the above embodiment 1. An element such as a Si transistor is provided in the element layer LF. The element layer MF is the element layer 20 described in the above embodiment 1. An element such as an OS transistor is provided in the element layer MF. The element layer UF is the element layer 40 described in the above embodiment 1. An element such as an OS transistor is provided in the element layer UF. The OS transistor included in the element layer UF can have a different structure from the OS transistor included in the element layer MF. This configuration allows transistors with different electrical characteristics to be stacked.

[0212] 21 illustrates a transistor 550 included in the element layer LF. The transistor 550 is provided over a substrate 311 and includes a conductive layer 316 functioning as a gate electrode, an insulating layer 315, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314 a and a low-resistance region 314 b functioning as a source region or a drain region.

[0213] Note that the transistor 550 can be a p-channel or n-channel transistor.

[0214] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0215] Note that the transistor 550 illustrated in FIG. 21 is just an example, and the structure is not limited to this example. An appropriate transistor may be used depending on the circuit configuration or the driving method.

[0216] A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between the element layer LF and the element layer MF, between the element layer MF and the element layer UF, or between the kth element layer UF and the k+1th element layer UF. Note that in the present embodiment and the like, the kth element layer UF may be referred to as element layer UF[k], and the k+1th element layer UF may be referred to as element layer UF[k+1]. Here, k is an integer greater than or equal to 1 and less than or equal to N.

[0217] In addition, multiple wiring layers can be provided depending on the design. In addition, in this specification and the like, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductive layer functions as the wiring and cases where a part of the conductive layer functions as the plug.

[0218] For example, an insulating layer 320, an insulating layer 322, an insulating layer 324, and an insulating layer 326 are stacked in this order as an interlayer film over the transistor 550. A conductive layer 328 or the like is embedded in the insulating layer 320 and the insulating layer 322. A conductive layer 330 or the like is embedded in the insulating layer 324 and the insulating layer 326. The conductive layer 328 and the conductive layer 330 function as contact plugs or wirings.

[0219] A wiring layer may be provided on the insulating layer 326 and the conductive layer 330. For example, in FIG. 21 , an insulating layer 350, an insulating layer 357, an insulating layer 352, and an insulating layer 354 are stacked in this order on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is formed in the insulating layer 350, the insulating layer 357, and the insulating layer 352. The conductive layer 356 functions as a contact plug or a wiring.

[0220] An insulating layer 514 included in the element layer MF is provided over the insulating layer 354. A conductive layer 358 is embedded in the insulating layer 514 and the insulating layer 354. The conductive layer 358 functions as a contact plug or a wiring. For example, a wiring functioning as a bit line and the transistor 550 are connected via the conductive layer 358, the conductive layer 356, the conductive layer 330, or the like.

[0221] The element layer MF is the element layer 20 described in Embodiment 1. A transistor 500B included in the element layer MF illustrated in FIG. 21 is an example of a transistor to which an OS transistor is applied. The transistor 500B included in the element layer MF can be applied to the transistors 31 to 34 included in the sense circuits 21 and 21B described in FIGS. 16A to 16C.

[0222] Here, a structural example of a transistor applicable to the transistor provided in the element layer MF will be described.

[0223] 22A and 22B are schematic cross-sectional views of an OS transistor that can be used as the transistor included in the element layer MF. A transistor 500 shown in FIGS. 22A and 22B can be replaced with the transistor 500B included in the element layer MF shown in FIG.

[0224] 22A and 22B , an insulating layer 516 is disposed over an insulating layer 514. The transistor 500 includes a conductive layer 503 disposed so as to be embedded in the insulating layer 516, an insulating layer 522 disposed over the insulating layer 516 and the conductive layer 503, an insulating layer 524 disposed over the insulating layer 522, a semiconductor layer 530 disposed over the insulating layer 524, conductive layers 542a and 542b disposed apart from each other on the semiconductor layer 530, an insulating layer 580 disposed over the conductive layers 542a and 542b and having an opening formed therebetween to overlap the conductive layers 542a and 542b, an insulating layer 545 disposed on a bottom surface and a side surface of the opening, and a conductive layer 560 disposed on the surface on which the insulating layer 545 is formed. The conductive layer 560 includes a conductive layer 560a provided inside the insulating layer 545 and a conductive layer 560b provided so as to be embedded inside the conductive layer 560a.

[0225] 22A and 22B , an insulating layer 544 is disposed between the semiconductor layer 530, the conductive layers 542a and 542b, and the insulating layer 580. An insulating layer 574 is disposed on the insulating layer 580, the conductive layer 560, and the insulating layer 545, and an insulating layer 581 is disposed on the insulating layer 574.

[0226] In the transistor 500, the conductive layer 560 functions as a gate electrode, the insulating layer 545 functions as a gate insulating film, and the conductive layers 542a and 542b function as a source electrode and a drain electrode, respectively. The conductive layer 560 may function as a first gate electrode. The conductive layer 503 may function as a second gate electrode. The insulating layers 522 and 524 function as second gate insulating films.

[0227] 22A and 22B , the second gate insulating film has a two-layer structure including insulating layers 522 and 524. However, the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the second gate insulating film is not limited to a stacked structure made of the same material, and may have a stacked structure made of different materials.

[0228] In the transistor 500, an oxide semiconductor layer is preferably used as the semiconductor layer 530 including the channel formation region. Semiconductor materials that can be used for the semiconductor layer 530 will be described later.

[0229] The channel formation region of a transistor using an oxide semiconductor for a semiconductor layer has a higher oxygen vacancy (V Ｏ It is preferable that the concentration of impurities such as hydrogen, nitrogen, and metal elements is low. In addition, hydrogen in the vicinity of the oxygen vacancy is replaced by a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ H) and generate electrons that become carriers. Therefore, in the channel formation region, V ＯIt is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0230] In addition, the source and drain regions of a transistor using an oxide semiconductor for a semiconductor layer have more oxygen vacancies than the channel formation region. Ｏ The source and drain regions of a transistor are n-type regions with a high carrier concentration and low resistance compared to the channel formation region, due to a high concentration of H or a high concentration of impurities such as hydrogen, nitrogen, and metal elements.

[0231] The band gap of the oxide semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using an oxide semiconductor with a wide band gap for the semiconductor layer, the off-state current of the transistor can be reduced. By using a transistor with a low off-state current for a memory cell, stored data can be retained for a long period of time. In other words, a refresh operation is not required or is performed very infrequently, and therefore the power consumption of the memory device can be sufficiently reduced.

[0232] 22A and 22B, the semiconductor layer 530 has a single-layer structure, but one embodiment of the present invention is not limited to this. For example, the semiconductor layer 530 can have a stacked structure of two or more layers.

[0233] 22A , when an oxide semiconductor is used for the semiconductor layer 530, a region 543a may be formed as a low-resistance region at the interface with the conductive layer 542a of the semiconductor layer 530 or in its vicinity. Similarly, a region 543b may be formed as a low-resistance region at the interface with the conductive layer 542b of the semiconductor layer 530 or in its vicinity. In this case, the region 543a and the region 543b function as a source region and a drain region, respectively. Furthermore, a channel formation region is formed in a region sandwiched between the region 543a and the region 543b.

[0234] 22A, the conductive layers 542a and 542b each have a single-layer structure, but this is not limited to this embodiment of the present invention. For example, the conductive layers 542a and 542b each can have a stacked structure of two or more layers.

[0235] 22A and 22B , the conductive layer 560 and the conductive layer 503 each have a two-layer structure, but one embodiment of the present invention is not limited to this. For example, the conductive layer 560 and the conductive layer 503 each may have a single-layer structure or a stacked structure of three or more layers.

[0236] The insulating layer 580 is provided over the conductive layers 542a and 542b with the insulating layer 544 interposed therebetween. The opening of the insulating layer 580 is formed to overlap the region between the conductive layers 542a and 542b. As a result, the conductive layer 560 is formed so as to be embedded in the opening of the insulating layer 580 and the region sandwiched between the conductive layers 542a and 542b.

[0237] When an oxide semiconductor is used for the semiconductor layer 530, the insulating layer 580 is preferably an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen). By performing heat treatment on the insulating layer 580 containing excess oxygen, oxygen is supplied from the insulating layer 580 to a channel formation region of the semiconductor layer 530, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor 500 and improve its reliability.

[0238] 22A and 22B show the insulating layer 545 as a single layer, one embodiment of the present invention is not limited to this. For example, the insulating layer 545 may have a stacked structure of two or more layers.

[0239] The insulating layer 544 is provided to cover the conductive layers 542a and 542b. The insulating layer 544 preferably has a barrier property against oxygen. With such a structure, the conductive layers 542a and 542b can be prevented from being oxidized.

[0240] An insulating layer 571a is disposed over the conductive layer 542a, and an insulating layer 571b is disposed over the conductive layer 542b. By providing the insulators 571a and 571b, it is possible to prevent the end portions of the conductive layers 542a and 542b from being excessively etched when the semiconductor film that becomes the semiconductor layer 530 and the conductive films that become the conductive layers 542a and 542b are collectively processed into island shapes. Therefore, it is possible to process minute transistors with high precision.

[0241] The insulating layer 574 preferably has a function of suppressing diffusion of impurities such as hydrogen. The insulating layer 574 also preferably has a function of capturing or fixing impurities such as hydrogen. With such a structure, diffusion of hydrogen into the semiconductor layer 530 can be suppressed. Furthermore, the hydrogen concentration in the semiconductor layer 530 can be reduced.

[0242] A conductive layer 540a is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571a, and a conductive layer 540b is disposed in openings formed in the insulating layers 581, 574, 580, 544, and 571b. The conductive layers 540a and 540b are disposed opposite each other with the conductive layer 560 interposed therebetween. The conductive layers 540a and 540b function as vias, contact plugs, or wiring.

[0243] 22A, the conductive layer 540a and the conductive layer 540b each have a two-layer structure, but one embodiment of the present invention is not limited to this. For example, the conductive layer 540a and the conductive layer 540b each may have a single-layer structure or a stacked structure of three or more layers.

[0244] The transistor 500 shown in FIGS. 22A and 22B is just an example, and the present invention is not limited to this configuration. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like.

[0245] With this structure, miniaturization or high integration can be achieved in a memory device including a transistor including an oxide semiconductor.

[0246] Note that a transistor that can be used in one embodiment of the present invention is not limited to the transistor 500 illustrated in FIGS. 22A and 22B . Structures different from those of the transistor illustrated in FIGS. 22A and 22B will be described in FIGS. 23A to 23D . FIG. 23A is a plan view of a transistor 500A that can be used as an OS transistor that can be used as a transistor included in the element layer MF. FIGS. 23B to 23D are cross-sectional views of the transistor 500A. The transistor 500A illustrated in FIGS. 23A to 23D can be replaced with the transistor 500B included in the element layer MF illustrated in FIG. 21.

[0247] 23B is a cross-sectional view of the portion indicated by the dashed-dotted line A1-A2 in FIG. 23A , and is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 23C is a cross-sectional view of the portion indicated by the dashed-dotted line A3-A4 in FIG. 23A , and is also a cross-sectional view of the transistor 500A in the channel width direction. FIG. 23D is a cross-sectional view of the portion indicated by the dashed-dotted line A5-A6 in FIG. 23A , and is also a cross-sectional view of the transistor 500A in the channel length direction. Here, the dashed-dotted line A5-A6 is perpendicular to the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4, and the dashed-dotted line A1-A2 and the dashed-dotted line A3-A4 are parallel to each other. Note that in the plan view of FIG. 23A , some elements are omitted for clarity, and some elements are shown transparently.

[0248] The transistor 500A includes an insulating layer 516 over a substrate (not shown), an insulator 521 over the insulating layer 516, an insulating layer 522 over the insulator 521, a semiconductor layer 530 over the insulating layer 522, conductive layers 542a and 542b over the semiconductor layer 530 and the insulating layer 522, an insulating layer 545 over the semiconductor layer 530, and a conductive layer 560 (conductive layers 560a and 560b) over the insulating layer 545. Note that hereinafter, the conductive layers 542a and 542b may be collectively referred to as conductive layers 542.

[0249] An insulator 575 is provided over the conductive layer 542, and an insulating layer 580 is provided over the insulator 575. The insulating layer 545 and the conductive layer 560 are disposed inside openings provided in the insulating layer 580 and the insulator 575. The openings reach the semiconductor layer 530, and the insulating layer 545 is in contact with the semiconductor layer 530 within the openings. An insulating layer 574 is provided over the insulating layer 580 and the conductive layer 560. An insulator 583 is provided over the insulating layer 574. An insulator 515 is provided under the insulating layer 516.

[0250] An insulator 541a is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540a is provided in contact with the side surface of the insulator 541a. The bottom surface of the conductive layer 540a is in contact with the top surface of the conductive layer 542a. An insulator 541b is provided in contact with the inner wall of an opening of the insulating layer 580 or the like, and a conductive layer 540b is provided in contact with the side surface of the insulator 541b. The bottom surface of the conductive layer 540b is in contact with the top surface of the conductive layer 542b. Note that hereinafter, the conductive layers 540a and 540b may be collectively referred to as the conductive layer 540. The insulators 541a and 541b may be collectively referred to as the insulator 541.

[0251] The semiconductor layer 530 has a region that functions as a channel formation region of the transistor 500A. The conductive layer 560 has a region that functions as a first gate electrode (upper gate electrode) of the transistor 500A. The insulating layer 545 has a region that functions as a first gate insulator of the transistor 500A.

[0252] The conductive layer 542a has a region functioning as one of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540a functions as a plug connected to the conductive layer 542a. The conductive layer 542b has a region functioning as the other of the source electrode and the drain electrode of the transistor 500A. The conductive layer 540b functions as a plug connected to the conductive layer 542b.

[0253] The semiconductor layer 530 is formed on and in contact with the insulating layer 522. The semiconductor layer 530 has a shape with a high aspect ratio (a shape in which the length in the height direction (H) is equal to or greater than the length of the base side (W) (H≧W)) in a cross-sectional view in the channel width direction. The semiconductor layer 530 having a shape with a high aspect ratio is sometimes referred to as having a fin-like shape.

[0254] Here, the aspect ratio of the semiconductor layer 530 in a cross-sectional view in the channel width direction refers to the ratio of the width L of the semiconductor layer 530 to the height H of the semiconductor layer 530. The aspect ratio of the semiconductor layer 530 is preferably as large as possible within a range in which the semiconductor layer 530 does not collapse during the manufacturing process of the transistor 500A. In the semiconductor layer 530, the height H of the semiconductor layer 530 is at least longer than the width L of the semiconductor layer 530. The height H of the semiconductor layer 530 is set to be more than 1 time and 400 times or less, preferably 2 times or more and 100 times or less, more preferably 5 times or more and 40 times or less, and even more preferably 10 times or more and 20 times or less, of the width L of the semiconductor layer 530.

[0255] In addition, in a cross-sectional view in the channel width direction, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably a right angle or a substantially right angle. For example, the angle formed between the side surface of the semiconductor layer 530 and the top surface of the insulating layer 522 is preferably 80° to 100°, more preferably 85° to 95°.

[0256] An insulating layer 545, a conductive layer 560, and a conductive layer 542 are provided to cover the semiconductor layer 530 having such a high aspect ratio. In the transistor 500A, the insulating layer 545 and a part of the conductive layer 560 are provided so as to sandwich the semiconductor layer 530 in two. As a result, in a cross-sectional view in the channel width direction, the semiconductor layer 530 and the conductive layer 560 are provided facing each other with the insulating layer 545 sandwiched between the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530. In other words, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the semiconductor layer 530 each function as a channel formation region. Therefore, compared to when the semiconductor layer 530 is formed in a planar shape, the channel width of the transistor 500A is larger by the side surface on the A1 side and the side surface on the A2 side of the semiconductor layer 530.

[0257] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 500A can be improved. This makes it possible to provide a transistor with high operating speed. Furthermore, the operating speed of a memory device using the transistor can be increased. Furthermore, in the above structure, by providing the semiconductor layer 530, the channel width can be increased without increasing the area occupied by the transistor 500A. This enables miniaturization or high integration of the transistor. Furthermore, by using the above structure, the area where the side surfaces of the conductive layer 560 and the semiconductor layer 530 face each other is increased, so that the threshold voltage can be controlled to make the transistor 500A normally off.

[0258] The upper portion of the semiconductor layer 530 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulating layer 545 and the conductive layer 542 near the upper portion of the semiconductor layer 530.

[0259] Because the semiconductor layer 530 has a high aspect ratio, it is preferably formed in the shape of a sidewall on the side surface of a pillar made of an insulator. Therefore, it is preferable to form the semiconductor layer 530 using the ALD method, which has good coverage. Furthermore, when the semiconductor layer 530 has a stacked structure, it is preferable to form at least one layer, preferably the layer in contact with the pillar, using the ALD method.

[0260] 23A , by forming the semiconductor layers 530 in a sidewall shape in contact with the side surfaces of the plurality of pillars, the plurality of semiconductor layers 530 can be formed simultaneously. By forming the plurality of semiconductor layers 530 in this manner, the distance between the semiconductor layers 530 can be set in accordance with the size and shape of the pillar. Therefore, the distance between the semiconductor layers 530 can be reduced, the area occupied by the transistor 500A can be reduced, and high integration of the transistors can be achieved.

[0261] Since the semiconductor layer 530 is formed in contact with the pillar and in a sidewall shape, the top surface of the semiconductor layer 530 has a circumferential shape (which can also be referred to as a frame shape, an annular shape, a doughnut shape, or a closed curve shape) with both ends coinciding, as shown in FIG. 23A . The semiconductor layer 530 can also have a shape with an opening in the center. Note that in FIG. 23A , the top surface of the semiconductor layer 530 is line-symmetric about the center A1-A2; however, one embodiment of the present invention is not limited to this. For example, the top surface of the semiconductor layer 530 may have an asymmetric shape.

[0262] The structure shown in FIG. 23A has two pillars arranged in the A1-A2 direction, and a circumferential semiconductor layer 530 formed in contact with the side surface of each pillar. As shown in FIG. 23A , the semiconductor layer 530 preferably overlaps with the conductive layer 560 at two or more locations in a top view. That is, the semiconductor layer 530 has two or more overlapping regions with the conductive layer 560. With this structure, as shown in FIG. 23B , multiple fin-shaped semiconductor layers 530 are formed in a cross-sectional view in the channel width direction. Each of the multiple fin-shaped semiconductor layers 530 functions as a channel formation region. That is, the transistor 500A functions as a multi-channel transistor. Therefore, the channel width of the transistor 500A can be further increased.

[0263] 23A to 23D can also be configured such that a conductive layer 503 is provided under an insulator 521, as illustrated in a transistor 500B in Figures 24A to 24D . The transistor 500B included in the element layer MF in Figure 21 is an example in which the transistor 500B in Figures 24A to 24D is used.

[0264] 24A to 24D , the conductive layer 503 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 500B. The insulating layer 522 and the insulator 521 each have a region that functions as a second gate insulator of the transistor 500B. Here, FIGS. 24A to 24D correspond to FIGS. 23A to 23D , and therefore the above can be referred to for detailed configurations.

[0265] In the transistor 500B, the conductive layer 503 is arranged to overlap with the semiconductor layer 530 and the conductive layer 560. Here, the conductive layer 503 is preferably provided so as to be embedded in an opening formed in the insulating layer 516. Furthermore, the conductive layer 503 is preferably provided to extend in the channel width direction as shown in FIGS. 24A and 24B . With this structure, when a plurality of transistors are provided, the conductive layer 503 functions as a wiring.

[0266] 24B and 24D , the conductive layer 503 preferably includes a conductive layer 503a and a conductive layer 503b. The conductive layer 503a is provided in contact with the bottom surface and sidewall of the opening. The conductive layer 503b is provided so as to fill a recess in the conductive layer 503a formed along the opening. Here, the height of the upper surface of the conductive layer 503 coincides or substantially coincides with the height of the upper surface of the insulating layer 516.

[0267] Here, the conductive layer 503a contains hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ It is preferable to have a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms, etc. Alternatively, it is preferable to have a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0268] By using a conductive material that can reduce hydrogen diffusion for the conductive layer 503a, impurities such as hydrogen contained in the conductive layer 503b can be prevented from diffusing into the semiconductor layer 530 through the insulating layer 516 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductive layer 503a, oxidation of the conductive layer 503b and a decrease in conductivity can be suppressed. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer 503a can have a single-layer structure or a stacked-layer structure of the above conductive materials. For example, the conductive layer 503a preferably contains titanium nitride.

[0269] The conductive layer 503b is preferably formed using a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0270] The conductive layer 503 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500B can be controlled by changing the potential applied to the conductive layer 503 independently of the potential applied to the conductive layer 560. In particular, applying a negative potential to the conductive layer 503 can increase the Vth of the transistor 500B and reduce its off-state current. Therefore, applying a negative potential to the conductive layer 503 can reduce the drain current when the potential applied to the conductive layer 560 is 0 V compared to when a negative potential is not applied.

[0271] The electrical resistivity of the conductive layer 503 is designed in consideration of the potential applied to the conductive layer 503, and the film thickness of the conductive layer 503 is set to match the electrical resistivity. The film thickness of the insulating layer 516 is approximately the same as that of the conductive layer 503. Here, it is preferable to make the film thicknesses of the conductive layer 503 and the insulating layer 516 thin within the range permitted by the design of the conductive layer 503. By making the film thickness of the insulating layer 516 thin, the absolute amount of impurities such as hydrogen contained in the insulating layer 516 can be reduced, and therefore, the diffusion of the impurities into the semiconductor layer 530 can be suppressed.

[0272] Note that although the above describes a stacked structure of the conductive layer 503a and the conductive layer 503b, one embodiment of the present invention is not limited thereto, and the conductive layer 503 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductive layer 503 has a three-layer stacked structure, the stacked structure of the conductive layer 503a and the conductive layer 503b may further include a conductor made of a material similar to that of the conductive layer 503a provided over the conductive layer 503b. In this case, the conductor may be formed so that the top surface of the conductive layer 503b is lower than the top of the conductive layer 503a and fills a recess formed by the conductive layer 503a and the conductive layer 503b.

[0273] The above is a description of an example of the structure of a transistor that can be applied to the transistor provided in the element layer MF. Note that the transistor that can be provided in the element layer MF can also be applied to the element layer UF.

[0274] The element layer UF is the element layer 40 described in the first embodiment. As shown in Fig. 25A, the memory cell 41E shown in the element layer UF in Fig. 21 has a transistor M2, a transistor M3, and a transistor M1 on an insulating layer 514. The memory cell 41E shown in the element layer UF in Fig. 21 can be a three-transistor NOSRAM, and corresponds to the memory cell 41E shown in Fig. 13D.

[0275] The transistor 500 described in Figures 22A and 22B can be applied to the transistors M1 to MT3 shown in Figures 21 and 25A. Alternatively, the transistor 500A described in Figures 23A to 23D or the transistor 500B described in Figures 24A to 24D can also be applied.

[0276] 21 and 25A share a single island-shaped semiconductor layer 530. In other words, a portion of the island-shaped semiconductor layer 530 functions as a channel formation region for the transistor M2, and another portion functions as a channel formation region for the transistor M3. The source of the transistor M2 and the drain of the transistor M3, or the drain of the transistor M2 and the source of the transistor M3, are shared. Therefore, the area occupied by the transistors M2 and M3 is smaller than when the transistors M2 and M3 are provided independently.

[0277] <Configuration Example of DOSRAM> Figure 26 shows a cross-sectional configuration example when a DOSRAM circuit configuration is used. Figure 26 illustrates a case in which an element layer MF is provided overlapping an element layer LF, and element layers UF[1] and UF[2] are provided overlapping an element layer MF. Figure 27A also shows an example cross-sectional structure of element layer UF[k]. Figure 27B also shows an equivalent circuit diagram of Figure 27A.

[0278] 26, each of the multiple element layers UF has multiple memory cells 41. In each of the element layers UF[1] and UF[2] shown in FIG. 26, two memory cells 41A can be connected to one bit line BL, as shown in FIG. 27A. The memory cell 41A shown in FIG. 26 has a transistor M1 and a capacitor C1. In the memory cell 41A shown in FIG. 26, the capacitor C1 is provided below the transistor M1. An OS transistor can be used as the transistor M1. The memory cell 41A shown in the element layer UF in FIG. 26 can be a one-transistor DOSRAM and corresponds to the memory cell 41A shown in FIG. 13A.

[0279] By stacking the element layer UF having multiple memory cells 41A on the element layers LF and MF, the signal propagation distance between the circuits can be shortened, and the operation of the memory device can be made faster. Furthermore, the number of wirings between the circuits can be increased, and the bandwidth (also called memory bandwidth) of the memory device can be improved. Therefore, the memory circuit can be used for applications such as high bandwidth memory (HBM).

[0280] Furthermore, conductive layers 363c and 361 are embedded in the interlayer film between the element layer MF and the element layer UF[1]. Furthermore, in each of the multiple element layers UF, a conductive layer 365 is embedded in the insulating layer 180, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 366 is embedded in the insulating layer 180 and the insulating layer 280, which will be described later. Furthermore, in each of the multiple element layers UF, a conductive layer 367 is embedded in the semiconductor layer 270, the insulating layer 250, and the insulating layer 285, which will be described later. The conductive layers 363c, 365, 366, and 367 function as vias, contact plugs, or wiring.

[0281] Note that the structure of the transistor 550 described with reference to FIG. 21 can be applied to the transistor 550 included in the element layer LF illustrated in FIG.

[0282] Note that the structure of the transistor 500B described with reference to FIG. 21 can be applied to the transistor 500B included in the element layer MF illustrated in FIG.

[0283] Next, a configuration example of the memory cells 41A included in the plurality of element layers UF shown in FIG. 26 will be described.

[0284] Fig. 28A is a plan view showing an example of the configuration of a memory cell 41A and its periphery included in each of multiple element layers UF. Fig. 28B is a plan view in which some of the components shown in Fig. 28A are omitted. Fig. 28C is a cross-sectional view taken along dashed dotted line A1-A2 shown in Fig. 28A. Note that in Fig. 28A, some of the components of the transistor VM1, such as the insulating layer 250, are omitted. Furthermore, some of the components, such as the insulating layer, are omitted in the plan views of subsequent transistors as well.

[0285] 28A to 28C, the transistor VM1 corresponds to the transistor M1 in FIG. 26, and the capacitor VC1 corresponds to the capacitor C1 in FIG.

[0286] In FIG. 28C, insulating layer 160 is disposed on a substrate (not shown), insulating layer 180 is disposed on insulating layer 160, insulating layer 280 is disposed on insulating layer 180, and insulating layer 285 is disposed on insulating layer 280.

[0287] A conductive layer 110 is provided on the insulating layer 160. As an example, the conductive layer 110 can be a wiring PL extending in the Y direction.

[0288] An opening 601 is provided in a region of the insulating layer 180 that overlaps with the conductive layer 110. The conductive layer 115 is provided so as to be in contact with the bottom surface and sidewall of the opening 601. That is, the conductive layer 115 has a region in contact with the top surface of the conductive layer 110 and a region in contact with the side surface of the insulating layer 180 in the opening 601. Note that in FIG. 28C , the conductive layer 115 has a region in contact with the top surface of the insulating layer 180.

[0289] An insulating layer 130 is provided on the insulating layer 180 and the conductive layer 115. A conductive layer 220 is provided on the insulating layer 130. The conductive layer 220 is provided so as to fill the opening 601.

[0290] The capacitor VC1 includes a conductive layer 115, a conductive layer 220, and an insulating layer 130.

[0291] In the capacitor VC1, the conductive layer 115 functions as one of a pair of electrodes, the conductive layer 220 functions as the other of the pair of electrodes, and the insulating layer 130 functions as a dielectric sandwiched between the pair of electrodes.

[0292] The transistor VM1 is provided above the capacitor VC1. The transistor VM1 includes a conductive layer 220, a conductive layer 240, a semiconductor layer 270, an insulating layer 250, and a conductive layer 260.

[0293] In the transistor VM1, the conductive layer 260 functions as a gate electrode, and the insulating layer 250 functions as a gate insulating film. The conductive layer 220 and the conductive layer 240 function as a source electrode and a drain electrode, respectively. As described above, the conductive layer 220 also functions as the other of the pair of electrodes of the capacitor VC1.

[0294] The entire region of the semiconductor layer 270 that faces the gate electrode via the gate insulating film between the source electrode and the drain electrode functions as a channel formation region. The region of the semiconductor layer 270 that contacts the source electrode functions as a source region, and the region that contacts the drain electrode functions as a drain region.

[0295] The insulating layer 280 can function as an interlayer insulating layer. The interlayer insulating layer here can be an interlayer film for separating the source electrode and the gate electrode of the transistor VM1.

[0296] The conductive layer 240 is provided on the insulating layer 280. The insulating layer 280 has an opening 602 that reaches the conductive layer 220. The conductive layer 240 has an opening 603 that reaches the opening 602. That is, the opening 603 has a region that overlaps with the opening 602.

[0297] 28A shows conductive layers 220, 240, 260, openings 602, and 603 as components of the transistor VM1. Here, Fig. 28B shows a configuration example in which the conductive layer 260 is omitted from the components shown in Fig. 28A. That is, Fig. 28B shows the conductive layers 220, 240, openings 602, and openings 603.

[0298] 28A and 28B show an example in which the shapes of the openings 602 and 603 are each circular in a plan view. By making the planar shapes of the openings 602 and 603 circular, the processing accuracy when forming the openings 602 and 603 can be improved, and the openings 602 and 603 can be formed in very small sizes. This allows for miniaturization or high integration of memory cells. Note that in this specification and the like, "circular" is not limited to a perfect circle. For example, the planar shapes of the openings 602 and 603 may be elliptical or may be shapes including curves. Alternatively, they may be polygonal, or may be polygonal shapes with rounded corners.

[0299] The description of the shapes of the openings 602 and 603 can also be applied to the opening 601 .

[0300] The conductive layer 240 is preferably not provided inside the opening 602. In other words, the conductive layer 240 is preferably not in contact with the side surface of the insulating layer 280 on the opening 602 side. With this structure, the opening 603 and the opening 602 can be formed at the same time, thereby simplifying the process.

[0301] 28C shows an example in which the bottom edge of conductive layer 240 in opening 603 coincides with or roughly coincides with the top edge of insulating layer 280 in opening 602. In this specification and the like, the bottom surface of conductive layer 240 refers to the surface on the insulating layer 280 side. The top surface of insulating layer 280 refers to the surface on the conductive layer 240 side.

[0302] Incidentally, "the edges are aligned or approximately aligned" can also be said to mean that the edges are aligned or approximately aligned. When the edges are aligned or approximately aligned, and when the planar shapes are aligned or approximately aligned, it can be said that at least a portion of the contours of the stacked layers overlap in a planar view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer. In these cases, it is also said that the edges are approximately aligned or the planar shapes are approximately aligned.

[0303] Hereinafter, an opening including openings 602 and 603 may be referred to as opening 290. That is, opening 290 reaching conductive layer 220 is provided in insulating layer 280 and conductive layer 240. Opening 602 is a part of opening 290, and opening 603 is another part of opening 290.

[0304] At least a portion of the semiconductor layer 270 is disposed in the opening 290. In the opening 290, the semiconductor layer 270 has a region in contact with a side surface of the conductive layer 240, a region in contact with a side surface of the insulating layer 280, and a region in contact with the top surface of the conductive layer 220. The semiconductor layer 270 has a region in contact with the top surface of the conductive layer 240.

[0305] At least a portion of the insulating layer 250 is disposed in the opening 290. The insulating layer 250 is provided on the semiconductor layer 270 and the insulating layer 280. The insulating layer 250 has a region in contact with the top surface of the semiconductor layer 270, a region in contact with the side surface of the semiconductor layer 270, a region in contact with the side surface of the conductive layer 240, and a region in contact with the top surface of the insulating layer 280.

[0306] The conductive layer 260 is provided on the insulating layer 250, and has a region in contact with the upper surface of the insulating layer 250. The conductive layer 260 is provided so as to fill the opening 290. The conductive layer 260 is provided so as to fill a recess in the insulating layer 250 that reflects the shape of the opening 290. The conductive layer 260 has a region that overlaps with the semiconductor layer 270, with the insulating layer 250 interposed therebetween.

[0307] 28C illustrates an example in which the conductive layer 260 has a region overlapping with the conductive layer 240 with the insulating layer 250 and the semiconductor layer 270 interposed therebetween; however, one embodiment of the present invention is not limited to this. For example, the conductive layer 260 may be provided so as not to overlap with the conductive layer 240. With such a structure, parasitic capacitance generated between the conductive layer 260 and the conductive layer 240 can be reduced. Therefore, the operation speed of the memory cell can be improved.

[0308] The transistor VM1 is configured such that the direction of the channel length is not substantially parallel to the substrate (not shown) but is along the sidewall of an opening 602 provided in the insulating layer 280. In this specification and the like, such a transistor may be referred to as a vertical transistor.

[0309] In a vertical transistor, the source region, the channel formation region, and the drain region can at least partially overlap each other in a plan view, which allows the area occupied by the vertical transistor (also referred to as a footprint) to be reduced.Furthermore, the vertical transistor has a structure that allows the channel length to be reduced and the channel width to be increased, which allows the on-resistance to be reduced (the on-current to be increased).

[0310] FIG. 28A shows an example in which the conductive layer 240 extends in a direction perpendicular to the conductive layers 110 and 260 .

[0311] Here, an enlarged view of the semiconductor layer 270 and its vicinity in Fig. 28C is shown in Fig. 29A, and a cross-sectional view in the XY plane including the conductive layer 240 is shown in Fig. 29B.

[0312] As shown in FIG. 29A, the semiconductor layer 270 has a region 270i, and regions 270na and 270nb that are provided so as to sandwich the region 270i.

[0313] Region 270na is a region of semiconductor layer 270 that contacts conductive layer 220. Region 270nb is a region of semiconductor layer 270 that contacts conductive layer 240. Region 270na and region 270nb each function as a source region or a drain region of transistor VM1. As shown in FIG. 29B , conductive layer 240 contacts the entire outer periphery of semiconductor layer 270. Therefore, the source region or drain region of transistor VM1 can be formed around the entire outer periphery of a portion of semiconductor layer 270 that is formed in the same layer as conductive layer 240.

[0314] Region 270i is a region in the semiconductor layer 270 that is sandwiched between regions 270na and 270nb. Region 270i functions as a channel formation region of transistor VM1. That is, the channel formation region of transistor VM1 is formed in a part of the semiconductor layer 270 that is located in a region between the conductive layer 220 and the conductive layer 240. It can also be said that the channel formation region of transistor VM1 is located in a region in contact with the insulating layer 280 or in a region in the vicinity of the insulating layer 280 in the semiconductor layer 270.

[0315] The channel length of the transistor VM1 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor VM1 is determined by the thickness of the insulating layer 280 on the conductive layer 220. In FIG. 29A, the channel length L of the transistor VM1 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the edge of the region where the semiconductor layer 270 and the conductive layer 220 contact each other and the edge of the region where the semiconductor layer 270 and the conductive layer 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 280 on the opening 602 side in a cross-sectional view.

[0316] In a planar transistor, the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulating layer 280. Therefore, the channel length of the transistor VM1 can be made into an extremely fine structure that is equal to or less than the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-state current of the transistor VM1, thereby improving the frequency characteristics. Therefore, a memory device with high operating speed can be provided.

[0317] Furthermore, as described above, the channel formation region, the source region, and the drain region can be formed in the opening 290. This reduces the area occupied by the transistor VM1 compared to a planar transistor in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows for higher integration of the memory device, thereby increasing the memory capacity per unit area.

[0318] Furthermore, in the XY plane including the channel formation region of the semiconductor layer 270, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are arranged concentrically, as in FIG. 29B . Therefore, the side surface of the centrally located conductive layer 260 faces the side surface of the semiconductor layer 270 via the insulating layer 250. That is, in a top view, the entire periphery of the semiconductor layer 270 forms the channel formation region. In this case, for example, the channel width of the transistor VM1 is determined by the outer periphery of the semiconductor layer 270. In other words, it can be said that the channel width of the transistor VM1 is determined by the maximum width of the opening 602. In FIGS. 29A and 29B, the maximum width D of the opening 602 is indicated by a double-headed, dashed arrow. In FIG. 29B, the channel width W of the transistor VM1 is indicated by a double-headed, dashed arrow. By increasing the maximum width D of the opening 602, the channel width per unit area can be increased, thereby increasing the on-current.

[0319] When the opening 602 is formed using photolithography, the maximum width D of the opening 602 is set by the exposure limit of photolithography. The maximum width D of the opening 602 is set by the film thickness of each of the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 provided in the opening 602. The maximum width D of the opening 602 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. When the opening 602 is circular in top view, the maximum width D of the opening 602 corresponds to the diameter of the opening 602, and the channel width W can be calculated as "D × π".

[0320] The maximum width D of the opening 602 may be calculated appropriately according to the shape of the opening 602 in a planar view. For example, if the opening 602 is rectangular in a planar view, the maximum width of the opening 602 may be the length of the diagonal of the rectangle. Alternatively, for example, if the opening 602 is elliptical, polygonal, or polygonal with rounded corners in a planar view, the maximum width of the opening 602 may be the diameter of the smallest circle (also referred to as the minimum encompassing circle) that encompasses the shape of the opening 602 in a planar view.

[0321] In the memory device of one embodiment of the present invention, the channel length L of the transistor VM1 is preferably smaller than at least the channel width W of the transistor VM1. The channel length L of the transistor VM1 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor VM1. With such a structure, a transistor with favorable electrical characteristics and high reliability can be realized.

[0322] Furthermore, by forming the opening 602 so as to have a substantially circular shape in top view, the semiconductor layer 270, the insulating layer 250, and the conductive layer 260 are provided concentrically. This makes the distance between the conductive layer 260 and the semiconductor layer 270 substantially uniform, allowing a gate electric field to be applied to the semiconductor layer 270 substantially uniformly.

[0323] 29A and the like, the opening 602 is provided so that the side surface of the opening 602 is perpendicular to the top surface of the conductive layer 220; however, one embodiment of the present invention is not limited to this. For example, the side surface of the opening 602 may have a tapered shape.

[0324] In this specification and the like, the term "tapered shape" refers to a shape in which at least a part of a side surface of a structure is inclined with respect to a substrate surface. For example, it is preferable that the structure has a region in which the angle between the inclined side surface and the substrate surface (also referred to as the taper angle) is less than 90°.

[0325] 28C , a portion of insulating layer 250 is located outside opening 603, i.e., on insulating layer 280. In this case, insulating layer 250 preferably covers the side edges of conductive layer 240. This can prevent conductive layer 260 and conductive layer 240 from shorting out.

[0326] The semiconductor layer 270 can be a single layer or a stack of semiconductors that can be used for the semiconductor layer 530. For the structure of the semiconductor layer 270, the structure of the semiconductor layer 530 can also be referred to.

[0327] The semiconductor layer 270 preferably has layered crystals that are approximately parallel to the side surface of the insulating layer 280 in the opening 602. With this configuration, the layered crystals of the semiconductor layer 270 are formed approximately parallel to the channel length direction of the transistor VM1, thereby increasing the on-state current of the transistor.

[0328] When the semiconductor layer 270 and the conductive layer 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the resistance of a region 270na of the semiconductor layer 270 decreases. When the semiconductor layer 270 comes into contact with the conductive layer 220, the resistance of the semiconductor layer 270 and the conductive layer 220 decreases, thereby reducing the contact resistance between the semiconductor layer 270 and the conductive layer 220. Similarly, when the semiconductor layer 270 and the conductive layer 240 come into contact with each other, the resistance of a region 270nb of the semiconductor layer 270 decreases. Therefore, the contact resistance between the semiconductor layer 270 and the conductive layer 240 can be reduced.

[0329] The conductive layer 240 can have a stacked structure of a first conductive layer and a second conductive layer over the first conductive layer. In this case, the first conductive layer can be formed using a conductive material with high conductivity, and the second conductive layer can be formed using a conductive material containing oxygen. When an oxide semiconductor is used for the semiconductor layer 270, the contact resistance between the second conductive layer of the conductive layer 240 and the semiconductor layer 270 can be reduced by using a conductive material containing oxygen for the second conductive layer of the conductive layer 240 that is in contact with the semiconductor layer 270, thereby suppressing a decrease in the on-state current of the transistor VM1 due to the contact resistance. For example, tungsten can be used for the first conductive layer of the conductive layer 240, and indium tin oxide containing silicon can be used for the second conductive layer of the conductive layer 240.

[0330] The conductive layer 220 has a recessed portion at a position overlapping with the opening 602. The semiconductor layer 270 is in contact with the bottom and side surfaces of the recessed portion of the conductive layer 220. Note that the recessed portion of the conductive layer 220 may be regarded as part of the opening 290.

[0331] By providing a recess in the position where the conductive layer 220 overlaps with the opening 602, the height of the bottom surface of the insulating layer 250 and the height of the bottom surface of the conductive layer 260 in the opening 290 can be made lower than the height of the top surface of the conductive layer 220 that is in contact with the insulating layer 280, with the top surface of the insulating layer 160 as the reference, compared to when the recess is not provided. Here, the height of each surface can be determined with the surface on which the memory cell or transistor is formed as the reference. Here, the top surface of the insulating layer 160 is used as the reference. The surface used as the reference is not particularly limited, and may be, for example, the top surface of a substrate on which the memory cell or transistor is provided as the reference.

[0332] This increases the contact area between the conductive layer 220 and the semiconductor layer 270, thereby reducing the contact resistance between the conductive layer 220 and the semiconductor layer 270. Therefore, a decrease in the on-state current of the transistor VM1 due to the contact resistance between the conductive layer 220 and the semiconductor layer 270 can be suppressed. Furthermore, a gate electric field is more easily applied to the channel formation region of the semiconductor layer 270, thereby improving the electrical characteristics of the transistor VM1. Furthermore, a gate electric field is more easily applied to the region of the semiconductor layer 270 that is in contact with the conductive layer 220, thereby increasing the on-state current of the transistor VM1. Furthermore, whether the conductive layer 220 or the conductive layer 240 is used as the drain electrode, the electrical characteristics of the transistor VM1 can be improved.

[0333] A conductive material containing oxygen is preferably used for the conductive layer 220. When an oxide semiconductor is used for the semiconductor layer 270, the use of a conductive material containing oxygen for the conductive layer 220 can reduce contact resistance between the semiconductor layer 270 and the conductive layer 220.

[0334] Alternatively, the conductive layer 220 may have a structure in which tungsten is stacked under a conductive material containing oxygen. By providing tungsten in this manner, the conductivity of the conductive layer 220 can be improved.

[0335] The insulating layers 280 and 285 preferably have a low dielectric constant because they function as interlayer films. By using a material with a low dielectric constant as the interlayer film, the capacitance value of parasitic capacitance generated between wirings can be reduced.

[0336] The concentration of impurities such as water and hydrogen in the insulating layer 280 is preferably reduced, which can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 270.

[0337] An insulator containing excess oxygen is preferably used for the insulating layer 280. By performing heat treatment on the insulating layer 280 containing excess oxygen, oxygen is supplied from the insulating layer 280 to the channel formation region of the semiconductor layer 270, and oxygen vacancies and V Ｏ It is possible to reduce H. This makes it possible to stabilize the electrical characteristics of the transistor VM1 and improve reliability.

[0338] <Constituent Materials of Storage Device> Constituent materials that can be used for the storage device will be described below.

[0339] [Substrate] Substrates that can be used in memory devices include, for example, insulating substrates, semiconductor substrates, or conductive substrates. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include those having an insulating region within the semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Other examples include substrates having a metal nitride or a metal oxide. Examples of other substrates include an insulating substrate with a conductor or semiconductor provided thereon, a semiconductor substrate with a conductor or insulator provided thereon, and a conductive substrate with a semiconductor or insulator provided thereon. Alternatively, a substrate having elements provided thereon may be used, such as a capacitor, a resistor, a switch, a light-emitting element, a memory element, and the like.

[0340] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, all of which have insulating properties.

[0341] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may occur due to thinner gate insulators. Using a high-k material for the insulator that functions as the gate insulator allows for lower voltage operation of the transistor while maintaining the physical film thickness. It also allows for thinner equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator. On the other hand, using a material with a low dielectric constant for the insulator that functions as the interlayer film can reduce the capacitance value of the parasitic capacitance that occurs between wiring. Therefore, it is advisable to select materials according to the insulator's function. Note that materials with a low dielectric constant also have high dielectric strength.

[0342] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0343] Examples of materials with a low dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. Other inorganic insulating materials with a low dielectric constant include silicon oxide doped with fluorine, silicon oxide doped with carbon, and silicon oxide doped with carbon and nitrogen. Another example is silicon oxide having vacancies. These silicon oxides may contain nitrogen.

[0344] Furthermore, a transistor using an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator that has a function of suppressing the permeation of impurities and oxygen. Examples of insulators that have a function of suppressing the permeation of impurities and oxygen include insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and can be used in a single layer or a stacked layer. Specifically, examples of insulators that have a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0345] An insulating layer, such as a gate insulating film, that is in contact with a semiconductor layer or that is provided near the semiconductor layer preferably has a region containing excess oxygen. For example, by providing an insulating layer having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide having vacancies.

[0346] Examples of insulators having a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0347] Examples of insulators having a barrier property against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.

[0348] An insulator having a barrier property against oxygen and an insulator having a barrier property against hydrogen can be said to be an insulator having a barrier property against one or both of oxygen and hydrogen.

[0349] Furthermore, examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. These oxides preferably have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0350] In this specification and the like, a barrier insulating film refers to an insulating film having barrier properties. The barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). The function of capturing or fixing (also referred to as gettering) a corresponding substance can be rephrased as barrier properties. When hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "barrier property against oxygen" refers to at least one of oxygen atoms, oxygen molecules, etc., which are difficult to diffuse.

[0351] [Conductor] As the conductor, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element as a component, or an alloy combining the aforementioned metal elements, etc., may be used. As the alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. may be used. Furthermore, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0352] Nitrogen-containing conductive materials, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; oxygen-containing conductive materials, such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metal elements, such as titanium, tantalum, or ruthenium, are preferred because they are conductive materials that are resistant to oxidation, have the function of suppressing oxygen diffusion, or maintain conductivity even after absorbing oxygen. Examples of oxygen-containing conductive materials include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification and elsewhere, a conductive film formed using a conductive material containing oxygen may be referred to as an oxide conductive film.

[0353] Furthermore, conductive materials containing tungsten, copper, or aluminum as a main component are preferred because they have high conductivity.

[0354] Furthermore, a plurality of conductive layers formed from the above materials may be stacked. For example, a stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-described material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0355] When an oxide semiconductor is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0356] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing oxygen and a metal element contained in the oxide semiconductor in which a channel is formed. Alternatively, the above-mentioned conductive materials containing the metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Alternatively, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may be used. Furthermore, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in the oxide semiconductor in which a channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0357] [Semiconductor Material] Indium oxide is preferably used for the semiconductor layer 270 of the semiconductor device. By using indium oxide for the semiconductor layer, the transistor can have large on-state current and high frequency characteristics.

[0358] In this specification and the like, indium oxide having at least a crystalline portion or a crystalline region in a film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystalline IO or crystalline IO include single-crystalline indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0359] Indium oxide is a semiconductor material having physical properties that are completely different from those of oxide semiconductors such as In—Ga—Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0360] The carrier concentration dependence of the Hall mobility of indium oxide, silicon, and IGZO will be explained. Figure 30A shows the carrier concentration dependence of the Hall mobility of silicon (Si) and indium oxide (InO Ｘ ) and FIG. 30B is a schematic diagram showing the carrier concentration dependence of the hole mobility for IGZO.

[0361] First, IGZO tends to exhibit higher hole mobility as the carrier concentration increases, as indicated by the arrows in Figure 30B. On the other hand, indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases, as indicated by the arrows in Figure 30A (see Non-Patent Document 1). This trend is similar to that of silicon; the lower the dopant (impurity) concentration in the material, the less impurity scattering there is and the higher the hole mobility. In other words, the higher the purity and intrinsic indium oxide, the higher the hole mobility. From these results, it can be said that indium oxide, unlike IGZO, is a material with physical properties similar to those of silicon. Note that the characteristics of indium oxide shown in Figure 30A are assumed to be single crystal. Therefore, when indium oxide is non-single crystal (e.g., polycrystalline), the characteristics may differ from those shown in Figure 30A.

[0362] 30A, the range R1 of low carrier concentration has extremely high hole mobility, and therefore can be said to be a range of carrier concentration suitable for, for example, a channel formation region of a transistor. For example, in the case of indium oxide, the range R1 is a range where the carrier concentration value is 1×10 １５ cm −３ The range includes, for example, 1×10 １４ cm −３ That's it, 1 x 10 １８ cm −３ By sufficiently reducing the carrier concentration, the Hall mobility can be reduced to 270 cm ２ It is expected that the resistance can be increased to about / (V·s).

[0363] In addition, in indium oxide, the region where the carrier concentration is in the range R1 may contain an element that lowers the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. By substituting these elements for indium, the carrier concentration can be lowered. Examples of elements that lower the carrier concentration include nitrogen, phosphorus, arsenic, and antimony. For example, by substituting nitrogen, phosphorus, arsenic, or antimony for oxygen, the carrier concentration can be lowered.

[0364] On the other hand, the range R2 with a high carrier concentration has a low electrical resistance, and can be said to be a range of carrier concentrations suitable for, for example, the source and drain regions of a transistor, a resistor, or a transparent conductive film. ２０ cm −３ The range includes, for example, 1×10 １９ cm −３ That's it, 1 x 10 ２２ cm −３ By increasing the carrier concentration sufficiently, the resistivity can be reduced to 1×10 −４ It is expected that the resistance can be reduced to Ω·cm or less.

[0365] In the indium oxide, the region having a carrier concentration in the range R2 may contain an element that increases the carrier concentration. For example, it is preferable that the indium oxide contains an element that is common to the source electrode and the drain electrode of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductive or semiconductive properties.

[0366] In this way, indium oxide uses a region with a low carrier concentration as the channel formation region of a transistor, and a region with a high carrier concentration as the source and drain regions of the transistor. In other words, indium oxide can be said to be an oxide capable of valence electron control. Note that IGZO may experience strain in the source and drain regions due to stress from electrodes in contact with the IGZO, resulting in the formation of n-type regions. On the other hand, unlike IGZO, indium oxide is capable of valence electron control, and therefore does not require strain to be formed in the film as with IGZO. Less strain in the film is expected to improve reliability. For example, by separately creating a region with a carrier concentration in the range R1 shown in FIG. 30A and a region with a carrier concentration in the range R2 in the indium oxide film, a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region) can be created. Note that valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technical concept that would not normally be conceived.

[0367] By using the above technical concept, the transistor having indium oxide in this specification and the like has two or more, preferably three or more, more preferably four or more, and most preferably five of the following characteristics (1) to (5): (1) high on-current (in other words, high mobility); (2) low off-current; (3) normally-off operation; (4) high reliability; and (5) high cutoff frequency (fT). For example, the transistor having indium oxide in this specification and the like has high mobility, low off-current, and is normally-off operation. The transistor has high mobility and is different from a normally-on transistor.

[0368] Next, an indium oxide film applied to a transistor will be described. The indium oxide film preferably has crystallinity (i.e., has crystal grains). Examples of films having crystal grains include single-crystal films, polycrystalline films, and amorphous films containing crystal grains (also called microcrystalline films). In particular, the indium oxide film is preferably a polycrystalline film, and more preferably a single-crystal film. A single-crystal film does not have grain boundaries. Impurities (typically, insulating impurities, insulating oxides, etc.) that hinder carrier flow tend to segregate at grain boundaries. The use of a single-crystal film can suppress carrier scattering at grain boundaries, thereby realizing a transistor exhibiting high field-effect mobility. Furthermore, the use of a single-crystal film has the excellent effect of suppressing variations in transistor characteristics due to the grain boundaries.

[0369] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using a polycrystalline film, it is preferable to use a film with as large a crystal grain size as possible and with few crystal grain boundaries. Note that in a transistor using an indium oxide polycrystalline film, if there is no crystal grain boundary in the channel formation region or no crystal grain boundary is observed, the channel formation region is located within a single crystal region included in the polycrystalline film, and therefore the transistor can be considered to be using single-crystal indium oxide.

[0370] The crystallinity of indium oxide can be analyzed by, for example, X-ray diffraction (XRD), transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0371] In this specification and the like, a semiconductor layer in which no crystal grain boundary is observed in the channel formation region, a semiconductor layer in which the channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis direction is the same in at least two regions in the channel formation region can be called a single crystal film. Also, a semiconductor layer in which, in the channel formation region, within one crystal grain, the direction of another crystal axis continuously changes around a certain crystal axis or a certain crystal orientation as the axis of rotation can be called a single crystal film.

[0372] The channel formation region refers to a region of the semiconductor layer that overlaps (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The current path in the channel formation region is the shortest distance between the source electrode and the drain electrode. Therefore, the crystal grains, crystal grain boundaries, crystal axes, crystal orientation, etc. in the channel formation region can be confirmed by observing a cross section including the semiconductor layer, the source electrode, and the drain electrode.

[0373] The indium oxide film in the channel formation region preferably has a lower impurity concentration. Impurities in the indium oxide film in the channel formation region can be a scattering source of carriers, which can lead to a decrease in field-effect mobility. These impurities can also hinder the crystal growth of the indium oxide film. Examples of impurities in the indium oxide film include boron and silicon. The indium oxide film preferably contains these impurities at concentrations of 0.1% or less, and more preferably 0.01% (100 ppm) or less. Carbon, hydrogen, and other elements may be contained in the film-forming gas or precursor during film formation, and may remain in the indium oxide film in greater amounts than the above-mentioned impurities.

[0374] The indium oxide film in the channel formation region may contain an element that can become the same trivalent cation as indium, as long as the crystal maintains a cubic crystal structure (bixbyite type). Examples of such an element include Group 13 elements of the periodic table, such as gallium and aluminum, and Group 3 elements of the periodic table. These elements exist mainly as trivalent cations in oxides, and therefore the carrier concentration of indium oxide can be maintained low.

[0375] By using such an indium oxide film in a transistor, the field effect mobility of the transistor can be increased to 50 cm ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V·s) or more.

[0376] One of the features of an indium oxide film is that it has higher oxygen permeability (diffusibility) than an IGZO film. As shown in FIG. 30C, Ｘ Oxygen (O) diffusing into the indium oxide film passes through the indium oxide film and becomes oxygen molecules (O ２ ) and is released as water molecules (H ２ O) may be released in the film. Ｏ In the case where an indium oxide film is present, oxygen atoms diffuse to compensate for the oxygen vacancies. Since oxygen diffuses easily in the indium oxide film, it can be said that oxygen vacancies are more easily compensated for in the indium oxide film than in the IGZO film.

[0377] As described above, an indium oxide film can more easily reduce oxygen vacancies in the film than an IGZO film. Therefore, by using such an indium oxide film in a transistor, a transistor with extremely high reliability can be realized.

[0378] Furthermore, as shown in FIG. 30C, the indium oxide film diffuses hydrogen. Hydrogen that diffuses into the indium oxide film from the outside passes through the indium oxide film and becomes hydrogen molecules (H ２ ) or reacts with oxygen contained in the membrane and is released as water molecules.

[0379] A transistor using an indium oxide film is an accumulation-type transistor that uses electrons as majority carriers. Assuming that the carrier relaxation time is constant, the smaller the effective mass of the electrons (carriers), the higher the electron mobility. In other words, by using indium oxide, which has a small effective mass of electrons, for a transistor, the on-state current or field-effect mobility of the transistor can be increased.

[0380] Table 1 shows the results of single crystal indium oxide (here, In ２ O ３ ) and single-crystal silicon (Si). As shown in Table 1, indium oxide is characterized by a small effective mass of electrons and a large effective mass of holes. Indium oxide also has the characteristic that the effective mass of electrons is almost independent of the crystal orientation. Therefore, by using crystalline indium oxide in a transistor, a transistor with high field-effect mobility and high frequency characteristics (also called f characteristics) can be realized. Furthermore, since the effective mass of holes is large, a transistor with extremely small off-current can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width can be reduced to 1 fA (1×10) in an environment of 125° C. −１５ A) or less, or 1aA (1 x 10 −１８ A) or less, and under room temperature (25°C) conditions, −１８ A) or less, or 1zA (1 x 10 −２１ Furthermore, as shown in Table 1, indium oxide has a smaller effective mass of electrons and a larger effective mass of holes than silicon, and therefore may be able to realize a transistor with higher field-effect mobility and lower off-state current than a Si transistor.

[0381]

[0382] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. The seed layer is preferably made of a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with indium oxide. This can improve the crystallinity of the indium oxide film. Note that a substrate (e.g., a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0383] One method for evaluating the degree of lattice mismatch is to use the value of the lattice mismatch shown below. The lattice mismatch Δa [%] of the crystals of the formed film (here, the indium oxide film) with respect to the crystals of the seed layer is expressed as Δa = ((L １ -L ２ ) / L ２ ) × 100, where L １ is the length or lattice constant of the unit lattice vector of the crystal of the formed film, and L ２ is the length of the unit cell vector or the lattice constant of the crystal of the seed layer.

[0384] The smaller the absolute value of the lattice mismatch Δa between the seed layer and the indium oxide film, the more preferable, and it is most preferably 0. For example, Δa can be set to −5% or more and 5% or less, preferably −4% or more and 4% or less, more preferably −3% or more and 3% or less, and even more preferably −2% or more and 2% or less.

[0385] Here, the indium oxide crystal has a cubic crystal structure (bixbyite type). For example, the crystal of yttria-stabilized zirconia (YSZ) can have a cubic crystal structure (fluorite type). The lattice mismatch of the indium oxide crystal with the cubic YSZ crystal is in the range of −2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on the YSZ substrate.

[0386] It should be noted that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not necessarily have the same crystal system or crystal orientation. For example, a film having crystals of a hexagonal or trigonal structure may be used under an indium oxide film having crystals of a cubic structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. Examples of hexagonal or trigonal crystals include wurtzite structure, YbFe ２ O ４ Type structure, Yb ２ Fe ３ O ７ YbFeFe alloys have the following structures: ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a ZnO-type structure is IGZO.

[0387] [Other Semiconductor Materials] The semiconductor material that can be used for the semiconductor layer is not limited to indium oxide. Metal oxides (oxide semiconductors) having semiconducting properties can also be used as the semiconductor layer. The oxide semiconductor preferably contains two or three elements selected from indium, element M, and zinc. The element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more elements selected from indium, gallium, and zinc.

[0388] Examples of metal oxides according to one embodiment of the present invention include indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, also referred to as AZO), and indium. Examples of usable materials include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0389] Alternatively, it is preferable to use a semiconductor of a single element, a compound semiconductor, or a layered material (also called an atomic layer material, a two-dimensional material, or the like) as the semiconductor material.

[0390] In this specification and the like, a layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0391] Examples of semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used as semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polysilicon (LTPS).

[0392] Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably has a cubic crystal structure.

[0393] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. Boron carbonitride, a layered material, has carbon atoms, nitrogen atoms, and boron atoms arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogen. Chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides also include transition metal chalcogenides and Group 13 chalcogenides.

[0394] For example, it is preferable to use a transition metal chalcogenide that functions as a semiconductor for the semiconductor layer. Specific examples of transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically, MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ By applying the above-mentioned transition metal chalcogenide to a semiconductor layer, a memory device with a large on-current can be provided.

[0395] According to one embodiment of the present invention, a novel transistor and a novel memory device can be provided. Alternatively, a memory device that can be miniaturized or highly integrated can be provided. Alternatively, a memory device with favorable frequency characteristics can be provided. Alternatively, a memory device with high operating speed can be provided. Alternatively, a memory device with favorable reliability can be provided. Alternatively, a memory device with low power consumption can be provided. Alternatively, a memory device including a transistor with large on-state current can be provided. Alternatively, a memory device with little variation in transistor characteristics can be provided. Alternatively, a memory device with favorable electrical characteristics can be provided.

[0396] The structures, configurations, methods, and the like described in this embodiment can be used in appropriate combination with structures, configurations, methods, and the like described in other embodiments.

[0397] Embodiment 3 In this embodiment, an application example of a memory device according to one embodiment of the present invention will be described.

[0398] <Memory Hierarchy of Memory Devices> Generally, various memory devices are used in semiconductor devices such as computers depending on the application. Figure 31 shows various memory devices by memory hierarchy. The higher the memory device located in the hierarchy, the faster the access speed is required, while the lower the memory device located in the hierarchy, the larger the memory capacity and higher the recording density are required. Figure 31 shows, from the top layer, memory integrated as a register in a processing unit such as a CPU, SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), and 3D NAND memory.

[0399] The memory embedded as a register in a processing unit such as a CPU is used for temporary storage of calculation results, and is therefore frequently accessed by the processing unit. Therefore, a higher operating speed is required than a larger memory capacity. Registers also have the function of storing setting information for the processing unit.

[0400] SRAM is used, for example, as a cache. A cache has the function of storing a copy of the information stored in the main memory. By storing a copy of frequently used data in the cache, the speed of accessing the data can be increased.

[0401] DRAM is used, for example, as a main memory. The main memory has the function of storing programs or data read from storage. The recording density of DRAM is approximately 0.1 to 0.3 Gbit / mm ２ is.

[0402] 3D NAND memory is used, for example, for storage. Storage has the function of storing data that requires long-term storage or various programs used in processing units. Therefore, storage requires a large memory capacity and a high recording density rather than an operating speed. The recording density of memory devices used for storage is approximately 0.6 to 6.0 Gbit / mm ２ is.

[0403] The storage device according to one embodiment of the present invention is excellent in that it has a high operating speed, is capable of retaining data for a long period of time, has high rewrite endurance, and can be driven at a low voltage. The storage device according to one embodiment of the present invention can be suitably used as a storage device located in a boundary area 901 that includes both a memory hierarchy where a main memory is located and a memory hierarchy where a storage is located.

[0404] Next, electronic components, electronic devices, and large scale computers that can use the memory device described in the above embodiment will be described. The electronic components, electronic devices, and large scale computers that use the memory device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0405] [Electronic Component] FIG. 32A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 709 is mounted. Electronic component 709 shown in FIG. 32A has memory device 710 inside mold 711. FIG. 32A omits some parts to show the interior of electronic component 709. Electronic component 709 has lands 712 on the outside of mold 711. Lands 712 are connected to electrode pads 713, and electrode pads 713 are connected to memory device 710 via wires 714. Electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and connected on printed circuit board 702 to complete mounting substrate 704.

[0406] The memory device 710 also includes a layer 715 having an arithmetic core and a layer 716 having a memory. The layer 716 having the memory is configured by stacking multiple memory cell arrays. The stacked configuration of the layer 715 having the arithmetic core and the layer 716 having the memory can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the layer 715 having the arithmetic core and the layer 716 having the memory as a monolithic stack, for example, a so-called on-chip memory configuration can be achieved, in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0407] Furthermore, by configuring an on-chip memory, it is possible to reduce the size of connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and therefore it is possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0408] Furthermore, it is preferable that the memory cell arrays included in the memory-containing layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, it is possible to improve either or both of the memory bandwidth and the memory access latency. Note that the bandwidth refers to the amount of data transferred per unit time, and the access latency refers to the time from access to the start of data exchange. Note that when Si transistors are used in the memory-containing layer 716, it is more difficult to achieve a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0409] The memory device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained during the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes. Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0410] Next, a perspective view of electronic component 730 is shown in Figure 32B. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a memory device 735 and multiple memory devices 710 provided on interposer 731.

[0411] For example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate can be used as the package substrate 732. For example, a silicon interposer or a resin interposer can be used as the interposer 731.

[0412] The interposer 731 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In addition, through electrodes may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be connected using the through electrodes. In addition, with a silicon interposer, a TSV may also be used as the through electrode.

[0413] In an HBM, many wirings must be connected to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted must have fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.

[0414] Furthermore, in SiPs, MCMs, and the like that use silicon interposers, a decrease in reliability due to differences in the coefficient of expansion between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) in which multiple integrated circuits are arranged horizontally on an interposer.

[0415] On the other hand, when connecting multiple integrated circuits with different terminal pitches using a silicon interposer, a TSV, or the like, a space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of the electronic component 730, the width of the terminal pitch becomes an issue, and it may be difficult to provide the many wirings necessary to achieve a wide memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferable. A composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithically stacked memory cell array.

[0416] A heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When providing a heat sink, it is preferable to align the height of the integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 710 and the memory device 735.

[0417] Electrodes 733 may be provided on the bottom of package substrate 732 in order to mount electronic component 730 on another substrate. FIG. 32B shows an example in which electrodes 733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0418] The electronic component 730 can be mounted on other substrates using various mounting methods, including, but not limited to, BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), and a quad flat non-leaded package (QFN).

[0419] 33A to 33D are diagrams illustrating configuration examples different from the electronic components 709 and 730 described above in Fig. 32A and Fig. 32B. Electronic components 730A to 730D illustrated in Fig. 33A to 33D have a configuration in which a layer 715 having an arithmetic core and a layer 716 having a memory are provided in a mold 711 on an interposer 731 provided with the above-described electrodes 733.

[0420] In the configuration of electronic component 730A shown in FIG. 33A , layer 715 having processor cores is provided on interposer 731 and connected to electrode pads (not shown) via wires 714. Layer 716 having memory formed on layer 715 having processor cores has the monolithic stack configuration described above. In the monolithic stack configuration, layer 716 having memory and layer 715 having processor cores are connected. Therefore, wires 714 between interposer 731 and layer 715 having processor cores can also serve as wiring between each layer having memory 716 and interposer 731, thereby reducing the number of wires.

[0421] While the configuration example of FIG. 33A illustrates a single monolithic stacked structure, a configuration in which an electronic component having a monolithic stacked structure is stacked with other electronic components is also possible. For example, as shown in FIG. 33B , a configuration in which a monolithic stacked structure is formed by stacking a layer 716A having memory and a layer 715A having an arithmetic core, and a layer 716B having memory and a layer 715B having an arithmetic core, are stacked together. The monolithic stacked structure stacked with other electronic components is fixed to a resin sheet 744 by an adhesive layer 743. This configuration allows for stacking multiple memory cell arrays with different circuit configurations. Having different circuit configurations allows for memory devices with different memory bandwidths and memory access latencies, making it suitable for use in a hierarchical structure such as a cache memory.

[0422] The configuration example of FIG. 33A can also be stacked with other electronic components. For example, as shown in FIG. 33C , an electronic component having a layer 715C with an operational core such as a processor provided in a mold 711 between interposers 731A and 731B, and the above-described electronic component 730A can be stacked to form electronic component 730C. The circuit layers can be connected via conductors such as electrodes 733. This configuration enables the processor and memory interface to operate at high speed. Furthermore, a gap (space) can be provided between the mold including the operational core layer 715C and the electronic component 730A, thereby making it difficult for heat generated in the operational core layer 715C to be transmitted to the electronic component 730A.

[0423] 33C , a memory layer having an OS transistor may be provided on a layer 715C having an arithmetic core such as a processor. For example, as shown in FIG. 33D , a memory layer 716C may be provided on the arithmetic core layer 715C, and stacked with electronic components 730A. This configuration enables the high-speed operation of the interface between the so-called on-chip memory configuration in which memory is formed directly on the processor, and the memory device configuration having stacked memory layers.

[0424] [Electronic Device] Fig. 34A is an external view showing an example of a portable electronic device. Fig. 34B is a simplified diagram showing data exchange within the portable electronic device. Portable electronic device 595 has a printed wiring board 596, a speaker 597, a camera 598, a microphone 599, etc.

[0425] In the portable electronic device 595, the electronic component 709 can be provided on the printed circuit board 596. The portable electronic device 595 can improve user convenience by processing and analyzing a plurality of pieces of data obtained by the speaker 597, the camera 598, the microphone 599, etc. using the electronic component 709. The portable electronic device 595 can also be used in systems that perform voice guidance, image search, etc.

[0426] The electronic component 709 performs arithmetic processing of the obtained image data using a neural network or the like, thereby enabling processing such as increasing the image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for autonomous driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration for lensless image sensors, positioning, character recognition, and reduction of reflected glare.

[0427] The portable game console 1100 shown in FIG. 35A includes a housing 1101, a housing 1102, a housing 1103, a display unit 1104, a connection unit 1105, operation keys 1107, and the like. The housings 1101, 1102, and 1103 are detachable. By attaching the connection unit 1105 provided on the housing 1101 to the housing 1108, the video output to the display unit 1104 can be output to another video device. On the other hand, by attaching the housings 1102 and 1103 to the housing 1109, the housings 1102 and 1103 are integrated and function as an operation unit. The electronic component 709 can be incorporated into chips or the like provided on the substrates of the housings 1102 and 1103.

[0428] 35B shows a stick-shaped electronic device 1120 of a USB connection type. The electronic device 1120 has a housing 1121, a cap 1122, a USB connector 1123, and a board 1124. The board 1124 is housed in the housing 1121. For example, a memory chip 1125 and a controller chip 1126 are attached to the board 1124. The electronic component 709 can be incorporated into the controller chip 1126 of the board 1124, etc.

[0429] 35C shows a humanoid robot 1130. The robot 1130 has sensors 2101 to 2106 and a control circuit 2110. For example, the control circuit 2110 can incorporate the electronic component 709 described above.

[0430] [Mainframe] The electronic component 709 can be used in a system 3000 including a mainframe that communicates with the electronic device, instead of being built into the electronic device. In this case, the electronic device and the mainframe constitute a computing system. Fig. 36 shows an example of the configuration of the system 3000.

[0431] The system 3000 is configured by an electronic device 3001 and a mainframe computer 3002. Communication between the electronic device 3001 and the mainframe computer 3002 can be performed via an internet line 3003.

[0432] The mainframe 3002 has a plurality of racks 3004. A plurality of circuit boards 3005 are provided on the racks, and the electronic components 709 described in the above embodiment can be mounted on the circuit boards 3005. This forms a neural network in the mainframe 3002. The mainframe 3002 can then perform neural network calculations using data input from the electronic device 3001 via the Internet line 3003. The results of calculations by the mainframe 3002 can be transmitted to the electronic device 3001 via the Internet line 3003 as necessary. This reduces the calculation load on the electronic device 3001.

[0433] This embodiment mode can be combined with the descriptions of other embodiment modes as appropriate.

[0434] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0435] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0436] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0437] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0438] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0439] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0440] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0441] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0442] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0443] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0444] In this specification and the like, terms such as "film" and "layer" may be interchangeable in some cases. For example, the term "conductive layer" may be changed to the term "conductive film." Or, for example, the term "insulating film" may be changed to the term "insulating layer."

[0445] In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows, or a device that has the function of selecting and switching a path for a current to flow.

[0446] In this specification, the channel length of a planar transistor refers to, for example, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap in a plan view of the transistor, or a distance between a source and a drain in a region where a channel is formed.

[0447] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0448] In this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration, device structure, etc. Also, a terminal, a wiring, etc. can be referred to as a node.

[0449] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0450] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0451] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0452] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0453] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" is sometimes used to define the connection relationship between circuit elements as a physical entity. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the intervention of a circuit element (e.g., a transistor, a switch, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0454] For example, assuming that a circuit including A and B is operating, if there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B, then it can be defined that "A and B are indirectly connected" as objects. Note that even if there is a time during the operation of the circuit when no electrical signal is exchanged or an interaction of electrical potential occurs between A and B, it can still be defined that "A and B are indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an interaction of electrical potential occurs between A and B.

[0455] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a gate insulating film of a transistor is present between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of the transistor are indirectly connected."

[0456] Another example of a case where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0457] 10: element layer, 11: global sense amplifier section, 12: data sense amplifier section, 13: global sense amplifier drive circuit section, 14: column line drive circuit section, 15: word line side drive circuit section, 16: controller section, 20: element layer, 21: sense circuit, 22: sense circuit section, 40: element layer, 41: memory cell, 42: memory cell array, 100: storage device

Claims

a sense circuit electrically connected to the memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via second bit lines; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier block via third bit lines; a word line side drive circuit unit having a plurality of word line side drive blocks that output word signals to the memory cells and sense circuit control signals to the sense circuits; a sense amplifier drive circuit unit having a plurality of sense amplifier drive blocks for driving the first sense amplifier block; a controller unit that outputs a sense amplifier driving block control signal for controlling the sense amplifier driving block and a word line side driving block control signal for controlling the word line side driving block; the sense amplifier drive block control signal is a signal that causes the plurality of sense amplifier drive blocks to control the first sense amplifier block; the word line side driver block control signal is a signal that causes the plurality of word line side driver blocks to output the word signals to the memory cells connected to the first sense amplifier block, and to output the sense circuit control signals to the sense circuits connected to the memory cells; storage device. 　 In claim 1, the memory cell and the sense circuit each have a first transistor; the first transistor has a first semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region; storage device. 　 In claim 1, a switching circuit electrically connected to the sense circuit and the first sense amplifier block; The memory cell has a first transistor; the sense circuit and the switching circuit each include a second transistor; the first transistor has a first semiconductor layer; the second transistor has a second semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region, the second semiconductor layer has indium oxide in a channel formation region; storage device. 　 a sense circuit electrically connected to the memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via second bit lines; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier block via third bit lines; a word line side drive circuit unit having a plurality of word line side drive blocks that output word signals to the memory cells and sense circuit control signals to the sense circuits; a sense amplifier drive circuit unit having a plurality of sense amplifier drive blocks for driving the first sense amplifier block; a controller unit that outputs a sense amplifier drive block control signal that controls the sense amplifier drive block, a word line side drive block control signal that controls the word line side drive block, and a second sense amplifier control signal that controls the second sense amplifier block, the sense amplifier drive block control signal is a signal that causes the plurality of sense amplifier drive blocks to control the first sense amplifier block; the word line side driver block control signal is a signal that causes the plurality of word line side driver blocks to output the word signals to the memory cells connected to the first sense amplifier block, and to output the sense circuit control signals to the sense circuits connected to the memory cells; the second sense amplifier control signal is a signal that puts one of the second sense amplifier blocks into a state in which it accesses data read out to the first sense amplifier block via the third bit line; storage device. 　 In claim 4, the memory cell and the sense circuit each have a first transistor; the first transistor has a first semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region; storage device. In claim 4, a switching circuit electrically connected to the sense circuit and the first sense amplifier block; The memory cell has a first transistor; the sense circuit and the switching circuit each include a second transistor; the first transistor has a first semiconductor layer; the second transistor has a second semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region, the second semiconductor layer has indium oxide in a channel formation region; storage device. 　 a sense circuit electrically connected to the memory cell via a first bit line; a first sense amplifier unit having a plurality of first sense amplifier blocks electrically connected to the sense circuit via second bit lines; a second sense amplifier unit having a plurality of second sense amplifier blocks electrically connected to the first sense amplifier block via third bit lines; a word line side drive circuit unit having a plurality of word line side drive blocks that output word signals to the memory cells and sense circuit control signals to the sense circuits; a sense amplifier drive circuit unit having a plurality of sense amplifier drive blocks for driving the first sense amplifier block; a controller unit that outputs a sense amplifier driving block control signal that controls the sense amplifier driving block and a word line side driving block control signal that controls the word line side driving block; the sense amplifier drive block control signal is a signal that causes one or more of the sense amplifier drive blocks to control the first sense amplifier block; the word line side driver block control signal is a signal that causes one or more of the word line side driver blocks to output the word signal to the memory cell connected to the first sense amplifier block, and output the sense circuit control signal to the sense circuit connected to the memory cell; storage device. 　 In claim 7, the memory cell and the sense circuit each have a first transistor; the first transistor has a first semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region; storage device. 　 In claim 7, a switching circuit electrically connected to the sense circuit and the first sense amplifier block; The memory cell has a first transistor; the sense circuit and the switching circuit each include a second transistor; the first transistor has a first semiconductor layer; the second transistor has a second semiconductor layer; the first semiconductor layer has an oxide semiconductor in a channel formation region, the second semiconductor layer has indium oxide in a channel formation region; storage device. 　 In claim 7, the controller unit has a function of outputting a second sense amplifier control signal that controls the second sense amplifier block; the second sense amplifier control signal is a signal that puts one of the second sense amplifier blocks into a state in which it accesses data read out to the first sense amplifier block via the third bit line; storage device.

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