Imaging device, endoscope, imaging system, and clock adjustment method

Abstract

This imaging device has pixels, a driving circuit for the pixels, a comparison circuit, a clock synchronization circuit, and an external disturbance detection circuit. The comparison circuit compares the phase / frequency of a first clock signal and the phase / frequency of a second clock signal. The clock synchronization circuit executes synchronization processing for generating the first clock signal in synchronization with the second clock signal. The external disurbance detection circuit compares the phase difference or the frequency difference between the first clock signal and the second clock signal with a threshold value. When the phase difference or the frequency difference is greater than the threshold value, the external disturbance detection circuit causes the clock synchronization circuit to stop the synchronization processing and fixes the phase or the frequency of the first clock signal.

Description

Imaging device, endoscope, imaging system, and clock adjustment method

[0001] The present disclosure relates to an imaging device, an endoscope, an imaging system, and a clock adjustment method.

[0002] An endoscope system has a scope (imaging device) and a control unit (control device). The scope and control unit are connected to each other by cables that transmit power supply voltage, video signals, clock signals, etc. An image sensor is mounted at the tip of the scope.

[0003] Endoscope systems are used simultaneously with high-frequency devices that generate high frequencies, such as electric scalpels, to treat affected areas. Therefore, the signal lines connecting the scope and the control unit may be exposed to noise. For example, if noise is applied to the signal line transmitting the clock signal, the image sensor may output an abnormal video signal.

[0004] The scope may have a phase-locked loop (PLL) that adjusts the phase and frequency of the clock signal within the scope based on the phase and frequency of the clock signal transferred from the control unit. If noise is added to the clock signal transferred from the control unit, the PLL cannot accurately adjust the phase and frequency of the clock signal within the scope. As a result, the image sensor within the scope may operate erroneously based on the clock signal.

[0005] Japanese Patent Application Laid-Open Publication No. 2018-094235 discloses an endoscope that suppresses the effects of noise applied to a video signal. However, this endoscope cannot prevent malfunction of the PLL within the scope.

[0006] Japanese Patent Application Publication No. 2018-094235

[0007] The present disclosure aims to provide an imaging device, an endoscope, an imaging system, and a clock adjustment method that can reduce the effect of external disturbances on the operation of adjusting the frequency or phase of a clock signal within the imaging device.

[0008] According to a first aspect of the present disclosure, an imaging device includes a pixel, a drive circuit, a comparison circuit, a clock synchronization circuit, and a disturbance detection circuit. The drive circuit drives the pixel based on a first clock signal. The comparison circuit compares the phase or frequency of the first clock signal with a second clock signal generated by an external circuit. The clock synchronization circuit performs synchronization processing to generate the first clock signal synchronized with the second clock signal based on the comparison result of the comparison circuit. The disturbance detection circuit detects a disturbance in the second clock signal. The disturbance detection circuit compares a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold. When the first difference or the second difference is greater than the threshold, the disturbance detection circuit causes the clock synchronization circuit to stop the synchronization processing and fix the phase or the frequency of the first clock signal.

[0009] According to a second aspect of the present disclosure, in the first aspect, the disturbance detection circuit may obtain the first value by counting a first signal indicating the phase of the first clock signal or the frequency of the first clock signal based on a third clock signal having a frequency higher than the frequency of the first clock signal and the frequency of the second clock signal. The disturbance detection circuit may obtain the second value by counting a second signal indicating the phase of the second clock signal or the frequency of the second clock signal based on the third clock signal. The disturbance detection circuit may obtain the first difference or the second difference by calculating the difference between the first value and the second value.

[0010] According to a third aspect of the present disclosure, in the second aspect, when the first value or the second value reaches a predetermined value, the disturbance detection circuit may reset the operation of counting the first signal and the operation of counting the second signal.

[0011] According to a fourth aspect of the present disclosure, in the first aspect, the clock synchronization circuit may include a charge pump, a filter, and a voltage-controlled oscillator. The charge pump may output a control signal based on a result of the comparison in the comparison circuit. The filter may output a voltage based on the control signal. The voltage-controlled oscillator may generate the first clock signal based on the voltage. When the first difference or the second difference is greater than the threshold, the disturbance detection circuit may cause the charge pump to stop outputting the control signal.

[0012] According to a fifth aspect of the present disclosure, in the first aspect, the disturbance detection circuit may be stopped when the imaging device is started up, and the disturbance detection circuit may start operating after a predetermined time has elapsed from the timing when the imaging device is started up.

[0013] According to a sixth aspect of the present disclosure, in the first aspect, the disturbance detection circuit may be stopped when the imaging device is started up, and the disturbance detection circuit may start operating after the imaging device is started up and the first clock signal is synchronized with the second clock signal.

[0014] According to a seventh aspect of the present disclosure, in the first aspect, after the disturbance detection circuit causes the clock synchronization circuit to stop the synchronization process and fix the phase or the frequency of the first clock signal, when the first difference or the second difference becomes equal to or less than the threshold value, the disturbance detection circuit may cause the clock synchronization circuit to resume the synchronization process.

[0015] According to an eighth aspect of the present disclosure, in the seventh aspect, after a predetermined time has elapsed from the time when the first difference or the second difference becomes equal to or less than the threshold value, the disturbance detection circuit may cause the clock synchronization circuit to resume the synchronization process.

[0016] According to a ninth aspect of the present disclosure, an imaging device includes a pixel, a drive circuit, a comparison circuit, a clock synchronization circuit, and a disturbance detection circuit. The drive circuit drives the pixel based on a first clock signal. The comparison circuit compares the phase or frequency of the first clock signal with a second clock signal generated by an external circuit. The clock synchronization circuit performs synchronization processing to generate the first clock signal synchronized with the second clock signal based on the comparison result of the comparison circuit. The disturbance detection circuit detects a disturbance in the second clock signal. The comparison circuit has a first input terminal and a second input terminal. The comparison circuit compares the phase or frequency of a signal input to the first input terminal with a signal input to the second input terminal. The disturbance detection circuit compares a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold. When the first difference or the second difference is greater than the threshold, the disturbance detection circuit inputs the first clock signal or the second clock signal to the first input terminal or the second input terminal. When the first difference or the second difference is equal to or less than the threshold, the disturbance detection circuit inputs the first clock signal to the first input terminal and inputs the second clock signal to the second input terminal.

[0017] According to a tenth aspect of the present disclosure, an endoscope includes a scope to be inserted into a living body, and the imaging device, wherein the imaging device is disposed at a tip of the scope.

[0018] According to an eleventh aspect of the present disclosure, there is provided an imaging system including an imaging device and a control device, the control device being connected to the imaging device via a signal line, the control device having the external circuit, and outputting the second clock signal to the signal line.

[0019] According to a twelfth aspect of the present disclosure, a clock adjustment method for adjusting the phase or frequency of a first clock signal for driving a pixel includes: comparing the phase or frequency of the first clock signal with a second clock signal generated by an external circuit in a comparison circuit; performing a synchronization process for generating the first clock signal synchronized with the second clock signal based on a comparison result in the comparison circuit; comparing a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold; and stopping the synchronization process and fixing the phase or frequency of the first clock signal when the first difference or the second difference is greater than the threshold.

[0020] According to the above aspects, the imaging device, endoscope, imaging system, and clock adjustment method can reduce the effect of external disturbances on the operation of adjusting the frequency or phase of a clock signal in the imaging device.

[0021] FIG. 1 is a schematic diagram showing the configuration of an endoscope system according to a first embodiment. FIG. 2 is a block diagram showing the configuration of a camera unit and a control unit included in the endoscope system according to the first embodiment. FIG. 3 is a block diagram showing the configuration of an image sensor included in the endoscope system according to the first embodiment. FIG. 4 is a block diagram showing the configuration of a PLL and a disturbance detection circuit included in the endoscope system according to the first embodiment. FIG. 5 is a circuit diagram showing the configuration of a phase / frequency detector and a charge pump included in the endoscope system according to the first embodiment. FIG. 6 is a timing chart showing the waveform of a signal in a PLL included in the endoscope system according to the first embodiment. FIG. 7 is a timing chart showing the waveform of a signal in a PLL included in the endoscope system according to the first embodiment. FIG. 8 is a flowchart showing a clock adjustment method according to the first embodiment. FIG. 9 is a block diagram showing the configuration of a PLL and a disturbance detection circuit included in an endoscope system according to a second embodiment. FIG. 10 is a circuit diagram showing the configuration of a phase / frequency detector and a charge pump included in the endoscope system according to the second embodiment. FIG. 11 is a flowchart showing the clock adjustment method according to the second embodiment. FIG. 12 is a block diagram showing the configuration of a PLL and a disturbance detection circuit included in an endoscope system according to a modification of the second embodiment.

[0022] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present disclosure will be described below with reference to the accompanying drawings. An example of an endoscope system having an imaging device will be described below. The endoscope system is an example of an imaging system.

[0023] (First Embodiment) Fig. 1 shows the configuration of an endoscope system 1 according to a first embodiment. The endoscope system 1 shown in Fig. 1 has an endoscope insertion portion 2, a transmission cable 3, an operation portion 4, a connector portion 5, a control unit 6, and a display device 7. The endoscope insertion portion 2 (scope), the transmission cable 3, the operation portion 4, and the connector portion 5 constitute an endoscope 8.

[0024] The endoscope insertion section 2 has an insertion section 2a. The insertion section 2a is part of the transmission cable 3. The insertion section 2a is inserted into a living body, which is a subject. The endoscope insertion section 2 generates a video signal by capturing an image of the inside of the subject. The endoscope insertion section 2 outputs the generated video signal to the control unit 6. A camera unit 9 shown in FIG. 2 is disposed at the tip 2b of the insertion section 2a. An operation section 4 is connected to the end of the insertion section 2a opposite to the tip 2b. The operation section 4 receives various operations for the endoscope insertion section 2 from the user.

[0025] The transmission cable 3 connects the camera unit 9 and the connector section 5. A video signal generated by the camera unit 9 is output to the connector section 5 via the transmission cable 3.

[0026] The connector section 5 is connected to the transmission cable 3 and the control unit 6. The connector section 5 performs predetermined processing on the video signal output from the endoscope insertion section 2. The connector section 5 outputs the video signal to the control unit 6.

[0027] The control unit 6 performs image processing on the video signal output from the connector section 5. Furthermore, the control unit 6 controls the entire endoscope system 1.

[0028] The display device 7 displays an image based on the video signal processed by the control unit 6. The display device 7 also displays various information related to the endoscope system 1.

[0029] The endoscope system 1 has a camera unit 9 (imaging device) and a control unit 6 (control device) shown in Fig. 2. Fig. 2 shows the configurations of the camera unit 9 and the control unit 6. The camera unit 9 is disposed at the tip 2b of the endoscope 8. The operation unit 4, connector unit 5, and display device 7 are not shown in Fig. 2.

[0030] The transmission cable 3 shown in Fig. 1 has a power supply line 30, a video line 31, and a clock line 32 shown in Fig. 2. The camera unit 9 and the control unit 6 are connected to each other by the power supply line 30, the video line 31, and the clock line 32.

[0031] The endoscope system 1 includes a light source device that generates illumination light to be irradiated onto the subject (not shown in FIG. 2).

[0032] The camera unit 9 has an image sensor 90, a voltage regulator 91, a video transmission circuit 92, a clock reception circuit 93, a PLL 94, a disturbance detection circuit 95, and a control circuit 96. The control unit 6 has a voltage generation circuit 60, a video processing circuit 61, a clock generation circuit 62, and a control circuit 63.

[0033] For example, the voltage generation circuit 60 is a voltage regulator. The voltage generation circuit 60 is electrically connected to the power supply line 30. The voltage generation circuit 60 generates a power supply voltage, which is a direct current (DC) voltage, and outputs the power supply voltage to the power supply line 30. The power supply line 30 is a signal line arranged in the transmission cable 3. The power supply line 30 transfers the power supply voltage to the camera unit 9. The power supply voltage transferred by the power supply line 30 is input to a voltage regulator 91 of the camera unit 9.

[0034] The voltage regulator 91 generates a DC voltage based on the power supply voltage transferred via the power supply line 30. The voltage regulator 91 can suppress the effects of noise applied to the power supply line 30 and can generate a DC voltage with a constant voltage value. The DC voltage generated by the voltage regulator 91 is output to the image sensor 90 and the like as a power supply voltage in the camera unit 9.

[0035] The image sensor 90 generates a video signal and outputs the video signal to a video transmission circuit 92. The video transmission circuit 92 is electrically connected to the video line 31. The video transmission circuit 92 outputs the video signal to the video line 31.

[0036] The video line 31 is a signal line arranged in the transmission cable 3. The video line 31 transfers the video signal to the control unit 6. The video processing circuit 61 receives the video signal transferred by the video line 31. The video processing circuit 61 performs predetermined signal processing on the video signal and outputs the video signal to the display device 7.

[0037] For example, the clock generation circuit 62 is a crystal oscillator. The clock generation circuit 62 is electrically connected to the clock line 32. The clock generation circuit 62 generates a clock signal and outputs the clock signal to the clock line 32. The control circuit 63 controls the voltage generation circuit 60, the video processing circuit 61, and the clock generation circuit 62.

[0038] The clock line 32 is a signal line disposed in the transmission cable 3. The clock line 32 transfers a clock signal to the camera unit 9.

[0039] The clock receiving circuit 93 receives the clock signal transferred by the clock line 32 and outputs the clock signal to the PLL 94 .

[0040] The PLL 94 generates a clock signal (internal clock signal) and performs synchronization processing. In the synchronization processing, the PLL 94 eliminates a phase and frequency discrepancy between the internal clock signal generated within the PLL 94 and the clock signal (external clock signal) output from the clock receiving circuit 93. In this way, the PLL 94 synchronizes the internal clock signal with the external clock signal. The PLL 94 outputs the internal clock signal synchronized with the external clock signal to the image sensor 90.

[0041] The disturbance detection circuit 95 detects disturbances (noise) in the external clock signal based on the state of the signal inside the PLL 94. When a disturbance in the external clock signal is detected, the disturbance detection circuit 95 causes the PLL 94 to stop synchronization processing and generate an internal clock signal having a fixed phase and frequency independent of the external clock signal. The control circuit 96 controls the disturbance detection circuit 95.

[0042] The phase and frequency deviation between the internal clock signal and the external clock signal occurs mainly in response to temperature changes. The deviation does not increase rapidly with temperature changes. On the other hand, when a high-frequency device is operating, the phase and frequency of the external clock signal change rapidly. To prevent the internal clock signal from being synchronized with such an external clock signal, the disturbance detection circuit 95 causes the PLL 94 to stop the synchronization process.

[0043] The disturbance detection circuit 95 may be configured as a digital circuit including at least one of a processor and a logic circuit. For example, the processor is a CPU (Central Processing Unit). For example, the logic circuit is at least one of an ASIC (Application Specific Integrated Circuit) and an FPGA (Field-Programmable Gate Array). The disturbance detection circuit 95 may include one or more processors. The disturbance detection circuit 95 may include one or more logic circuits.

[0044] The computer of the camera unit 9 may load a program and execute the loaded program. The program includes instructions that define the operation of the disturbance detection circuit 95. In other words, the functions of the disturbance detection circuit 95 may be realized by software. The program may be transmitted from a computer storing the program to the camera unit 9 via a transmission medium or by transmission waves in the transmission medium. A "transmission medium" that transmits the program is a medium that has the function of transmitting information. Media that have the function of transmitting information include networks (communication networks) such as the Internet and communication lines (communication lines) such as telephone lines. The above-mentioned program may realize some of the above-mentioned functions. Furthermore, the above-mentioned program may be a difference file (difference program). The above-mentioned functions may be realized by combining a program already recorded on the computer with a difference program.

[0045] 3 shows the configuration of the image sensor 90. The image sensor 90 has an imaging section 20, a timing generator 21, a vertical selection circuit 22, a column circuit section 23, a horizontal selection circuit 24, and an output section 25.

[0046] The imaging unit 20 has two or more pixels 26 arranged in a matrix. The two or more pixels 26 form an array of m rows and n columns. The number of rows (m) is two or more, and the number of columns (n) is two or more. The number of rows and the number of columns do not need to be the same. Each pixel 26 outputs a first pixel signal having a signal level and a second pixel signal having a reset level.

[0047] The timing generator 21 and the vertical selection circuit 22 constitute a drive circuit 28 that drives two or more pixels 26. The timing generator 21 generates a timing signal based on the internal clock signal output from the PLL 94, and outputs the timing signal to the vertical selection circuit 22. The vertical selection circuit 22 selects pixels 26 arranged in the row direction in an array of two or more pixels 26. The vertical selection circuit 22 controls the operation of the selected pixels 26. The vertical selection circuit 22 outputs a control signal for controlling the two or more pixels 26 for each row in the array of two or more pixels 26. The voltage of the control signal changes at a timing according to the timing signal.

[0048] The column circuit unit 23 has two or more column circuits 27. Each column circuit 27 is arranged for each column in an array of two or more pixels 26. Each column circuit 27 is connected to a vertical signal line 33 extending in the vertical direction, i.e., the column direction. The vertical signal line 33 is arranged for each column in the array of two or more pixels 26. The vertical signal line 33 is connected to the pixels 26 in each column. Each column circuit 27 is electrically connected to each pixel 26 via the vertical signal line 33. Each column circuit 27 holds the first pixel signal and the second pixel signal output from each pixel 26.

[0049] Each column circuit 27 is connected to a horizontal signal line 34 extending in the horizontal direction, i.e., the row direction. A selection pulse is output from the horizontal selection circuit 24 to each column circuit 27. The column circuit 27 selected based on the selection pulse outputs a first pixel signal and a second pixel signal to the horizontal signal line 34.

[0050] One column circuit 27 may be arranged for each of two or more columns in an array of two or more pixels 26, and one column circuit 27 may be used in a time-division manner for two or more columns. Therefore, it is sufficient that the column circuits 27 are arranged to correspond to one or more columns in an array of two or more pixels 26.

[0051] The horizontal signal line 34 is connected to the output unit 25. The horizontal selection circuit 24 sequentially selects the column circuits 27 by sequentially outputting selection pulses to the column circuits 27. The first pixel signal and the second pixel signal output from the column circuit 27 selected by the horizontal selection circuit 24 are transferred to the output unit 25.

[0052] The output unit 25 generates a video signal based on the first pixel signal and the second pixel signal. For example, the video signal is a difference between the first pixel signal and the second pixel signal. The output unit 25 outputs the video signal to the video transmission circuit 92.

[0053] 4 shows the configuration of the PLL 94 and the disturbance detection circuit 95. The PLL 94 has a phase / frequency detector (PFD) 940, a charge pump (CP) 941, a filter 942, a voltage-controlled oscillator (VCO) 943, and a frequency divider 944. The disturbance detection circuit 95 has a counter 950, a determination circuit 951, and a control circuit 952.

[0054] An internal clock signal CLK1 and an external clock signal CLK2 are input to the PFD 940. The internal clock signal CLK1 is generated inside the PLL 94. The external clock signal CLK2 is output from the clock receiving circuit 93. The PFD 940 compares the phase of the internal clock signal CLK1 with the phase of the external clock signal CLK2. The PFD 940 also compares the frequency of the internal clock signal CLK1 with the frequency of the external clock signal CLK2. The PFD 940 outputs a pulse signal indicating the comparison result to the CP 941 and the disturbance detection circuit 95.

[0055] The CP 941 outputs a control signal to the filter 942 based on the pulse signal output from the PFD 940. The control signal has a current value according to the result of comparison by the PFD 940. The filter 942 outputs an oscillation control signal to the VCO 943 based on the control signal output from the CP 941. The oscillation control signal has a voltage value according to the control signal output from the CP 941.

[0056] VCO 943 generates a clock signal having a phase and frequency according to the oscillation control signal output from filter 942. The frequency of the clock signal generated by VCO 943 is higher than the frequency of internal clock signal CLK1 and the frequency of external clock signal CLK2. The clock signal generated by VCO 943 is output to frequency divider 944. The clock signal generated by VCO 943 is also output to image sensor 90 and the like as clock signal CLK3. Frequency divider 944 generates internal clock signal CLK1 having a frequency that is 1 / N times the frequency of the clock signal output from VCO 943, where N is an integer of 2 or greater.

[0057] The CP 941 , filter 942 , VCO 943 , and frequency divider 944 constitute a clock synchronization circuit 945 that performs synchronization processing to generate an internal clock signal CLK 1 synchronized with the external clock signal CLK 2 based on the comparison result in the FPD 940 .

[0058] The counter 950 counts the time width of the pulse signal output from the PFD 940 and outputs the count value to a determination circuit 951. This counting is performed in synchronization with the clock signal CLK3 output from the VCO 943. The counter 950 has a first counter 9500 and a second counter 9501. The determination circuit 951 determines whether or not a disturbance is applied to the external clock signal CLK2 based on the count value and outputs a signal indicating the determination result to a control circuit 952. The control circuit 952 controls the CP 941 in accordance with the signal output from the determination circuit 951.

[0059] 5 shows the configuration of the PFD 940 and the CP 941. The PFD 940 has a delay circuit 9400, a delay circuit 9401, and an AND circuit 9402. The CP 941 has a switch 9410, a switch 9411, a current source 9412, a current source 9413, a selector 9414, and a selector 9415.

[0060] The power supply voltage VDD is input to the D terminal of the delay circuit 9400, and the internal clock signal CLK1 is input to the clock terminal of the delay circuit 9400. When the voltage of the internal clock signal CLK1 changes from low (L) level to high (H) level, the delay circuit 9400 outputs a signal UP having the power supply voltage VDD (H level) from the Q terminal. The H level is higher than the L level.

[0061] The power supply voltage VDD is input to the D terminal of the delay circuit 9401, and the external clock signal CLK2 is input to the clock terminal of the delay circuit 9401. When the voltage of the external clock signal CLK2 changes from the L level to the H level, the delay circuit 9401 outputs a signal DN having the power supply voltage VDD (H level) from the Q terminal.

[0062] Signals UP and DN are input to an AND circuit 9402. The AND circuit 9402 outputs a reset signal RST corresponding to the result of the AND operation of signals UP and DN to delay circuits 9400 and 9401. The reset signal RST has an H level or an L level. When a reset signal RST having an L level is input to delay circuit 9400, delay circuit 9400 resets signal UP. When a reset signal RST having an L level is input to delay circuit 9401, delay circuit 9401 resets signal DN.

[0063] A signal UP is input to a switch 9410 via a selector 9414, and a signal DN is input to a switch 9411 via a selector 9415. The states of the switches 9410 and 9411 can be switched between an ON state and an OFF state. When the voltage of the signal UP (signal DN) is at an H level, the switch 9410 (switch 9411) is in an ON state. When the voltage of the signal UP (signal DN) is at an L level, the switch 9410 (switch 9411) is in an OFF state.

[0064] When switch 9410 is in the on state, switch 9410 applies the current flowing in current source 9412 to filter 942. When switch 9410 is in the off state, switch 9410 stops applying current to filter 942. When switch 9411 is in the on state, switch 9411 draws the same current as the current flowing in current source 9413 from filter 942. When switch 9411 is in the off state, switch 9411 stops drawing current from filter 942.

[0065] The signal UP is input to the selector 9414, and the signal DN is input to the selector 9415. The state of the selector 9414 (selector 9415) can be switched between a first state and a second state in response to a control signal CTL1 (control signal CTL2) output from the control circuit 952. When the state of the selector 9414 (selector 9415) is the first state, the selector 9414 (selector 9415) outputs the signal UP (signal DN) to the switch 9410 (switch 9411). When the state of the selector 9414 (selector 9415) is the second state, the selector 9414 (selector 9415) outputs a signal having an L level to the switch 9410 (switch 9411).

[0066] When no disturbance is applied to external clock signal CLK2, control circuit 952 outputs control signals CTL1 and CTL2 for setting the states of selectors 9414 and 9415 to the first state. When a disturbance is applied to external clock signal CLK2, control circuit 952 outputs control signals CTL1 and CTL2 for setting the states of selectors 9414 and 9415 to the second state.

[0067] When the selectors 9414 and 9415 are in the second state, each of the selectors 9414 and 9415 outputs a signal having an L level. At this time, the switches 9410 and 9411 are in the OFF state. Therefore, the output of the control signal from the CP 941 to the filter 942 is stopped, and the application of current to the filter 942 and the extraction of current from the filter 942 are stopped. The filter 942 outputs an oscillation control signal having a fixed voltage to the VCO 943. As a result, the PLL 94 stops the synchronization process, and the VCO 943 outputs the internal clock signal CLK1 having a fixed phase and frequency. The VCO 943 maintains the phase and frequency of the internal clock signal CLK1 before the synchronization process was stopped. After the PLL 94 stops the synchronization process, the phase / frequency of the internal clock signal CLK1 does not necessarily match the phase / frequency of the external clock signal CLK2.

[0068] 6 and 7 show waveforms of the internal clock signal CLK1, the external clock signal CLK2, the signal UP, the signal DN, and the reset signal RST. The operation of the PLL 94 will be explained using FIGS.

[0069] 6 shows the waveforms of the signals when the frequency of signal UP is higher than the frequency of signal DN. Immediately before timing T10, the voltages of internal clock signal CLK1, external clock signal CLK2, signals UP and DN, and reset signal RST are all at the L level.

[0070] The voltage of internal clock signal CLK1 changes to H level at timing T10. Therefore, the voltage of signal UP changes to H level at timing T10. Since the voltage of signal UP is H level and the voltage of signal DN is L level, AND circuit 9402 outputs reset signal RST having L level.

[0071] The voltage of external clock signal CLK2 changes to H level at timing T11, which is after timing T10. Therefore, the voltage of signal DN changes to H level at timing T11. Because the voltage of signal UP is H level and the voltage of signal DN is also H level, AND circuit 9402 outputs reset signal RST having H level. Therefore, signals UP and DN are reset immediately after timing T11, and the voltages of signals UP and DN each change to L level. Because the voltages of signals UP and DN each are L level, AND circuit 9402 outputs reset signal RST having L level.

[0072] The voltage of internal clock signal CLK1 changes to L level at timing T12, which is later than timing T11. The voltage of external clock signal CLK2 changes to L level at timing T13, which is later than timing T12. Thereafter, the same operations as above are repeated.

[0073] 6, when the frequency of signal UP is higher than the frequency of signal DN, the duration of the H level of signal UP is longer than the duration of the H level of signal DN. When the frequency of signal UP is lower than the frequency of signal DN, the duration of the H level of signal UP is shorter than the duration of the H level of signal DN.

[0074] 7 shows the waveforms of the signals when the phase of signal UP leads the phase of signal DN. Signal UP and signal DN have the same frequency. Just before timing T20, the voltages of internal clock signal CLK1, external clock signal CLK2, signals UP and DN, and reset signal RST are all at the L level.

[0075] The voltage of internal clock signal CLK1 changes to H level at timing T20. Therefore, the voltage of signal UP changes to H level at timing T20. Since the voltage of signal UP is H level and the voltage of signal DN is L level, AND circuit 9402 outputs reset signal RST having L level.

[0076] The voltage of external clock signal CLK2 changes to H level at timing T21, which is after timing T20. Therefore, the voltage of signal DN changes to H level at timing T21. Because the voltage of signal UP is H level and the voltage of signal DN is also H level, AND circuit 9402 outputs reset signal RST having H level. Therefore, signals UP and DN are reset immediately after timing T21, and the voltages of signals UP and DN each change to L level. Because the voltages of signals UP and DN are L level, AND circuit 9402 outputs reset signal RST having L level.

[0077] The voltage of the internal clock signal CLK1 changes to L level at timing T22, which is later than timing T21. The voltage of the external clock signal CLK2 changes to L level at timing T23, which is later than timing T22. Thereafter, the same operations as above are repeated.

[0078] 8 shows a clock adjustment method in the first embodiment. Using FIG. 8, the process of controlling the execution of synchronization processing in the PLL 94 will be explained.

[0079] The signal UP output from the delay circuit 9400 is input to the first counter 9500, and the signal DN output from the delay circuit 9401 is input to the second counter 9501. The first counter 9500 counts up during a period when the voltage of the signal UP is at an H level, thereby measuring the time width of the pulse of the signal UP. The second counter 9501 counts up during a period when the voltage of the signal DN is at an H level, thereby measuring the time width of the pulse of the signal DN. The first counter 9500 and the second counter 9501 count up in synchronization with the clock signal CLK3 output from the VCO 943. The first counter 9500 and the second counter 9501 output their count values ​​to the determination circuit 951 (step S100).

[0080] The determination circuit 951 determines whether the difference (the difference is a positive integer) between the count value of the signal UP and the count value of the signal DN is equal to or greater than a threshold value. Based on this, the determination circuit 951 determines whether or not to stop synchronization processing in the PLL 94. The threshold value is pre-stored in the memory in the camera unit 9. The determination circuit 951 outputs the determination result to the control circuit 952 (step S105).

[0081] If the difference between the two count values ​​is less than the threshold value in step S105, it can be determined that no disturbance has been applied to the external clock signal CLK2. At this time, the determination circuit 951 determines whether the count value of the signal UP or the count value of the signal DN has reached the threshold value. By making this determination, the determination circuit 951 determines whether to reset the count values ​​of the first counter 9500 and the second counter 9501. The threshold value is pre-stored in the memory within the camera unit 9 (step S135).

[0082] When the count value of the signal UP and the count value of the signal DN are less than the threshold value in step S135, step S100 is executed. When the count value of the signal UP or the count value of the signal DN reaches the threshold value in step S135, the determination circuit 951 resets the count values ​​of the first counter 9500 and the second counter 9501 (step S140). The determination circuit 951 may reset the count values ​​of the first counter 9500 and the second counter 9501 every time one line period or one frame period has elapsed. After the count values ​​of the first counter 9500 and the second counter 9501 have been reset, step S100 is executed.

[0083] If the difference between the two count values ​​is equal to or greater than the threshold value in step S105, it can be determined that a disturbance is being applied to external clock signal CLK2 in response to the operation of the high-frequency device. At this time, control circuit 952 outputs control signal CTL1 to selector 9414 to set the state of selector 9414 to the second state, and outputs control signal CTL2 to selector 9415 to set the state of selector 9415 to the second state. This causes control circuit 952 to cause PLL 94 to stop synchronization processing (step S110).

[0084] After the PLL 94 stops the synchronization process, the decision circuit 951 resets the count values ​​of the first counter 9500 and the second counter 9501 (step S115).

[0085] After the count values ​​of the first counter 9500 and the second counter 9501 are reset, the first counter 9500 counts up during the period when the voltage of the signal UP is at H level, thereby measuring the time width of the pulse of the signal UP. The second counter 9501 counts up during the period when the voltage of the signal DN is at H level, thereby measuring the time width of the pulse of the signal DN. The first counter 9500 and the second counter 9501 count up in synchronization with the clock signal CLK3 output from the VCO 943. The first counter 9500 and the second counter 9501 output their count values ​​to the determination circuit 951 (step S120).

[0086] The determination circuit 951 determines whether the difference between the count value of the signal UP and the count value of the signal DN is less than a threshold value. Based on this, the determination circuit 951 determines whether or not to resume synchronization processing in the PLL 94. The threshold value is pre-stored in memory within the camera unit 9. This threshold value may be the same as or different from the threshold value used in step S105. The determination circuit 951 outputs the determination result to the control circuit 952 (step S125).

[0087] If the difference between the two count values ​​is equal to or greater than the threshold value in step S125, a disturbance has been applied to the external clock signal CLK2. Therefore, the synchronization process in the PLL 94 remains stopped. The judgment circuit 951 determines whether the count value of the signal UP or the count value of the signal DN has reached the threshold value. By making this judgment, the judgment circuit 951 determines whether to reset the count values ​​of the first counter 9500 and the second counter 9501. The threshold value is pre-stored in the memory within the camera unit 9. This threshold value is the same as the threshold value in step S135 (step S145).

[0088] When the count values ​​of the signals UP and DN are less than the thresholds in step S145, step S120 is executed. When the count value of the signal UP or the count value of the signal DN reaches the threshold in step S145, the determination circuit 951 resets the count values ​​of the first counter 9500 and the second counter 9501 (step S150). The determination circuit 951 may reset the count values ​​of the first counter 9500 and the second counter 9501 every time one line period or one frame period elapses. After the count values ​​of the first counter 9500 and the second counter 9501 are reset, step S120 is executed.

[0089] If the difference between the two count values ​​is less than the threshold value in step S125, the control circuit 952 starts the timer. When the timer value reaches a predetermined value, the control circuit 952 outputs a control signal CTL1 to the selector 9414 to set the state of the selector 9414 to the first state, and outputs a control signal CTL2 to the selector 9415 to set the state of the selector 9415 to the first state. This causes the control circuit 952 to cause the PLL 94 to resume synchronization processing. The predetermined value is pre-stored in the memory in the camera unit 9 (step S130). After step S130, step S135 is executed.

[0090] If the difference between the two count values ​​is less than the threshold in step S125, it can be determined that the high-frequency device has stopped operating and that no disturbances are being applied to the external clock signal CLK2. However, immediately after the high-frequency device has stopped operating, the effects of the disturbances are not completely eliminated. Therefore, even if the high-frequency device has stopped operating, there is a possibility that the disturbances will be applied to the external clock signal CLK2 again. Therefore, after a predetermined time has elapsed since it was determined that the high-frequency device has stopped operating, the control circuit 952 causes the PLL 94 to resume synchronization processing.

[0091] When a predetermined time has elapsed since the PLL 94 stopped the synchronization process in step S110, the control circuit 952 may cause the PLL 94 to resume the synchronization process. At the time the synchronization process is resumed, a disturbance may have been applied to the external clock signal CLK2. In this case, the determination circuit 951 determines in step S105 that the difference between the count value of the signal UP and the count value of the signal DN is equal to or greater than the threshold value, and the control circuit 952 causes the PLL 94 to stop the synchronization process again in step S110.

[0092] Immediately after the endoscope system 1 is started up, it is assumed that there is a large difference between the phase / frequency of the internal clock signal CLK1 and the phase / frequency of the external clock signal CLK2, regardless of the operation of the high-frequency device. When the disturbance detection circuit 95 operates in this state, the phase / frequency of the internal clock signal CLK1 is fixed, and the state in which there is a large difference between the phase / frequency of the internal clock signal CLK1 and the phase / frequency of the external clock signal CLK2 continues.

[0093] To prevent such a state from continuing and to synchronize the internal clock signal CLK1 with the external clock signal CLK2, the control circuit 96 may cause the disturbance detection circuit 95 to stop operating until a predetermined time has elapsed since the start-up of the endoscope system 1. A value indicating the predetermined time may be stored in advance in a memory in the camera unit 9. When the predetermined time has elapsed, the control circuit 96 may cause the disturbance detection circuit 95 to start operating.

[0094] Each time the endoscope system 1 is started, the control circuit 96 may measure the time from the first timing to the second timing (synchronization time). The first timing is the timing at which the endoscope system 1 is started. The second timing is the timing at which the internal clock signal CLK1 is synchronized with the external clock signal CLK2. The predetermined time may be, for example, the average of synchronization times measured multiple times.

[0095] When the endoscope system 1 is started, the disturbance detection circuit 95 is stopped from operating. After the endoscope system 1 is started, the control circuit 96 may determine whether the internal clock signal CLK1 is synchronized with the external clock signal CLK2. When the internal clock signal CLK1 is synchronized with the external clock signal CLK2, the control circuit 96 may cause the disturbance detection circuit 95 to start operating.

[0096] An imaging device (camera unit 9) according to each aspect of the present disclosure includes two or more pixels 26, a drive circuit 28, an FPD 940 (comparison circuit), a clock synchronization circuit 945, and a disturbance detection circuit 95. The drive circuit 28 drives the two or more pixels 26 based on an internal clock signal CLK1 (first clock signal). The FPD 940 compares the phase of the internal clock signal CLK1 with the phase of an external clock signal CLK2 generated by a clock generation circuit 62 (external circuit), or compares the frequency of the internal clock signal CLK1 with the frequency of the external clock signal CLK2. The clock synchronization circuit 945 performs synchronization processing to generate an internal clock signal CLK1 synchronized with the external clock signal CLK2 based on the comparison result in the FPD 940. The disturbance detection circuit 95 detects a disturbance in the external clock signal CLK2. The disturbance detection circuit 95 compares a first difference between the phase of the internal clock signal CLK1 in the FPD 940 and the phase of the external clock signal CLK2 or a second difference between the frequency of the internal clock signal CLK1 in the FPD 940 and the frequency of the external clock signal CLK2 with a threshold value. When the first difference or the second difference is greater than the threshold value, the disturbance detection circuit 95 causes the clock synchronization circuit 945 to stop synchronization processing and fix the phase or frequency of the internal clock signal CLK1.

[0097] An imaging system (endoscopic system 1) according to each aspect of the present disclosure includes a camera unit 9 (imaging device) and a control unit 6 (control device). The control unit 6 is connected to the camera unit 9 via a clock line 32 (signal line). The control unit 6 includes a clock generation circuit 62 (external circuit) and outputs an external clock signal CLK2 to the clock line 32.

[0098] Each aspect of the present disclosure may include the following modifications. The disturbance detection circuit 95 obtains a first value by counting a signal UP (first signal) indicating the phase or frequency of the internal clock signal CLK1 based on a clock signal CLK3 (third clock signal) having a frequency higher than the frequencies of the internal clock signal CLK1 and the external clock signal CLK2. The disturbance detection circuit 95 obtains a second value by counting a signal DN (second signal) indicating the phase or frequency of the external clock signal CLK2 based on the clock signal CLK3. The disturbance detection circuit 95 obtains the first difference or the second difference by calculating the difference between the first value and the second value.

[0099] Each aspect of the present disclosure may include the following modifications: When the first value or the second value reaches a predetermined value, the disturbance detection circuit 95 resets the operation of counting the signal UP and the operation of counting the signal DN.

[0100] Each aspect of the present disclosure may include the following modifications. The clock synchronization circuit 945 has a CP 941, a filter 942, and a VCO 943. The CP 941 outputs a control signal based on the comparison result in the FPD 940. The filter 942 outputs a voltage based on the control signal. The VCO 943 generates an internal clock signal CLK1 based on the voltage. When the first difference or the second difference is greater than a threshold, the disturbance detection circuit 95 causes the CP 941 to stop outputting the control signal.

[0101] Each aspect of the present disclosure may include the following modifications: When the camera unit 9 is started, the disturbance detection circuit 95 is stopped. After a predetermined time has elapsed since the camera unit 9 was started, the disturbance detection circuit 95 starts operating.

[0102] Each aspect of the present disclosure may include the following modifications: When the camera unit 9 is started, the disturbance detection circuit 95 is stopped from operating. After the camera unit 9 is started and the internal clock signal CLK1 is synchronized with the external clock signal CLK2, the disturbance detection circuit 95 starts operating.

[0103] Each aspect of the present disclosure may include the following modifications: After the disturbance detection circuit 95 causes the clock synchronization circuit 945 to stop synchronization processing and fix the phase or frequency of the internal clock signal CLK1, when the first difference or the second difference becomes equal to or less than the threshold value, the disturbance detection circuit 95 causes the clock synchronization circuit 945 to resume synchronization processing.

[0104] Each aspect of the present disclosure may include the following modifications: After a predetermined time has elapsed from the time when the first difference or the second difference becomes equal to or less than the threshold value, the disturbance detection circuit 95 causes the clock synchronization circuit 945 to resume synchronization processing.

[0105] An endoscope 8 according to each aspect of the present disclosure includes an endoscope insertion portion 2 (scope) to be inserted into a living body, and a camera unit 9. The camera unit 9 is disposed at the tip of the endoscope insertion portion 2.

[0106] In the first embodiment, when it is detected that a disturbance is applied to the external clock signal CLK2, the disturbance detection circuit 95 causes the clock synchronization circuit 945 to stop synchronization processing and fix the phase or frequency of the internal clock signal CLK1. This allows the camera unit 9 to reduce the effect of the disturbance on the operation of adjusting the frequency or phase of the clock signal within the camera unit 9.

[0107] The disturbance detection circuit 95 stops operating immediately after the camera unit 9 is started up, so the camera unit 9 can quickly synchronize the internal clock signal CLK1 with the external clock signal CLK2.

[0108] When the first difference or the second difference becomes equal to or smaller than the threshold value after the clock synchronization circuit 945 has stopped the synchronization process, it can be determined that no disturbance has been applied to the external clock signal CLK2, and the disturbance detection circuit 95 can cause the clock synchronization circuit 945 to resume the synchronization process.

[0109] After a predetermined time has elapsed since the first difference or the second difference became equal to or smaller than the threshold, it can be determined that the influence of the disturbance has been completely eliminated, and the disturbance detection circuit 95 can cause the clock synchronization circuit 945 to resume synchronization processing.

[0110] Second Embodiment A second embodiment of the present disclosure will be described. In the second embodiment, the camera unit 9 has a PLL 94a shown in FIG.

[0111] 9 shows the configuration of a PLL 94a and a disturbance detection circuit 95. The PLL 94a has a PFD 940, a CP 941a, a filter 942, a VCO 943, a frequency divider 944, and a selector 946. The disturbance detection circuit 95 has a counter 950, a determination circuit 951, and a control circuit 952. Only the parts that differ from those shown in FIG. 4 will be described, and a description of the parts that are the same as those shown in FIG. 4 will be omitted.

[0112] The state of the selector 946 can be switched between a first state and a second state in response to a control signal output from the control circuit 952. When the selector 946 is in the first state, the selector 946 outputs the external clock signal CLK2 to the PFD 940. When the selector 946 is in the second state, the selector 946 outputs the internal clock signal CLK1 to the PFD 940.

[0113] When no disturbance is applied to external clock signal CLK2, control circuit 952 outputs a control signal to set the state of selector 946 to the first state. When a disturbance is applied to external clock signal CLK2, control circuit 952 outputs a control signal to set the state of selector 946 to the second state.

[0114] 10 shows the configuration of a PFD 940 and a CP 941a. The PFD 940 has a delay circuit 9400, a delay circuit 9401, and an AND circuit 9402. The CP 941a has a switch 9410, a switch 9411, a current source 9412, and a current source 9413. Only the parts that differ from those shown in FIG. 5 will be described, and a description of the parts that are the same as those shown in FIG. 5 will be omitted.

[0115] The external clock signal CLK2 or the internal clock signal CLK1 output from the selector 946 is input to the clock terminal of the delay circuit 9401. The CP 941a does not have the selectors 9414 and 9415 shown in FIG. 5. The signal UP output from the delay circuit 9400 is input to the switch 9410, and the signal DN output from the delay circuit 9401 is input to the switch 9411.

[0116] When selector 946 is in the first state, internal clock signal CLK1 is input to the clock terminal of delay circuit 9400, and external clock signal CLK2 is input to the clock terminal of delay circuit 9401. When selector 946 is in the second state, internal clock signal CLK1 is input to the clock terminal of delay circuit 9400 and the clock terminal of delay circuit 9401.

[0117] The same internal clock signal CLK1 is input to the clock terminal of delay circuit 9400 and the clock terminal of delay circuit 9401. Therefore, the phase of signal UP output from delay circuit 9400 is the same as the phase of signal DN output from delay circuit 9401, and the frequency of signal UP output from delay circuit 9400 is the same as the frequency of signal DN output from delay circuit 9401. As a result, VCO 943 outputs internal clock signal CLK1 having a fixed phase and frequency.

[0118] Fig. 11 shows a clock adjustment method according to the second embodiment. The process of controlling the execution of synchronization processing in the PLL 94a will be described using Fig. 11. The process that differs from the process shown in Fig. 8 will be described, and a description of the same process as the process shown in Fig. 8 will be omitted.

[0119] If the difference between the two count values ​​is equal to or greater than the threshold value in step S105, the control circuit 952 outputs a control signal to the selector 946 to set the state of the selector 946 to the second state, thereby causing the control circuit 952 to stop the synchronization process in the PLL 94a (step S110a).

[0120] When the synchronization process is stopped in step S110a, the control circuit 952 starts a timer. When the timer value reaches a predetermined value, the control circuit 952 outputs a control signal to the selector 946 to set the state of the selector 946 to the first state. This causes the control circuit 952 to cause the PLL 94a to resume the synchronization process. The predetermined value is pre-stored in the memory in the camera unit 9 (step S130a). After step S130a, step S135 is executed.

[0121] An imaging device (camera unit 9) according to each aspect of the present disclosure includes two or more pixels 26, a drive circuit 28, an FPD 940 (comparison circuit), a clock synchronization circuit 945, and a disturbance detection circuit 95. The drive circuit 28 drives the two or more pixels 26 based on an internal clock signal CLK1 (first clock signal). The FPD 940 compares the phase of the internal clock signal CLK1 with the phase of an external clock signal CLK2 generated by a clock generation circuit 62 (external circuit), or compares the frequency of the internal clock signal CLK1 with the frequency of the external clock signal CLK2. The clock synchronization circuit 945 performs synchronization processing to generate an internal clock signal CLK1 synchronized with the external clock signal CLK2 based on the comparison result in the FPD 940. The disturbance detection circuit 95 detects a disturbance in the external clock signal CLK2. The PFD 940 has a first input terminal (the clock terminal of the delay circuit 9400) and a second input terminal (the clock terminal of the delay circuit 9401). The PFD 940 compares the phase of a signal input to the first input terminal with the phase of a signal input to the second input terminal, or compares the frequency of a signal input to the first input terminal with the frequency of a signal input to the second input terminal. The disturbance detection circuit 95 compares a first difference between the phase of an internal clock signal CLK1 in the FPD 940 and the phase of an external clock signal CLK2, or a second difference between the frequency of the internal clock signal CLK1 in the FPD 940 and the frequency of the external clock signal CLK2, with a threshold value. When the first difference or the second difference is greater than the threshold value, the disturbance detection circuit 95 inputs the internal clock signal CLK1 or the external clock signal CLK2 to the first input terminal or the second input terminal. When the first difference or the second difference is equal to or smaller than the threshold, the disturbance detection circuit 95 inputs the internal clock signal CLK1 to the first input terminal and the external clock signal CLK2 to the second input terminal.

[0122] In the second embodiment, when it is detected that a disturbance is applied to the external clock signal CLK2, the disturbance detection circuit 95 causes the clock synchronization circuit 945 to fix the phase or frequency of the internal clock signal CLK1. This allows the camera unit 9 to reduce the effect of the disturbance on the operation of adjusting the frequency or phase of the clock signal within the camera unit 9.

[0123] (Modification of the Second Embodiment) A modification of the second embodiment of the present disclosure will be described. In the modification of the second embodiment, the camera unit 9 has a PLL 94b shown in FIG.

[0124] 12 shows the configuration of a PLL 94b and a disturbance detection circuit 95. The PLL 94b has a PFD 940, a CP 941a, a filter 942, a VCO 943, a frequency divider 944, and a selector 946. The disturbance detection circuit 95 has a counter 950, a determination circuit 951, and a control circuit 952. Only the parts that differ from those shown in FIG. 9 will be described, and a description of the parts that are the same as those shown in FIG. 9 will be omitted.

[0125] When the selector 946 is in the first state, the selector 946 outputs the internal clock signal CLK1 to the PFD 940. When the selector 946 is in the second state, the selector 946 outputs the external clock signal CLK2 to the PFD 940.

[0126] When selector 946 is in the first state, internal clock signal CLK1 is input to the clock terminal of delay circuit 9400, and external clock signal CLK2 is input to the clock terminal of delay circuit 9401. When selector 946 is in the second state, external clock signal CLK2 is input to the clock terminal of delay circuit 9400 and the clock terminal of delay circuit 9401.

[0127] The same external clock signal CLK2 is input to the clock terminal of delay circuit 9400 and the clock terminal of delay circuit 9401. Therefore, the phase of signal UP output from delay circuit 9400 is the same as the phase of signal DN output from delay circuit 9401, and the frequency of signal UP output from delay circuit 9400 is the same as the frequency of signal DN output from delay circuit 9401. As a result, VCO 943 outputs internal clock signal CLK1 having a fixed phase and frequency.

[0128] In a modification of the second embodiment, the camera unit 9 can reduce the influence of external disturbances on the operation of adjusting the frequency or phase of the clock signal in the camera unit 9, similar to the second embodiment.

[0129] Although preferred embodiments of the present disclosure have been described above, the present disclosure is not limited to these embodiments and their modifications. Addition, omission, substitution, and other modifications of the configuration are possible without departing from the spirit of the present disclosure. Furthermore, the present disclosure is not limited by the above description, but is limited only by the scope of the appended claims.

[0130] According to each embodiment of the present disclosure, the imaging device, endoscope, imaging system, and clock adjustment method can reduce the effect of external disturbances on the operation of adjusting the frequency or phase of a clock signal in the imaging device.

[0131] REFERENCE SIGNS LIST 1 Endoscope system 2 Endoscope insertion section 2a Insertion section 2b Tip 3 Transmission cable 4 Operation section 5 Connector section 6 Control unit 7 Display device 8 Endoscope 9 Camera unit 20 Imaging section 21 Timing generator 22 Vertical selection circuit 23 Column circuit section 24 Horizontal selection circuit 25 Output section 26 Pixel 27 Column circuit 28 Drive circuit 30 Power supply line 31 Video line 32 Clock line 60 Voltage generation circuit 61 Video processing circuit 62 Clock generation circuit 63, 96, 952 Control circuit 90 Image sensor 91 Voltage regulator 92 Video transmission circuit 93 Clock reception circuit 94, 94a, 94b PLL 95 Disturbance detection circuit 940 PFD 941, 941a CP 942 Filter 943 VCO 944 Frequency divider 945: Clock synchronization circuit 946, 9414, 9415: Selector 950: Counter 951: Decision circuit 9400, 9401: Delay circuit 9402: AND circuit 9410, 9411: Switch 9412, 9413: Current source 9500: First counter 9501: Second counter

Claims

1. An imaging device comprising: pixels; a drive circuit that drives the pixels based on a first clock signal; a comparison circuit that compares the phase or frequency of the first clock signal with a second clock signal generated by an external circuit; a clock synchronization circuit that performs synchronization processing to generate the first clock signal synchronized with the second clock signal based on a result of the comparison in the comparison circuit; and a disturbance detection circuit that detects a disturbance in the second clock signal, wherein the disturbance detection circuit compares a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold, and when the first difference or the second difference is greater than the threshold, causes the clock synchronization circuit to stop the synchronization processing and fix the phase or the frequency of the first clock signal.

2. The imaging device according to claim 1, wherein the disturbance detection circuit: obtains a first value by counting a first signal indicating the phase of the first clock signal or the frequency of the first clock signal based on a third clock signal having a frequency higher than the frequency of the first clock signal and the frequency of the second clock signal; obtains a second value by counting a second signal indicating the phase of the second clock signal or the frequency of the second clock signal based on the third clock signal; and obtains the first difference or the second difference by calculating the difference between the first value and the second value.

3. The imaging device according to claim 2, wherein when the first value or the second value reaches a predetermined value, the disturbance detection circuit resets the operation of counting the first signal and the operation of counting the second signal.

4. The imaging device according to claim 1, wherein the clock synchronization circuit comprises: a charge pump that outputs a control signal based on the result of comparison in the comparison circuit; a filter that outputs a voltage based on the control signal; and a voltage-controlled oscillator that generates the first clock signal based on the voltage; and when the first difference or the second difference is greater than the threshold value, the disturbance detection circuit causes the charge pump to stop outputting the control signal.

5. The imaging device according to claim 1, wherein the disturbance detection circuit is inactive when the imaging device is started, and the disturbance detection circuit starts operating after a predetermined time has elapsed from the timing when the imaging device is started.

6. The imaging device according to claim 1, wherein the disturbance detection circuit is inactive when the imaging device is started, and the disturbance detection circuit starts operating after the imaging device is started and the first clock signal is synchronized with the second clock signal.

7. The imaging device according to claim 1, wherein, after the disturbance detection circuit has caused the clock synchronization circuit to stop the synchronization process and fixed the phase or the frequency of the first clock signal, when the first difference or the second difference becomes equal to or less than the threshold value, the disturbance detection circuit causes the clock synchronization circuit to resume the synchronization process.

8. The imaging device according to claim 7, wherein the disturbance detection circuit causes the clock synchronization circuit to resume the synchronization process after a predetermined time has elapsed since the first difference or the second difference became equal to or less than the threshold value.

9. A pixel, comprising: a drive circuit that drives the pixel based on a first clock signal; a comparison circuit that compares the phase or frequency of the first clock signal with a second clock signal generated by an external circuit; a clock synchronization circuit that performs synchronization processing to generate the first clock signal synchronized with the second clock signal based on a result of the comparison in the comparison circuit; and a disturbance detection circuit that detects a disturbance in the second clock signal, wherein the comparison circuit has a first input terminal and a second input terminal, and the comparison circuit compares the phase or frequency of a signal input to the first input terminal with a signal input to the second input terminal, and the disturbance detection circuit compares a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold, and when the first difference or the second difference is greater than the threshold, inputs the first clock signal or the second clock signal to the first input terminal and the second input terminal, When the first difference or the second difference is equal to or smaller than the threshold, the first clock signal is input to the first input terminal, and the second clock signal is input to the second input terminal.

10. An endoscope comprising: a scope to be inserted into a living body; and the imaging device according to claim 1, wherein the imaging device is disposed at the tip of the scope.

11. An imaging system comprising: an imaging device according to claim 1; and a control device connected to said imaging device via a signal line, having said external circuit, and outputting said second clock signal to said signal line.

12. A clock adjustment method for adjusting the phase or frequency of a first clock signal for driving a pixel, comprising: comparing the phase or frequency of the first clock signal with that of a second clock signal generated by an external circuit in a comparison circuit; performing a synchronization process to generate the first clock signal synchronized with the second clock signal based on the comparison result in the comparison circuit; comparing a first difference indicating the phase difference or a second difference indicating the frequency difference in the comparison circuit with a threshold; and stopping the synchronization process and fixing the phase or frequency of the first clock signal when the first difference or the second difference is greater than the threshold.

Images