Semiconductor device and method for fabricating semiconductor device

Abstract

This semiconductor device has an active region (90) through which a current flows and a termination structure (91) which is disposed outside the active region (90) and in which is formed a breakdown voltage structure surrounding the periphery of the active region (90). The termination structure (91) comprises: a silicon semiconductor substrate (18) using antimony as a n-type dopant; a n-type first semiconductor region (100) provided on a surface layer of a front surface of the semiconductor substrate (18); and a p-type second semiconductor region (11) selectively provided on the front surface of the silicon semiconductor substrate (18). The impurity concentration of the first semiconductor region (100) is lower than the impurity concentration of the second semiconductor region (11), and is the same as or higher than the impurity concentration of a bulk region (111) on a back-surface side of the semiconductor substrate (18).

Description

Semiconductor device and method for manufacturing the same

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same.

[0002] 2. Description of the Related Art Conventionally, semiconductor devices using a silicon (Si) substrate in which antimony (Sb) is used as an n-type dopant material have been known (see, for example, Patent Documents 1 and 2 listed below).

[0003] JP 2020-074381 A JP 2017-063187 A

[0004] Conventional semiconductor devices using Sb as an n-type dopant material have a problem in that the n-type impurity concentration on the surface of the Si substrate decreases.

[0005] In order to solve the above-mentioned problems associated with the conventional techniques, the present disclosure aims to provide a semiconductor device and a method for manufacturing the semiconductor device that can prevent a decrease in the n-type impurity concentration on the surface of a Si substrate when Sb is used as an n-type dopant material.

[0006] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: It includes an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The termination structure includes a silicon semiconductor substrate using antimony as an n-type dopant, a first n-type semiconductor region provided in a surface layer on the front surface of the silicon semiconductor substrate, and a second p-type semiconductor region selectively provided on the front surface of the silicon semiconductor substrate. The impurity concentration of the first semiconductor region is lower than the impurity concentration of the second semiconductor region and is the same as or higher than the impurity concentration of a bulk region on the back surface of the silicon semiconductor substrate.

[0007] According to the above disclosure, it is possible to stably control the n-type impurity concentration in the front surface of the semiconductor substrate, and the impurity concentration in the front surface of the semiconductor substrate is not affected by the amount of Sb incorporated into the thermal oxide film, thereby providing a power semiconductor with stable breakdown voltage characteristics and long-term reliability.

[0008] The semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure have the advantage that when Sb is used as an n-type dopant material, it is possible to prevent a decrease in the n-type impurity concentration on the surface of the Si substrate.

[0009] Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment, Fig. 2 is a graph showing the n-type impurity concentration distribution of the semiconductor device according to the embodiment, and Fig. 3 is a graph showing the n-type impurity concentration distribution of a conventional semiconductor device.

[0010] <Outline of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, a semiconductor device according to the present disclosure has the following features: It includes an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The termination structure includes a silicon semiconductor substrate using antimony as an n-type dopant, a first n-type semiconductor region provided in a surface layer on the front surface of the silicon semiconductor substrate, and a second p-type semiconductor region selectively provided on the front surface of the silicon semiconductor substrate. The impurity concentration of the first semiconductor region is lower than the impurity concentration of the second semiconductor region and is the same as or higher than the impurity concentration of a bulk region on the back surface of the silicon semiconductor substrate.

[0011] According to the above disclosure, it is possible to stably control the n-type impurity concentration in the front surface of the semiconductor substrate, and the impurity concentration in the front surface of the semiconductor substrate is not affected by the amount of Sb incorporated into the thermal oxide film, thereby providing a power semiconductor with stable breakdown voltage characteristics and long-term reliability.

[0012] In addition, the semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the first semiconductor region is doped with any one of phosphorus, antimony, and arsenic, or a combination thereof.

[0013] Furthermore, in the semiconductor device disclosed above, the impurity concentration of the first semiconductor region is higher than the impurity concentration of the bulk region by not less than −5% and not more than +5%.

[0014] Furthermore, in the semiconductor device disclosed above, the impurity concentration of the first semiconductor region is 10% to 20% higher than the impurity concentration of the bulk region.

[0015] In addition, in the semiconductor device according to the present disclosure, the thickness of the first semiconductor region is 5.0 μm or more and 12.0 μm or less.

[0016] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a manufacturing method of a semiconductor device according to the present disclosure has the following features. The method is a manufacturing method of a semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region. The method includes a first step of forming an n-type first semiconductor region in a surface layer on the front surface of a silicon semiconductor substrate using antimony as an n-type dopant, and a second step of selectively forming a p-type second semiconductor region on the front surface of the silicon semiconductor substrate. In the first step, the impurity concentration of the first semiconductor region is formed to be the same as or higher than the impurity concentration of a bulk region on the back surface side of the silicon semiconductor substrate than that of the second semiconductor region.

[0017] <Findings underlying the present disclosure> First, problems with conventional semiconductor devices will be described. Conventionally, when Sb is used as an n-type dopant material, Sb has a tendency to be easily incorporated into a thermally oxidized film by thermal oxidation, and when the semiconductor device is completed, the n-type impurity concentration on the Si substrate surface tends to decrease.

[0018] Fig. 3 is a graph showing the n-type impurity concentration distribution of a conventional semiconductor device. In Fig. 3, the vertical axis represents the n-type impurity concentration, the horizontal axis represents the depth from the Si substrate surface, and position S represents the outermost surface of the Si substrate. Fig. 3 shows the n-type impurity concentration distribution near the Si substrate surface in a conventional semiconductor device fabricated using a Si substrate using Sb as an n-type dopant.

[0019] 3, in the vicinity of the Si substrate surface T, Sb is incorporated into the thermal oxide film, and the n-type impurity concentration is about 30% lower than the n-type impurity concentration in the substrate bulk region 111. The amount of reduction in the n-type impurity concentration in the Si substrate surface is determined by the amount incorporated into the thermal oxide film, and is therefore affected by variations in the thickness of the thermal oxide film and the heat treatment conditions during the wafer process, making the amount of reduction in the n-type impurity concentration in the Si substrate surface prone to become unstable. The n-type impurity concentration in the Si substrate surface affects the electric field distribution in the breakdown voltage structure of the semiconductor device, which poses the problem of variations in the breakdown voltage characteristics and charge resistance, which are related to the long-term reliability of the semiconductor device.

[0020] Preferred embodiments of a semiconductor device and a method for manufacturing a semiconductor device according to the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - symbols attached to n or p indicate higher and lower impurity concentrations than layers and regions without these symbols, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, descriptions of "same" or "equivalent" should preferably include variations within 5% in consideration of variations in manufacturing.

[0021] (Embodiment) The structure of a semiconductor device according to an embodiment will be described using an IGBT (Insulated Gate Bipolar Transistor) as an example. Fig. 1 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment. The semiconductor device according to the embodiment shown in Fig. 1 is an IGBT 150 with a trench gate structure.

[0022] The IGBT 150 includes an active region 90 and an edge termination region 91 surrounding the active region 90. The active region 90 is a region through which current flows when the IGBT is in an on-state. The edge termination region 91 includes a breakdown voltage maintaining region that relieves the electric field on the front surface side of the semiconductor substrate in the drift region and maintains a breakdown voltage. Note that the boundary between the active region 90 and the edge termination region 91 is provided on only one side with a n-type dielectric layer, which will be described later. + The gate trench 40 is the center of the gate trench 40 in which the emitter region 12 is provided.

[0023] n of the active region 90 - n-type drift layer - An n-type accumulation layer may be provided in the surface layer of the front surface of the n-type semiconductor substrate (silicon semiconductor substrate) 18. The doped region 100 described later may be the n-type accumulation layer. An n-type accumulation layer does not necessarily have to be provided. - The n-type semiconductor substrate 18 is a Si substrate using Sb as an n-type dopant material. - A p-type base region 14 is provided on the front surface side of the p-type semiconductor substrate 18. The p-type base region 14 functions as a channel region in the IGBT 150. An n-type - A gate trench 40 is provided that reaches the semiconductor substrate 18. The gate trench 40 has n-type + The p-type emitter regions 12 are provided and arranged at predetermined intervals in, for example, a striped planar layout, separating the p-type base region 14 into a plurality of regions (mesa portions). A gate insulating film 50 is provided inside the gate trench 40 along the inner wall of the gate trench 40, and a gate electrode 51 is provided inside the gate insulating film 50.

[0024] Inside the p-type base region 14, n-type semiconductor layers are formed in each mesa portion. + An n-type emitter region 12 is optionally provided. + The n-type emitter region 12 faces the gate electrode 51 across the gate insulating film 50 provided on the inner wall of the gate trench 40. The emitter electrode 52 is connected to the n-type emitter region 12 via a contact hole. + The n-type emitter region 12 is in contact with the n-type emitter region 12 and is electrically insulated from the gate electrode 51 by the interlayer insulating film 38. + An opening may be selectively provided in the p-type emitter region 12, and the emitter electrode 52 and the p-type base region 14 may be electrically connected through the opening. A barrier metal 53 may be provided between the emitter electrode 52 and the interlayer insulating film 38 to prevent diffusion of metal atoms from the emitter electrode 52 toward the gate electrode 51, for example.

[0025] Furthermore, a contact electrode 54 may be embedded in a contact hole formed in the interlayer insulating film 38. The contact electrode 54 is, for example, a metal film made of tungsten (W), which has high embedding properties. A protective film 97, such as a passivation film made of polyimide, is optionally provided on the emitter electrode 52.

[0026] n - Inside the n-type semiconductor substrate 18, on the rear surface side of the substrate, + A field stop (FS) layer 20 is provided. + The FS layer 20 is connected to the p-type base region 14 and the n-type - The pn junction between the semiconductor substrate 18 and the p + This has the function of suppressing the extension of the depletion layer toward the collector region 22 .

[0027] n - The surface layer on the back side of the n-type semiconductor substrate 18 + n type FS layer 20 - At a shallow position from the rear surface of the semiconductor substrate 18, p + A p-type collector region 22 is provided. + The surface of the collector region 22 (n - The back electrode 24 functions as a collector electrode.

[0028] n of the edge termination region 91 - A field oxide film 95 is provided on the front surface side of the n-type semiconductor substrate 18, and a conductive film 96 is provided on the field oxide film 95. The conductive film 96 may be made of a polycrystalline silicon film. - The field plate electrode 94 is provided on the n-type semiconductor substrate 18 and the conductive film 96. The field plate electrode 94 is in contact with the conductive film 96 through a contact hole formed in the interlayer insulating film 38, and is isolated from the n-type semiconductor substrate 18 by the field oxide film 95. -The field plate electrode 94 may be insulated from the conductive film 96. A barrier metal 53 may be provided between the field plate electrode 94 and the interlayer insulating film 38 to prevent diffusion of metal atoms from the field plate electrode 94 toward the conductive film 96. The contact electrode 54 may be embedded in a contact hole formed in the interlayer insulating film 38. The contact electrode 54 is, for example, a metal film made of tungsten (W), which has high embeddability.

[0029] The edge termination region 91 has a p + The edge termination region 91 is provided with a p well region 11. + a p-type guard ring (a p-type second semiconductor region) 92 and a p-type + An n-type channel stopper 74 is provided. The channel stopper 74 may also be n-type. A plurality of guard rings 92 may be provided. FIG. 1 shows an example in which a plurality of guard rings 92 are provided.

[0030] Guard ring 92 may be provided in edge termination region 91 to surround active region 90. When multiple guard rings 92 are provided, the impurity concentrations of the guard rings 92 may be the same. A conductive film 96 is provided on guard ring 92, and guard ring 92 contacts conductive film 96 via a contact hole formed in field oxide film 95. A field plate electrode 94 is provided on the upper surface of interlayer insulating film 38 so as to contact the surfaces of channel stopper 74 and guard ring 92. A protective film 97, such as a passivation film made of polyimide, is provided on interlayer insulating film 38 and field plate electrode 94. A protective film 97, such as a passivation film made of polyimide, is provided on the back surface of edge termination region 91. + collector region 22 and n + A mold FS layer 20 is provided.

[0031] In the embodiment, the n of the edge termination region 91 - An n-type dopant doped region (n-type first semiconductor region) 100 is provided on the front surface side of the n-type semiconductor substrate 18. The n-type dopant doped region 100 is formed by doping n-type dopants during wafer processing. -The n-type dopant doped region 100 is formed by doping the front surface of the n-type semiconductor substrate 18 with an n-type dopant such as phosphorus (P), arsenic (As), Sb, or a combination thereof, and activating and diffusing it by heat treatment. The n-type dopant doped region 100 is formed by Sb being incorporated into a thermal oxide film, and the n-type impurity concentration is reduced. - The impurity concentration of the semiconductor substrate 18 may be compensated for. + If the n-type dopant doped region 100 is deeper than the n-type well region 11, the breakdown voltage may decrease. + It is preferable that the n-type dopant doped region 100 is shallower than the n-type well region 11. The n-type dopant doped region 100 may be formed continuously from the edge termination region 91 to the active region 90. By continuing to the active region 90, it acts as a so-called n-type accumulation layer, and by appropriately setting the concentration, it is possible to reduce the on-state voltage without reducing the breakdown voltage. Furthermore, the n-type dopant doped region 100 may not be formed in the active region 90. By not forming the n-type dopant doped region 100 in the active region 90, it is possible to eliminate concerns about a reduction in the breakdown voltage.

[0032] 2 is a graph showing the n-type impurity concentration distribution of the semiconductor device according to the embodiment. In FIG. 2, the vertical axis represents the n-type impurity concentration, and the horizontal axis represents the n - The position S indicates the depth from the front surface of the semiconductor substrate 18. - 2 shows the top surface of the front surface of the n-type semiconductor substrate 18. In FIG. 2, the n-type impurity concentration distribution in the vicinity of the surface of the Si substrate in a semiconductor device fabricated using Sb as an n-type dopant in the conventional and embodiment modes. In FIG. 2, the substrate surface region 110 is n - p-type semiconductor substrate 18 + In the region where the well region 11 is provided, the bulk region 111 is p + From the well region 11, n - This is the region on the back surface side (back surface electrode 28 side) of the semiconductor substrate 18.

[0033] As shown in FIG. - The impurity concentration of the substrate surface region 110 of the n-type semiconductor substrate 18 is -The impurity concentration of the substrate surface region 110 is set to be equal to or higher than the impurity concentration of the bulk region 111 of the type semiconductor substrate 18. The dashed line (2) in Figure 2 represents the case where the impurity concentration of the substrate surface region 110 is set to be equal to or higher than the impurity concentration of the bulk region 111. For example, the impurity concentration of the substrate surface region 110 is 10% to 20% higher than the impurity concentration of the bulk region 111. The dashed line (1) in Figure 2 represents the case where the impurity concentration of the substrate surface region 110 is set to be equal to the impurity concentration of the bulk region 111. For example, the impurity concentration of the substrate surface region 110 is -5% to +5% higher than the impurity concentration of the bulk region 111.

[0034] Here, if the impurity concentration of the substrate surface region 110 is made higher than the impurity concentration of the bulk region 111, the depletion layer is less likely to extend in the edge termination region 91, and the breakdown voltage is lower than when the impurity concentration of the substrate surface region 110 is made equal to the impurity concentration of the bulk region 111. For this reason, the characteristics of the semiconductor device are improved when the impurity concentration of the substrate surface region 110 is made equal to the impurity concentration of the bulk region 111. However, making the impurity concentration of the substrate surface region 110 equal to the impurity concentration of the bulk region 111 makes it difficult to stably adjust the impurity concentration of the substrate surface region 110, making manufacturing difficult.

[0035] In this way, the n of Si using Sb - An n-type dopant doped region 100 is provided on the front surface side of the n-type semiconductor substrate 18. - The n-type impurity concentration on the front surface of the n-type semiconductor substrate 18 can be stably controlled. - The impurity concentration on the front surface of the semiconductor substrate 18 is not affected by the amount of Sb incorporated into the thermal oxide film (field oxide film 95). This makes it possible to provide a power semiconductor with stable breakdown voltage characteristics and long-term reliability. The breakdown voltage characteristics and long-term reliability are more stable when the impurity concentration in the substrate surface region 110 is 10% to 20% higher than the impurity concentration in the bulk region 111 than when the impurity concentration in the substrate surface region 110 is -5% to +5% higher than the impurity concentration in the bulk region 111.

[0036] (Method of Manufacturing a Semiconductor Device According to an Embodiment) Next, a method of manufacturing a semiconductor device according to an embodiment will be described. For example, the semiconductor device is manufactured as follows. First, an n-type semiconductor layer that will become an n-type drift layer of the active region 90 is formed. - A gate trench 40, a gate insulating film 50, and a gate electrode 51 are formed in this order on the front surface side of the n-type semiconductor substrate 18 by a general method to form a MOS gate. - On the front surface side of the n-type semiconductor substrate 18, a - Alternatively, an n-type accumulation layer may be formed at a shallow depth from the front surface of the n-type semiconductor substrate 18 by, for example, ion implantation or epitaxial growth.

[0037] Next, n - The front surface of the semiconductor substrate 18 is doped with n-type dopants such as P, As, Sb, etc., by ion implantation or the like. P, As, Sb, etc. may be doped singly or in combination. Thereafter, the n-type dopants are activated and diffused by heat treatment, thereby forming n-type dopants in the edge termination region 91. - An n-type dopant doped region 100 is formed on the front surface side of the n-type semiconductor substrate 18. The n-type dopant doped region 100 is formed by first - The front surface of the semiconductor substrate 18 may be doped with an n-type dopant by ion implantation or the like, and diffused before the MOS gate and n-type accumulation layer of the active region 90 are formed.

[0038] As mentioned above, Sb is easily taken into the thermal oxide film (field oxide film 95). For example, as shown in FIG. -The impurity concentration on the front surface of the silicon-doped semiconductor substrate 18 is about 30% lower. Therefore, when the impurity concentration of the substrate surface region 110 is to be made equal to that of the bulk region 111, the substrate surface region 110 is doped with an n-type dopant so that the impurity concentration is about 30% higher than that of the bulk region 111. In this way, Sb is incorporated into the thermal oxide film, so that after the thermal oxide film is formed, the impurity concentration of the substrate surface region 110 becomes equal to that of the bulk region 111. Similarly, when the impurity concentration of the substrate surface region 110 is to be made higher than that of the bulk region 111, the substrate surface region 110 is doped with an n-type dopant so that the impurity concentration is more than 30% higher than that of the bulk region 111. Furthermore, since P diffuses more easily than As, it is preferable to use P as the n-type dopant. When As is used, it is preferable to dope As with P because it is less diffusible.

[0039] Next, in the edge termination region 91, n - A field oxide film 95 is formed on the front surface of the semiconductor substrate 18. Next, in the edge termination region 91, the field oxide film 95 is patterned, and using the field oxide film 95 as a mask, ions of a p-type impurity such as boron (B) are implanted to form an n-type impurity. - The surface layer of the front surface of the semiconductor substrate 18 is + The mold well region 11, the guard ring 92 and the channel stopper 74 are selectively formed.

[0040] Next, p in the active region 90 and edge termination region 91 + By ion implantation of p-type impurities such as boron (B) into the active region 90 side of the well region 11, the n-type impurity is made to be lower than the bottom of the gate trench 40. - A p-type base region 14 is formed at a shallow depth from the front surface of the semiconductor substrate 18. Alternatively, if an n-type accumulation layer is present, the p-type base region 14 is formed at a shallow depth from the front surface of the semiconductor substrate 18. - A p-type base region 14 is formed at a shallow depth from the front surface of a semiconductor substrate 18 .

[0041] Next, n-type impurities such as phosphorus (P) and arsenic (As) are ion-implanted into the p-type base region 14. +The emitter region 12 is selectively formed. Next, an interlayer insulating film 38 such as a BPSG film is deposited (formed) so as to cover the gate electrode 51.

[0042] Next, the interlayer insulating film 38 is patterned to form contact holes, and n + The p-type emitter region 12 is exposed, and the channel stopper 74, p-type + The well region 11 and the guard ring 92 are exposed. Next, a contact electrode 54 is formed inside the contact hole via a barrier metal 53. Next, an emitter electrode 52 is formed, for example, by sputtering, covering the entire surface of the interlayer insulating film 38 so as to contact the contact electrode 54 inside the contact hole. A field plate electrode 94 is also formed, for example, by sputtering, in the edge termination region 91 so as to cover a portion of the surface of the interlayer insulating film 38 so as to contact the contact electrode 54 inside the contact hole. Note that the contact electrode 54 does not necessarily have to be formed; in that case, the emitter electrode 52 may be filled into the contact hole. The emitter electrode 52 and the field plate electrode 94 may be formed simultaneously or separately. In this manner, the front surface element structure of the semiconductor device according to the embodiment is formed.

[0043] Next, n - The n-type semiconductor substrate 18 is ground from the back side to a thickness corresponding to the thickness of the product to be used as a semiconductor device. - A p-type impurity such as boron (B) is ion-implanted into the entire rear surface of the n-type semiconductor substrate 18. - The surface layer of the entire back surface of the semiconductor substrate 18 is p + Next, the n-type collector region 22 is formed. - The n-type semiconductor substrate 18 is ion-implanted with n-type impurities such as phosphorus or protons on the entire rear surface thereof. - Inside the n-type semiconductor substrate 18 + The FS layer 20 is formed. + collector region 22 + The FS layer 20 may be formed first.

[0044] Next, by heat treatment (annealing), p +collector region 22 and n + The mold FS layer 20 is activated. Next, the entire front surface of the substrate is covered with a surface protection film (not shown) such as a polyimide film, and the surface protection film is patterned to expose the emitter electrode 52 and each electrode pad.

[0045] Next, p + A back electrode 24 is formed in contact with the collector region 22. The semiconductor wafer is then cut (diced) into individual chips, thereby completing the IGBT 150 shown in FIG.

[0046] As described above, according to the embodiment, the n-type Si film using Sb can be obtained. - The front surface of the semiconductor substrate is doped with an n-type dopant by ion implantation or the like, followed by heat treatment, to form an n-type dopant doped region. - The n-type impurity concentration on the front surface of the n-type semiconductor substrate can be stably controlled. - The impurity concentration on the front surface of the semiconductor substrate is not affected by the amount of Sb incorporated into the thermal oxide film, making it possible to provide a power semiconductor with stable voltage resistance characteristics and long-term reliability.

[0047] As described above, the present disclosure can be modified in various ways without departing from the spirit of the present disclosure, and in each of the above-described embodiments, for example, the dimensions of each part, the impurity concentration, etc. are variously set according to the required specifications, etc. Furthermore, although the embodiments of the present disclosure have been described using a trench-type IGBT as an example, the present disclosure is not limited to this and can be applied to semiconductor devices of various configurations, such as a planar-type IGBT, a MOS-type semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and a diode.

[0048] As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices such as inverters, power supply devices for various industrial machines, and automotive igniters.

[0049] 11 p. + Well region 12 n+ p-type emitter region 14 p-type base region 18 n - Type semiconductor substrate 20n + Type FS layer 22p + 1. N-type collector region 24 rear electrode 38 interlayer insulating film 40 gate trench 50 gate insulating film 51 gate electrode 52 emitter electrode 53 barrier metal 54 contact electrode 74 channel stopper 90 active region 91 edge termination region 92 guard ring 94 field plate electrode 95 field oxide film 96 conductive film 97 protective film 100 n-type dopant doped region 110 surface region 111 bulk region 150 IGBT

Claims

1. A semiconductor device comprising: an active region through which a current flows; and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region, wherein the termination structure comprises: a silicon semiconductor substrate using antimony as an n-type dopant; a first n-type semiconductor region provided in a surface layer of the front surface of the silicon semiconductor substrate; and a second p-type semiconductor region selectively provided on the front surface of the silicon semiconductor substrate, wherein the impurity concentration of the first semiconductor region is lower than the impurity concentration of the second semiconductor region and is the same as or higher than the impurity concentration of a bulk region on the back surface of the silicon semiconductor substrate.

2. The semiconductor device according to claim 1, wherein said first semiconductor region is doped with one of phosphorus, antimony, and arsenic, or a combination thereof.

3. The semiconductor device according to claim 1, wherein the impurity concentration of said first semiconductor region is higher than the impurity concentration of said bulk region by not less than -5% and not more than +5%.

4. The semiconductor device according to claim 1, wherein the impurity concentration of said first semiconductor region is 10% to 20% higher than the impurity concentration of said bulk region.

5. The semiconductor device according to claim 1, wherein the thickness of said first semiconductor region is 5.0 μm or more and 12.0 μm or less.

6. A method for manufacturing a semiconductor device having an active region through which a current flows, and a termination structure disposed outside the active region and having a breakdown voltage structure surrounding the periphery of the active region, the method comprising: a first step of forming an n-type first semiconductor region in a surface layer on the front surface of a silicon semiconductor substrate using antimony as an n-type dopant in the termination structure; and a second step of selectively forming a p-type second semiconductor region on the front surface of the silicon semiconductor substrate, wherein in the first step, the impurity concentration of the first semiconductor region is formed to be the same as or higher than the impurity concentration of a bulk region on the back surface side of the silicon semiconductor substrate than the second semiconductor region.

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