Photodetection device

Abstract

[Problem] To reliably join a first substrate, such as a wafer, and a second substrate, such as a logic chip. [Solution] This photodetection device comprises: a first substrate having a pixel region in which a plurality of photoelectric conversion elements for performing photoelectric conversion is arranged, and an out-of-pixel region disposed around the pixel region; and a second substrate to be joined to the first substrate by a first pad. The out-of-pixel region has a wiring pattern, a dummy pattern, the first pad, a second pad for connecting a bonding wire, and a shield pattern. An interval between the wiring patterns in the out-of-pixel region is smaller than at least one of an interval between the dummy patterns, an interval between the second pad and the wiring pattern, and an interval between the shield pattern and the wiring pattern.

Description

Photodetector

[0001] The present disclosure relates to a light detection device.

[0002] An imaging device has been proposed that improves the area efficiency of a substrate by stacking a wafer on which sensor elements are arranged and a logic chip (see Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2020-80363

[0004] In the imaging device described in Patent Document 1, a silicon nitride film constituting the inner lens is arranged from the pixel region to the extra-pixel region, and the silicon nitride film located on the pad in the extra-pixel region is removed to form a pad opening, exposing the pad electrode, and CoW (Chip on Wafer) bonding is performed with the logic chip using a solder bump.

[0005] The depth of the pad openings on the wafer tends to increase due to improved light-collecting characteristics and an increase in the number of layers stacked, making it difficult to bond the solder bumps of the logic chip to the pad electrodes on the wafer.

[0006] Therefore, the present disclosure provides a photodetector capable of bonding a first substrate such as a wafer and a second substrate such as a logic chip with high reliability.

[0007] In order to solve the above problems, according to the present disclosure, there is provided a photodetector device comprising: a first substrate having a pixel region in which a plurality of photoelectric conversion elements that perform photoelectric conversion are arranged, and an extra-pixel region arranged around the pixel region; and a second substrate joined to the first substrate by first pads, wherein the extra-pixel region has a wiring pattern, a dummy pattern, the first pad, a second pad for connecting a bonding wire, and a shield pattern, and a spacing between the wiring patterns in the extra-pixel region is smaller than at least one of the spacing between the dummy patterns, the spacing between the second pad and the wiring pattern, or the spacing between the shield pattern and the wiring pattern.

[0008] The wiring pattern and the shield pattern are electrically connected to any of the input nodes or output nodes in the pixel region, and the dummy pattern is electrically insulated from all of the input nodes and output nodes in the pixel region.

[0009] The pixel region may have a plurality of first optical members that collect light incident on each of the plurality of photoelectric conversion elements, and may further include an insulating film that is arranged from the pixel region to the extra-pixel region, is used as a material for the plurality of first optical members, and is used as an etching stopper film when forming the first pads.

[0010] The insulating film may be arranged in the extra-pixel region so as to cover at least a portion of the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern.

[0011] The refractive index difference between the first optical members in the pixel region may be within a predetermined value.

[0012] The optical element may further include a plurality of second optical members arranged closer to the light incident surface than the plurality of first optical members and guiding incident light to the plurality of first optical members.

[0013] The plurality of first optical members may be a laminated film made of an insulating material, and a silicon nitride film included in the laminated film may be used as the etching stopper film.

[0014] The second substrate may be disposed on the light incident surface side of the first substrate.

[0015] The second substrate may be disposed on the side opposite to the light incident surface of the first substrate.

[0016] Among the structures including the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern arranged in the extra-pixel region, the area density of structures in which the spacing between adjacent structures is smaller than a predetermined spacing may be less than a predetermined ratio.

[0017] The distance between at least some of the structures arranged in the extra-pixel region may be equal to or greater than the predetermined distance.

[0018] Of the structures arranged in the extra-pixel region, the area density of structures spaced apart by an interval of less than 9 μm may be less than 10%.

[0019] At least some of the structures disposed in the extra-pixel region may be spaced apart by a distance of 9 μm or more.

[0020] A ratio of a height of the structures in the extra-pixel region to a distance between the structures in the extra-pixel region may be equal to or less than a predetermined value.

[0021] The ratio of the height of the structures in the extra-pixel region to the distance between the structures in the extra-pixel region may be 0.1 or less.

[0022] The first substrate and the second substrate may be bonded via the first pad by CoW (Chip on Wafer) bonding.

[0023] The semiconductor device may further include a third substrate bonded to the surface of the first substrate opposite to the surface to which the second substrate is bonded.

[0024] The pixel regions may be distributed over the first substrate and the third substrate.

[0025] The pixel region may include pixels having the photoelectric conversion elements that detect a phase difference.

[0026] 2A is a block diagram showing a schematic configuration of a photodetector according to the present disclosure. FIG. 2A is a diagram showing a cross-sectional configuration of a photodetector according to an embodiment, and FIG. 2B is a diagram showing a planar configuration. FIG. 2B is a planar layout diagram of a sensor substrate. FIG. 3 is a diagram showing the relationship between the spacing between wiring patterns in an extra-pixel region and the spacing between dummy patterns. FIG. 4 is a diagram showing the relationship between the spacing between wiring patterns in an extra-pixel region and the spacing between a bonding pad and a wiring pattern. FIG. 5A to FIG. 5D are plan views showing representative specific examples of dummy patterns. FIG. 6 is a diagram explaining the aspect ratio of structures arranged in the extra-pixel region. FIG. 7 is a cross-sectional view showing the cross-sectional shape of a stacked insulating film for an inner lens in a photodetector according to a comparative example. FIG. 8 is a diagram showing the variation in film thickness of a silicon nitride film included in a stacked insulating film arranged from the pixel region to the extra-pixel region in a comparative example. FIG. 9 is a cross-sectional view showing the cross-sectional shape of an insulating film for an inner lens in a photodetector according to the present embodiment. FIG. 10 is a diagram showing the variation in film thickness of a silicon nitride film included in an insulating film arranged from the pixel region to the extra-pixel region in the present embodiment. 1 is a cross-sectional view of a photodetector according to a first modified example of an embodiment; 2 is a cross-sectional view of a photodetector according to a second modified example of an embodiment; 3 is a cross-sectional view of a normal pixel included in a photodetector according to an embodiment; 4 is a cross-sectional view of a phase difference pixel included in a photodetector according to an embodiment; 5 is a cross-sectional view of a photodetector according to a third modified example of an embodiment; 6 is a block diagram showing an example of a schematic configuration of a vehicle control system; 7 is an explanatory diagram showing an example of installation positions of an outside vehicle information detection unit and an imaging unit;

[0027] Hereinafter, an embodiment of a light detection device according to the present disclosure will be described with reference to the drawings. The following description will focus on the main components of the light detection device, but the light detection device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] FIG. 1 is a block diagram showing a schematic configuration of a photodetector 1 according to the present disclosure. The photodetector 1 shown in FIG. 1 shows a schematic configuration of an image sensor. Note that the photodetector 1 according to the present disclosure is not necessarily limited to an image sensor that acquires gradation information photoelectrically converted at each pixel to generate a captured image, but can also be applied to an event-based vision sensor (EVS) that detects event information at each pixel to generate an event image. This specification mainly describes an example in which the photodetector 1 according to the present disclosure is applied to a photodetector 1 such as an image sensor or an EVS. However, the photodetector 1 according to the present disclosure can also be applied to various electronic devices other than the photodetector 1.

[0029] 1 , the photodetector 1 according to the present disclosure includes a pixel array unit 2a and a peripheral circuit unit 2b. The peripheral circuit unit 2b includes, for example, a vertical drive unit 3, a column processing unit 4, a horizontal drive unit 5, a system control unit 6, a signal processing unit 7, and a data storage unit 8, and can be broadly divided into a control circuit and a logic circuit, as described below. The signal processing unit 7 and the data storage unit 8 may be mounted on the same substrate as the pixel array unit 2a, the vertical drive unit 3, etc., or may be arranged on a separate substrate. Note that the processing of the signal processing unit 7 and the data storage unit 8 may be performed by an external signal processing unit, such as a DSP (Digital Signal Processor) circuit, provided on a semiconductor chip separate from the photodetector 1.

[0030] The pixel array section 2a has a configuration in which unit pixels px, each having a photoelectric conversion section that generates and accumulates electric charges according to the amount of light received, are two-dimensionally arranged in a matrix in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Here, the row direction refers to the pixel rows of the pixel array section 2a, i.e., the row direction, and the column direction refers to the pixel columns of the pixel array section 2a, i.e., the column direction. The specific circuit configuration of the unit pixels px will be described later. Hereinafter, unit pixels px may be abbreviated to pixels px.

[0031] In the pixel array section 2a, pixel drive lines L serving as row signal lines are wired in the row direction for each pixel row, and vertical signal lines VSL serving as column signal lines are wired in the column direction for each pixel column. The pixel drive lines L transmit drive signals for driving the pixels px when reading out signals. Although FIG. 1 illustrates each pixel drive line L as a single line, the number of lines is not limited to one. One end of the pixel drive line L is connected to an output terminal of the vertical drive section 3 corresponding to each row.

[0032] The vertical drive unit 3 is composed of a shift register, an address decoder, etc., and drives each pixel px of the pixel array unit 2a simultaneously for all pixels or in row units, etc. The vertical drive unit 3, together with the system control unit 6, constitutes a drive unit that controls the operation of each pixel px of the pixel array unit 2a. Although the specific configuration of the vertical drive unit 3 is not shown in the figure, it generally has two scan systems: a readout scan system and a sweep scan system.

[0033] The readout scanning system sequentially selects and scans the pixels px of the pixel array unit 2a row by row to read out signals from the pixels px. The signals read out from the pixels px are analog signals. The sweep scanning system performs sweep scanning on the readout rows to be read out by the readout scanning system, prior to the readout scanning by an exposure time.

[0034] The sweep-out scanning by this sweep-out scanning system sweeps out unnecessary charges from the photoelectric conversion units of the pixels px in the readout row, thereby resetting the photoelectric conversion units of each pixel px. Then, sweeping out (resetting) the unnecessary charges by this sweep-out scanning system performs a so-called electronic shutter operation. Here, the electronic shutter operation refers to the operation of discarding the charges in the photoelectric conversion units and starting a new exposure (starting the accumulation of charges).

[0035] The signal read by the readout scanning system corresponds to the amount of light received since the immediately preceding readout operation or electronic shutter operation. The exposure period for pixel px is the period from the readout timing of the immediately preceding readout operation or the sweep timing of the electronic shutter operation to the readout timing of the current readout operation.

[0036] The signals output from each pixel px in a pixel row selected and scanned by the vertical drive unit 3 are input to the column processing unit 4 through each vertical signal line VSL for each pixel column. The column processing unit 4 performs predetermined signal processing on the signals output from each pixel px in the selected row through the vertical signal line VSL for each unit pixel column in the pixel array unit 2a, and temporarily holds the pixel signals after signal processing.

[0037] Specifically, the column processing unit 4 performs at least noise removal processing, such as CDS (Correlated Double Sampling) processing or DDS (Double Data Sampling) processing, as signal processing. For example, CDS processing removes reset noise and pixel-specific fixed pattern noise such as threshold variations of the amplification transistor in the unit pixel. In addition to noise removal processing, the column processing unit 4 also has, for example, an AD (analog-digital) conversion function, and converts analog pixel signals into digital signals and outputs them.

[0038] The horizontal driving unit 5 is configured with a shift register, an address decoder, etc., and sequentially selects unit circuits corresponding to pixel columns in the column processing unit 4. By selective scanning by this horizontal driving unit 5, pixel signals that have been signal-processed for each unit circuit in the column processing unit 4 are sequentially output.

[0039] The system control unit 6 is composed of a timing generator that generates various timing signals, and controls the driving of the vertical driving unit 3, column processing unit 4, and horizontal driving unit 5 based on the various timings generated by the timing generator.

[0040] The signal processing unit 7 has at least an arithmetic processing function and performs various signal processing such as arithmetic processing on the pixel signals output from the column processing unit 4. The data storage unit 8 temporarily stores data necessary for the signal processing in the signal processing unit 7. The pixel signals that have been signal processed in the signal processing unit 7 are converted into a predetermined format and output from the output unit 9 to the outside of the photodetector device 1.

[0041] FIG. 2 is a diagram showing a cross-sectional configuration ( FIG. 2A ) and a planar configuration ( FIG. 2B ) of a photodetector 1 according to an embodiment of the present disclosure. The photodetector 1 according to an embodiment is, for example, a back-illuminated (back-illuminated) CMOS (Complementary Metal Oxide Semiconductor) image sensor. More specifically, the photodetector 1 according to an embodiment is a stacked image sensor in which a semiconductor chip 50 having various signal processing circuits for performing signal processing is flip-chip mounted (CoW bonding) on ​​a sensor element 10 (first semiconductor element) mounted on a sensor substrate (first substrate) 11. Hereinafter, the semiconductor chip 50 may be referred to as a logic chip, semiconductor substrate, or second substrate. Note that FIG. 2A illustrates a cross-sectional configuration taken along line A-A in FIG. 2B .

[0042] (Sensor Element) The sensor element 10 includes a pixel region 11a in which a plurality of photoelectric conversion units 12 are two-dimensionally arranged on a sensor substrate 11 (first substrate), and an extra-pixel region 11b provided around the pixel region 11a. The pixel array unit 2a of FIG. 1 is arranged in the pixel region 11a. At least a part of the peripheral circuit unit 2b of FIG. 1 is arranged in the extra-pixel region 11b. Each of the plurality of pixels px arranged in the pixel array unit 2a has a photoelectric conversion unit 12.

[0043] In the sensor element 10, the back surface (surface SF1) of the sensor substrate 11 is a light incident surface, and a multilayer wiring layer 20 is provided on the front surface (surface SF2) of the sensor substrate 11. In the extra-pixel region 11b of the sensor element 10, the semiconductor chip 50 is bonded to the sensor substrate 11 by flip-chip mounting (CoW bonding) via pads 34 (first pads) provided on the back surface (surface SF1) of the sensor substrate 11.

[0044] The extra-pixel region 11b of the sensor element 10 is further provided with a pad (second pad) 36 connected to an external substrate (not shown) via a bonding wire on the back surface (surface SF1) of the sensor substrate 11. The pads 34 and 36 are electrically connected by, for example, a wiring layer 33 provided on the surface SF1 of the sensor substrate 11, a through via 13 penetrating the sensor substrate 11, and a multilayer wiring layer 20 provided on the front surface (surface SF2) of the sensor substrate 11.

[0045] A shield pattern 14 is provided on the back surface of the sensor substrate 11. The shield pattern 14 is a wiring pattern for shielding. The pads 14 are arranged so as to cover the vertical signal lines VSL. The locations and number of the pads 34, 36, and 14 are arbitrary.

[0046] In this specification, the pads 34 may be referred to as bump pads 34 and the pads 36 may be referred to as bonding pads 36 .

[0047] (Light-Receiving Region) The pixel region 11a is provided with a photoelectric conversion unit 12 for each pixel px, which selectively detects light in different wavelength ranges and performs photoelectric conversion. The photoelectric conversion unit 12 is, for example, an n-type semiconductor region formed in the thickness direction of the sensor substrate 11 (the Z-axis direction in FIG. 2 ), and is configured with a pn-junction photodiode (PD) with a p-type semiconductor region provided along the surface SF2 of the sensor substrate 11, and is, for example, formed buried in the sensor substrate 11 for each pixel px.

[0048] The sensor substrate 11 further includes, near the surface SF2, a charge storage section that stores signal charges generated by the photoelectric conversion section 12 and a transfer transistor (TG) that transfers the signal charges to the charge storage section. In addition to the transfer transistor (TG), other transistors, such as a reset transistor (RST), an amplification transistor (Amp), and a selection transistor (SEL), are also provided near the surface SF2 of the sensor substrate 11. These transistors, such as metal oxide semiconductor field effect transistors (MOSEFTs), constitute a pixel circuit provided for each pixel px. Each pixel circuit may have a three-transistor configuration including the transfer transistor (TG), reset transistor (RST), and amplification transistor (Amp), or a four-transistor configuration with the addition of a selection transistor (SEL). Transistors other than the transfer transistor (TG) may be shared between pixels.

[0049] In the pixel region 11a, for example, an interlayer insulating layer 31, an inner lens (first optical member) 37L, a planarizing layer 38, a protective layer 40, a color filter 41, and an on-chip lens (second optical member) 42L are provided in this order on the light incident surface (surface SF1) side of the sensor substrate 11. The inner lens 37L, the color filter 41, and the on-chip lens 42L are provided for each pixel px.

[0050] The interlayer insulating layer 31, the inner lens 37L, the planarizing layer 38, the protective layer 40, the color filter 41, and the on-chip lens 42L are each made of, for example, a light-transmitting material, such as silicon nitride (SiN) or silicon oxynitride (SiON), or a laminate film thereof.

[0051] Furthermore, pixel isolation portions 35 and 39 are stacked between the pixels px. The pixel isolation portion 35 is provided in a part of the interlayer insulating layer 31, and the pixel isolation portion 39 is provided in a part of the planarization layer 38. The pixel isolation portions 35 and 39 are made of a material having light-blocking properties, such as tungsten (W).

[0052] (Extra-pixel Region) In the extra-pixel region 11b, for example, an interlayer insulating layer 31, a stacked insulating film 17, a planarizing layer 38, a protective layer 40, and an on-chip lens layer 42 are stacked in this order on the surface SF1 side of the sensor substrate 11. The stacked insulating film 17 is a material that forms the inner lens 37L. The on-chip lens layer 42 is a material that forms the on-chip lens 42L. The stacked insulating film 17 and the on-chip lens layer 42 extend continuously from the pixel region 11a to the extra-pixel region 11b.

[0053] The extra-pixel region 11b is provided with, for example, four pads 34 (two of which are shown in FIG. 2A and four of which are shown in FIG. 2B ) for mounting the semiconductor chip 50 on the sensor element 10, and a plurality of pads 36 to which bonding wires for connection to an external substrate are connected. Inside the interlayer insulating layer 31, for example, a wiring layer 33 that electrically connects the pads 34 and 36 is provided. Furthermore, inside the interlayer insulating layer 31, for example, between the pixel region 11a and the extra-pixel region 11b, a light-shielding film 32 made of a conductive material with light-shielding properties, such as tungsten (W), is provided.

[0054] The sensor substrate 11 is provided with through vias 13 that penetrate between the surface SF1 and the surface SF2, for example. The through vias 13 are provided for each of the pads 34 and 36, for example.

[0055] (Multi-layer wiring layer) A plurality of insulating layers 21 are stacked on the surface SF2 of the sensor substrate 11, and wiring layers 22 are arranged on at least some of the insulating layers 21. The wiring layers 22 are stacked, and each wiring layer 22 is connected by, for example, a via or a contact.

[0056] Each through via 13 that penetrates the sensor substrate 11 is connected at one end to a wiring layer 33 that is connected to a pad 34 or a pad 36 provided on the surface SF1 side of the sensor substrate 11, and at the other end to a wiring layer 22 that is provided on the surface SF2 side of the sensor substrate 11. The pads 34 and 36 are electrically connected via the respective wiring layers 33 that include the through vias 13. The wiring layer 33 is disposed on the interlayer insulating layer 31. The wiring layer 33 may also be stacked on the interlayer insulating layer 31. The wiring layer 33 includes a plurality of vertical signal lines VSL. These vertical signal lines VSL are electrically connected to a plurality of vertical signal lines VSL that extend in the column direction in the pixel array section 2.

[0057] Bump pads 34, bonding pads 36, shield wiring layer 14, dummy wiring layer 15, and the like are arranged on the wiring layer 33 disposed on the light incident surface side of the sensor substrate 11. In this specification, the dummy wiring layer 15 may be referred to as a dummy pattern, and the shield wiring layer 14 may be referred to as a shield pattern. A wiring pattern electrically connected to the wiring layer 33 may be arranged at the same layer height (layer) as the bump pads 34, bonding pads 36, shield wiring layer 14, and dummy wiring layer 15. A laminated insulating film 17 for the inner lens 37L is arranged on these bump pads 34, bonding pads 36, shield pattern 14, wiring pattern, and dummy pattern. The laminated insulating film 17 is, for example, a laminated film in which a SiON film, a silicon nitride film (SiN film), and a SiON film are laminated in this order.

[0058] (Pads) The pads 34 are so-called land electrodes for flip-chip mounting (CoW bonding) the semiconductor chip 50 on the sensor element 10. The pads 34 are provided, for example, in openings H1 that expose a portion of a metal film connected to the wiring layer 33 provided in the interlayer insulating layer 31. The pads 34 have, for example, a laminated structure of multiple metal films. For example, the pads 34 have a laminated structure in which metal films 34a, 34b, and 34c are laminated in this order from the sensor substrate 11 side. Conductive materials such as tantalum (Ta), tantalum nitride (TaN), and copper (Cu) can be used as the material for the pads 34. Of these, it is preferable to use, for example, tantalum (Ta) for the metal film 34a that directly contacts the wiring layer 33, tantalum nitride (TaN) for the metal film 34b provided between the metal films 34a and 34c, and copper (Cu) for the metal film 34c that is connected to the semiconductor chip 50 via the bumps 52. An opening H1 that exposes the pad 34 is provided in the laminated insulating film 17, the planarizing layer 38, the protective layer 40, and the on-chip lens layer 42 above the pad 34.

[0059] A bonding wire (not shown) is connected to the pad 36. The pad 36 is used for connection to an external substrate via a bonding wire and is provided, for example, on the interlayer insulating layer 31. The pad 36 is made of a material such as a single layer of aluminum (Al) or a laminated film with a barrier metal. An opening H2 exposing the pad 36 is provided in the laminated insulating film 17, the planarizing layer 38, the protective layer 40, and the on-chip lens layer 42 above the pad 36.

[0060] Furthermore, it is desirable that pad 36 be provided at approximately the same height as pad 34. Here, "approximately the same height" does not necessarily mean that they are the same height. For example, the difference in height between the bottom surfaces of pads 34 and 36 is equal to or less than the thickness of the insulating layer on which one of pads 34 and 36 is provided. This makes it easier to process pads 34 and 36.

[0061] The shield wiring layer 14 and the dummy wiring layer 15 are disposed at the same height (layer) as the pad 36. The pad 36, the shield wiring layer 14, and the dummy wiring layer 15 are formed of the same conductive material (e.g., aluminum (Al)), and therefore can be formed in the same manufacturing process. The shield wiring 14 is set to a predetermined reference voltage (e.g., power supply voltage). On the other hand, the voltage level of the dummy wiring layer 15 is in an undefined (floating) state. The shield wiring 14 may be disposed at a different height from the pad 34.

[0062] The shield wiring layer 14 is arranged to cover at least a portion of the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL. More specifically, the shield wiring layer 14 is arranged opposite the vertical signal line VSL or the wiring layer 33 connected to the vertical signal line VSL via the stacked insulating film 17. The shield wiring layer 14 is provided mainly for the purpose of preventing noise generated in the semiconductor chip 50 from being transmitted to the vertical signal line VSL. In this specification, the shield wiring layer (shield pattern) 14 may be referred to as a conductive member. The planar shape of the shield pattern 14 will be described later.

[0063] The dummy wiring layer 15 is provided for the purpose of improving the stability of processing by adjusting the aperture ratio of the mask during dry etching, etc. Furthermore, since there is a risk of steps being formed if there are too few structures in the planarization process, providing the dummy wiring layer 15 can improve the flatness during film formation.

[0064] The semiconductor chip 50, which is flip-chip mounted (CoW bonding) on ​​the sensor substrate (first substrate) 11 of the sensor element 10, is a logic chip on which various signal processing circuits for performing signal processing are formed. Pads 51 made of aluminum (Al) or the like are arranged on the surface of the semiconductor chip 50 facing the sensor element 10. The pads 51 of the semiconductor chip 50 and the pads 34 of the sensor element 10 are joined via solder bumps 52. In this way, the semiconductor chip 50 is flip-chip mounted (CoW bonding) on ​​the light irradiation surface (back surface) side of the sensor element 10.

[0065] (Plane Layout of Sensor Substrate) Fig. 3 is a plan layout diagram of the sensor substrate 11. As shown in Fig. 3, the sensor substrate 11 includes a pixel region 11a and an extra-pixel region 11b arranged around the pixel region 11a.

[0066] In the extra-pixel region 11b, the wiring pattern 11w, the dummy pattern 11d, the bump pads 34, the bonding pads 36, and the shield pattern 14 are arranged. The shield pattern 14 and the vertical signal lines are arranged so that at least a portion of them overlap in the stacking direction. In addition, in the extra-pixel region 11b, a stacked insulating film 17 is arranged so as to cover at least a portion of the wiring pattern 11w, the dummy pattern 11d, the bump pads 34, the bonding pads 36, and the shield pattern 14. The stacked insulating film 17 is a constituent material of the inner lens 37L. In the extra-pixel region 11b, steps are formed in the stacked insulating film 17 at the locations where the wiring pattern 11w, the dummy pattern 11d, the bump pads 34, the bonding pads 36, and the shield pattern 14 are arranged. Therefore, in this specification, the stacked insulating film 17 may be referred to as a base step pattern 17.

[0067] In the photodetector 1 according to this embodiment, the spacing between the wiring patterns 11w in the extra-pixel region 11b is smaller than at least one of the spacing between the dummy patterns 11d, the spacing between the bonding pad 36 and the wiring pattern 11w, and the spacing between the shield pattern 14 and the wiring pattern 11w. This makes it possible to suppress variations in the film thickness of the stacked insulating film 17 used as the material for the inner lens 37L from the pixel region 11a to the extra-pixel region 11b. Therefore, the refractive index difference between each pixel of the inner lens 37L can be suppressed within a predetermined value.

[0068] As will be described later, the constituent material of the inner lens 37L can actually be the laminated insulating film 17 made of an insulating material. In this specification, an example of suppressing variations in the film thickness of the silicon nitride film included in the laminated insulating film 17 will be mainly described.

[0069] The silicon nitride film for the inner lens 37L is used as an etching stopper film when forming a pad opening for the bump pad 34.

[0070] The wiring pattern 11w is electrically connected to any of the input nodes or output nodes of the pixel region 11a, and includes patterns for transmitting a power supply voltage, a ground voltage, and various signals.

[0071] The dummy pattern 11d is electrically insulated from all input and output nodes in the pixel region 11a, and is arranged mainly to suppress variations in area density of various patterns in the extra-pixel region 11b.

[0072] The shield pattern 14 is set to a predetermined voltage level (for example, a power supply voltage or a ground voltage). The shield pattern 14 is arranged, for example, between a vertical signal line and a wiring layer so that noise generated in the vertical signal line does not propagate to the wiring layer. Note that the shield pattern 14 may also be arranged near various signal lines other than the vertical signal line.

[0073] By making the spacing between the wiring patterns 11w in the extra-pixel region 11b wider than the spacing between the dummy patterns 11d, the spacing between the second pad and the wiring pattern 11w, or the spacing between the shield pattern 14 and the wiring pattern, the variation in the thickness of the silicon nitride film for the inner lens 37L is reduced.

[0074] In FIG. 3, bonding pads 36 are provided on both sides of the extra-pixel region 11b in the first direction X and the second direction Y, and bump pads 34, wiring patterns 11w, and shield patterns 14 are provided on both sides of the second direction Y. However, this is just one example, and the wiring patterns 11w, dummy patterns 11d, shield patterns 14, bump pads 34, and bonding pads 36 may be arranged in any positions in the extra-pixel region 11b.

[0075] 4A is a diagram showing the relationship between the spacing between the wiring patterns 11w and the spacing between the dummy patterns 11d in the extra-pixel region 11b. Fig. 4A shows an example in which the spacing between the wiring patterns 11w is smaller than the spacing between the dummy patterns 11d. In the case of Fig. 4A, the spacing between the dummy patterns 11d in the extra-pixel region 11b is wider, which makes it possible to suppress fluctuations in the film thickness of the stacked insulating film 17 (particularly the silicon nitride film in the stacked insulating film 17) for the inner lens 37L arranged from the pixel region 11a to the extra-pixel region 11b.

[0076] 4B is a diagram showing the relationship between the spacing between the wiring patterns 11w in the extra-pixel region 11b and the spacing between the bonding pad 36 and the wiring pattern 11w. Fig. 4B shows an example in which the spacing between the wiring patterns 11w is smaller than the spacing between the bonding pad 36 and the wiring pattern 11w. In the case of Fig. 4B, the spacing between the bonding pad 36 and the wiring pattern 11w in the extra-pixel region 11b is wider, which makes it possible to suppress fluctuations in the film thickness of the silicon nitride film for the inner lens 37L arranged from the pixel region 11a to the extra-pixel region 11b.

[0077] 4C is a diagram showing the relationship in size between the spacing between the wiring patterns 11w in the extra-pixel region 11b and the spacing between the shield pattern 14 and the wiring pattern 11w. Fig. 4C shows an example in which the spacing between the wiring patterns 11w is smaller than the spacing between the shield pattern 14 and the wiring pattern 11w. In the case of Fig. 4C, the spacing between the shield pattern 14 and the wiring pattern 11w in the extra-pixel region 11b is wider, which makes it possible to suppress fluctuations in the film thickness of the silicon nitride film for the inner lens 37L that is disposed from the pixel region 11a to the extra-pixel region 11b.

[0078] 4A, 4B, and 4C, it is not necessary to satisfy all three of the magnitude relationships shown in Fig. 4A, 4B, and 4C, but it is sufficient to satisfy at least one of them. By satisfying at least one of the three magnitude relationships shown in Fig. 4A, 4B, and 4C, it is possible to suppress fluctuations in the film thickness of the silicon nitride film for the inner lens 37L arranged from the pixel region 11 a to the extra-pixel region 11 b.

[0079] In this specification, the wiring pattern 11w, dummy pattern 11d, bump pad 34, bonding pad 36, and shield pattern 14 arranged in the extra-pixel region 11b are collectively referred to as structures. As described above, the dummy pattern 11d arranged in the extra-pixel region 11b is provided to prevent unevenness in the area density of the structures in the extra-pixel region 11b. If the area density of the structures arranged in the extra-pixel region 11b varies depending on the location, the thickness of the silicon nitride film for the inner lens 37L described above will vary greatly when it is arranged from the pixel region 11a to the extra-pixel region 11b. If the thickness of the silicon nitride film varies greatly, for example, the thickness of the silicon nitride film covering the bump pad 34 in the extra-pixel region 11b will become too thin, making it impossible to reliably perform CoW bonding at the bump pad 34. Therefore, in this embodiment, if unevenness in the area density of the structures in the extra-pixel region 11b occurs, the dummy pattern 11d is arranged in a location with low area density to reduce the unevenness in area density. As a result, in this embodiment, among the structures including the wiring pattern 11w, dummy pattern 11d, bump pad 34, bonding pad 36, and shield pattern 14 arranged in the extra-pixel region 11b, the area density of structures in which the spacing between adjacent structures is smaller than a predetermined spacing is made less than a predetermined ratio.

[0080] In this embodiment, among the structures arranged in the extra-pixel region 11 b, at least some of the structures are spaced apart by a predetermined distance or more. As a specific example, in this embodiment, among the structures arranged in the extra-pixel region, the area density of structures spaced apart by less than 9 μm is set to less than 10%. As a result, when structures such as the wiring pattern 11 w, the dummy pattern 11 d, the bump pads 34, the bonding pads 36, and the shield pattern 14 in the extra-pixel region 11 b are covered with the stacked insulating film 17, the step of the stacked insulating film 17 in the extra-pixel region 11 b can be reduced, and the variation in the film thickness of the silicon nitride film in the stacked insulating film 17 can be suppressed.

[0081] In this embodiment, the spacing between at least some of the structures arranged in the extra-pixel region 11 b is set to 9 μm or more, which reduces the proportion of structures spaced apart by less than 9 μm, thereby making it possible to uniform the thickness of the silicon nitride film in the stacked insulating film 17.

[0082] The shape and size of the dummy patterns 11d are arbitrary. Figure 5 is a plan view showing a typical example of the dummy patterns 11d. Figure 5A shows an example in which rectangular dummy patterns 11d are arranged at equal intervals in a first direction (horizontal direction) X and a second direction (vertical direction) Y. Figure 5B shows an example in which diamond-shaped dummy patterns 11d are arranged at equal intervals in the first direction X and the second direction Y. Figure 5C shows an example in which circular or elliptical dummy patterns 11d are arranged at equal intervals in the first direction X and the second direction Y. Figure 5D shows an example in which polygonal (e.g., hexagonal) dummy patterns 11d are arranged at equal intervals in the first direction X and the second direction Y.

[0083] 5 shows a typical example of the dummy pattern 11 d, and dummy patterns 11 d of the illustrated shape or other shapes may be arbitrarily combined and formed at any location in the extra-pixel region 11 b. The size of the dummy pattern 11 d is also arbitrary, and dummy patterns 11 d of two or more different sizes may be arranged at any location in the extra-pixel region 11 b.

[0084] 6 is a diagram illustrating the aspect ratio of the structures 30 arranged in the extra-pixel region 11b. The aspect ratio is the ratio (H / SP) of the height H of the structures 30 to the spacing SP between adjacent structures 30. By setting the aspect ratio to a predetermined value or less, for example, 0.1 or less, the area density and step height of the structures 30 in the extra-pixel region 11b are reduced overall, and fluctuations in the film thickness of the silicon nitride film for the inner lens 37L arranged from the pixel region 11a to the extra-pixel region 11b can be suppressed.

[0085] Fig. 7 is a cross-sectional view showing the cross-sectional shape of the laminated insulating film 17 for the inner lens 37L in the photodetector 1 according to a comparative example. As shown in Fig. 7, the laminated insulating film 17 is a laminated film formed by laminating a SiON film 17a, a silicon nitride film (SiN film) 17b, and a SiON film 17c. Fig. 8 is a diagram showing the variation in film thickness of the silicon nitride film 17b included in the laminated insulating film 17 arranged from the pixel region 11a to the extra-pixel region 11b in the comparative example.

[0086] In the comparative example, the proportion of structures 30 disposed in the extra-pixel region 11b is greater than in this embodiment, and the size relationships shown in FIGS. 4A to 4C are not satisfied. Therefore, as shown in FIG. 8, the film thickness of the silicon nitride film varies significantly. More specifically, the silicon nitride film 17b has a maximum thickness near the center of the pixel region 11a and decreases toward the edge of the pixel region 11a, resulting in a film thickness in the extra-pixel region 11b that is smaller than that in the pixel region 11a. This makes it difficult to use the silicon nitride film 17b as an etching stopper film to expose the metal film of the bump pad 34 in the extra-pixel region 11b. This may result in the silicon nitride film 17b being completely removed, potentially removing the underlying metal film as well.

[0087] Fig. 9 is a cross-sectional view showing the cross-sectional shape of the stacked insulating film 17 for the inner lens 37L in the photodetector 1 according to this embodiment. Fig. 10 is a diagram showing the variation in film thickness of the silicon nitride film 17b included in the insulating film arranged from the pixel region 11a to the extra-pixel region 11b according to this embodiment. The solid line in Fig. 10 shows the cross-sectional shape of the silicon nitride film 17b according to this embodiment, and the dashed line shows the cross-sectional shape of the silicon nitride film 17b according to the comparative example shown in Fig. 8.

[0088] 9 and 7, in this embodiment, the area density of structures 30, such as wiring patterns 11w or dummy patterns 11d, arranged in the extra-pixel region 11b is lower than in the comparative example. This reduces the step of the silicon nitride film 17b in the extra-pixel region 11b, thereby suppressing variations in the film thickness of the silicon nitride film 17b in the extra-pixel region 11b. This allows the process of exposing the metal film of the bump pad 34 to be performed reliably using the silicon nitride film 17b as an etching stop film.

[0089] Furthermore, according to this embodiment, no steep steps are generated in the silicon nitride film 17b in the extra-pixel region 11b, and therefore the quality of the film formed when the silicon nitride film 17b or the like is formed by CVD can be improved.

[0090] (Stacked Structure) The semiconductor substrate 50 is bonded to the light incident surface side of the sensor substrate 11 with CoW, but another semiconductor substrate 54 may be bonded to the surface side opposite the light incident surface. Also, the semiconductor substrate 50 may be bonded to the surface side opposite the light incident surface with CoW bonding or the like.

[0091] FIG. 11A is a cross-sectional view of a photodetector 1a according to a first modification of an embodiment. The photodetector 1a according to the first modification shown in FIG. 11A has a stacked structure in which a semiconductor substrate 54 is bonded to the surface (front surface) opposite the light incident surface of the photodetector 1 shown in FIG. 2 by a cupper-to-cupper connection (CCC). Bonding may be performed using vias, bumps, or the like instead of CCC. A stacked wiring layer 23 and an insulating layer 24 are stacked on the semiconductor substrate 54, and a Cu wiring layer 25 provided on the insulating layer 21 of the silicon substrate 11 is directly bonded to a Cu wiring layer 26 provided on the insulating layer 24 of the semiconductor substrate 54. A logic circuit 45, for example, is formed on the semiconductor substrate 54. The logic circuit 45 performs signal processing on image data output from the photodetector 1a, for example.

[0092] 11B is a cross-sectional view of a photodetector 1b according to a second modified example of an embodiment. The photodetector 1b according to the second modified example shown in FIG. 11B is characterized in that a part of the pixel circuit arranged on the sensor substrate 11 is provided on a semiconductor substrate (third substrate) 54. A semiconductor layer on which a logic circuit 45 is formed and a semiconductor layer on which a part 46 of the pixel circuit is formed are stacked on the semiconductor substrate 54.

[0093] As a result, in the second modified example, the circuit area of ​​the pixel circuit can be increased, and for example, only the photoelectric conversion units 12 and transfer transistors can be arranged on the sensor substrate 11. This increases the amount of charge that can be photoelectrically converted by each photoelectric conversion unit 12, thereby improving sensitivity.

[0094] (Phase Difference Detection Pixels) The photodetector 1 according to an embodiment may include phase difference pixels that detect phase difference information. In this case, normal pixels that detect gradation information and phase difference pixels may be mixed.

[0095] 12A is a cross-sectional view of a normal pixel included in the photodetector 1 according to one embodiment, and Fig. 12B is a cross-sectional view of a phase difference pixel included in the photodetector 1 according to one embodiment. The ratio of normal pixels to phase difference pixels included in the photodetector 1 is arbitrary.

[0096] As shown in Figures 12A and 12B, both the normal pixel and the phase difference pixel include an on-chip lens 42L, a color filter 41, an inner lens 37L, a wiring layer 33, and a photoelectric conversion unit 12, which are arranged in this order from the light incident surface side.

[0097] As shown in Fig. 12A , the normal pixel has a first optical waveguide 47 and a second optical waveguide 48 arranged in a part of the wiring layer. The first optical waveguide 47 and the second optical waveguide 48 are arranged in the depth direction. As shown in Fig. 12B , the phase difference pixel has a third optical waveguide 49 arranged at the same layer height as the second optical waveguide 48 of the normal pixel. In addition, the wiring layer has a light-shielding film 55 arranged offset from the central axis of the pixel.

[0098] In the photodetector 1 having normal pixels and phase difference pixels shown in FIGS. 12A and 12B , the structure of the extra-pixel region 11 b is the same as that shown in FIG. 2 , and the processing accuracy of the bump pad 34 can be improved by making the extra-pixel region 11 b satisfy the size relationship shown in at least one of FIGS. 4A to 4C , for example.

[0099] (Location of Pads) In the above description, an example was shown in which bump pads 34 were provided on the light incident surface side and the semiconductor chip was bonded by CoW bonding, but the semiconductor chip may also be bonded on the surface side opposite the light incident surface. In this case, the semiconductor chip may be bonded on the surface side opposite the light incident surface by CoW bonding, or the semiconductor chip may be bonded using other bonding methods (for example, CCC, vias, bumps, etc.).

[0100] 13 is a cross-sectional view of a photodetector 1c according to a third modification of the embodiment. The photodetector 1 in FIG. 13 has a silicon layer 27 laminated on the sensor substrate 11 instead of the semiconductor substrate 50 bonded to the bump pad 34 by CoW bonding, and a metal film 28 is connected to the silicon layer 27 on the surface opposite to the light incident surface via a contact 29.

[0101] Thus, in one embodiment, in the extra-pixel region 11b, at least one of the distance between the dummy patterns 11d, the distance between the bonding pad 36 and the wiring pattern 11w, and the distance between the shield wiring layer (shield pattern) 14 and the wiring pattern 11w is set wider than the distance between the wiring patterns 11w. This reduces the variation in the thickness of the silicon nitride film 17b for the inner lens 37L disposed from the pixel region 11a to the extra-pixel region 11b. This allows the silicon nitride film 17b to effectively function as an etching stop film when exposing the metal film of the bump pad 34 in the extra-pixel region 11b. This improves the processing accuracy of the bump pad 34.

[0102] Furthermore, according to this embodiment, the ratio (aspect ratio) of the distance between the structures 30 in the extra-pixel region 11 b to the height of the structures 30 is set to, for example, 0.1 or less, thereby eliminating a deep step structure in a narrow space, allowing the reaction gas supplied when depositing the silicon nitride film 17 b or the like by the CVD method to flow uniformly, and suppressing variations in the amount of film deposition.

[0103] Furthermore, in this embodiment, regardless of the stacked structure of the photodetector 1, variations in the amount of film formed when forming the silicon nitride film 17b and the like can be suppressed.

[0104] Furthermore, according to this embodiment, variations in the shape and size of the inner lens 37L and the on-chip lens can be suppressed, so that the difference in refractive index of incident light for each pixel can be reduced, and sensitivity and oblique incident light characteristics can be improved.

[0105] Furthermore, according to this embodiment, the uniform thickness of the silicon nitride film 17b makes it easy to partially etch away the silicon nitride film 17b, thereby making it possible to uniform the thickness of the metal film of the bump pad 34 and the bonding pad 36. Also, the amount of fluorine used when etching away the silicon nitride film 17b can be reduced, thereby reducing corrosion of the metal film due to fluorine. Therefore, in the bonding pad 36, the process of joining a bonding wire to the metal film can be performed reliably, improving the yield.

[0106] <Application to a Mobile Body> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0107] FIG. 14 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0108] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 14, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0109] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0110] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0111] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0112] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0113] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0114] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0115] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0116] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0117] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying the passengers of the vehicle or the outside of the vehicle of information. In the example of Fig. 14, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0118] FIG. 15 is a diagram showing an example of the installation position of the imaging unit 12031.

[0119] In FIG. 15, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0120] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0121] 15 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0122] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0123] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0124] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0125] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0126] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 and the like among the configurations described above. Specifically, the imaging device 100 according to the present disclosure can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, a clearer captured image can be obtained, thereby reducing driver fatigue.

[0127] The present technology may be configured as follows: (1) A photodetector including: a first substrate having a pixel region in which a plurality of photoelectric conversion elements that perform photoelectric conversion are arranged, and an extra-pixel region arranged around the pixel region; and a second substrate joined to the first substrate at a first pad, wherein the extra-pixel region has a wiring pattern, a dummy pattern, the first pad, a second pad for connecting a bonding wire, and a shield pattern, and a spacing between the wiring patterns in the extra-pixel region is smaller than at least one of a spacing between the dummy patterns, a spacing between the second pad and the wiring pattern, or a spacing between the shield pattern and the wiring pattern. (2) The photodetector according to (1), wherein the wiring pattern is electrically connected to any input node or output node of the pixel region, the dummy pattern is electrically insulated from all input nodes and output nodes of the pixel region, and the shield pattern is set to a predetermined voltage level. (3) The photodetector according to (1) or (2), wherein the pixel region has a plurality of first optical members that condense light incident on each of the plurality of photoelectric conversion elements, and further comprises an insulating film that is arranged from the pixel region to the extra-pixel region and is used as a material for the plurality of first optical members and as an etching stopper film when forming the first pads. (4) The photodetector according to (3), wherein the insulating film is arranged in the extra-pixel region so as to cover at least a portion of the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern. (5) The photodetector according to (3) or (4), wherein a refractive index difference between the plurality of first optical members in the pixel region is within a predetermined value. (6) The photodetector according to any one of (3) to (5), further comprising a plurality of second optical members that are arranged closer to the light incident surface than the plurality of first optical members and that guide incident light to the plurality of first optical members. (7) The photodetector according to any one of (3) to (6), wherein the plurality of first optical members are a laminated film made of an insulating material, and a silicon nitride film included in the laminated film is used as the etching stopper film.(8) The photodetector according to any one of (1) to (7), wherein the second substrate is disposed on the light incident surface side of the first substrate. (9) The photodetector according to any one of (1) to (7), wherein the second substrate is disposed on the surface side opposite the light incident surface of the first substrate. (10) The photodetector according to any one of (1) to (9), wherein, among structures including the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern disposed in the extra-pixel region, an area density of structures in which a distance between adjacent structures is smaller than a predetermined distance is less than a predetermined rate. (11) The photodetector according to (10), wherein, among the structures disposed in the extra-pixel region, at least some of the structures are spaced apart by the predetermined distance or more. (12) The photodetector according to (10) or (11), wherein, among the structures disposed in the extra-pixel region, an area density of structures in which a distance between structures is less than 9 μm is less than 10%. (13) The photodetector according to any one of (10) to (12), wherein a distance between at least some of the structures arranged in the extra-pixel region is 9 μm or more. (14) The photodetector according to any one of (10) to (13), wherein a ratio of a height of the structures in the extra-pixel region to a distance between the structures in the extra-pixel region is equal to or less than a predetermined value. (15) The photodetector according to (14), wherein a ratio of a height of the structures in the extra-pixel region to a distance between the structures in the extra-pixel region is 0.1 or less. (16) The photodetector according to any one of (1) to (15), wherein the bonding of the first substrate and the second substrate via the first pad is by CoW (chip on wafer) bonding. (17) The photodetector according to any one of (1) to (16), further comprising a third substrate bonded to a surface of the first substrate opposite to a surface to which the second substrate is bonded. (18) The photodetector according to (17), wherein the pixel regions are distributed over the first substrate and the third substrate. (19) The photodetector according to any one of (1) to (18), wherein the pixel regions include pixels having the photoelectric conversion elements that detect a phase difference.

[0128] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0129] 1, 1a, 1b, 1c photodetector, 2a pixel array section, 2b peripheral circuit section, 3 vertical drive section, 4 column processing section, 5 horizontal drive section, 6 system control section, 7 signal processing section, 8 data storage section, 9 output section, 10 sensor element, 11 sensor substrate, 11a pixel region, 11b extra-pixel region, 11d dummy pattern, 11w wiring pattern, 12 photoelectric conversion section, 13 through via, 14 shield wiring layer (shield pattern), 15 dummy wiring layer, 17 laminated insulating film (underlayer step pattern), 17a SiON film, 17b silicon nitride film, 17c SiON film, 20 multilayer wiring layer, 21 insulating layer, 22 wiring layer, 23 laminated wiring layer, 24 insulating layer, 25 Cu wiring layer, 26 Cu wiring layer, 27 silicon layer, 28 metal film, 29 contact, 30 1. Structure, 31 interlayer insulating layer, 32 light-shielding film, 33 wiring layer, 34 bump pads, 34a, 34b, 34c metal film, 35 pixel separation section, 36 bonding pad, 37L inner lens, 38 planarization layer, 39 pixel separation section, 40 protective layer, 41 color filter, 42 on-chip lens layer, 42L on-chip lens, 45 logic circuit, 47 first optical waveguide, 48 second optical waveguide, 49 third optical waveguide, 50 semiconductor substrate (semiconductor chip), 51 pad, 52 solder bump, 52 bump, 54 semiconductor substrate, 55 light-shielding film, 100 imaging device

Claims

1. A photodetector comprising: a first substrate having a pixel region in which a plurality of photoelectric conversion elements that perform photoelectric conversion are arranged, and an extra-pixel region arranged around the pixel region; and a second substrate joined to the first substrate by first pads, wherein the extra-pixel region has a wiring pattern, a dummy pattern, the first pad, a second pad for connecting a bonding wire, and a shield pattern, and the spacing between the wiring patterns in the extra-pixel region is smaller than at least one of the spacing between the dummy patterns, the spacing between the second pad and the wiring pattern, or the spacing between the shield pattern and the wiring pattern.

2. The photodetector device according to claim 1, wherein the wiring pattern is electrically connected to any of the input nodes or output nodes of the pixel region, the dummy pattern is electrically insulated from all of the input nodes and output nodes of the pixel region, and the shield pattern is set to a predetermined voltage level.

3. The photodetector according to claim 1, wherein the pixel region has a plurality of first optical members that condense light incident on each of the plurality of photoelectric conversion elements, and further comprises an insulating film that is arranged from the pixel region to the extra-pixel region, is used as a material for the plurality of first optical members, and is used as an etching stopper film when the first pads are formed.

4. The photodetector device according to claim 3, wherein the insulating film is arranged in the extra-pixel region so as to cover at least a portion of the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern.

5. The photodetector according to claim 3, wherein the refractive index difference between the plurality of first optical members in the pixel region is within a predetermined value.

6. The light detection device according to claim 3, further comprising a plurality of second optical members arranged closer to the light incident surface than the plurality of first optical members, and guiding incident light to the plurality of first optical members.

7. The photodetector according to claim 3, wherein the plurality of first optical members are a laminated film made of an insulating material, and a silicon nitride film included in the laminated film is used as the etching stopper film.

8. The photodetector according to claim 1, wherein the second substrate is disposed on the light incident surface side of the first substrate.

9. The photodetector according to claim 1, wherein the second substrate is disposed on the side opposite to the light incident surface of the first substrate.

10. The photodetector device according to claim 1, wherein, among structures including the wiring pattern, the dummy pattern, the first pad, the second pad, and the shield pattern arranged in the extra-pixel region, the area density of structures in which the spacing between adjacent structures is smaller than a predetermined spacing is less than a predetermined ratio.

11. The photodetector according to claim 10, wherein the distance between at least some of the structures arranged in the extra-pixel region is equal to or greater than the predetermined distance.

12. The photodetector according to claim 10, wherein, of the structures arranged in the extra-pixel region, the area density of structures spaced apart by an interval of less than 9 μm is less than 10%.

13. The photodetector according to claim 10, wherein the distance between at least some of the structures arranged in the extra-pixel region is 9 μm or more.

14. The photodetector according to claim 10, wherein a ratio of the height of the structures in the extra-pixel region to the distance between the structures in the extra-pixel region is equal to or less than a predetermined value.

15. The photodetector according to claim 14, wherein the ratio of the height of the structures in the extra-pixel region to the distance between the structures in the extra-pixel region is 0.1 or less.

16. The photodetector device according to claim 1, wherein the first substrate and the second substrate are bonded via the first pad by CoW (Chip on Wafer) bonding.

17. The photodetector according to claim 1, further comprising a third substrate bonded to the surface of the first substrate opposite to the surface to which the second substrate is bonded.

18. The photodetector device according to claim 17, wherein the pixel regions are distributed over the first substrate and the third substrate.

19. The photodetector according to claim 1, wherein the pixel region includes pixels having the photoelectric conversion elements that detect a phase difference.

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