Wafer mounting stand

Abstract

The present invention provides a wafer mounting stand that can stably support a wafer and minimize damage to the wafer in a semiconductor device manufacturing process. A wafer mounting stand according to one embodiment of the present invention comprises a ceramic substrate and a plurality of protrusions. The plurality of protrusions are provided on one surface of the ceramic substrate in the thickness direction. The ceramic substrate and the plurality of protrusions have different crystal structures. The Vickers hardness of each of the plurality of protrusions is 0.47-0.70 with respect to the Vickers hardness of the ceramic substrate.

Description

Wafer mounting table

[0001] The present invention relates to a wafer stage.

[0002] A semiconductor manufacturing apparatus for manufacturing semiconductor devices typically includes a wafer mounting table on which a semiconductor wafer is mounted. The semiconductor wafer is subjected to any appropriate process (e.g., a film formation process, an etching process) while supported on the wafer mounting table. One such wafer mounting table has been proposed (see, for example, Patent Document 1), which includes a plate-shaped ceramic sintered body and a plurality of protrusions provided on the surface of the ceramic sintered body, the surface roughness Ra of the ceramic sintered body in a portion where the protrusions are not present being 0.1 μm or less, and the protrusions being an aerosol deposition (hereinafter referred to as AD) film or a thermal spray film made of the same material as the ceramic sintered body.

[0003] International Publication No. 2020 / 261990

[0004] In a semiconductor device manufacturing process, a semiconductor wafer is placed on a wafer mounting table so that it contacts multiple protrusions. When various processes (e.g., film formation processes, etching processes) are performed in this state, the semiconductor wafer may thermally expand and slide against the protrusions. With the wafer mounting table described in Patent Document 1, depending on the type of semiconductor wafer, the wear resistance of the protrusions may be insufficient, causing the protrusions to wear due to the sliding of the semiconductor wafer. In this case, the performance of the protrusions may not be sufficiently maintained, resulting in a problem of unstable support of the semiconductor wafer by the protrusions. Therefore, efforts have been made to improve the wear resistance of the protrusions. However, improving the wear resistance of the protrusions may result in damage to the semiconductor wafer. A primary object of the present invention is to provide a wafer mounting table that can stably support a semiconductor wafer and prevent damage to the semiconductor wafer during a semiconductor device manufacturing process.

[0005] [1] A wafer stage according to one embodiment of the present invention includes a ceramic substrate and a plurality of protrusions. The plurality of protrusions are provided on one surface of the ceramic substrate in the thickness direction. The ceramic substrate and the plurality of protrusions have different crystal structures. The Vickers hardness of each of the plurality of protrusions is 0.47 or more and 0.70 or less relative to the Vickers hardness of the ceramic substrate. [2] In the wafer stage described in [1] above, the plurality of protrusions and the ceramic substrate may contain the same inorganic material. [3] In the wafer stage described in [1] or [2] above, the dimension of each of the plurality of protrusions in the thickness direction of the ceramic substrate may be 5 μm or more. [4] In each of the plurality of protrusions included in the wafer stage described in any one of [1] to [3] above, the half-width of an X-ray diffraction peak at 2θ = 37° to 38° may be 0.11° or more. [5] In the wafer mounting table described in any one of [1] to [4] above, each of the plurality of protrusions may have a bottom surface, a top surface, and a side surface. The bottom surface is adjacent to the one surface of the ceramic base. The top surface is spaced apart from the bottom surface in the thickness direction of the ceramic base. The side surface connects the peripheral edge of the bottom surface to the peripheral edge of the top surface. [6] In the wafer mounting table described in [5] above, a connecting portion between the top surface and the side surface may have a curved shape. [7] In the wafer mounting table described in [5] or [6] above, when each of the plurality of protrusions is viewed in a cross section parallel to the thickness direction of the ceramic base, an angle formed between the bottom surface and the side surface may be 11° to 70°. [8] In the wafer mounting table described in any one of [5] to [7] above, the top surface includes a flat region. The flat region has a parallelism within a range of ±4% based on the thickness at the center of the protrusion. The area of ​​the flat region may be 62% to 95% when the area of ​​the bottom surface is taken as 100%.

[0006] According to one embodiment of the present invention, a wafer mounting table can be realized that can stably support a semiconductor wafer and prevent the semiconductor wafer from being damaged in a semiconductor device manufacturing process.

[0007] Fig. 1 is a schematic cross-sectional view of a wafer stage according to an embodiment of the present invention, Fig. 2 is a schematic enlarged view of a protrusion provided on the wafer stage of Fig. 1.

[0008] Hereinafter, embodiments of the present invention will be described, but the present invention is not limited to these embodiments. In addition, in order to clarify the explanation, the width, thickness, shape, etc. of each part may be shown schematically in the drawings compared to the embodiments, but this is merely an example and does not limit the interpretation of the present invention.

[0009] A. Overview of the Wafer Placement Platform Fig. 1 is a schematic cross-sectional view of a wafer placement platform according to one embodiment of the present invention. The wafer placement platform 100 is typically a component of a semiconductor manufacturing apparatus for manufacturing semiconductor devices. The wafer placement platform 100 is a device that can be distributed independently and is industrially applicable.

[0010] In one embodiment, the wafer mounting table 100 includes a ceramic substrate 1 and a plurality of protrusions 2. The plurality of protrusions 2 are provided on one surface 1a of the ceramic substrate in the thickness direction. The ceramic substrate 1 and the plurality of protrusions 2 typically have different crystal structures. The Vickers hardness (HV) of each of the plurality of protrusions 2 is 0.47 or more, preferably 0.50 or more, relative to the Vickers hardness (HV) of the ceramic substrate 1. On the other hand, the Vickers hardness of each of the plurality of protrusions 2 is 0.70 or less, preferably 0.65 or less, relative to the Vickers hardness of the ceramic substrate 1. Hereinafter, the Vickers hardness of each of the plurality of protrusions relative to the Vickers hardness of the ceramic substrate may be referred to as the Vickers hardness of the protrusion / the Vickers hardness of the ceramic substrate. The Vickers hardness is measured, for example, based on JIS R 1610:2003. According to this configuration, the Vickers hardness of the protrusions divided by the Vickers hardness of the ceramic substrate is equal to or greater than the lower limit, thereby improving the wear resistance of the protrusions. Therefore, during the semiconductor device manufacturing process, the multiple protrusions can be prevented from being worn by the sliding of the semiconductor wafer, and the performance of the multiple protrusions can be sufficiently maintained. As a result, the multiple protrusions can stably support the semiconductor wafer, allowing various processes (e.g., film formation processes, etching processes) to be appropriately performed on the semiconductor wafer. Since the wear resistance of the protrusions in this wafer mounting table is improved, the wafer mounting table can be used repeatedly and its lifespan can be extended. Furthermore, since the Vickers hardness of the protrusions divided by the Vickers hardness of the ceramic substrate is equal to or less than the upper limit, the semiconductor wafer can be prevented from being scratched even when it slides against the multiple protrusions during the semiconductor device manufacturing process. Therefore, both improved wear resistance of the protrusions and reduced scratching of the semiconductor wafer can be achieved.

[0011] The Vickers hardness of each of the multiple protrusions 2 is smaller than the Vickers hardness of the ceramic substrate 1. The Vickers hardness of the protrusions 2 is, for example, 2000 or less, preferably 1800 or less, more preferably 1500 or less, and even more preferably 1200 or less. On the other hand, the Vickers hardness of the protrusions 2 is, for example, 800 or more, preferably 1000 or more, and more preferably 1100 or more. The Vickers hardness of the ceramic substrate 1 is, for example, 1400 or more, preferably 1600 or more, more preferably 1900 or more, and even more preferably 2050 or more. On the other hand, the Vickers hardness of the ceramic substrate 1 is, for example, 2300 or less, or, for example, 2100 or less. When the Vickers hardness of the protrusions and / or the Vickers hardness of the ceramic substrate are in such a range, the Vickers hardness of the protrusions / ceramic substrate can be stably adjusted to the above range.

[0012] The porosity of each of the multiple protrusions 2 is typically smaller than the porosity of the ceramic substrate 1. The porosity of the protrusions 2 is, for example, 0.20% or less, preferably 0.10% or less, and more preferably 0.09% or less. On the other hand, the lower limit of the porosity of the protrusions 2 is, for example, 0% or more, preferably 0.01% or more, more preferably 0.03% or more, and even more preferably 0.07% or more. When the porosity of the protrusions is within this range, improvement of the wear resistance of the protrusions and suppression of scratches on the semiconductor wafer can be more stably achieved at the same time. The porosity of the protrusions is measured, for example, by image processing from a cross-sectional image, more specifically, by cross-sectional observation using a scanning electron microscope (SEM) as described in paragraph

[0023] of JP 2024-9020 A.

[0013] As described above, the ceramic substrate 1 and the plurality of protrusions 2 have different crystal structures. In other words, the plurality of protrusions 2 are not formed by cutting out the ceramic substrate 1, but by film formation on the ceramic substrate 1. In one embodiment, each of the plurality of protrusions 2 is formed by an ion-assisted deposition (hereinafter, referred to as IAD) film. When the protrusions are formed by an IAD film, the density of the protrusions can be stably improved compared to when the protrusions are formed by an AD film or a thermal spray film, and the Vickers hardness of the protrusions / ceramic substrate can be stably adjusted within the above-mentioned range. Therefore, even if a semiconductor wafer slides against the protrusions during various processes (e.g., film formation processes, etching processes) on a semiconductor wafer, wear on the protrusions can be stably suppressed.

[0014] Each of the plurality of protrusions 2 is not limited to an IAD film. The protrusions 2 may be a sputtered film, a vacuum deposition film, or an ion plating film. If the protrusions 2 are a sputtered film, a vacuum deposition film, or an ion plating film, the density of the protrusions can be sufficiently improved.

[0015] B. Details of the Wafer Mounting Table Hereinafter, each component of the wafer mounting table will be described in detail.

[0016] B-1. Ceramic substrate In the ceramic substrate 1, the surface 1a on which the plurality of protrusions 2 are provided typically extends in a direction intersecting the thickness direction of the ceramic substrate 1. In the illustrated example, the surface 1a of the ceramic substrate extends in a direction perpendicular to the thickness direction of the ceramic substrate 1 (hereinafter, sometimes referred to as the surface direction of the ceramic substrate).

[0017] In one embodiment, the surface 1a of the ceramic substrate 1 is a polished surface that has been polished by any appropriate polishing method. The protruding valley space volume Vvv of the surface 1a of the ceramic substrate 1 is, for example, 0.7 ml / mm ２ or less, preferably 0.5 ml / mm ２ More preferably, it is 0.4 ml / mm ２ More preferably, it is 0.3 ml / mm ２and particularly preferably 0.25 ml / mm ２ The following is the case. When the surface of the ceramic substrate has such a protruding valley space volume, it is possible to prevent particle sources (typically processing residues) generated during polishing of the ceramic substrate from accumulating in minute depressions present on the surface of the ceramic substrate, and it is also possible to prevent the formation of a crushed layer on the surface of the protruding portion facing the ceramic substrate (contact surface 2a, top surface 23, described later). Therefore, it is possible to prevent particles from falling off from the crushed layer of the protruding portion. This makes it possible to prevent the generation of particles in the manufacturing process of semiconductor devices. On the other hand, the lower limit of the protruding valley space volume Vvv on the surface 1a of the ceramic substrate 1 is typically 0 ml / mm ２ The protruding valley space volume is measured in accordance with ISO 25178, for example.

[0018] The core space volume Vvc on the surface 1a of the ceramic substrate 1 is, for example, 5.0 ml / mm ２ and preferably 3.6 ml / mm ２ More preferably, it is 2.0 ml / mm ２ More preferably, it is 1.5 ml / mm ２ and particularly preferably 1.1 ml / mm ２ When the surface of the ceramic substrate has such a core space volume, the particle sources present on the polished surface of the ceramic substrate can be further reduced. On the other hand, the lower limit of the core space volume Vvc on the surface 1a of the ceramic substrate 1 is typically 0 ml / mm ２ The core space volume is measured in accordance with ISO 25178, for example.

[0019] The arithmetic mean height Sa on the surface 1a of the ceramic substrate 1 is, for example, 0.2 μm or less, preferably 0.1 μm or less, and more preferably 0.05 μm or less. On the other hand, the lower limit of the arithmetic mean height Sa on the surface 1a of the ceramic substrate 1 is typically 0 μm. When the surface of the ceramic substrate has such an arithmetic mean height, the adhesion of the convex portions to the surface of the ceramic substrate can be improved. The arithmetic mean height is measured, for example, in accordance with ISO 25178.

[0020] The arithmetic mean roughness Ra of the surface 1a of the ceramic substrate 1 is, for example, 0.2 μm or less, preferably 0.1 μm or less. On the other hand, the lower limit of the arithmetic mean roughness Ra of the surface 1a of the ceramic substrate 1 is typically 0 μm. When the surface of the ceramic substrate has such an arithmetic mean roughness, the adhesion of the convex portions to the surface of the ceramic substrate can be stably improved. The arithmetic mean roughness is measured, for example, in accordance with ISO 25178.

[0021] The ceramic base 1 has any appropriate shape depending on the application of the wafer mounting table 100. A typical shape of the ceramic base 1 is a plate shape. The ceramic base 1 preferably has a disk shape. The thickness of the ceramic base 1 is, for example, 3 mm to 50 mm.

[0022] The ceramic substrate 1 is made of any suitable ceramic material. The thermal expansion coefficient of the ceramic material is, for example, 2.0×10 －６ / ℃~10.0×10 －６ / °C. Examples of such ceramic materials include alumina (Al ２ O ３ ), aluminum nitride (AlN), mullite (Al ６ O １３ Si ２ ), spinel (MgAl ２ O ４ ), zirconia (ZrO ２ The ceramic materials may be used alone or in combination. Among these ceramic materials, alumina (Al２ O ３ The ceramic material may contain any suitable stabilizer. Examples of the stabilizer include yttria (Y ２ O ３ ), calcium oxide (CaO). The stabilizing materials may be used alone or in combination.

[0023] The porosity of the ceramic substrate 1 is, for example, 0.01% or more. On the other hand, the porosity of the ceramic substrate 1 is, for example, 5% or less, and preferably 1% or less. The porosity of the ceramic substrate is measured in accordance with, for example, JIS R1634.

[0024] The relative density of the ceramic substrate 1 is, for example, 99.0% or more, and preferably 99.5% or more. On the other hand, the upper limit of the relative density of the ceramic substrate 1 is typically 100%. The relative density of the ceramic substrate is measured in accordance with, for example, JIS R1634.

[0025] Furthermore, when the ceramic substrate 1 is viewed in cross section parallel to the thickness direction, in an 85 μm × 65 μm SEM (scanning electron microscope) image including the surface 1a on which the convex portion is provided, the number of cracks present in the region from the surface 1a to the thickness direction of the ceramic substrate 1 (for example, the region within 50 μm from the surface 1a) is, for example, 3 or less, preferably 2 or less, more preferably 1 or less, and even more preferably 0. If the number of cracks present near the surface of the ceramic substrate is below this upper limit, the generation of particles in the semiconductor device manufacturing process can be more stably suppressed. The size of the crack in the thickness direction of the ceramic substrate is, for example, 0.5 μm or more.

[0026] B-2. Convex portions A plurality of convex portions 2 are arbitrarily and appropriately provided on the surface 1a of the ceramic substrate 1. The plurality of convex portions 2 are typically arranged at intervals from one another. In one embodiment, the plurality of convex portions 2 are arranged at equal intervals from one another.

[0027] Each of the plurality of protrusions 2 typically has a contact surface 2 a that can come into contact with the semiconductor wafer 7. The contact surface 2 a is located away from the surface 1 a of the ceramic substrate 1 in the thickness direction of the ceramic substrate 1. The contact surface 2 a may be a flat surface or a curved surface. In one embodiment, the contact surface 2 a is a flat surface that extends in a direction intersecting the thickness direction of the ceramic substrate 1. In the illustrated example, the contact surface 2 a extends in a direction perpendicular to the thickness direction of the ceramic substrate 1.

[0028] Each of the multiple protrusions 2 has any appropriate shape including the contact surface 2a described above. Examples of the cross-sectional shape of the protrusions 2 cut in the thickness direction of the ceramic substrate 1 include a quadrangle, a pentagon, a polygon with hexagons or more, a semicircle, and a semi-ellipse. In one embodiment, the protrusions 2 have a quadrangle in the cross section cut in the thickness direction of the ceramic substrate 1. Examples of the shape of the protrusions 2 seen in the thickness direction of the ceramic substrate 1 include a triangle, a quadrangle, a pentagon, a polygon with hexagons or more, a circle, and an ellipse.

[0029] Corners of the protrusion 2 may be chamfered. In the illustrated example, among the multiple corners of the protrusion 2, the corners located away from the ceramic substrate 1 (connection portions between the contact surface 2 a and the side surface) are chamfered.

[0030] More specifically, as shown in FIG. 2 , each of the multiple protrusions 2 has a bottom surface 22, a top surface 23, and a side surface 24. Note that FIG. 2 is a schematic cross-sectional view of the protrusion 2, but hatching is omitted for convenience. The bottom surface 22 is adjacent to the surface 1 a of the ceramic substrate 1. That is, the bottom surface 22 is in contact with the surface 1 a of the ceramic substrate 1. In the illustrated example, the bottom surface 22 extends in the planar direction of the ceramic substrate 1. The top surface 23 is spaced from the bottom surface 22 in the thickness direction of the ceramic substrate 1. The top surface 23 functions as the contact surface 2 a described above and is described in the same manner as the contact surface 2 a. The side surface 24 connects the peripheral edge of the bottom surface 22 to the peripheral edge of the top surface 23. In the illustrated example, the side surface 24 extends in a direction intersecting both the thickness direction and the planar direction of the ceramic substrate 1.

[0031] In one embodiment, the connection portion 25 between the top surface 23 and the side surface 24 has a curved shape. When the connection portion between the top surface and the side surface has a curved shape, it is possible to prevent the semiconductor wafer from being damaged when the semiconductor wafer is placed on the wafer mounting table so as to come into contact with the multiple protrusions. The radius of curvature of the connection portion 25 having a curved shape is, for example, 2 μm to 6000 μm, and preferably 5 μm to 2000 μm. If the radius of curvature of the connection portion is within this range, it is possible to stably prevent the semiconductor wafer from being damaged.

[0032] In the illustrated example, the protrusions 2 have a trapezoidal shape in a cross section cut in the thickness direction of the ceramic substrate 1. When each of the multiple protrusions 2 is viewed in cross section parallel to the thickness direction of the ceramic substrate 1, the angle θ between the bottom surface 22 and the side surface 24 is, for example, 5° to 70°, preferably 11° to 70°. When the angle θ between the bottom surface and the side surface is within this range, even if the protrusions gradually wear and become smaller in the thickness direction with repeated use of the wafer mounting table, the area of ​​the top surface (contact surface) of the protrusions can be prevented from changing. Therefore, even with repeated use of the wafer mounting table, the performance of the protrusions can be sufficiently maintained, and the generation of particle sources can be suppressed. As a result, the life of the wafer mounting table can be extended.

[0033] In one embodiment, the top surface 23 includes a flat region R. The flat region R has a parallelism within a range of ±4% based on the thickness at the center of the convex portion 2. In other words, when the thickness at the center of the convex portion 2 is 100%, the flat region R corresponds to the portion of the convex portion 2 whose thickness is within a range of 96% to 104%. When the area of ​​the bottom surface 22 is 100%, the area of ​​the flat region R is, for example, 20% to 95%, preferably 62% to 95%. When the area ratio of the flat region is within this range, fluctuations in the area of ​​the top surface (contact surface) of the convex portion can be stably suppressed even with repeated use of the wafer mounting table. This can further extend the life of the wafer mounting table.

[0034] In one embodiment, when the top surface 23 is observed by electron backscatter diffraction (EBSD), no EBSD pattern is detected.

[0035] The shapes of the plurality of protrusions 2 may all be the same, or at least some may be different.

[0036] 1, the maximum dimension L of the protrusions 2 in the direction perpendicular to the thickness direction of the ceramic substrate 1 is, for example, 0.3 mm to 5.0 mm, preferably 0.5 mm to 2.5 mm, and more preferably 0.5 mm to 1.0 mm. The maximum dimensions L of the multiple protrusions 2 may all be substantially the same, or at least some of them may be different.

[0037] Furthermore, the dimension of the protrusions 2 in the thickness direction of the ceramic substrate 1 (hereinafter referred to as thickness T) is, for example, 5 μm or more, preferably 10 μm or more. On the other hand, the thickness T of the protrusions 2 is, for example, 50 μm or less, preferably 30 μm or less, and more preferably 20 μm or less. When the protrusions are made of an IAD film, the thickness of the protrusions can be stably adjusted within this range. The thicknesses T of the multiple protrusions 2 are typically all substantially the same.

[0038] Each of the plurality of protrusions 2 is made of any suitable inorganic material. The thermal expansion coefficient of the inorganic material is, for example, 2.0×10 －６ / ℃~10.0×10 －６ / °C. As the inorganic material, for example, alumina (Al ２ O ３ ), aluminum nitride (AlN), mullite, spinel, zirconia, and yttria. The inorganic materials can be used alone or in combination. The inorganic material constituting the protrusions 2 and the ceramic material constituting the ceramic substrate 1 can be the same or different. When the protrusions 2 and the ceramic substrate 1 are made of the same material, the adhesion of the protrusions 2 to the ceramic substrate 1 can be improved. On the other hand, when the protrusions 2 and the ceramic substrate 1 are made of different materials, any appropriate function can be imparted to the wafer mounting table 100. When the protrusions 2 and the ceramic substrate 1 are made of different materials, the absolute value of the difference in the thermal expansion coefficients of these materials is, for example, 7×10 －６ / °C or less, preferably 3 x 10 －６ / ° C. or less. In one embodiment, the plurality of projections 2 and the ceramic substrate 1 contain the same inorganic material.

[0039] Each of the plurality of protrusions 2 is prepared by forming a film of the inorganic material described above on the surface 1a of the ceramic substrate 1 using an appropriate film-forming method (e.g., ion-assisted deposition, sputtering, vacuum deposition, ion plating). Therefore, the protrusions 2 can be dense bodies having a laminated structure. When the protrusions are dense bodies, the protrusions are grain boundary-less, meaning that there are essentially no grain boundaries in the protrusions. This makes it possible to more stably suppress wear, shedding, and / or partial shedding of the protrusions, and also to suppress attacks such as corrosion caused by grain boundaries. Therefore, the wear resistance of the protrusions can be further improved, and the generation of particle sources from the protrusions can be more stably suppressed.

[0040] Furthermore, for each of the multiple protrusions 2, the half-width of the peak in X-ray diffraction at 2θ = 37° to 38° is, for example, 0.11° or more, preferably 0.3° or more. Meanwhile, the half-width of the peak in X-ray diffraction at 2θ = 37° to 38° is, for example, 1.5° or less, preferably 1.0° or less. When the half-width of the X-ray diffraction peak of the protrusions is within this range, the protrusions have a suitable crystalline structure, and particle source generation from the protrusions can be more stably suppressed. Furthermore, a broad peak may be observed at 2θ = 30° to 40° by X-ray diffraction measurement. This is thought to be due to a layer in which the ceramic substrate and the ion-assisted deposition film are mixed by ion-assisted deposition. The half-width of the X-ray diffraction peak of the protrusions is measured, for example, by X-ray diffraction measurement under the following conditions. <Measurement conditions> X-ray: Cu tube (40 kV, 30 mA) Detector: One-dimensional detector (D / tex Ultra 250) Optical system: Focusing method Length limiting slit: 10 mm 2θ scan range: 10° to 120°

[0041] C. Method for Manufacturing Wafer Mounting Table Next, a method for manufacturing a wafer mounting table according to one embodiment will be described. In one embodiment, the method for manufacturing a wafer mounting table includes a step of preparing the ceramic base 1 (preparation step) and a step of forming a plurality of protrusions 2 on the surface 1 a of the ceramic base 1 (protrusion formation step).

[0042] C-1. Preparation Step In one embodiment, in the preparation step, first, the raw ceramic material is formed into a plate-shaped body by any appropriate forming method.

[0043] Examples of the molding method include press molding, sheet molding, cold isostatic pressing (CIP) molding, and doctor blade molding, and preferably press molding.

[0044] The compact is then fired under any suitable conditions in a vacuum or a non-oxidizing atmosphere. Examples of firing methods include hot pressing and hot isostatic pressing (HIP), with hot pressing being preferred. This sinters the ceramic material contained in the compact, producing a plate-shaped sintered compact.

[0045] If necessary, one or both thickness-wise surfaces of the fired body are polished by any appropriate polishing method to achieve the above-mentioned surface roughness (protruding valley space volume Vvv, core space volume Vvc, arithmetic mean height Sa, and arithmetic mean roughness Ra). Examples of polishing methods include lapping, polishing, CMP polishing, brush polishing, wet blasting, and rubber blasting. The polishing methods may be performed alone or in combination. Of the polishing methods, lapping and polishing are preferred. In this way, the ceramic substrate 1 is prepared.

[0046] C-2. Convex Portion Forming Step Next, in one embodiment, the inorganic material described above is subjected to ion-assisted deposition under any appropriate conditions at predetermined positions on the surface 1a of the ceramic substrate 1. As a result, multiple convex portions 2 are formed on the surface 1a of the ceramic substrate 1, and the wafer mounting table 100 is manufactured. In addition, a shielding band 21 may be formed along the outer edge of the surface 1a of the ceramic substrate 1. The shielding band 21 may be formed by ion-assisted deposition or may be formed by processing the ceramic substrate 1. The shielding band 21 is preferably formed by ion-assisted deposition from the perspective of ease of the manufacturing process. In this case, the multiple convex portions 2 include the shielding band 21 arranged along the outer edge of the surface 1a of the ceramic substrate 1.

[0047] The above describes in detail a method for manufacturing a wafer mounting table that includes a step of forming the plurality of protrusions 2 by ion-assisted deposition (deposition step). However, the method for manufacturing a wafer mounting table is not limited to this. The plurality of protrusions 2 may be formed on the surface 1 a of the ceramic substrate 1 by, for example, sputtering, vacuum deposition, or ion plating.

[0048] D. Uses of the Wafer Mounting Table The wafer mounting table 100 is applied to any suitable semiconductor manufacturing apparatus 101. The semiconductor manufacturing apparatus 101 is typically capable of performing any suitable process on a semiconductor wafer 7. Examples of processes that can be performed on the semiconductor wafer 7 include film formation processes such as chemical vapor deposition (CVD) and atomic layer deposition (ALD); etching processes; and ashing processes.

[0049] In one embodiment, semiconductor manufacturing apparatus 101 includes ring 4, cooling plate 6, focus ring 5, and wafer stage 100 described above.

[0050] The ring 4 has any appropriate configuration depending on the application. The ring 4 is configured to support the cooling plate 6. The cooling plate 6 has any appropriate configuration. The cooling plate 6 is configured to support the wafer mounting table 100. The cooling plate 6 is capable of cooling the wafer mounting table 100. The focus ring 5 is provided to surround at least a portion of the wafer mounting table 100 when viewed in the thickness direction of the wafer mounting table 100. The focus ring 5 has any appropriate configuration.

[0051] The wafer mounting table 100 is located on the opposite side of the cooling plate 6 from the ring 4. The wafer mounting table 100 is typically attached to the cooling plate 6 via an adhesive material (not shown). With the wafer mounting table 100 attached to the cooling plate 6, the multiple protrusions 2 are located on the opposite side of the ceramic base 1 from the cooling plate 6.

[0052] The ceramic substrate 1 may be provided with a conductor. The conductor is typically embedded in the ceramic substrate 1. The conductor has any appropriate function depending on the application of the wafer mounting table 100. The number of conductors provided in the ceramic substrate 1 is not particularly limited. The ceramic substrate 1 may be provided with multiple conductors. Examples of conductors include an ESC electrode, an RF electrode, a resistance heating element, and a GND electrode. Among the conductors, an ESC electrode and a resistance heating element are preferred. When the ceramic substrate 1 is provided with an ESC electrode, the wafer mounting table 100 functions as an electrostatic chuck. More specifically, the electrostatic chuck is configured to chuck the semiconductor wafer 7 supported by the multiple protrusions 2 by the Johnson-Rahbek (JR) force.

[0053] The present invention will be specifically explained below with reference to examples and comparative examples, but the present invention is not limited to these examples. The methods for measuring each property are as follows.

[0054] (1) Wear Resistance of Convex Portions Test pieces were cut out from the wafer mounting tables obtained in the Examples and Comparative Examples. The test pieces had a rectangular shape measuring 20 mm x 20 mm when viewed from the thickness direction of the ceramic substrate. Among the multiple convex portions provided on the test piece, convex portions to be measured (hereinafter sometimes referred to as target convex portions) were arbitrarily selected, and the height of the target convex portion was measured using a laser microscope. A sliding test was performed on this test piece. More specifically, the test piece was fixed to a first fixture provided in a friction and wear tester (manufactured by Bruker, UMT-TribolaB). Then, a silicon wafer having the same shape and size as the test piece was bonded to a second fixture provided in the friction and wear tester, and the silicon wafer was brought into contact with the convex portions of the test piece from above (the side opposite the ceramic substrate). Then, the first fixture was slid against the second fixture while applying a load from above (the side opposite the test piece). The test load was equivalent to 2.7 N (50 Torr), the number of sliding strokes was 0.5 (one way), the speed was 0.1 mms / sec, and the stroke was 1 mm. Next, the height of the target convex portion after the sliding test was measured using a laser microscope. Thereafter, the change in height of the target convex portion before and after the sliding test was calculated, and the wear resistance of the convex portion was evaluated according to the following criteria. The results are shown in Table 1. Good: The change in height of the target convex portion (i.e., the amount of wear) was less than 1 μm. Poor: The change in height of the target convex portion (i.e., the amount of wear) was 1 μm or more.

[0055] (2) Presence or absence of scratches on the wafer A 20 mm x 20 mm Si wafer was placed on the multiple convex portions of the wafer mounting tables obtained in the examples and comparative examples, and the Si wafer was allowed to slide. Thereafter, the presence or absence of scratches on the Si wafer was confirmed using a white light interferometer. The results are shown in Table 1.

[0056] <<Example 1>> Al ２ O ３The powder (median diameter: 1 μm) was filled into a predetermined mold and then uniaxially pressed to obtain a plate-shaped compact. The compact was then fired at 1600°C for 2 hours in a nitrogen atmosphere. More specifically, the compact was first placed in a hot press die made of graphite and set in a hot press furnace. Then, the compact was pressed against a pressure of 200 kgf / cm in the thickness direction. ２ In this state, the compact was fired under the above-mentioned conditions (temperature and time). ２ O ３ The powder is sintered to form a plate-shaped Al ２ O ３ A sintered body was obtained. ２ O ３ One surface in the thickness direction of the sintered body was polished by lapping. Thus, a ceramic substrate having a polished surface was prepared. On the polished surface of the ceramic substrate, the protruding valley space volume Vvv was 0.5 mL / mm ２ and the core space volume Vvc is 3.6 mL / mm ２ The Vickers hardness of the ceramic substrate is shown in Table 1. Next, a masking tape was attached to the polished surface of the ceramic substrate. A plurality of openings was formed in a predetermined pattern on the masking tape. Then, Al was applied to the polished surface exposed through the plurality of openings in the masking tape. ２ O ３ The polished surface was then polished by ion-assisted deposition (IAD) to form multiple protrusions. The masking tape was then peeled off and removed from the polished surface. In this manner, a wafer stage having a ceramic substrate and multiple protrusions was manufactured. The porosity and Vickers hardness of each of the multiple protrusions are shown in Table 1.

[0057] Example 2 A wafer mounting table was manufactured in the same manner as in Example 1, except that the deposition rate in the IAD was reduced and the porosity of the convex portions was changed to 0.08%.

[0058] Example 3 A wafer mounting table was manufactured in the same manner as in Example 1, except that the deposition rate in the IAD was reduced and the porosity of the convex portions was changed to 0.06%.

[0059] <<Comparative Example 1>> A wafer mounting table was manufactured in the same manner as in Example 1, except that the method for forming the convex portions was changed from IAD to thermal spraying.

[0060] <<Comparative Example 2>> A wafer mounting table was manufactured in the same manner as in Example 1, except that the method for forming the convex portions was changed from IAD to aerosol deposition (AD).

[0061] <<Comparative Example 3>> A wafer mounting table was manufactured in the same manner as in Example 1, except that the method for forming the convex portions was changed from IAD to chemical vapor deposition (CVD).

[0062] <<Comparative Example 4>> A wafer mounting table was manufactured in the same manner as in Example 1, except that a plurality of protrusions were formed by thermal spraying yttria.

[0063]

[0064] <Evaluation> As shown in Table 1, when the Vickers hardness of each of the plurality of protrusions is 0.47 or more and 0.70 or less relative to the Vickers hardness of the ceramic substrate, it is found that the wear resistance of the protrusions can be improved and scratches on the Si wafer can be suppressed.

[0065] A wafer stage according to one embodiment of the present invention is typically used in semiconductor manufacturing equipment, and can be particularly suitably used as a susceptor, heater, electrostatic chuck, or the like.

[0066] REFERENCE SIGNS LIST 1 ceramic substrate 1a surface 2 convex portion 100 wafer mounting table

Claims

1. A wafer mounting table comprising: a ceramic base; and a plurality of protrusions provided on one surface of the ceramic base in the thickness direction, wherein the ceramic base and the plurality of protrusions have mutually different crystal structures, and the Vickers hardness of each of the plurality of protrusions is 0.47 or more and 0.70 or less relative to the Vickers hardness of the ceramic base.

2. The wafer stage according to claim 1, wherein the plurality of protrusions and the ceramic base material contain the same inorganic material.

3. The wafer stage according to claim 1 or 2, wherein the dimension of each of the plurality of protrusions in the thickness direction of the ceramic base is 5 μm or more.

4. The wafer stage according to claim 1 or 2, wherein the half-width of the peak at 2θ=37° to 38° in X-ray diffraction for each of the plurality of convex portions is 0.11° or more.

5. A wafer mounting table as described in claim 1 or 2, wherein each of the plurality of protrusions has a bottom surface adjacent to the one surface of the ceramic base, a top surface spaced apart from the bottom surface in the thickness direction of the ceramic base, and a side surface connecting the peripheral edge of the bottom surface with the peripheral edge of the top surface.

6. The wafer stage according to claim 5, wherein the connecting portion between the top surface and the side surface has a curved shape.

7. The wafer mounting table according to claim 5, wherein when each of the plurality of protrusions is viewed in cross section parallel to the thickness direction of the ceramic base, the angle formed between the bottom surface and the side surface is 11° to 70°.

8. The wafer mounting table according to claim 5, wherein the top surface includes a flat region having a parallelism within a range of ±4% based on the thickness at the center of the convex portion, and the area of ​​the flat region is 62% to 95% when the area of ​​the bottom surface is 100%.

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