Display panel and electronic device comprising same

Abstract

Disclosed in one embodiment of the present invention is a display panel comprising: a first pixel circuit and a second pixel circuit arranged on a substrate, each including a driving transistor and a storage capacitor and being adjacent to each other in a first direction; data lines which extend in a second direction crossing the first direction, and which are electrically connected to each of the first pixel circuit and the second pixel circuit; a first insulating layer arranged on the data lines; a voltage layer arranged on the insulating layer; a second insulating layer arranged on the voltage layer; and a light-emitting diode including a pixel electrode arranged on the second insulating layer, an opposite electrode on the pixel electrode, and a light-emitting layer between the pixel electrode and the opposite electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other and bridge portions connecting the plurality of main portions to each other, and the main portions being interposed between the data lines and the pixel electrode and including a first main portion overlapping the data lines and the pixel electrode.

Description

Display panel and electronic device including same

[0001] Aspects of one or more embodiments relate to a display panel and an electronic device including the same.

[0002] Display panels are now being used in a variety of electronic devices. As the scope of display panel use expands, consumer demand for high-quality display panels is increasing. Manufacturing high-quality display panels requires arranging electronic components of various configurations within a narrow area.

[0003] Aspects of one or more embodiments include a display panel and an electronic device including the same.

[0004] According to some embodiments of the present disclosure, a display panel is disclosed, which includes a light emitting diode including a first pixel circuit and a second pixel circuit disposed on a substrate, each including a driving transistor and a storage capacitor, and data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit, a first insulating layer disposed on the data lines, a voltage layer disposed on the first insulating layer, a second insulating layer disposed on the voltage layer, and a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light emitting layer between the pixel electrode and the counter electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other, and bridge portions connecting the plurality of main portions, and wherein the main portions include a first main portion interposed between the data lines and the pixel electrode and overlapping the data lines and the pixel electrode.

[0005] According to some embodiments, the data line electrically connected to the first pixel circuit and the data line electrically connected to the second pixel circuit may be arranged symmetrically with respect to a virtual line between the first pixel circuit and the second pixel circuit.

[0006] According to some embodiments, the first pixel circuit and the second pixel circuit and other pixel circuits are transmitted with data connection lines, each passing through the first pixel circuit and the second pixel circuit, and the first main portion can overlap with the data connection lines.

[0007] According to some embodiments, the data connection line passing through the first pixel circuit and the data connection line passing through the second pixel circuit may be arranged symmetrically with respect to the virtual line.

[0008] According to some embodiments, each of the first pixel circuit and the second pixel circuit further includes a switching transistor electrically connected to the driving transistor and the voltage layer, and a semiconductor layer of the driving transistor of each of the first pixel circuit and the second pixel circuit includes a different material from a semiconductor layer of the switching transistor, and the semiconductor layer of the driving transistor includes an oxide semiconductor material, and the semiconductor layer of the switching transistor includes polysilicon.

[0009] According to some embodiments, the display panel further includes a hold capacitor electrically connected to the driving transistor and the voltage layer, a conductive layer disposed under the semiconductor layer of the driving transistor, and an insulating layer interposed between the conductive layer and the switching transistor, wherein the hold capacitor may include a first hold electrode electrically connected to the voltage layer and a second hold electrode overlapping the first hold electrode.

[0010] According to some embodiments, the storage capacitor includes a first storage electrode and a second storage electrode overlapping each other, and the conductive layer may include the second storage electrode and the second hold electrode.

[0011] According to some embodiments, the first hold electrode may include a first lower hold electrode disposed below the conductive layer with the insulating layer therebetween, and a first upper hold electrode positioned opposite the first lower hold electrode with the conductive layer therebetween.

[0012] According to some embodiments, each of the first pixel circuit and the second pixel circuit further includes a connection electrode electrically connecting the semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor, a first conductive layer under the semiconductor layer of the driving transistor, and a second conductive layer between the first conductive layer and the semiconductor layer of the driving transistor, wherein a connection point of the connection electrode and the semiconductor layer of the driving transistor may overlap the first conductive layer and the second conductive layer.

[0013] According to some embodiments, each of the storage capacitors of the first pixel circuit and the second pixel circuit may include a first storage electrode and a second storage electrode overlapping each other, the first conductive layer may include the first storage electrode, and the second conductive layer may include the second storage electrode.

[0014] According to some embodiments, the display panel further includes a bank layer disposed on the pixel electrode and including an opening overlapping the pixel electrode, wherein the opening defined in the bank layer can overlap the first main portion.

[0015] According to some embodiments, the main parts include a second main part, a third main part, a fourth main part, and a fifth main part arranged around the first main part, and in a plane, the second main part, the third main part, the fourth main part, and the fifth main part are respectively arranged at corners of an imaginary square centered on the first main part, wherein the second main part and the third main part are arranged along the first direction, the fourth main part is spaced apart from the second main part along the second direction, and the fifth main part is spaced apart from the third main part along the second direction.

[0016] According to some embodiments, the light emitting diode is electrically connected to the first pixel circuit, and the pixel electrode of the light emitting diode can overlap a virtual line between the first pixel circuit and the second pixel circuit.

[0017] According to some embodiments, the voltage layer may have a voltage level that is the same as the voltage applied to the counter electrode of the light emitting diode.

[0018] According to some embodiments of the present disclosure, a display panel includes a lower cover forming an exterior and having an opening exposing a portion of the display panel to a front surface, wherein the display panel is disposed on a substrate, and includes a driving transistor and a storage capacitor, and includes a first pixel circuit and a second pixel circuit adjacent to each other along a first direction, and data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit, a first insulating layer disposed on the data lines, a voltage layer disposed on the insulating layer, a second insulating layer disposed on the voltage layer, and a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light-emitting layer between the pixel electrode and the counter electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other, and bridge portions connecting the plurality of main portions, the main portions being interposed between the data lines and the pixel electrode and the data lines and the An electronic device is disclosed, comprising a first main portion overlapping a pixel electrode.

[0019] According to some embodiments, the data line electrically connected to the first pixel circuit and the data line electrically connected to the second pixel circuit may be arranged symmetrically with respect to a virtual line between the first pixel circuit and the second pixel circuit.

[0020] According to some embodiments, the display panel further includes data connection lines that transmit data signals to the first pixel circuit and the second pixel circuit and other pixel circuits, and pass through the first pixel circuit and the second pixel circuit, respectively, wherein the data connection line passing through the first pixel circuit and the data connection line passing through the second pixel circuit are arranged symmetrically with respect to the virtual line, and the first main portion can overlap the data connection lines.

[0021] According to some embodiments, the display panel further includes a bank layer disposed on the pixel electrode and including an opening overlapping the pixel electrode, wherein the opening defined in the bank layer can overlap the first main portion.

[0022] According to some embodiments, each of the first pixel circuit and the second pixel circuit further includes a switching transistor electrically connected to the driving transistor and the voltage layer, a connection electrode electrically connecting a semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor, a first conductive layer under the semiconductor layer of the driving transistor, and a second conductive layer between the first conductive layer and the semiconductor layer of the driving transistor, wherein the semiconductor layer of the driving transistor of each of the first pixel circuit and the second pixel circuit includes a different material from the semiconductor layer of the switching transistor, and a connection point of the connection electrode and the semiconductor layer of the driving transistor may overlap the first conductive layer and the second conductive layer.

[0023] According to some embodiments, each of the storage capacitors of the first pixel circuit and the second pixel circuit may include a first storage electrode and a second storage electrode overlapping each other, the first conductive layer may include the first storage electrode, and the second conductive layer may include the second storage electrode.

[0024] According to some embodiments, a display panel and electronic device can be provided that provide a relatively fast response speed and relatively high-quality images. The aforementioned effects are exemplary, and the effects of the present disclosure are not limited to those described above.

[0025] FIG. 1 is a perspective view illustrating an electronic device according to some embodiments.

[0026] FIG. 2 is an exploded perspective view illustrating an electronic device according to some embodiments.

[0027] FIG. 3 is a block diagram showing an electronic device according to some embodiments.

[0028] FIG. 4 is a plan view schematically illustrating a display panel according to some embodiments.

[0029] FIG. 5 is a side view schematically illustrating a display panel according to some embodiments.

[0030] FIG. 6 is a plan view schematically illustrating a display panel according to some embodiments.

[0031] FIGS. 7A and 7B are enlarged plan views of part VII of FIG. 6, respectively, as a part of a display device according to some embodiments.

[0032] FIG. 8 is an equivalent circuit diagram of a light-emitting diode and pixel circuit of a display panel according to some embodiments.

[0033] FIG. 9 is a plan view schematically illustrating pixel circuits of a display panel according to some embodiments.

[0034] FIG. 10 is a cross-sectional view of a display panel according to some embodiments, showing a cross-section taken along line X-X' of FIG. 6.

[0035] FIGS. 11 to 19 are plan views illustrating a process for forming a pixel circuit of a display panel according to some embodiments.

[0036] FIG. 20 is a plan view showing light emitting diodes arranged on pixel circuits according to some embodiments.

[0037] FIG. 21 is a cross-sectional view taken along line XXI-XXI' of FIG. 20 according to some embodiments.

[0038] FIG. 22 is a cross-sectional view taken along line XXI-XXI' of FIG. 20 according to some embodiments.

[0039] Fig. 23 is a plan view showing an excerpt of the voltage layer of Fig. 19.

[0040] FIG. 24 is a plan view showing voltage layers on first and second pixel circuits according to some embodiments.

[0041] According to some embodiments of the present disclosure, a display panel is disclosed, which includes a light emitting diode including a first pixel circuit and a second pixel circuit disposed on a substrate, each including a driving transistor and a storage capacitor, and data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit, a first insulating layer disposed on the data lines, a voltage layer disposed on the first insulating layer, a second insulating layer disposed on the voltage layer, and a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light emitting layer between the pixel electrode and the counter electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other, and bridge portions connecting the plurality of main portions, and wherein the main portions include a first main portion interposed between the data lines and the pixel electrode and overlapping the data lines and the pixel electrode.

[0042] According to some embodiments of the present disclosure, a display panel includes a lower cover forming an exterior and having an opening exposing a portion of the display panel to a front surface, wherein the display panel is disposed on a substrate, and includes a driving transistor and a storage capacitor, and includes a first pixel circuit and a second pixel circuit adjacent to each other along a first direction, and data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit, a first insulating layer disposed on the data lines, a voltage layer disposed on the insulating layer, a second insulating layer disposed on the voltage layer, and a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light-emitting layer between the pixel electrode and the counter electrode, wherein the voltage layer includes a plurality of main portions spaced apart from each other, and bridge portions connecting the plurality of main portions, the main portions being interposed between the data lines and the pixel electrode and the data lines and the An electronic device is disclosed, comprising a first main portion overlapping a pixel electrode.

[0043] The embodiments of the present invention are capable of various modifications and multiple embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the embodiments of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

[0044] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals, and redundant descriptions thereof will be omitted.

[0045] In the following examples, the terms first, second, etc. are not used in a limiting sense, but are used for the purpose of distinguishing one component from another.

[0046] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0047] In the following examples, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0048] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only the case where it is directly on top of the other part, but also the case where another film, region, component, etc. is interposed in between.

[0049] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0050] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0051] In the following embodiments, when it is said that a film, region, component, etc. are connected, it includes not only cases where the films, regions, or components are directly connected, but also cases where other films, regions, or components are interposed between the films, regions, or components and thus indirectly connected. For example, when it is said in this specification that a film, region, component, etc. are electrically connected, it includes not only cases where the films, regions, or components are directly electrically connected, but also cases where other films, regions, or components are interposed between them and thus indirectly electrically connected.

[0052] In this specification, “at least one of A and B,” “at least one of A or B,” or “at least one selected from A and B” may mean A, B, or both A and B.

[0053] FIG. 1 is a perspective view showing an electronic device (1) according to some embodiments, FIG. 2 is an exploded perspective view showing an electronic device (1) according to some embodiments, and FIG. 3 is a block diagram showing an electronic device (1) according to some embodiments.

[0054] Referring to FIGS. 1 and 2, an electronic device (1) is a device that displays a moving image (e.g., a video image) or a still image (e.g., a still image), and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc. The electronic device (1) according to some embodiments can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). An electronic device (1) according to some embodiments may be used as a dashboard of a vehicle, a CID (Center Information Display) placed or arranged on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, and a display placed on the back of a front seat as entertainment for the rear seat of a vehicle.

[0055] For convenience of explanation, FIGS. 1 and 2 illustrate an electronic device (1) according to some embodiments being used as a smart phone. The electronic device (1) according to some embodiments may include a cover window (70), a display panel (10), a data driver (20), a display circuit board (30), a component (40), a bracket (60), a main circuit board (50), a battery (80), and a lower cover (90).

[0056] In the plan view of this specification, “left,” “right,” “upper,” and “lower” indicate directions when looking at the display panel (10) from a direction perpendicular to the display panel (10). For example, “left” indicates the -x direction, “right” indicates the +x direction, “upper” indicates the +y direction, and “lower” indicates the -y direction.

[0057] The electronic device (1) may have a rectangular shape on a plane. For example, the electronic device (1) may have a rectangular shape on a plane having a short side in the x direction and a long side in the y direction, as shown in Fig. 1. The corner where the short side in the x direction and the long side in the y direction meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the electronic device (1) is not limited to a rectangle, and may be formed in another polygonal, oval, or irregular shape.

[0058] The cover window (70) can be placed on the upper part of the display panel (10) to cover the upper surface of the display panel (10). As a result, the cover window (70) can function to protect the upper surface of the display panel (10).

[0059] The cover window (70) may include a transparent cover portion (DA70) corresponding to the display panel (10) and a light-blocking cover portion (NDA70) surrounding the transparent cover portion (DA70). The light-blocking cover portion (NDA70) may include an opaque material (e.g., a colored opaque material) that blocks light. The light-blocking cover portion (NDA70) may include a pattern that can be shown to a user when an image is not displayed.

[0060] The display panel (10) can be placed at the bottom of the cover window (70). The display panel (10) can overlap with the transparent cover portion (DA70) of the cover window (70).

[0061] The display panel (10) includes a display area (DA). The display area (DA) is an area where an image is displayed, and the display area (DA) may include an area (hereinafter, referred to as a component area) that transmits light emitted from a component (40) positioned at the bottom of the display panel (10). The component may include a sensor or camera that utilizes visible light, infrared rays, or sound.

[0062] The display panel (10) may be a light-emitting display panel including a light-emitting diode. The light-emitting diode may include an organic light-emitting diode including an organic light-emitting layer. In some embodiments, the light-emitting diode may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including inorganic semiconductor-based materials. When a voltage is applied in the forward direction to the PN junction diode, holes and electrons are injected, and energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The above-described inorganic light-emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0063] The display panel (10) may be a rigid display panel that is rigid and does not bend easily, or a flexible display panel that is flexible and can be easily bent, folded, or rolled without damage to the display panel (10). For example, the display panel (10) may be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a bent display panel with an area other than the display surface bent, a rollable display panel that can be rolled and unfolded, and a stretchable display panel that can be stretched.

[0064] The display panel (10) may be a transparent display panel that is implemented transparently so that an object or background placed on the lower surface of the display panel (10) can be viewed from the upper surface of the display panel (10). According to some embodiments, the display panel (10) may be a reflective display panel that can reflect an object or background on the upper surface of the display panel (10).

[0065] The data driver (20) may be placed on the display panel (10) in the form of an integrated circuit (IC). As another embodiment, the data driver (20) may be placed on a display circuit board (30).

[0066] A display circuit board (30) can be attached to one side of the display panel (10). The display circuit board (30) can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is hard and does not bend easily, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0067] According to some embodiments, a touch sensor driver may be disposed on the display circuit board (30). The touch sensor driver may be formed as an integrated circuit. The touch sensor driver may be attached to the display circuit board (30). The touch sensor driver may be electrically connected to the touch electrodes of the touch screen layer of the display panel (10) via the display circuit board (30).

[0068] The touch screen layer of the display panel (10) can detect a user's touch input using at least one of various touch methods such as a resistive film method and an electrostatic capacitance method. For example, when the touch screen layer of the display panel (10) detects a user's touch input using an electrostatic capacitance method, the touch sensor driver can determine whether a user's touch has occurred by applying drive signals to the drive electrodes among the touch electrodes and detecting voltages charged in the mutual capacitance (hereinafter referred to as "mutual capacitance") between the drive electrodes and the sense electrodes through the sense electrodes among the touch electrodes. The user's touch may include a contact touch and a proximity touch. A contact touch refers to a case where an object such as a user's finger or a pen directly contacts a cover window (70) disposed on the touch screen layer. A proximity touch refers to a case where an object such as a user's finger or a pen is positioned close to the cover window (70), such as hovering. The touch sensor driving unit transmits sensor data to the main processor (510) according to the detected voltages, and the main processor (510) can calculate the touch coordinates where the touch input occurred by analyzing the sensor data.

[0069] A control unit for supplying driving voltages for driving pixels, a gate driver, and a data driver (20) of the display panel (10) may be placed on the display circuit board (30).

[0070] A bracket (60) for supporting the display panel (10) may be arranged at the lower portion of the display panel (10). The bracket (60) may include plastic, metal, or both plastic and metal. A first camera hole (CMH1) into which a camera device (531) is inserted, a battery hole (BH) into which a battery (80) is arranged, and a cable hole (CAH) through which a cable connected to the display circuit board (30) passes may be formed in the bracket (60). A component hole (CPH) overlapping the display panel (10) may be provided in the bracket (60). The component hole (CPH) may overlap with components (40) of the main circuit board (50) in a third direction (z direction). According to some embodiments, the display area (DA) of the display panel (10) may overlap with components (40) of the main circuit board (50) in the third direction (z direction). In another embodiment, the bracket (60) may not have a component hole (CPH) formed therein.

[0071] According to some embodiments, the component (40) may include first to fourth components (41, 42, 43, 44) overlapping the display panel (10). The first to fourth components (41, 42, 43, 44) may be provided with a proximity sensor, an illumination sensor, an iris sensor, a facial recognition sensor, and a camera (or an image sensor), respectively. The proximity sensor using infrared rays can detect an object placed close to the upper surface of the electronic device (1), and the illumination sensor can detect the brightness of light incident on the upper surface of the electronic device (1). In addition, the iris sensor can photograph the iris of a person placed on the upper surface of the electronic device (1), and the camera can photograph an object placed on the upper surface of the electronic device (1). The component (40) is not limited to the proximity sensor, the illumination sensor, the iris sensor, the facial recognition sensor, and the camera, and various sensors described below may be placed.

[0072] A main circuit board (50) and a battery (80) may be placed at the bottom of the bracket (60). The main circuit board (50) may be a printed circuit board or a flexible printed circuit board.

[0073] The main circuit board (50) may include a main processor (510), a camera device (531), a main connector (55), and components (40). The main processor (510) may be formed as an integrated circuit. The camera device (531) may be disposed on both the upper and lower surfaces of the main circuit board (50), and each of the main processor (510) and the main connector (55) may be disposed on either the upper or lower surface of the main circuit board (50).

[0074] The main processor (510) can control all functions of the electronic device (1). For example, the main processor (510) can output digital video data to the data driver (20) through the display circuit board (30) so that the display panel (10) can display an image. The main processor (510) can receive detection data from the touch sensor driver. The main processor (510) can determine whether a user touches the screen based on the detection data and execute an operation corresponding to the user's direct touch or proximity touch. The main processor (510) can be an application processor, a central processing unit, or a system chip formed of an integrated circuit.

[0075] The camera device (531) processes image frames, such as still images or moving images, obtained by the image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), or a laser sensor. The camera device (531) may be connected to an image sensor among the components (40) overlapping the second display area (DA2) and may process an image input to the image sensor.

[0076] A cable (35) passing through a cable hole (CAH) of a bracket (60) can be connected to the main connector (55), and thus the main circuit board (50) can be electrically connected to the display circuit board (30).

[0077] In addition to the main processor (510), camera device (531), and main connector (55), the main circuit board (50) may further include a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580) as shown in FIG. 3.

[0078] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless Internet module (523), a short-range communication module (524), or a location information module (525).

[0079] The broadcast reception module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a terrestrial channel.

[0080] The mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, or a server on a mobile communication network constructed according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signal may include various types of data according to transmission and reception of a voice call signal, a video call signal, or text / multimedia message.

[0081] The wireless Internet module (523) refers to a module for wireless Internet access. The wireless Internet module (523) can be configured to transmit and receive wireless signals in a communication network according to wireless Internet technologies. Wireless Internet technologies include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, and DLNA (Digital Living Network Alliance).

[0082] The short-range communication module (524) is for short-range communication, and can support short-range communication using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, or Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between an electronic device (1) and a wireless communication system, between an electronic device (1) and another electronic device, or between an electronic device (1) and a network where another electronic device (or an external server) is located through a short-range wireless communication network (Wireless Area Network). The short-range wireless communication network may be a short-range wireless personal area network (Wireless Personal Area Network). The other electronic device may be a wearable device capable of exchanging (or linking) data with the electronic device (1).

[0083] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1), and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0084] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, and an input device (533) for receiving information from a user.

[0085] The camera device (531) processes image frames, such as still images or moving images, obtained by an image sensor in video call mode or shooting mode. The processed image frames can be displayed on a display panel (10) or stored in a memory (570).

[0086] A microphone (532) processes external acoustic signals into electrical voice data. The processed voice data can be utilized in various ways depending on the function being performed (or the application being executed) by the electronic device (1).

[0087] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) can include a mechanical input means or a touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1). The touch input means can be formed of a touch screen layer of the display panel (10).

[0088] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), information about the surrounding environment surrounding the electronic device (1), or user information, and generate a sensing signal corresponding thereto. Based on these sensing signals, the main processor (510) may control the operation or behavior of the electronic device (1), or perform data processing, functions, or operations related to an application installed in the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a G-sensor, a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a fingerprint recognition sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), or a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric recognition sensor, etc.).

[0089] The output unit (550) is for generating output related to visual, auditory, or tactile sensations, and may include at least one of a display panel (10), an audio output unit (551), a haptic module (552), or an optical output unit (553).

[0090] The display panel (10) displays (outputs) information processed in the electronic device (1). For example, the display panel (10) may display execution screen information of an application running in the electronic device (1), or UI (User Interface) or GUI (Graphical User Interface) information according to the execution screen information. The display panel (10) may include a display layer that displays an image and a touch screen layer that detects a user's touch input. Accordingly, the display panel (10) may function as one of the input devices (533) that provides an input interface between the electronic device (1) and the user, and at the same time, function as one of the output units (550) that provides an output interface between the electronic device (1) and the user.

[0091] The audio output unit (551) can output audio data received from the wireless communication unit (520) or stored in the memory (570) in a call signal reception mode, a call mode or a recording mode, a voice recognition mode, a broadcast reception mode, etc. The audio output unit (551) also outputs audio signals related to functions performed in the electronic device (1) (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower portion of the display panel (10) to vibrate the display panel (10) and output audio. The audio generating device may be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0092] The haptic module (552) generates various tactile effects that can be felt by the user. The haptic module (552) can provide vibrations to the user as tactile effects. The haptic module (552) can not only deliver tactile effects through direct contact, but can also be implemented so that the user can feel the tactile effects through the kinesthetic senses of the fingers or arms.

[0093] The light output unit (553) outputs a signal to notify the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, receiving a missed call, an alarm, receiving a schedule reminder, receiving an email, receiving information through an application, etc. The signal output by the light output unit (553) is implemented by the electronic device (1) emitting light of a single color or multiple colors from the front or rear. The signal output may be terminated when the electronic device (1) detects the user's confirmation of an event.

[0094] The interface unit (560) serves as a passageway for various types of external devices connected to the electronic device (1). The interface unit (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, or an earphone port. The electronic device (1) may perform appropriate control related to the connected external device in response to the external device being connected to the interface unit (560).

[0095] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a plurality of applications (application programs) running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the plurality of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510), and can also temporarily store input / output data, such as phone books, messages, still images, and moving images. In addition, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and audio data regarding various sounds provided to the audio output unit (551). The memory (570) may include at least one type of storage medium among a flash memory type, a hard disk type, an SSD (Solid State Disk type), an SDD (Silicon Disk Drive type), a multimedia card micro type, a card type memory (e.g., SD or XD memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, or an optical disk.

[0096] The power supply unit (580) receives external power and internal power under the control of the main processor (510) and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery (80). In addition, the power supply unit (580) has a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery (80) wirelessly without using the connection port. The battery (80) may be arranged so as not to overlap the main circuit board (50) in the third direction (z direction). The battery (80) may overlap the battery hole (BH) of the bracket (60).

[0097] The lower cover (90) forms the outer appearance of the electronic device (1) and may have an opening that exposes a portion of the display panel (10) on the front surface. The lower cover (90) has an open surface corresponding to the display panel (10) and may be assembled with the display panel (10). The lower cover (90) may be positioned on the opposite side of the cover window (70) with the display panel (10) interposed therebetween. The lower cover (90) may be positioned below the main circuit board (50) and the battery (80). The lower cover (90) may be fixed by being fastened to a bracket (60). The lower cover (90) may form the lower appearance of the electronic device (1). The lower cover (90) may include plastic, metal, or both plastic and metal.

[0098] A second camera hole (CMH2) that exposes the lower surface of the camera device (531) may be formed in the lower cover (90). The position of the camera device (531) and the positions of the first and second camera holes (CMH1, CMH2) corresponding to the camera device (531) are not limited to the embodiments illustrated in FIGS. 1 and 2 and may be varied in various ways.

[0099] FIG. 4 is a plan view schematically illustrating a display panel (10) according to some embodiments, and FIG. 5 is a side view schematically illustrating a display panel (10) according to some embodiments.

[0100] The display panel (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA) (e.g., outside or surrounding the footprint of the display area). The display area (DA) is a portion or area that displays an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. For example, FIG. 4 illustrates that the display area (DA) has a roughly rectangular shape with rounded corners, but the present disclosure is not limited thereto.

[0101] A peripheral area (PA) may be arranged outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA) and a second peripheral area (PA2) adjacent to one side of the display area (DA) and extending in a second direction (e.g., -y direction). A width of the second peripheral area (PA2) along the first direction (e.g., x-axis direction) may be narrower than a width of the display area (DA). This structure may facilitate bending of at least a portion of the second peripheral area (PA2).

[0102] The shape of the plane of the display panel (10) illustrated in FIG. 4 may be substantially the same as the shape of the substrate (100) included in the display panel (10). When the display panel (10) is said to include a display area (DA) and a peripheral area (PA) outside the display area (DA), this may indicate that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, it will be described that the substrate (100) has a display area (DA) and a peripheral area (PA).

[0103] The display panel (10) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display panel (10) may be bent in the bending region (BR), as illustrated in FIG. 5, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in a third direction (e.g., the z-direction). Although FIG. 5 illustrates the display panel (10) being bent, the present disclosure is not limited thereto. According to some embodiments, the display panel (10) is a foldable display panel, and the display region (DA) may be bent around a bending axis crossing the display region (DA). According to some embodiments, the display panel (10) may not be bent. The sub-region (SR) may be a non-display area.

[0104] A data driver (20) may be placed in a sub-region (SR) of a display panel (10). The data driver (20) may be placed in the display panel (10) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0105] A display circuit board (30) may be attached to an end of a sub-area (SR) of a display panel (10). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-area (SR) of the display panel (10).

[0106] FIG. 6 is a plan view schematically showing a display panel (10) according to some embodiments.

[0107] Referring to FIG. 6, the display panel (10) may include a substrate (100). Various components constituting the display panel (10) may be arranged on the substrate (100).

[0108] The substrate (100) may include glass, metal, or a polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate (100) may have a multilayer structure including two layers including the aforementioned polymer resin and an inorganic layer interposed between the layers.

[0109] A plurality of pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA).

[0110] A gate driving circuit (e.g., a first scan driving circuit (11), a second scan driving circuit (12), a light emission control driving circuit (13)), a pad (14), a first power supply wiring (15), and a second power supply wiring (16) can be arranged in the peripheral area (PA).

[0111] The first scan driving circuit (11) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12) can be arranged on the opposite side of the first scan driving circuit (11) with the display area (DA) therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (11), and the rest can be connected to the second scan driving circuit (12). According to some embodiments, the second scan driving circuit (12) can be omitted.

[0112] The light emission control driving circuit (13) is arranged on the side of the first scan driving circuit (11) and can provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 6, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present disclosure is not limited thereto. According to some embodiments, the light emission control driving circuits (13) may be arranged on both sides of the display area (DA).

[0113] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) may be exposed without being covered by an insulating layer and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display panel (10).

[0114] The display circuit board (30) transmits a signal or power of the control unit to the display panel (10). The control signal generated by the control unit can be transmitted to the gate driving circuit through the display circuit board (30), respectively. In addition, the control unit can provide a first power voltage and a second power voltage (ELVDD, ELVSS, FIG. 8) to the first and second power supply lines (15, 16), respectively. The first power voltage (ELVDD, hereinafter referred to as driving voltage) is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply line (15), and the second power voltage (ELVSS, hereinafter referred to as common voltage) can be provided to the opposite electrode of the light emitting diode (LED) connected to the second power supply line (16). The first power supply line (15) can extend in the first direction (e.g., x direction). The second power supply line (16) has a loop shape with one side open. It can partially surround the display area (DA).

[0115] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the input line (IL) and the data line (DL) electrically connected to the input line (IL).

[0116] FIGS. 7A and 7B are enlarged plan views of part VII of FIG. 6, respectively, as a part of a display device according to some embodiments.

[0117] Referring to Fig. 7a, a data line (DL) extending along a second direction (e.g., y direction) is arranged in the display area (DA), and an input line (IL) is arranged in the peripheral area (PA). The input line (IL) can transmit a data signal of a data driver (20, Fig. 6) to the data line (DL). For convenience of explanation, Fig. 7a illustrates a case where the data line (DL) includes first to sixth data lines (DL1, DL2, DL3, DL4, DL5, DL6) and the input line (IL) includes first to sixth input lines (IL1, IL2, IL3, IL4, IL5, IL6), but the number of data lines (DL) and the number of input lines (IL) may be seven or more.

[0118] Some of the data lines (DL) may be directly connected to the input lines, while others of the data lines (DL) may be electrically connected via data transfer lines (DTL) between the input lines (IL) and the corresponding data lines (DL).

[0119] According to some embodiments, the first, third, and fifth data lines (DL1, DL3, and DL5) may receive data signals from the first, third, and fifth input lines (IL1, IL3, and IL5), respectively. The first, third, and fifth input lines (IL1, IL3, and IL5) may be electrically connected to the first, third, and fifth data lines (DL1, DL3, and DL5), respectively. The first, third, and fifth input lines (IL1, IL3, and IL5) may be formed integrally with the first, third, and fifth data lines (DL1, DL3, and DL5), or may be connected through a first contact hole (CNT1) as shown in FIG. 7a.

[0120] According to some embodiments, the second, fourth, and sixth data lines (DL2, DL4, and DL6) may receive data signals from the second, fourth, and sixth input lines (IL2, IL4, and IL6), respectively, via the first to third data transmission lines (DTL1, DTL2, and DTL3). The second, fourth, and sixth input lines (IL2, IL4, and IL6) may be electrically connected to the second, fourth, and sixth data lines (DL2, DL4, and DL6), respectively, via the first to third data transmission lines (DTL1, DTL2, and DTL3).

[0121] The first to third data transmission lines (DTL1, DTL2, DTL3) can each be arranged in the display area (DA). The second input line (IL2) is electrically connected to the second data line (DL2) via the first data transmission line (DTL1), the fourth input line (IL4) is electrically connected to the fourth data line (DL4) via the second data transmission line (DTL2), and the sixth input line (IL6) is electrically connected to the sixth data line (DL6) via the third data transmission line (DTL3).

[0122] Each of one end of the first to third data transmission lines (DTL1, DTL2, DTL3) can be connected to the second, fourth, and sixth input lines (IL2, IL4, IL6) through the second contact hole (CNT2), and each of the other ends of the first to third data transmission lines (DTL1, DTL2, DTL3) can be connected to the second, fourth, and sixth data lines (DL2, DL4, DL6) through the third contact hole (CNT3). Although FIG. 7A illustrates that the second contact hole (CNT2) and the third contact hole (CNT3) are located in the peripheral area (PA), the present disclosure is not limited thereto. According to some embodiments, the second contact hole (CNT2) and / or the third contact hole (CNT3) can be located in the display area (DA).

[0123] According to some embodiments, the first to third data transmission lines (DTL1, DTL2, DTL3) may each include a first connection line (DH1, DH2, DH3), a second connection line (DV1, DV2, DV3), and a third connection line (DV1', DV2', DV3'). The first connection line (DH1, DH2, DH3) may extend in a first direction (e.g., x-direction), and the second connection line (DV1, DV2, DV3) and the third connection line (DV1', DV2', DV3') may extend in a second direction (e.g., y-direction) substantially parallel to the data line (DL).

[0124] Each of the second, fourth, and sixth input lines (IL2, IL4, and IL6) can be connected to the second connection lines (DV1, DV2, and DV3) through the second contact hole (CNT2), and each of the third connection lines (DV1', DV2', and DV3') can be connected to the second, fourth, and sixth data lines (DL2, DL4, and DL6) through the third contact hole (CNT3). Each of the first connection lines (DH1, DH2, and DH3) can be connected to the second connection lines (DV1, DV2, and DV3) and the third connection lines (DV1', DV2', and DV3') through the first connection contact hole (DH-CNT1) and the second connection contact hole (DH-CNT2).

[0125] According to some embodiments, the second connection lines (DV1, DV2, DV3) and the third connection lines (DV1', DV2', DV3') may be disposed on the same layer, and the first connection lines (DH1, DH2, DH3) may be disposed on a different layer from the second connection lines (DV1, DV2, DV3) and the third connection lines (DV1', DV2', DV3'). In this case, being disposed on the same layer may mean that they are formed simultaneously through the same mask process and include the same material.

[0126] Although Fig. 7a illustrates that the first to third data transmission lines (DTL1, DTL2, DTL3) include first connection lines (DH1, DH2, DH3), second connection lines (DV1, DV2, DV3) and third connection lines (DV1', DV2', DV3'), respectively, the present invention is not limited thereto. In another embodiment, as illustrated in Fig. 7b, the first to third data transmission lines (DTL1, DTL2, DTL3) may include first connection lines (DH1, DH2, DH3) and second connection lines (DV1, DV2, DV3), respectively. In this case, the second connection lines (DV1, DV2, DV3) may be electrically connected to data lines, for example, the second, fourth and sixth data lines (DL2, DL4, DL6), through a second connection contact hole (DH-CNT2).

[0127] Although FIGS. 7A and 7B illustrate a structure in which one connection line extending in a second direction (e.g., y-direction) is arranged between two adjacent data lines (DL), the present disclosure is not limited thereto. According to some embodiments, two connection lines (e.g., data connection lines (DVL, FIG. 18) of FIG. 18) may be arranged between two adjacent data lines (DL), as in the embodiment described with reference to FIG. 18.

[0128] FIG. 8 is an equivalent circuit diagram of a light emitting diode (LED) and a pixel circuit (PC) of a display panel (10, FIG. 6) according to some embodiments.

[0129] Referring to FIG. 8, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. According to some embodiments, the pixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, and T6), a storage capacitor (Cst), and a hold capacitor (Chd). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to sixth transistors (T2, T3, T4, T5, and T6) may be switching transistors that transmit a signal. The first terminal (first electrode) of each of the first to sixth transistors (T1, T2, T3, T4, T5, and T6) may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source.

[0130] According to some embodiments, one or more of the first to sixth transistors (T1, T2, T3, T4, T5, T6) may be a p-channel MOSFET (PMOS), and the others may be n-channel MOSFETs (NMOS). For example, the fifth transistor (T5) may be a PMOS, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4 T6) may be NMOS. According to some embodiments, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first, second, third, and fourth transistors (T1, T2, T3, T4) may be NMOS. Alternatively, the first to sixth transistors (T1, T2, T3, T4, T5, T6) may all be NMOS or all may be PMOS.

[0131] One or more of the first to sixth transistors (T1, T2, T3, T4, T5, T6) may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and one or more of the first to sixth transistors (T1, T2, T3, T4, T5, T6) may be a transistor having an oxide semiconductor layer. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, T6) may include an oxide semiconductor layer having high carrier mobility and low leakage current.

[0132] In the following, embodiments will be described in which the fifth transistor (T5) is a PMOS (p-channel MOSFET) including a silicon semiconductor, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, and T6) are NMOS (n-channel MOSFETs) including an oxide semiconductor.

[0133] The pixel circuit (PC) may be electrically connected to a gate line that transmits a signal to each of the gates of the first to sixth transistors (T1, T2, T3, T4, T5, and T6). For example, the pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal (GW), an initialization gate line (GBL) that transmits an initialization signal (GB), a reference gate line (GRL) that transmits a reference signal (GR), a first emission control line (EML) that transmits a first emission control signal (EM), a second emission control line (EMBL) that transmits a second emission control signal (EMB), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel circuit (PC) may be connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (Vref), and an initialization voltage line (VL) that transmits an initialization voltage (Vaint).

[0134] A first transistor (T1) may be electrically connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a gate (G1) connected to the first node (N1), a first terminal electrically connected to the driving voltage line (PL), and a second terminal connected to a second node (N2). The first terminal may be a drain (D) and the second terminal may be a source (S).

[0135] A first terminal of a first transistor (T1) is connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal of the first transistor (T1) can be connected to a pixel electrode of a light-emitting diode (LED). The first transistor (T1) can receive a data signal (DATA) according to a switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the light-emitting diode (LED).

[0136] The second transistor (T2) may be electrically connected between the data line (DL) and the first node (N1). The second transistor (T2) may include a gate connected to the scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on by a scan signal (GW) transmitted to the scan line (GWL) to electrically connect the data line (DL) and the first node (N1), and may transmit a data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0137] A third transistor (T3) may be electrically connected between a first node (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to the reference gate line (GRL), a first terminal connected to the first node (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a reference signal (GR) transmitted to the reference gate line (GRL) and may transmit a reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0138] The fourth transistor (T4) may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). The fourth transistor (T4) may include a gate connected to the initialization gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and a light-emitting diode (LED), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by the initialization signal (GB) transmitted to the initialization gate line (GBL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VL) to the pixel electrode of the light-emitting diode (LED).

[0139] The fifth transistor (T5) may be electrically connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the first emission control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to the first emission control signal (EM) transmitted to the first emission control line (EML).

[0140] The sixth transistor (T6) may be connected between the first transistor (T1) and the light emitting diode (LED). The sixth transistor (T6) may include a gate connected to the second light emitting control line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the light emitting diode (LED). The sixth transistor (T6) may be turned on by the second light emitting control signal (EMB) transmitted to the second light emitting control line (EMBL) to electrically connect the second node (N2) and the pixel electrode of the light emitting diode (LED).

[0141] Although FIG. 8 illustrates that the fifth transistor (T5) and the sixth transistor (T6) operate in response to different light emission control signals (EM, EMB), the present disclosure is not limited thereto. According to some embodiments, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same light emission control signal.

[0142] According to some embodiments, the reference signal (GR) may be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row. The initialization signal (GB) may be substantially synchronized with the scan signal (GW). According to some embodiments, the initialization signal (GB) may be substantially synchronized with the scan signal (GW) or the reference signal (GR) of the pixel circuit (PC) located in the next row.

[0143] The storage capacitor (Cst) may be connected between the first node (N1) and the second node (N2). In other words, the pixel circuit (PC) according to some embodiments of the present invention may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2). The first storage electrode (CEs1) of the storage capacitor (Cst) may be connected to the first node (N1), and the second storage electrode (CEs2) may be connected to the second node (N2). The storage capacitor (Cst) may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0144] According to some embodiments, a hold capacitor (Chd) may be connected between a driving voltage line (PL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be connected to the driving voltage line (PL), and a second hold electrode (CEh2) may be connected to a second node (N2). The hold capacitor (Chd) may allow the voltage of the second node (N2) of the first transistor (T1) to remain constant and not fluctuate when a peripheral signal fluctuates.

[0145] A light emitting diode (LED) includes a pixel electrode connected to a second node (N2) and a counter electrode on the pixel electrode, and the counter electrode can be supplied with a common voltage (ELVSS). The counter electrode can be a common electrode shared by a plurality of light emitting diodes (LEDs).

[0146] Although FIG. 8 illustrates the pixel circuit (PC) as including six transistors and two capacitors, the present disclosure is not limited thereto. In another embodiment, the pixel circuit (PC) may include five transistors and two capacitors. According to some embodiments, the pixel circuit (PC) may include seven transistors and two capacitors. Furthermore, according to some embodiments, the pixel circuit (PC) may include additional or fewer components without departing from the spirit and scope of the embodiments according to the present disclosure.

[0147] FIG. 9 is a plan view schematically illustrating pixel circuits of a display panel (10) according to some embodiments. For convenience of explanation, FIG. 9 illustrates two pixel circuits, for example, a first pixel circuit (PC1) and a second pixel circuit (PC2), arranged in the same row along a first direction (e.g., x-direction), but the present disclosure is not limited thereto. The display panel (10) includes a plurality of pixel circuits arranged to form rows in the first direction (e.g., x-direction) and columns in the second direction (e.g., y-direction).

[0148] Referring to FIG. 9, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include transistors and capacitors. According to some embodiments, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first to sixth transistors (T1, T2, T3, T4, T5, T6), a storage capacitor (Cst), and a hold capacitor (Chd) described above with reference to FIG. 8.

[0149] The transistors and capacitors of the first pixel circuit (PC1) may be arranged symmetrically with the transistors and capacitors of the second pixel circuit (PC2), respectively. For example, the first transistor (T1) of the first pixel circuit (PC1) may be symmetrical with the first transistor (T1) of the second pixel circuit (PC2) with respect to an imaginary line (IML) passing between the first pixel circuit (PC1) and the second pixel circuit (PC2) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the first pixel circuit (PC1) may be symmetrical with the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2), respectively, with respect to the imaginary line (IML).

[0150] Gate lines electrically connected to the first pixel circuit (PC1) and the second pixel circuit (PC2), such as a scan line (GWL), an initialization gate line (GBL), a reference gate line (GRL), a first emission control line (EML), and a second emission control line (EMBL), can extend in a first direction (e.g., an x-direction).

[0151] A first pixel circuit (PC1) may be electrically connected to a data line (DL) passing through the first pixel circuit (PC1), and a second pixel circuit (PC2) may be electrically connected to a data line (DL) passing through the second pixel circuit (PC2). The data line (DL) may extend along a second direction (e.g., y direction). The data line (DL) electrically connected to the first pixel circuit (PC1) and the data line (DL) electrically connected to the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML).

[0152] A first pixel circuit (PC1) may be electrically connected to a voltage line passing through the first pixel circuit (PC1), for example, a reference voltage line (VRL) and an initialization voltage line (VL). A second pixel circuit (PC2) may be electrically connected to a voltage line passing through the second pixel circuit (PC2), for example, a reference voltage line (VRL) and an initialization voltage line (VL). The reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the first pixel circuit (PC1) may be symmetrical with respect to the reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the second pixel circuit (PC2), respectively, and the aforementioned imaginary line (IML). The reference voltage line (VRL) and the initialization voltage line (VL) may each extend along a second direction (e.g., a y direction).

[0153] In some embodiments, the data connection line (DVL) may extend along the second direction (e.g., the y direction). The data connection line (DVL) may be a signal line corresponding to a portion of the data transmission line (DTL) described above with reference to FIG. 7a or FIG. 7b, for example, one of the second connection lines (DV1, DV2, DV3, FIG. 7a, FIG. 7b), or one of the third connection lines (DV1', DV2', DV3', FIG. 7a). The data connection line (DVL) may be electrically connected to the data lines of pixel circuits arranged in a different column from the first and second pixel circuits (PC1, PC2) illustrated in FIG. 9, so as to transmit data signals to pixel circuits arranged in a different column.

[0154] FIG. 10 is a cross-sectional view of a display panel (10) according to some embodiments, showing a cross-section taken along line X-X' of FIG. 6.

[0155] Referring to FIG. 10, the display panel (10) may include a circuit layer including transistors and capacitors disposed on a substrate (100), and a display element layer disposed on the aforementioned circuit layer and including a light-emitting diode (LED). The circuit layer may include the transistors and capacitors described above with reference to FIGS. 8 and 9, and FIG. 10 illustrates a first transistor (T1), a fifth transistor (T5), a storage capacitor (Cst), and a hold capacitor (Chd).

[0156] The substrate (100) may include a glass material, a ceramic material, a metal material, a plastic material, or a material having flexible or bendable properties. When the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyether imide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0157] The substrate (100) may have a single-layer or multi-layer structure of the above material, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate (100) may have a structure in which a layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material are alternately laminated.

[0158] A lower metal layer (1110) may be disposed on the substrate (100). The lower metal layer (1110) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer (1110) may be a single layer including molybdenum, have a double layer structure in which a molybdenum layer and a titanium layer are stacked, or have a triple layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0159] The lower metal layer (1110) may have a voltage level of a constant voltage. For example, the lower metal layer (1110) may have the same voltage level (e.g., driving voltage, ELVDD) as the driving voltage line (PL) described with reference to FIG. 8. The lower metal layer (1110) may shield light traveling to the fifth semiconductor layer (A5) of the fifth transistor (T5) and protect the fifth transistor (T5) from electrostatic discharge (ESD).

[0160] The lower metal layer (1110) may be electrically connected to a portion of the driving voltage line (PL, FIG. 6) or the first power supply line (15, FIG. 6) in an area other than the display area (DA, FIG. 6), for example, a peripheral area (PA).

[0161] The buffer layer (101) may be disposed on the lower metal layer (1110). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0162] A transistor including a silicon semiconductor layer may be arranged on the buffer layer (101). In this regard, FIG. 10 illustrates a fifth semiconductor layer (A5) of a fifth transistor (T5). The fifth semiconductor layer (A5) may include polysilicon. The fifth semiconductor layer (A5) may include a channel region (C5) and impurity regions (S5, D5) doped with impurities, which are arranged on both sides of the channel region (C5). One of the impurity regions (S5, D5) of the fifth semiconductor layer (A5) may be a source and the other may be a drain.

[0163] The first gate insulating layer (103) may be disposed on the fifth semiconductor layer (A5). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0164] The fifth gate electrode (G5) is disposed on the first gate insulating layer (103) and may overlap the channel region (C5) of the fifth semiconductor layer (A5). On the same layer as the fifth gate electrode (G5), for example, on the first gate insulating layer (103), a sub-layer of the first storage electrode (CEs1) of the storage capacitor (Cst) and the first hold electrode (CEh1) of the hold capacitor (Chd), for example, a first lower hold electrode (CEh1a), may be disposed.

[0165] The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include the same material. The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. According to some embodiments, the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may be a single layer including molybdenum.

[0166] The second gate insulating layer (105) may be disposed on the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd). The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. According to some embodiments, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0167] A conductive layer (1410, hereinafter referred to as a fifth conductive layer) may be disposed on a second gate insulating layer (105). The fifth conductive layer (1410) may overlap a first storage electrode (CEs1) of a storage capacitor (Cst) and a first lower hold electrode (CEh1a) of a hold capacitor (Chd). The fifth conductive layer (1410) may include a second electrode (CEs2) of the storage capacitor (Cst) and a second hold electrode (CEh2) of the hold capacitor (Chd). One part of the fifth conductive layer (1410) may be the second electrode (CEs2) of the capacitor (Cst), and another part of the fifth conductive layer (1410) may be the second hold electrode (CEh2) of the hold capacitor (Chd). In other words, the second electrode (CEs2) of the capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd) can be connected as one body.

[0168] The fifth conductive layer (1410), for example, the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd), may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. According to some embodiments, the fifth conductive layer (1410) may be a single layer including molybdenum.

[0169] The first interlayer insulating layer (107) may be disposed on the fifth conductive layer (1410). The first interlayer insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. For example, the first interlayer insulating layer (107) may have a stacked structure of a layer including silicon oxide and a layer including silicon nitride.

[0170] The first semiconductor layer (A1) of the first transistor (T1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd) may be disposed on the first interlayer insulating layer (107) and may include the same material. The first semiconductor layer (A1) of the first transistor (T1) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0171] The first semiconductor layer (A1) may include a channel region (C1) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source and the other may be a drain.

[0172] The first semiconductor layer (A1) may be arranged on a different layer from the fifth semiconductor layer (A5) described above. The vertical distance from the substrate (100) to the first semiconductor layer (A1) may be greater than the vertical distance from the substrate (100) to the fifth semiconductor layer (A5).

[0173] The first upper hold electrode (CEh1b) of the hold capacitor (Chd) may overlap the fifth conductive layer (1410) and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) below the fifth conductive layer (1410). The first upper hold electrode (CEh1b) of the hold capacitor (Chd) may be electrically connected to the first lower hold electrode (CEh1a).

[0174] The third gate insulating layer (109) may be disposed on the first semiconductor layer (A1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd). The third gate insulating layer (109) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. According to some embodiments, the third gate insulating layer (109) may be a single-layer including silicon oxide.

[0175] Although FIG. 10 illustrates that the third gate insulating layer (109) passes through the side surface of the first semiconductor layer (A1) and contacts the top surface of the first interlayer insulating layer (107), the present disclosure is not limited thereto. According to some embodiments, the third gate insulating layer (109) may be formed to have substantially the same pattern and / or the same width as the first gate electrode (G1) described below. In other words, the third gate insulating layer (109) may not pass through the side surface of the first semiconductor layer (A1) and contact the top surface of the first interlayer insulating layer (107).

[0176] The first gate electrode (G1) may be disposed on the third gate insulating layer (109). The first gate electrode (G1) may overlap the channel region (C1) of the first semiconductor layer (A1). The first gate electrode (G1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. According to some embodiments, the first gate electrode (G1) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0177] The second interlayer insulating layer (111) may be disposed on the first gate electrode (G1). The second interlayer insulating layer (111) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. According to some embodiments, the second interlayer insulating layer (111) may have a stacked structure of a layer including silicon nitride and a layer including silicon oxynitride.

[0178] The first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may be disposed on the same layer, for example, the second interlayer insulating layer (111). The first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may include the same material. The first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. According to some embodiments, the first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730) may have a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0179] The first organic insulating layer (113) may be disposed on the first connection electrode (1710), the second connection electrode (1720), and the third connection electrode (1730). The first organic insulating layer (113) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0180] The data line (DL) and the initialization voltage line (VL) may be arranged on the first organic insulating layer (113). The data line (DL) and the initialization voltage line (VL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. According to some embodiments, the data line (DL) and the initialization voltage line (VL) may have a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0181] The second organic insulating layer (115) may be placed on the data line (DL) and the initialization voltage line (VL). The second organic insulating layer (115) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0182] The voltage layer (1900) may be disposed on the second organic insulating layer (115). According to some embodiments, the voltage layer (1900) may have a voltage level of the driving voltage line (PL) described with reference to FIG. 8. The voltage layer (1900) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. According to some embodiments, the voltage layer (1900) may have a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer.

[0183] The third organic insulating layer (117) may be disposed on the voltage layer (1900). The third organic insulating layer (117) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0184] A light emitting diode (LED) may be disposed on the third organic insulating layer (117). The light emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) on the third organic insulating layer (117).

[0185] An outer portion of the pixel electrode (210) may be covered by a bank layer (119), and an inner portion of the pixel electrode (210) may overlap an intermediate layer (220) through an opening (119OP) of the bank layer (119). The pixel electrode (210) may be arranged to correspond to each light-emitting diode (LED), and the counter electrode (230) may be arranged to correspond to a plurality of light-emitting diodes (LEDs). In other words, the counter electrode (230) may be extended to overlap a plurality of pixel electrodes (210). A plurality of light-emitting diodes (LEDs) may share the counter electrode (230), and a stacked structure of the pixel electrode (210), the intermediate layer (220), and the counter electrode (230) may correspond to a light-emitting diode (LED).

[0186] The intermediate layer (220) may include an emission layer. In some embodiments, the intermediate layer (220) may further include an emission layer and a functional layer. The functional layer may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). According to some embodiments, the intermediate layer (220) may include a first stack including an emission layer and a functional layer, a second stack including an emission layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of a tandem light emitting diode (LED) including a plurality of emission layers can be further increased by the negative charge generation layer and the positive charge generation layer.

[0187] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0188] The counter electrode (230) may be formed of a conductive material having a low work function. The counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0189] According to some embodiments, an encapsulation layer may be disposed on a light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0190] FIGS. 11 to 19 are plan views illustrating a process for forming a pixel circuit of a display panel (10) according to some embodiments. FIGS. 11 to 19 illustrate a process for forming components corresponding to the first pixel circuit (PC1) and the second pixel circuit (PC2) described with reference to FIG. 9. For convenience of explanation, the first pixel circuit (PC1) is described as being located in the (i)-th row and the (j)-th column, and the second pixel circuit (PC2) is described as being located in the (i)-th row and the (j+1)-th column.

[0191] Referring to FIG. 11, a lower metal layer (1110) may be disposed on a substrate. The lower metal layer (1110) may include a first portion (1111) extending along a second direction (e.g., y direction), and a second portion (1112) and a third portion (1113) connected to the first portion (1111) but extending along the first direction (e.g., x direction) as a whole.

[0192] According to some embodiments, the first portion (1111) of the lower metal layer (1110) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second portion (1112) and the third portion (1113) of the lower metal layer (1110) may be positioned on opposite sides with the first portion (1111) therebetween. The second portion (1112) and the third portion (1113) may extend generally along the first direction (e.g., the x-direction), but may be locally bent. The lower metal layer (1110) may include the metallic material described above with reference to FIG. 10.

[0193] The lower metal layer (1110) may have a voltage level of a constant voltage. For example, the lower metal layer (1110) may be electrically connected to the first power supply line (15, FIG. 6) at the periphery of the display area (DA) of the display panel (10, FIG. 6).

[0194] A buffer layer (101, FIG. 10) may be formed on the structure illustrated in FIG. 11, and a first silicon semiconductor pattern (1210) may be formed on the buffer layer (101, FIG. 10) as illustrated in FIG. 12. The first silicon semiconductor pattern (1210) may include silicon, for example, polysilicon.

[0195] Referring to FIG. 12, the first silicon semiconductor pattern (1210) may have an isolated shape and may extend along a first direction (e.g., x-direction). The first silicon semiconductor pattern (1210) may intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The first silicon semiconductor pattern (1210) may include a fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). In other words, the fifth semiconductor layer (A5) of the first pixel circuit (PC1) and the fifth semiconductor layer (A5) of the second pixel circuit (PC2) may be integrally connected.

[0196] The first silicon semiconductor pattern (1210) may overlap with the lower metal layer (1110). For example, the first silicon semiconductor pattern (1210) may overlap with the third portion (1113) of the lower metal layer (1110). The fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may overlap with the third portion (1113) of the lower metal layer (1110).

[0197] A first gate insulating layer (103, FIG. 10) may be formed on the structure illustrated in FIG. 12, and a gate line and a conductive layer may be formed as illustrated in FIG. 13. FIG. 13 illustrates that a first emission control line (EML), a first conductive layer (1310), a second conductive layer (1320), a third conductive layer (1330), and a fourth conductive layer (1340) are formed on the first gate insulating layer (103, FIG. 10).

[0198] Referring to FIG. 13, the first emission control line (EML), the first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may be spaced apart from each other. The first emission control line (EML), the first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0199] The first emission control line (EML) can extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0200] The first emission control line (EML) may include a fifth gate electrode (G5) of a fifth transistor (T5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). A portion of the first emission control line (EML) may protrude to overlap with a fifth semiconductor layer (A5) of the fifth transistor (T5), and a portion of the protruding first emission control line (EML) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5, FIG. 12) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and doped regions (S5, D5) disposed on both sides of the channel region (C5) and doped with impurities. One of the doped regions (S5, D5) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0201] The first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may be disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2). The first conductive layer (1310), the second conductive layer (1320), the third conductive layer (1330), and the fourth conductive layer (1340) may each have an isolated shape. The first conductive layer (1310) and the third and fourth conductive layers (1330, 1340) of the first pixel circuit (PC1), and the first conductive layer (1310) and the third and fourth conductive layers (1330, 1340) of the second pixel circuit (PC2) may be disposed symmetrically with respect to the aforementioned virtual line (IML).

[0202] The second conductive layer (1320) has an isolated shape and may extend in a first direction (e.g., x direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1320) may intersect a virtual line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1320) may include a stem portion extending in the first direction (e.g., x direction) and a branch portion branching from the stem portion and protruding along a second direction (e.g., -y direction). The branch portion of the first pixel circuit (PC1) and the branch portion of the second pixel circuit (PC2) may be substantially symmetrically arranged with respect to the virtual line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0203] The second conductive layer (1320) may include a first lower hold electrode (CEh1a), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd) described with reference to FIG. 10. In other words, the first lower hold electrode (CEh1a) of the hold capacitor (Chd) of the first pixel circuit (PC1) may be integrally connected to the first lower hold electrode (CEh1a) of the hold capacitor (Chd) of the second pixel circuit (PC2).

[0204] The third conductive layer (1330) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first storage electrode (CEs1) of the storage capacitor (Cst) described with reference to FIG. 10.

[0205] A second gate insulating layer (105, FIG. 10) may be formed on the structure illustrated in FIG. 13, and a gate line and a conductive layer may be formed as illustrated in FIG. 14. FIG. 14 illustrates that an initialization gate line (GBL), a reference gate line (GRL), and a fifth conductive layer (1410) are formed on the second gate insulating layer (105, FIG. 10).

[0206] Referring to FIG. 14, an initialization gate line (GBL), a reference gate line (GRL), and a fifth conductive layer (1410) are arranged to be spaced apart from each other. The initialization gate line (GBL), the reference gate line (GRL), and the fifth conductive layer (1410) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0207] Each of the initialization gate line (GBL) and the reference gate line (GRL) may extend along a first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). Each of the initialization gate line (GBL) and the reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0208] The fifth conductive layer (1410) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth conductive layer (1410) disposed in the first pixel circuit (PC1) and the fifth conductive layer (1410) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be disposed substantially symmetrically with respect to the aforementioned virtual line (IML).

[0209] The fifth conductive layer (1410) can overlap the third conductive layer (1330) of the first pixel circuit (PC1), the third conductive layer (1330) of the second pixel circuit (PC2), and the second conductive layer (1320) passing through the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0210] The fifth conductive layer (1410) may include a second hold electrode (CEh2) of a hold capacitor (Chd, FIG. 10) and a second storage electrode (CEs2) of a storage capacitor (Cst, FIG. 10). In other words, the second hold electrode (CEh2) of the hold capacitor (Chd) and the second storage electrode (CEs2) of the storage capacitor (Cst) may be formed integrally.

[0211] A first interlayer insulating layer (107, FIG. 10) can be formed on the structure illustrated in FIG. 14, and semiconductor patterns can be formed as illustrated in FIG. 15. FIG. 15 illustrates that a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540) are formed on the first interlayer insulating layer (107, FIG. 10).

[0212] Referring to FIG. 15, the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be arranged to be spaced apart from each other. The first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may each include ITZO (InSnZnO), IGZO (InGaZnO), or the like.

[0213] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The first oxide semiconductor pattern (1510) may include a first semiconductor layer (A1), a fourth semiconductor layer (A4), and a sixth semiconductor layer (A6). In other words, the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the first pixel circuit (PC1) may be integrally connected, and the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the second pixel circuit (PC2) may be integrally connected. The first oxide semiconductor pattern (1510) may have a shape that is folded several times.

[0214] The first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) may overlap with the fifth conductive layer (1410) and the initialization gate line (GBL) described with reference to FIG. 14, and the fourth conductive layer (1340) described with reference to FIG. 13, respectively.

[0215] According to some embodiments, on a plane, the shapes of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be different from each other. A part of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may be arranged in a pixel circuit that is arranged in the same row as the first pixel circuit (PC) but in an adjacent column (e.g., the (i)-th row and the (j-1)-th column).

[0216] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second oxide semiconductor pattern (1520) may be bent to have an approximately "L" shape. The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML).

[0217] The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of the second transistor (T2) and a third semiconductor layer (A3) of the third transistor (T3). In other words, the second semiconductor layer (A2) of the second transistor (T2) and the third semiconductor layer (A3) of the third transistor (T3) may be connected integrally.

[0218] The second semiconductor layer (A2) and the third semiconductor layer (A3) may overlap with the first conductive layer (1310) described with reference to FIG. 13 and the reference gate line (GRL) described with reference to FIG. 14, respectively.

[0219] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML).

[0220] The third oxide semiconductor pattern (1530) may overlap with the fifth conductive layer (1410) described with reference to FIG. 14 and the second conductive layer (1320) described with reference to FIG. 13. The third oxide semiconductor pattern (1530) may include a first upper hold electrode (CEh1b), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd, FIG. 10).

[0221] The fourth oxide semiconductor pattern (1540) may be arranged on the first pixel circuit (PC1). The fourth oxide semiconductor pattern (1540) may be arranged at a position corresponding to one end of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and may correspond to a type of dummy electrode.

[0222] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, a conductive process using plasma or the like may be performed on at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540). According to some embodiments, the entire region of the third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b) may be conductive to form a hold capacitor (Chd, FIG. 8).

[0223] A third gate insulating layer (109, FIG. 10) can be formed on the structure illustrated in FIG. 15, and gate lines, voltage lines, and conductive layers (e.g., electrode layers) can be formed as illustrated in FIG. 16.

[0224] Referring to FIG. 16, a horizontal initialization voltage line (VHL), a second emission control line (EMBL), a horizontal reference voltage line (VRHL), and first to fourth electrode layers (1610, 1620, 1230, 1640) can be formed on a third gate insulating layer (109, FIG. 10).

[0225] The horizontal initialization voltage line (VHL), the second emission control line (EMBL), the horizontal reference voltage line (VRHL), and the first to fourth electrode layers (1610, 1620, 1230, 1640) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials.

[0226] The horizontal initialization voltage line (VHL) may extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The horizontal initialization voltage line (VHL) may be electrically connected to an initialization voltage line (VL) which will be described later with reference to FIG. 18.

[0227] The second emission control line (EMBL) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second emission control line (EMBL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0228] A horizontal reference voltage line (VRHL) may extend along a first direction (e.g., x-direction) so as to pass through a first pixel circuit (PC1) and a second pixel circuit (PC2). The horizontal reference voltage line (VRHL) may be electrically connected to a reference voltage line (VRL) which will be described later with reference to FIG. 18.

[0229] The first electrode layer (1610), the second electrode layer (1620), and the fourth electrode layer (1640) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may each have an isolated shape. The first, second, and fourth electrode layers (1610, 1620, 1640) of the first pixel circuit (PC1) and the first, second, and fourth electrode layers (1610, 1620, 1640) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML).

[0230] The third electrode layer (1630) has an isolated shape and can extend along the first direction (e.g., the x-direction). The third electrode layer (1630) can be arranged across the first pixel circuit (PC1) and the second pixel circuit (PC2). The third electrode layer (1630) can intersect the aforementioned virtual line (IML).

[0231] The first to fourth electrode layers (1610, 1620, 1630, 1640) and the second emission control line (EMBL) may include a gate electrode of a transistor.

[0232] Each of the first electrode layers (1610) of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a first gate electrode (G1) of the first transistor (T1). Referring to FIGS. 15 and 16, the first semiconductor layer (A1) of the first transistor (T1) may include a channel region (C1) overlapping the first electrode layer (1610) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0233] The second electrode layer (1620) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a third gate electrode (G3) of a third transistor (T3). Referring to FIGS. 15 and 16, the third semiconductor layer (A3) of the third transistor (T3) may include a channel region (C3) overlapping the second electrode layer (1620) and conductive regions (S3, D3) arranged on both sides of the channel region (C3). One of the conductive regions (S3, D3) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0234] The second electrode layer (1620) may be electrically connected to a reference gate line (GRL) disposed below the third semiconductor layer (A3, FIG. 15) through a contact hole (CNT). The second electrode layer (1620) and a portion of the reference gate line (GRL) may overlap each other with the channel region (C3) of the third transistor (T3) interposed therebetween. A portion of the reference gate line (GRL) overlapping the channel region (C3) of the third transistor (T3) may correspond to the lower gate electrode of the third transistor (T3), and the switching performance of the third transistor (T3) may be relatively improved through such a dual gate structure.

[0235] The third electrode layer (1630) may include a second gate electrode (G2) of the second transistor (T2). Referring to FIGS. 15 and 16, the second semiconductor layer (A2) of the second transistor (T2) may include a channel region (C2) overlapping the third electrode layer (1630) and conductive regions (S2, D2) arranged on both sides of the channel region (C2). One of the conductive regions (S2, D2) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0236] The third electrode layer (1630) is electrically connected to a scan line (GWL) to be described later with reference to FIG. 17. The third electrode layer (1630) may be electrically connected to a first conductive layer (1310) disposed below a second semiconductor layer (A2, FIG. 15) through a contact hole (CNT). The third electrode layer (1630) and the first conductive layer (1310) may overlap each other with the channel region (C2) of the second transistor (T2) interposed therebetween. The first conductive layer (1310) may correspond to a lower gate electrode of the second transistor (T2), and the switching performance of the second transistor (T2) may be relatively improved through such a double gate structure.

[0237] The fourth electrode layer (1640) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a fourth gate electrode (G4) of the fourth transistor (T4). Referring to FIGS. 15 and 16, the fourth semiconductor layer (A4) of the fourth transistor (T4) may include a channel region (C4) overlapping with the fourth electrode layer (1640) and conductive regions (S4, D4) arranged on both sides of the channel region (C4). One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0238] The fourth electrode layer (1640) can be electrically connected to an initialization gate line (GBL) disposed below the fourth semiconductor layer (A4, FIG. 15) through a contact hole (CNT). A portion of the fourth electrode layer (1640) and the initialization gate line (GBL) can overlap each other with the channel region (C4) of the fourth transistor (T4) interposed therebetween. A portion of the initialization gate line (GBL) overlapping the channel region (C4) of the fourth transistor (T4) can correspond to the lower gate electrode of the fourth transistor (T4), and the switching performance of the fourth transistor (T4) can be relatively improved through such a dual gate structure.

[0239] The second emission control line (EMBL) may include the sixth gate electrode (G6) of the sixth transistor (T6). Referring to FIGS. 15 and 16, the sixth semiconductor layer (A6) of the sixth transistor (T6) may include a channel region (C6) overlapping the second emission control line (EMBL) and conductive regions (S6, D6) arranged on both sides of the channel region (C6). One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0240] The second light emission control line (EMBL) may be electrically connected to the fourth conductive layer (1340) disposed below the sixth semiconductor layer (A6, FIG. 15) through a contact hole (CNT). A portion of the second light emission control line (EMBL) and the fourth conductive layer (1340) may overlap each other with the channel region (C6) of the sixth transistor (T6) interposed therebetween. The fourth conductive layer (1340) may correspond to the lower gate electrode of the sixth transistor (T6), and the switching performance of the fourth transistor (T4) may be improved through such a dual gate structure.

[0241] A second interlayer insulating layer (111, FIG. 10) may be formed on the structure illustrated in FIG. 16, and gate lines and conductive layers (e.g., connection electrodes) may be formed as illustrated in FIG. 17. FIG. 17 illustrates that scan lines (GWL) and first to eighth connection electrodes (1710, 1720, 1730, 1740, 1750, 1760, 1770, 1780) are formed on the second interlayer insulating layer (111, FIG. 10).

[0242] The scan line (GWL) and the first to eighth connecting electrodes (1710, 1720, 1730, 1740, 1750, 1760, 1770, 1780) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0243] The scan line (GWL) can extend along a first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The scan line (GWL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0244] The first connecting electrode (1710) has an isolated shape and can extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first connecting electrode (1710) can intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0245] The first connection electrode (1710) can be electrically connected to the second conductive layer (1320) and the third oxide semiconductor pattern (1530) through contact holes (CNT'). The first connection electrode (1710) can be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5, FIG. 16) through the contact hole (CNT'). The first connection electrode (1710) can connect the voltage layer (1900, FIG. 19) to be described later and the fifth transistor (T5, FIG. 16). The first connection electrode (1710) can be electrically connected to the voltage layer (1900, FIG. 19) and the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b), respectively.

[0246] The second connection electrode (1720) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second connection electrode (1720) may electrically connect the first transistor (T1, FIG. 16) and the fifth transistor (T5, FIG. 16) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). The second connection electrode (1720) may be electrically connected to the first semiconductor layer (A1) of the first transistor (T1, FIG. 16) through a contact hole (CNT') and may be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5, FIG. 16) through the contact hole (CNT'). The second connection electrode (1720) may electrically connect the first transistor (T1, FIG. 16) and the fifth transistor (T5, FIG. 16). In each of the first pixel circuit (PC1) and the second pixel circuit (PC2), a contact hole (CNT', FIG. 17) corresponding to a connection point for electrical connection between the second connection electrode (1720) and the first semiconductor layer (A1) may overlap with a third conductive layer (1330, see FIG. 14) and a fifth conductive layer (1410, see FIG. 14). The third conductive layer (1330, see FIG. 14) may be positioned below the first semiconductor layer (A1), and the fifth conductive layer (1410, see FIG. 14) may be positioned between the third conductive layer (1330, see FIG. 14) and the first semiconductor layer (A1). On a plane, the entire contact hole (CNT', see FIG. 17) corresponding to the connection point for electrical connection between the second connection electrode (1720) and the first semiconductor layer (A1) may overlap with the third conductive layer (1330, see FIG. 14) and the fifth conductive layer (1410, see FIG. 14). In a comparative example, when the edge of the third conductive layer (1330, see FIG. 14) and / or the edge of the fifth conductive layer (1410, see FIG. 14) is positioned below the contact hole (CNT', see FIG. 17), a step structure by the edge of the third conductive layer (1330, see FIG. 14) and / or the edge of the fifth conductive layer (1410, see FIG. 14) may be positioned below the contact hole (CNT').Due to the step structure, an accidental or unintended electrical connection may occur between the fifth conductive layer (1410, see FIG. 14) and the second connection electrode (1720). However, according to one or more embodiments, the entire contact hole (CNT', see FIG. 17), which corresponds to a connection point for electrical connection between the second connection electrode (1720) and the first semiconductor layer (A1), may overlap with the third conductive layer (1330, see FIG. 14) and the fifth conductive layer (1410, see FIG. 14). Therefore, the occurrence of an accidental or unintended electrical connection can be prevented.

[0247] The third connection electrode (1730) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third connection electrode (1730) may correspond to the first node described with reference to FIG. 8. The third connection electrode (1730) may electrically connect the first transistor (T1, FIG. 16), the third transistor (T3, FIG. 16), and the first storage electrode (CEs1) of the storage capacitor (Cst, FIG. 16) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). The third connecting electrode (1730) is electrically connected to the first electrode layer (1610) corresponding to the first gate electrode of the first transistor (T1, FIG. 16) through the contact hole (CNT'), is electrically connected to the third semiconductor layer (A3) through the contact hole (CNT'), and can be electrically connected to the third conductive layer (1330) through the contact hole (CNT').

[0248] The fourth connection electrode (1740) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fourth connection electrode (1740) may correspond to the second node described with reference to FIG. 8. The fourth connection electrode (1740) may electrically connect the second storage electrode (CEs2), the second hold electrode (CEh2), the first transistor (T1, FIG. 16), and the sixth transistor (T6, FIG. 16) of the storage capacitor (Cst, FIG. 16). The fourth connection electrode (1740) may be electrically connected to the fifth conductive layer (1410) including the second storage electrode (CEs2) and the second hold electrode (CEh2) through a contact hole (CNT'), and may be electrically connected to the first oxide semiconductor pattern (1510) through the contact hole (CNT'). The connection point of the fourth connecting electrode (1740) and the first oxide semiconductor pattern (1510) may be located between an area corresponding to the first semiconductor layer (A1) of the first oxide semiconductor pattern (1510) and an area corresponding to the sixth semiconductor layer (A6, FIG. 15).

[0249] The fifth connection electrode (1750) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth connection electrode (1750) may be electrically connected to a third transistor (T3, FIG. 16). The fifth connection electrode (1750) may be electrically connected to a third semiconductor layer (A3) through a contact hole (CNT'). The fifth connection electrode (1750) may be connected to a reference voltage line (VRL, FIG. 18) to be described later to transmit a reference voltage (Vref, FIG. 8) to the third transistor (T3, FIG. 16).

[0250] The sixth connection electrode (1760) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The sixth connection electrode (1760) may be electrically connected to the second transistor (T2, FIG. 16). The sixth connection electrode (1760) may be electrically connected to the second transistor (T2, FIG. 16) through a contact hole (CNT'). The sixth connection electrode (1760) may be connected to a data line (DL, FIG. 18) to be described later to transmit a data signal (DATA, FIG. 8) to the second transistor (T2, FIG. 16).

[0251] The seventh connection electrode (1770) located in the second pixel circuit (PC2) may have an isolated shape. The seventh connection electrode (1770) may electrically connect the fourth transistor (T4, FIG. 16) of the second pixel circuit (PC2) and the initialization voltage line (VL) described later with reference to FIG. 18. The seventh connection electrode (1770) may be electrically connected to the fourth semiconductor layer (A4) of the fourth transistor (T4, FIG. 16) through a contact hole (CNT').

[0252] The fourth transistor (T4, FIG. 16) located in the first pixel circuit (PC1) may be electrically connected to an initialization voltage line (not shown) passing through the first pixel circuit (PC1) and an adjacent pixel circuit. For example, a part of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may extend to an adjacent pixel circuit arranged in the (i)th row and the (j-1)th column, and the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) may be electrically connected to an initialization voltage line passing through the adjacent pixel circuit.

[0253] The dummy connection electrode (1770') located in the first pixel circuit (PC1) may have an isolated shape. The dummy connection electrode (1770') may be electrically connected to the fourth oxide semiconductor pattern (1540) through a contact hole (CNT').

[0254] The eighth connection electrode (1780) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The eighth connection electrode (1780) may be electrically connected to the sixth transistor (T6, FIG. 16). The eighth connection electrode (1780) may be electrically connected to the sixth semiconductor layer (A6) and the fourth semiconductor layer (A4) through a contact hole (CNT). The eighth connection electrode (1780) may be electrically connected to the first oxide semiconductor pattern (1510) through the contact hole (CNT'), and the connection point between the eighth connection electrode (1780) and the first oxide semiconductor pattern (1510) may be positioned between an area corresponding to the sixth semiconductor layer (A6) and an area corresponding to the fourth semiconductor layer (A4) among the first oxide semiconductor pattern (1510). The eighth connecting electrode (1780) can electrically connect the pixel electrode of the light-emitting diode (LED, Fig. 8), the fourth transistor (T4, Fig. 16), and the sixth transistor (T6, Fig. 16).

[0255] A first organic insulating layer (113, FIG. 10) may be formed on the structure described with reference to FIG. 17, and first via contact holes (VCNT1) may be formed. Thereafter, as illustrated in FIG. 18, a data line (DL), a data connection line (DVL), an initialization voltage line (VL), a reference voltage line (VRL), a ninth connection electrode (1810), and a tenth connection electrode (1820) may be formed.

[0256] Referring to FIG. 18, each of the data line (DL), the data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) may extend along a second direction (e.g., the y direction). The data line (DL), the data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the first pixel circuit (PC1) and the data line (DL), the data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the second pixel circuit (PC2) may be substantially symmetrical with respect to the imaginary line (IML).

[0257] The data line (DL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the sixth connection electrode (1760) described with reference to FIG. 17 through the first via contact hole (VCNT1), and can provide a data signal to the second transistor (T2, FIG. 16).

[0258] The data connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be electrically connected to pixel circuits arranged in different columns from the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0259] An initialization voltage line (VL) passing through the second pixel circuit (PC2) can be electrically connected to a seventh connection electrode (1770, Fig. 17) located in the second pixel circuit (PC2) through a first via contact hole (VCNT1) to provide an initialization voltage to a fourth transistor (T4, Fig. 16) of the second pixel circuit (PC2).

[0260] An initialization voltage line (VL) passing through the first pixel circuit (PC1) can be electrically connected to a dummy connection electrode (1770') described with reference to FIG. 17 through a first via contact hole (VCNT1). As described above with reference to FIG. 17, the fourth transistor (T4, FIG. 16) located in the first pixel circuit (PC1) can be electrically connected to an initialization voltage line (not shown) passing through an adjacent pixel circuit adjacent to the first pixel circuit (PC1).

[0261] A reference voltage line (VRL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the fifth connection electrode (1750) described with reference to FIG. 17 through the first via contact hole (VCNT1), and can provide a reference voltage to the third transistor (T3, FIG. 16).

[0262] The ninth connection electrode (1810) and the tenth connection electrode (1820) may each have an isolated shape. The ninth connection electrode (1810) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the first connection electrode (1710) described with reference to FIG. 17 through the first via contact hole (VCNT1). The first connection electrode (1710, FIG. 17) and the ninth connection electrode (1810) may electrically connect a voltage layer (1900) and a hold capacitor (Chd, FIG. 8) to be described later.

[0263] The tenth connection electrode (1820) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be electrically connected to the eighth connection electrode (1780) described with reference to FIG. 17 through the first via contact hole (VCNT1). The eighth connection electrode (1780) and the tenth connection electrode (1820) can electrically connect the pixel electrode of the light emitting diode (LED, FIG. 8) to the fourth transistor (T4, FIG. 16) and the sixth transistor (T6, FIG. 16).

[0264] A second organic insulating layer (115, FIG. 10) may be formed on the structure described with reference to FIG. 18, and second via contact holes (VCNT2) may be formed. FIG. 19 illustrates that the voltage layer (1900) and the eleventh connection electrode (1955) described with reference to FIG. 8 are formed on the second organic insulating layer (115, FIG. 10).

[0265] Referring to FIG. 19, the voltage layer (1900) may include main parts (1910) that are spaced apart from each other and bridge parts (1920, 1930) that connect the main parts (1910). The main parts (1910) and the bridge parts (1920, 1930) may be connected as one body, and the self-resistance of the voltage layer (1900) may be relatively reduced through the above-described structure. The connection structure of the main parts (1910) and the bridge parts (1920, 1930) may have a mesh shape on a plane. According to some embodiments, the voltage layer (1900) may include the driving voltage line (PL) described with reference to FIG. 8. In other words, the voltage layer (1900) may have the function of the driving voltage line (PL) described with reference to FIG. 8.

[0266] The main portion (1910) may overlap with a voltage line or a signal line therebelow. According to some embodiments, one of the main portions (1910) may be positioned on an imaginary line (IML) and may overlap with a data line (DL) and a data connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2). Another one of the main portions (1910) may overlap with a reference voltage line (VRL) passing through the first pixel circuit (PC1). Still another one of the main portions (1910) may overlap with a reference voltage line (VRL) passing through the second pixel circuit (PC2). The main portion (1910) may overlap with an emitting area (EA, FIG. 20) of a light emitting diode (LED, FIG. 20), which will be described later with reference to FIG. 20.

[0267] The bridge portions (1920, 1930) may extend along a first diagonal direction (OB1) and / or a second diagonal direction (OB2) intersecting a first direction (e.g., x-direction) and a second direction (e.g., y-direction). Each of the bridge portions (1920, 1930) may connect adjacent main portions (1910). According to some embodiments, the first bridge portion (1920) of the bridge portions (1920, 1930) may extend along the first diagonal direction (OB1) to integrally connect two adjacent main portions (1910). The second bridge portion (1930) of the bridge portions (1920, 1930) may extend along the second diagonal direction (OB2) to integrally connect two adjacent main portions (1910).

[0268] In some embodiments, the voltage layer (1900) may be electrically connected to a transistor or capacitor via a bridge portion (1920, 1930).

[0269] The third bridge portion (1930) passing through the first pixel circuit (PC1) can be electrically connected to the ninth connection electrode (1810, FIG. 18) located in the first pixel circuit (PC1) through the second via contact hole (VCNT2). The ninth connection electrode (1810, FIG. 18) can be electrically connected to the first connection electrode (1710, FIG. 17) located in the first pixel circuit (PC1). The first connection electrode (1710, FIG. 17) can be electrically connected to the second conductive layer (1320, FIG. 13) including the first lower hold electrode (CEh1a) of the hold capacitor (Chd), the third oxide semiconductor pattern (1530, FIG. 15) including the first upper hold electrode (CEh1b) of the hold capacitor (Chd), and the fifth semiconductor layer (A5) of the fifth transistor (T5, FIG. 12). Accordingly, the driving voltage of the voltage layer (1900) can be transmitted to the fifth transistor (T5) of the first pixel circuit (PC1) and the first hold electrode (CEh1) of the hold capacitor (Chd).

[0270] The second bridge portion (1920) passing through the second pixel circuit (PC2) can be electrically connected to the ninth connection electrode (1810, FIG. 18) located in the second pixel circuit (PC2) through the second via contact hole (VCNT2). The ninth connection electrode (1810) can be electrically connected to the first connection electrode (1710, FIG. 17) located in the second pixel circuit (PC2). The first connection electrode (1710, FIG. 17) can be electrically connected to the second conductive layer (1320) including the first lower hold electrode (CEh1a) of the hold capacitor (Chd), the third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b) of the hold capacitor (Chd), and the fifth semiconductor layer (A5) of the fifth transistor (T5). Accordingly, the driving voltage of the voltage layer (1900) can be transmitted to the fifth transistor (T5) of the second pixel circuit (PC2) and the first hold electrode (CEh1) of the hold capacitor (Chd).

[0271] The eleventh connection electrode (1955) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. Each of the eleventh connection electrodes (1955) may be electrically connected to the tenth connection electrode (1820, FIG. 18) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) through the second via contact hole (VCNT2).

[0272] A third organic insulating layer (117, FIG. 10) may be formed on the structure described with reference to FIG. 19, and third via contact holes (VCNT3) passing through the third organic insulating layer (117, FIG. 10) may be formed. Pixel electrodes (210, FIG. 20) of a light-emitting diode (LED, FIG. 20), which will be described later with reference to FIG. 20, may be arranged on the third organic insulating layer (117). Each pixel electrode (210, FIG. 20) may be electrically connected to an 11th connection electrode (1955) of a corresponding pixel circuit through the third via contact hole (VCNT3).

[0273] Although FIG. 19 illustrates that the main portion (1910) has a circular shape, the present disclosure is not limited thereto. According to some embodiments, the main portion (1910) may have an elliptical or polygonal shape (such as a square, pentagon, hexagon, or octagon).

[0274] FIG. 20 is a plan view showing light emitting diodes arranged on pixel circuits according to some embodiments, FIG. 21 is a cross-sectional view taken along line XXI-XXI' of FIG. 20 according to some embodiments, and FIG. 22 is a cross-sectional view taken along line XXI-XXI' of FIG. 20 according to some embodiments. According to some embodiments, as illustrated in FIG. 20, the pixel electrode (210) may overlap with the initialization voltage line (VL, FIG. 18), but for convenience of explanation, the initialization voltage line (VL, FIG. 18) is omitted in FIGS. 21 and 22, respectively.

[0275] Referring to Fig. 20, light emitting diodes (LEDs) may be arranged to be spaced apart from each other. Fig. 20 illustrates four light emitting diodes (LEDs) arranged around one light emitting diode (LED, hereinafter referred to as the first light emitting diode, LED1) electrically connected to a first pixel circuit (PC1). The first light emitting diode (LED1) may overlap the first pixel circuit (PC1) and the second pixel circuit (PC2). For example, the first light emitting diode (LED1) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0276] Among the four light emitting diodes (LEDs) arranged around the first light emitting diode (LED1), one light emitting diode (LED, hereinafter referred to as the second light emitting diode, LED2) can be electrically connected to the first pixel circuit (PC1). The pixel electrodes (210) of each of the first light emitting diode (LED1) and the second light emitting diode (LED2) can be electrically connected to the corresponding pixel circuit through the third via contact hole (VCNT3) described with reference to FIG. 19.

[0277] Referring to FIGS. 20 and 21, the light emitting diodes (LEDs) can overlap with the main portion (1910) of the corresponding voltage layer (1900), respectively. The light emitting area (EA) of each light emitting diode (LED) can overlap with the main portion (1910) of the voltage layer (1900).

[0278] The main portion (1910) of the voltage layer (1900) is disposed below the pixel electrode (210) and the main portion (1910) as illustrated in FIG. 21, and may be disposed between lines providing signals, such as data lines (DL) and data connection lines (DVL). The main portion (1910) can reduce or prevent the occurrence of parasitic capacitance between each of the data lines (DL) and / or data connection lines (DVL) and the pixel electrode (210), and can prevent deterioration of display quality due to parasitic capacitance.

[0279] In the embodiments described with reference to FIGS. 19 to 21, the voltage layer (1900) is described as a component corresponding to the driving voltage line (PL) described with reference to FIG. 8, and has a voltage level (e.g., constant voltage) of the driving voltage (ELVDD, FIG. 8), but the present disclosure is not limited thereto. According to some embodiments, the voltage layer (1900) between each of the data lines (DL) and / or the data connection lines (DVL) and the pixel electrode (210) may have a voltage level (e.g., constant voltage) equal to the common voltage (ELVSS, FIG. 8), and in this case, the configuration corresponding to the driving voltage line may be arranged in the same layer as the data line (DL, FIG. 18), etc.

[0280] According to some embodiments, the width (W1) of the main portion (1910) may be greater than the width of the light-emitting area (EA) of each light-emitting diode (LED), as illustrated in FIG. 21. The light-emitting area (EA) of the light-emitting diode (LED) may be defined by an opening (119OP) of the bank layer (119) overlapping with the pixel electrode (210). The opening (119OP) of the bank layer may overlap with the main portion (1910) and the data line (DL) and data connection line (DVL) disposed below the main portion (1910). In one embodiment, the width (W1) of the main portion (1910) may be greater than the width of the opening (119OP) of the bank layer (119) overlapping with the main portion (1910).

[0281] According to some embodiments, the width (W1) of the main portion (1910) may be smaller than the width of the light-emitting area (EA) of each light-emitting diode (LED), as illustrated in FIG. 22. In other words, the width (W1) of the main portion (1910) may be smaller than the width of the opening (119OP) of the bank layer (119) overlapping the pixel electrode (210).

[0282] According to the embodiments described with reference to FIG. 21, since the width (W1) of the main portion (1910) is larger than the width of the light-emitting area (EA), a portion of the pixel electrode (210) corresponding to the light-emitting area (EA) can be maintained in a relatively flat state. The upper surface of a portion of the pixel electrode (210) corresponding to the light-emitting area (EA) can be relatively flat.

[0283] According to the embodiments described with reference to FIG. 22, since the width (W1) of the main portion (1910) is smaller than the width of the light-emitting area (EA), the upper surface of the third organic insulating layer (117) disposed under a portion of the pixel electrode (210) corresponding to the light-emitting area (EA) may not be flat under the light-emitting area (EA). A first vertical distance (H1) from the substrate (100) to the pixel electrode (210) corresponding to the center of the light-emitting area (EA) may be greater than a second vertical distance (H2) from the substrate (100) to the pixel electrode (210) corresponding to the edge of the light-emitting area (EA). When having a structure as illustrated in FIG. 21, it is possible to sufficiently secure luminance in the front direction (e.g., z direction), and when having a structure as illustrated in FIG. 22, it is possible to increase luminance in the front direction (e.g., z direction) and an oblique direction.

[0284] FIG. 23 is a plan view showing an excerpt of the voltage layer (1900) of FIG. 19, and FIG. 24 is a plan view showing a voltage layer (1900) on the first and second pixel circuits (PC1, PC2) according to some embodiments.

[0285] Referring to FIG. 23, the main parts (1910) may be arranged to be spaced apart from each other. According to some embodiments, the main parts (1910) may be arranged at each of the four corners of a virtual square (VSQ) centered around one main part (1910). The sizes of the main parts (1910) may be different from each other. In this regard, FIG. 23 illustrates that the size (or width) of the main part (1910) located at the center of the virtual square (VSQ) is larger than the size (or width) of the main parts (1910) located at each corner, but the present disclosure is not limited thereto. According to some embodiments, the size (or width) of the main part (1910) located at the center of the virtual square (VSQ) may be smaller than the size (or width) of the main parts (1910) located at each corner.

[0286] In the embodiments described with reference to FIGS. 19 and 23, the first and second bridge portions (1920, 1930) connecting the main portions (1910) of the voltage layer (1900) extend along the first diagonal direction (OB1) and the second diagonal direction (OB2). Accordingly, the main portion (1910) located at the center of the virtual square (VSQ) can be directly connected to the main portions (1910) located at the four corners of the virtual square (VSQ).

[0287] According to some embodiments, as illustrated in FIG. 24, the first bridge portion (1920) and the second bridge portion (1930) may extend in a first direction (e.g., x-direction) and a second direction (e.g., y-direction), respectively. For example, among the main portions (1910) located at the four corners of the virtual square (VSQ), two main portions (1910) adjacent along the first direction (e.g., x-direction) may be connected to each other through the first bridge portion (1920) extending in the first direction (e.g., x-direction).

[0288] The main part (1910) located at the center of the virtual square (VSQ) can be connected to the four main parts (1910) described above through the second bridge part (1930) extending in the second direction (e.g., y direction). For example, the second bridge part (1930) extending in the second direction (e.g., +y direction) from the main part (1910) located at the center of the virtual square (VSQ) can be connected to the first bridge part (1920) connecting two main parts (1910) located at the corners of the virtual square (VSQ). In addition, the second bridge part (1930) extending in the second direction (e.g., -y direction) from the main part (1910) located at the center of the virtual square (VSQ) can be connected to the first bridge part (1920) connecting two main parts (1910) located at the corners of the virtual square (VSQ). That is, the main part (1910) located at the center of the virtual square (VSQ) can be connected to the main parts (1910) located at the four corners of the virtual square (VSQ) through the connection structure of the second bridge parts (1930) connected above and below and the second bridge parts (1930).

[0289] According to the above-described embodiments, the occurrence of parasitic capacitance between a line providing a data signal and a pixel electrode can be prevented or reduced through the shielding structure of the main portion of the voltage layer (1900). According to the above-described embodiments, the switching performance can be relatively improved because the switching transistors have a dual gate structure located below and above the semiconductor layer. According to the above-described embodiments, oxide transistors can be included. Through the above-described features, the embodiments can provide a display panel and electronic device that are capable of high-speed driving or response speed and provide high-quality images.

[0290] While the present invention has been described above with reference to one embodiment illustrated in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and variations of the embodiments are possible. Therefore, the true scope of technical protection of the present invention should be determined by the technical spirit of the appended claims.

Claims

1. A first pixel circuit and a second pixel circuit, each of which is arranged on a substrate and includes a driving transistor and a storage capacitor, and is adjacent along a first direction; Data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit; A first insulating layer disposed on the above data lines; A voltage layer disposed on the first insulating layer; A second insulating layer disposed on the voltage layer; and A light emitting diode including a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light emitting layer between the pixel electrode and the counter electrode, The above voltage layer is, Multiple, mutually separated main parts; and Includes bridge parts connecting the above multiple main parts, The above main parts include a first main part interposed between the data lines and the pixel electrode and overlapping the data lines and the pixel electrode. Display panel.

2. In paragraph 1, A display panel in which a data line electrically connected to the first pixel circuit and a data line electrically connected to the second pixel circuit are arranged symmetrically with respect to a virtual line between the first pixel circuit and the second pixel circuit as the center.

3. In paragraph 2, The first pixel circuit and the second pixel circuit transmit data signals to other pixel circuits, and further include data connection lines passing through the first pixel circuit and the second pixel circuit, respectively. The first main part above is a display panel that overlaps with the data connection lines.

4. In paragraph 3, A display panel in which the data connection line passing through the first pixel circuit and the data connection line passing through the second pixel circuit are arranged symmetrically with the virtual line as the center.

5. In paragraph 1, Each of the first pixel circuit and the second pixel circuit further includes a switching transistor electrically connected to the driving transistor and the voltage layer, The semiconductor layer of each of the driving transistors of the first pixel circuit and the second pixel circuit includes a different material from the semiconductor layer of the switching transistor, The semiconductor layer of the driving transistor includes an oxide semiconductor material, A display panel, wherein the semiconductor layer of the switching transistor comprises polysilicon.

6. In paragraph 5, A hold capacitor electrically connected to the driving transistor and the voltage layer; A conductive layer disposed under the semiconductor layer of the driving transistor; and Further comprising an insulating layer interposed between the conductive layer and the switching transistor, A display panel, wherein the hold capacitor includes a first hold electrode electrically connected to the voltage layer and a second hold electrode overlapping the first hold electrode.

7. In paragraph 6, The above storage capacitor includes a first storage electrode and a second storage electrode that overlap each other, A display panel, wherein the conductive layer includes the second storage electrode and the second hold electrode.

8. In paragraph 6, The above first holding electrode is, A first lower hold electrode disposed under the conductive layer with the insulating layer interposed therebetween; and A display panel comprising a first upper hold electrode positioned opposite the first lower hold electrode with the conductive layer interposed therebetween.

9. In paragraph 5, Each of the first pixel circuit and the second pixel circuit, A connection electrode electrically connecting the semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor; A first conductive layer under the semiconductor layer of the driving transistor; and Further comprising a second conductive layer between the first conductive layer and the semiconductor layer of the driving transistor, A display panel, wherein the connection point of the semiconductor layer of the above-mentioned connecting electrode and the above-mentioned driving transistor overlaps with the first conductive layer and the second conductive layer.

10. In paragraph 9, The storage capacitors of each of the first pixel circuit and the second pixel circuit include a first storage electrode and a second storage electrode that overlap each other, A display panel, wherein the first conductive layer includes the first storage electrode, and the second conductive layer includes the second storage electrode.

11. In paragraph 1, Further comprising a bank layer disposed on the pixel electrode and including an opening overlapping the pixel electrode, The opening defined in the above bank layer overlaps the first main portion, the display panel.

12. In paragraph 1, The above main parts include a second main part, a third main part, a fourth main part, and a fifth main part arranged around the first main part, On a plane, the second main part, the third main part, the fourth main part, and the fifth main part are each positioned at the corners of an imaginary square centered on the first main part. The second main part and the third main part are arranged along the first direction, The above fourth main part is spaced apart from the second main part along the second direction, A display panel in which the fifth main portion is spaced apart from the third main portion along the second direction.

13. In paragraph 1, The above light-emitting diode is electrically connected to the first pixel circuit, A display panel, wherein the pixel electrode of the light-emitting diode overlaps with a virtual line between the first pixel circuit and the second pixel circuit.

14. In paragraph 1, A display panel, wherein the voltage layer has the same voltage level as the voltage applied to the counter electrode of the light-emitting diode.

15. Display panel; and A lower cover forming an exterior and having an opening exposing a portion of the display panel on the front surface, The above display panel, A first pixel circuit and a second pixel circuit, each of which is disposed on a substrate and includes a driving transistor and a storage capacitor, and is adjacent along a first direction; Data lines extending in a second direction intersecting the first direction and electrically connected to each of the first pixel circuit and the second pixel circuit; A first insulating layer disposed on the above data lines; A voltage layer disposed on the above insulating layer; A second insulating layer disposed on the voltage layer; and A light emitting diode including a pixel electrode disposed on the second insulating layer, a counter electrode on the pixel electrode, and a light emitting layer between the pixel electrode and the counter electrode, The above voltage layer is, Multiple, mutually separated main parts; and Includes bridge parts connecting the above multiple main parts, The above main parts include a first main part interposed between the data lines and the pixel electrode and overlapping the data lines and the pixel electrode. Electronic devices.

16. In paragraph 15, An electronic device in which a data line electrically connected to the first pixel circuit and a data line electrically connected to the second pixel circuit are arranged symmetrically with respect to a virtual line between the first pixel circuit and the second pixel circuit as the center.

17. In paragraph 16, The display panel further includes data connection lines that transmit data signals to the first pixel circuit and the second pixel circuit and other pixel circuits, and pass through the first pixel circuit and the second pixel circuit, respectively. The data connection line passing through the first pixel circuit and the data connection line passing through the second pixel circuit are arranged symmetrically with the virtual line as the center, An electronic device wherein the first main portion overlaps with the data connection lines.

18. In paragraph 17, The display panel further includes a bank layer disposed on the pixel electrode and including an opening overlapping the pixel electrode, An electronic device wherein the opening defined in the above bank layer overlaps the first main portion.

19. In paragraph 15, Each of the first pixel circuit and the second pixel circuit, A switching transistor electrically connected to the driving transistor and the voltage layer; A connecting electrode electrically connecting the semiconductor layer of the driving transistor and the semiconductor layer of the switching transistor; A first conductive layer under the semiconductor layer of the driving transistor; and Further comprising a second conductive layer between the first conductive layer and the semiconductor layer of the driving transistor, The semiconductor layer of each of the driving transistors of the first pixel circuit and the second pixel circuit includes a different material from the semiconductor layer of the switching transistor, An electronic device, wherein the connection point of the above-mentioned connecting electrode and the semiconductor layer of the above-mentioned driving transistor overlaps the first conductive layer and the second conductive layer.

20. In paragraph 19, The storage capacitors of each of the first pixel circuit and the second pixel circuit include a first storage electrode and a second storage electrode that overlap each other, An electronic device, wherein the first conductive layer includes the first storage electrode, and the second conductive layer includes the second storage electrode.

Images