Display panel and electronic device comprising same

Abstract

One embodiment of the present invention provides a display panel comprising: a substrate; a pixel circuit layer disposed on the substrate and including a first pixel circuit; and a light-emitting diode electrically connected to the first pixel circuit, wherein the pixel circuit layer includes: a first conductive layer including a first conductive pattern disposed on the substrate; a second conductive layer including a second conductive pattern disposed on the first conductive layer and partially overlapping the first conductive pattern; and a first semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the second conductive pattern, wherein the first semiconductor pattern is conductive.

Description

Display panel and electronic device including same

[0001] The present invention relates to a display panel and an electronic device including the same.

[0002] In recent years, display devices have become increasingly versatile. Furthermore, as their applications expand, the demand for high-resolution displays is increasing. Manufacturing high-resolution displays requires arranging electronic components of various configurations within a narrow area.

[0003] This technical background section should be understood to include some background information useful for understanding the technology in question. However, this technical background section may contain ideas, concepts, or insights that were unknown or unrecognized by those skilled in the relevant technical field prior to the corresponding effective filing date disclosed herein.

[0004] The technical challenges to be achieved by this specification are not limited to those described herein, and other technical challenges not described herein will be readily apparent to those skilled in the art from this specification. Embodiments of the present invention aim to provide a display panel with improved display quality and an electronic device including the same. However, these challenges are exemplary and do not limit the scope of the present invention.

[0005] One embodiment of the present invention provides a display panel including: a substrate; a pixel circuit layer disposed on the substrate and including a first pixel circuit; and a light emitting diode electrically connected to the first pixel circuit; wherein the pixel circuit layer includes: a first conductive layer including a first conductive pattern disposed on the substrate; a second conductive layer including a second conductive pattern disposed on the first conductive layer and partially overlapping the first conductive pattern; and a first semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the second conductive pattern; wherein the first semiconductor pattern is conductive.

[0006] In one embodiment, the first semiconductor layer may include an oxide semiconductor material.

[0007] In one embodiment, a constant voltage can be applied to the first conductive pattern and the first semiconductor pattern.

[0008] In one embodiment, the first pixel circuit may include: a first transistor connected between a driving voltage line and the light-emitting diode; a storage capacitor connected between a first node to which a gate electrode of the first transistor is connected and a second node to which a first electrode of the first transistor is connected; and a hold capacitor connected to the second node.

[0009] In one embodiment, the first semiconductor layer further includes a second semiconductor pattern disposed on the same layer as the first semiconductor pattern and including a channel region of the first transistor, and the first semiconductor pattern and the second semiconductor pattern may be disposed to be spaced apart from each other.

[0010] In one embodiment, the hold capacitor includes a first sub-hold capacitor and a second sub-hold capacitor that are formed to overlap each other, and the first sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the first conductive pattern, and the second sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the first semiconductor pattern.

[0011] In one embodiment, the hold capacitor may be connected between the second node and the driving voltage line.

[0012] In one embodiment, the first conductive pattern and the first semiconductor pattern are electrically connected to the driving voltage line and can receive the same driving voltage.

[0013] In one embodiment, the first pixel circuit may further include a second transistor connected between a data line and the first node; and a third transistor connected between a reference voltage line and the first node.

[0014] In one embodiment, the hold capacitor is connected between the second node and the driving voltage line, and the first pixel circuit further includes an auxiliary hold capacitor connected between the lower gate electrode of the first transistor and the reference voltage line; the auxiliary hold capacitor includes a third sub-hold capacitor and a fourth sub-hold capacitor that are formed to overlap each other, the first conductive layer further includes a third conductive pattern that is spaced apart from the first conductive pattern, the first semiconductor layer further includes a third semiconductor pattern that is spaced apart from the first semiconductor pattern and is conductive, the third sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the third conductive pattern, and the fourth sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the third semiconductor pattern.

[0015] In one embodiment, the first conductive layer further includes a fourth conductive pattern disposed on the same layer as the first conductive pattern but spaced apart from the first conductive pattern, and the second conductive pattern may be extended to partially overlap the fourth conductive pattern.

[0016] In one embodiment, the storage capacitor includes a first sub-storage capacitor and a second sub-storage capacitor, the first sub-storage capacitor is formed by overlapping a portion of the second conductive pattern with the fourth conductive pattern, the second sub-storage capacitor is formed by overlapping a portion of the second conductive pattern with the first semiconductor pattern, and the first semiconductor pattern can be electrically connected to an electrode corresponding to the first node.

[0017] In one embodiment, the first pixel circuit further includes a fourth transistor connected between the driving voltage line and the first transistor; the pixel circuit layer further includes a second semiconductor layer including a channel region of the fourth transistor; the second semiconductor layer is disposed between the substrate and the first conductive layer, and the second semiconductor layer may include a silicon semiconductor material.

[0018] Another embodiment of the present invention provides an electronic device comprising: a display panel; and a lower cover forming an exterior and having an opening exposing a portion of the display panel on a front surface, wherein the display panel comprises: a substrate; a pixel circuit layer disposed on the substrate and including a first pixel circuit; and a light emitting diode electrically connected to the first pixel circuit; wherein the pixel circuit layer comprises: a first conductive layer including a first conductive pattern disposed on the substrate; a second conductive layer disposed on the first conductive layer and including a second conductive pattern partially overlapping the first conductive pattern; and a first semiconductor layer disposed on the second conductive layer and including a first semiconductor pattern overlapping the second conductive pattern; wherein the first semiconductor pattern is conductive.

[0019] In one embodiment, the first semiconductor layer may include an oxide semiconductor material.

[0020] In one embodiment, a constant voltage can be applied to the first conductive pattern and the first semiconductor pattern.

[0021] In one embodiment, the first pixel circuit may include: a first transistor connected between a driving voltage line and the light-emitting diode; a storage capacitor connected between a first node to which a gate electrode of the first transistor is connected and a second node to which a first electrode of the first transistor is connected; and a hold capacitor connected to the second node.

[0022] In one embodiment, the hold capacitor may include a first sub-hold capacitor and a second sub-hold capacitor that are formed to overlap each other, wherein the first sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the first conductive pattern, and the second sub-hold capacitor may be formed by overlapping a portion of the second conductive pattern with the first semiconductor pattern.

[0023] In one embodiment, the hold capacitor may be connected between the second node and the driving voltage line.

[0024] In one embodiment, the first conductive pattern and the first semiconductor pattern are electrically connected to the driving voltage line and can receive the same driving voltage.

[0025] According to some embodiments of the present invention, a display panel and electronic device capable of high-speed operation or response speed and providing high-quality images can be provided. The aforementioned effects are exemplary, and the effects of the present invention are not limited to those described above.

[0026] FIG. 1 is a schematic perspective view showing an electronic device according to one embodiment of the present invention.

[0027] Figure 2 is a schematic exploded perspective view showing an electronic device according to one embodiment of the present invention.

[0028] FIG. 3 is a block diagram showing an electronic device according to one embodiment of the present invention.

[0029] FIG. 4 is a plan view schematically illustrating a display panel according to one embodiment of the present invention.

[0030] FIG. 5 is a side view schematically illustrating a display panel according to one embodiment of the present invention.

[0031] Figure 6 is a plan view schematically showing a display panel according to one embodiment of the present invention.

[0032] FIGS. 7A and 7B are schematic plan views each showing an enlarged portion of part VII of FIG. 6 as a part of a display panel according to one embodiment of the present invention.

[0033] Figure 8 is a schematic equivalent circuit diagram of a light-emitting diode and pixel circuit of a display panel according to one embodiment of the present invention.

[0034] FIG. 9 is a plan view schematically showing pixel circuits of a display panel according to one embodiment of the present invention.

[0035] FIGS. 10 to 18 are schematic plan views illustrating a process for forming a pixel circuit of a display panel according to one embodiment of the present invention.

[0036] FIG. 19 is a schematic plan view of a portion of a display panel according to one embodiment of the present invention, which is an enlarged view of portion B of FIG. 9.

[0037] FIG. 20 is a cross-sectional view of a display panel according to one embodiment of the present invention, showing a schematic cross-section along line I-I' of FIG. 19.

[0038] FIG. 21 is a schematic equivalent circuit diagram of a light-emitting diode and pixel circuit of a display panel according to another embodiment of the present invention.

[0039] FIG. 22 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention.

[0040] FIG. 23 is a schematic equivalent circuit diagram of a light-emitting diode and pixel circuit of a display panel according to another embodiment of the present invention.

[0041] FIG. 24 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention.

[0042] FIG. 25 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention.

[0043] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. However, the present invention may be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to fully and completely describe the present invention and fully convey the scope of the invention to those skilled in the art.

[0044] The size, thickness, proportions, and dimensions of elements in the drawings may be exaggerated for clarity and ease of explanation. Identical numbers and / or reference symbols represent identical elements throughout the drawings.

[0045] As used herein, the singular forms "a", "an" and "the" are to be construed to include the plural forms, unless the context clearly indicates otherwise.

[0046] The term "and / or" as used in the specification and claims should be interpreted to include all combinations of "and" and "or." For example, "A and / or B" can be interpreted as "A, B, or A and B." The terms "and" and "or" can be used in either a conjunctive or disjunctive sense and can be interpreted equivalently to "and / or."

[0047] The phrase "at least one of" as used in the specification and claims should be interpreted and understood to mean "at least one selected from the group consisting of." For example, "at least one of A and B" could be interpreted as "A, B, or A and B." As another example, the phrase "at least one of A, B, or C" could be interpreted as "A, B, C, A and B, A and C, B and C, A and B and C," or variations thereof.

[0048] The present invention is capable of various modifications and embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, as well as the methods for achieving them, will become clearer with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be implemented in various forms.

[0049] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. When describing with reference to the drawings, identical or corresponding components are given the same drawing reference numerals, and redundant descriptions thereof will be omitted.

[0050] Although terms such as first, second, etc. may be used herein to describe various elements, these terms should not be construed as limiting the elements. These terms are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, even if a second element is referred to as a first element, this does not depart from the scope of this disclosure. As illustrated in the drawings, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used for convenience in describing the relationship between one element or member and another. These spatially relative terms should be understood to encompass various directions in which the device is used or operated, not just the directions depicted in the drawings. For example, if a device illustrated in the drawings is flipped over, a device positioned "below" or "beneath" another device may be positioned "above" the other device. Therefore, the descriptive term "below" can encompass not only the lower position but also the upper position. The devices may also be placed in different orientations, and thus spatial relative terms may be interpreted differently depending on the placement direction.

[0051] The term “overlap” or “overlapped” means that the first object can be on top of, below, or to the side of the second object, and vice versa. The term “overlap” may also include laminated, stacked, abutting, facing, extending upward, covering, partially covering, or other appropriate expressions, as would be understood by one of ordinary skill in the art.

[0052] The terms "face" and "facing" imply that a first element directly or indirectly faces a second element. Even if a third element intervenes between the first and second elements, the first and second elements can still be understood as indirectly facing each other, as if they were facing each other.

[0053] As used herein, the words "comprises," "comprising," "includes," "including," "has," "have," "having" and variations thereof specify the presence of described features, components, steps, operations, elements, members and / or groups thereof, but do not preclude the presence or addition of one or more other features, components, steps, operations, elements, members and / or groups thereof.

[0054] The expression “in a schematic plan view” means looking down on an object from above, and the expression “in a schematic cross-sectional view” means looking down on a cross-section vertically cut through the object from the side. Therefore, the expression “in a schematic plan view” as used herein may mean looking down on an object from above in the third direction, the “z” direction. In addition, the expression “in a schematic cross-sectional view” means looking down on an object from the side in a cross-section vertically cut through the object in the first direction “x” or the second direction “y”. The third direction “z” may also be referred to as a “thickness direction.”

[0055] The terms "about" or "approximately" as used herein mean that the stated value is within an acceptable range of deviation that can be determined by a person skilled in the art based on the stated value. This is determined by considering the measurement object and the error inherent in the measurement (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, 20%, 10%, or 5% of the stated value.

[0056] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted in a way consistent with their commonly understood meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined so herein.

[0057] Embodiments may be described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will appreciate that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits, such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc., which may be formed through semiconductor-based manufacturing techniques or other manufacturing processes.

[0058] When blocks, units and / or modules are implemented by microprocessors or similar hardware, they may be programmed and controlled to perform various functions using software (e.g., microcode), and optionally may be driven by firmware and / or software.

[0059] Additionally, it is contemplated that each block, unit and / or module may be implemented by dedicated hardware, or may be implemented in combination in such a way that some functions are performed by dedicated hardware, and other functions are performed by a processor (e.g., one or more programmed microprocessors and associated circuitry).

[0060] Each block, unit and / or module of the embodiment may be physically separated into two or more interacting individual blocks, units and / or modules without departing from the scope of this disclosure.

[0061] Additionally, the blocks, units and / or modules of the embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0062] In the examples below, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0063] In the examples below, terms such as “include” or “have” mean that a feature or component described in the specification is present, and do not preclude the possibility that one or more other features or components may be added.

[0064] In the following examples, when a part such as a film, region, component, etc. is said to be on or above another part, it includes not only a case where it is directly on top of the other part, but also a case where another film, region, component, etc. is interposed in between.

[0065] For convenience of explanation, the sizes of components in the drawings may be exaggerated or reduced. For example, the sizes and thicknesses of each component shown in the drawings are arbitrarily indicated for convenience of explanation, and thus the present invention is not necessarily limited to what is shown.

[0066] In some embodiments, where implementations are otherwise feasible, specific process sequences may be performed in a different order than described. For example, two processes described in succession may be performed substantially simultaneously, or in a reverse order from the described order.

[0067] When a specification refers to an element (or region, layer, portion, etc.) as being "on," "disposed on," "connected to," or "coupled to" another element, this means that the element may be directly disposed, connected, or coupled to the other element, or that there may be intervening elements therebetween. Furthermore, the terms "connected to" or "coupled to" can include physical or electrical connections or couplings. Furthermore, when an element is referred to as being "in contact with" or "contacted with" another element, the element can be in "electrical contact," "physical contact," "indirect contact," or "direct contact" with the other element.

[0068] FIG. 1 is a schematic perspective view showing an electronic device (1) according to one embodiment of the present invention, FIG. 2 is a schematic exploded perspective view showing an electronic device (1) according to one embodiment of the present invention, and FIG. 3 is a block diagram showing an electronic device (1) according to one embodiment of the present invention.

[0069] Referring to FIGS. 1 and 2, an electronic device (1) according to one embodiment is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc. The electronic device (1) according to one embodiment can be used in a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD). An electronic device (1) according to one embodiment can be used as a dashboard of a vehicle, a CID (Center Information Display) placed on a center fascia or dashboard of a vehicle, a room mirror display replacing a side mirror of a vehicle, and a display placed on the back of a front seat as entertainment for the rear seat of a vehicle.

[0070] For convenience of explanation, FIGS. 1 and 2 illustrate an electronic device (1) according to one embodiment being used as a smart phone. The electronic device (1) according to one embodiment may include a cover window (70), a display panel (10), a data driver (20), a display circuit board (30), a component (40), a bracket (60), a main circuit board (50), a battery (80), and a lower cover (90).

[0071] In the schematic plan views of the present specification and drawings, “left,” “right,” “upper,” and “lower” indicate directions when looking at the display panel (10) from a direction perpendicular to the display panel (10). For example, “left” indicates a negative first direction (e.g., the -x direction), “right” indicates a positive first direction (e.g., the +x direction), “upper” indicates a positive second direction (e.g., the +y direction), and “lower” indicates a negative second direction (e.g., the -y direction).

[0072] The electronic device (1) may be formed in a rectangular shape on a plane. For example, the electronic device (1) may have a rectangular shape on a plane having a short side in a first direction (e.g., x direction) and a long side in a second direction (e.g., y direction), as shown in FIG. 1. An edge where the short side in the first direction (e.g., x direction) and the long side in the second direction (e.g., y direction) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the electronic device (1) is not limited to a rectangle, and may be formed in another polygonal, oval, or irregular shape.

[0073] The cover window (70) can be placed on the upper part of the display panel (10) to cover the upper surface of the display panel (10). As a result, the cover window (70) can function to protect the upper surface of the display panel (10).

[0074] The cover window (70) may include a transparent cover portion (DA70) corresponding to the display panel (10) and a light-blocking cover portion (NDA70) surrounding the transparent cover portion (DA70). The light-blocking cover portion (NDA70) may include an opaque material (e.g., a colored opaque material) that blocks light. The light-blocking cover portion (NDA70) may include a pattern that can be shown to a user when an image is not displayed.

[0075] The display panel (10) can be placed at the bottom of the cover window (70). The display panel (10) can overlap with the transparent cover portion (DA70) of the cover window (70).

[0076] The display panel (10) includes a display area (DA). The display area (DA) is an area where an image is displayed, and the display area (DA) may include an area (hereinafter, referred to as a component area) that transmits light emitted from a component (40) positioned at the bottom of the display panel (10). The component may include a sensor or camera that utilizes visible light, infrared rays, or sound.

[0077] The display panel (10) may be a light-emitting display panel including a light-emitting diode. The light-emitting diode may include an organic light-emitting diode including an organic light-emitting layer. In some embodiments, the light-emitting diode may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including inorganic semiconductor-based materials. When a voltage is applied in the forward direction to the PN junction diode, holes and electrons are injected, and energy generated by the recombination of the holes and electrons is converted into light energy to emit light of a predetermined color. The above-described inorganic light-emitting diode may have a width of several to several hundred micrometers, and in some embodiments, the inorganic light-emitting diode may be referred to as a micro LED.

[0078] The display panel (10) may be a rigid display panel that is rigid and does not bend easily, or a flexible display panel that is flexible and can be easily bent, folded, or rolled. For example, the display panel (10) may be a foldable display panel that can be folded and unfolded, a curved display panel with a curved display surface, a bent display panel with an area other than the display surface that is bent, a rollable display panel that can be rolled and unfolded, and a stretchable display panel that can be stretched.

[0079] The display panel (10) may be a transparent display panel that is implemented transparently so that an object or background placed on the lower surface of the display panel (10) can be viewed from the upper surface of the display panel (10). Alternatively, the display panel (10) may be a reflective display panel that can reflect an object or background on the upper surface of the display panel (10).

[0080] The data driver (20) may be placed on the display panel (10) in the form of an integrated circuit (IC). As another embodiment, the data driver (20) may be placed on a display circuit board (30).

[0081] A display circuit board (30) can be attached to one side of the display panel (10). The display circuit board (30) can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that is hard and does not bend easily, or a composite printed circuit board including both a rigid printed circuit board and a flexible printed circuit board.

[0082] In one embodiment, a touch sensor driver may be disposed on a display circuit board (30). The touch sensor driver may be formed as an integrated circuit. The touch sensor driver may be attached to the display circuit board (30). The touch sensor driver may be electrically connected to touch electrodes of a touch screen layer of a display panel (10) via the display circuit board (30).

[0083] The touch screen layer of the display panel (10) can detect a user's touch input using at least one of various touch methods such as a resistive film method and an electrostatic capacitance method. For example, when the touch screen layer of the display panel (10) detects a user's touch input using an electrostatic capacitance method, the touch sensor driver can determine whether a user's touch has occurred by applying drive signals to the drive electrodes among the touch electrodes and detecting voltages charged in the mutual capacitance (hereinafter referred to as "mutual capacitance") between the drive electrodes and the sense electrodes through the sense electrodes among the touch electrodes. The user's touch may include a contact touch and a proximity touch. A contact touch refers to a case where an object such as a user's finger or a pen directly contacts a cover window (70) disposed on the touch screen layer. A proximity touch refers to a case where an object such as a user's finger or a pen is positioned close to the cover window (70), such as hovering. The touch sensor driving unit transmits sensor data to the main processor (510) according to the detected voltages, and the main processor (510) can calculate the touch coordinates where the touch input occurred by analyzing the sensor data.

[0084] A control unit for supplying driving voltages for driving pixels, a gate driver, and a data driver (20) of the display panel (10) may be placed on the display circuit board (30).

[0085] A bracket (60) for supporting the display panel (10) may be arranged at the bottom of the display panel (10). The bracket (60) may include plastic, metal, or both plastic and metal. A first camera hole (CMH1) into which a camera device (531) is inserted, a battery hole (BH) into which a battery (80) is arranged, and a cable hole (CAH) through which a cable connected to the display circuit board (30) passes may be formed in the bracket (60). A component hole (CPH) overlapping the display panel (10) may be provided in the bracket (60). The component hole (CPH) may overlap with components (40) of the main circuit board (50) in a third direction (z direction). In one embodiment, the display area (DA) of the display panel (10) may overlap with components (40) of the main circuit board (50) in the third direction (z direction). In another embodiment, the bracket (60) may not have a component hole (CPH) formed therein.

[0086] In one embodiment, the component (40) may include first to fourth components (41, 42, 43, 44) that overlap and face each other in a third direction (e.g., z-direction) on the display panel (10). The first to fourth components (41, 42, 43, 44) may each be provided with a proximity sensor, a light sensor, an iris sensor, a face recognition sensor, and a camera (or image sensor) or a combination thereof. The proximity sensor using infrared rays can detect an object placed close to the upper surface of the electronic device (1), and the light sensor can detect the brightness of light incident on the upper surface of the electronic device (1). In addition, the iris sensor can photograph the iris of a person placed on the upper surface of the electronic device (1), and the camera can photograph an object placed on the upper surface of the electronic device (1). The component (40) is not limited to a proximity sensor, a light sensor, an iris sensor, a facial recognition sensor, and a camera, and various sensors described later may be arranged.

[0087] A main circuit board (50) and a battery (80) may be placed at the bottom of the bracket (60). The main circuit board (50) may be a printed circuit board or a flexible printed circuit board.

[0088] The main circuit board (50) may include a main processor (510), a camera device (531), a main connector (55), and a component (40), or a combination thereof. The main processor (510) may be formed as an integrated circuit. The camera device (531) may be disposed on both the upper and lower surfaces of the main circuit board (50), and each of the main processor (510) and the main connector (55) may be disposed on either the upper or lower surface of the main circuit board (50).

[0089] The main processor (510) can control all functions of the electronic device (1). For example, the main processor (510) can output digital video data to the data driver (20) through the display circuit board (30) so that the display panel (10) can display an image. The main processor (510) can receive detection data from the touch sensor driver. The main processor (510) can determine whether a user touches the screen based on the detection data and execute an operation corresponding to the user's direct touch or proximity touch. The main processor (510) can be an application processor, a central processing unit, or a system chip formed of an integrated circuit.

[0090] The camera device (531) processes image frames, such as still images or moving images, obtained by the image sensor in camera mode and outputs them to the main processor (510). The camera device (531) may include at least one of a camera sensor (e.g., CCD, CMOS, etc.), a photo sensor (or image sensor), and a laser sensor, or a combination thereof. The camera device (531) may be connected to an image sensor among components (40) overlapping the display area (DA) and may process images input to the image sensor.

[0091] A cable (35) passing through a cable hole (CAH) of a bracket (60) can be connected to the main connector (55), and thus the main circuit board (50) can be electrically connected to the display circuit board (30).

[0092] In addition to the main processor (510), camera device (531), and main connector (55), the main circuit board (50) may further include a wireless communication unit (520), an input unit (530), a sensor unit (540), an output unit (550), an interface unit (560), a memory (570), and / or a power supply unit (580) as shown in FIG. 3.

[0093] The wireless communication unit (520) may include at least one of a broadcast reception module (521), a mobile communication module (522), a wireless Internet module (523), a short-range communication module (524), and a location information module (525), or a combination thereof.

[0094] The broadcast reception module (521) receives broadcast signals and / or broadcast-related information from an external broadcast management server via a broadcast channel. The broadcast channel may include a satellite channel or a terrestrial channel.

[0095] The mobile communication module (522) transmits and receives wireless signals with at least one of a base station, an external terminal, and a server on a mobile communication network constructed according to technical standards or communication methods for mobile communication (e.g., GSM (Global System for Mobile communication), CDMA (Code Division Multi Access), CDMA2000 (Code Division Multi Access 2000), EV-DO (Enhanced Voice-Data Optimized or Enhanced Voice-Data Only), WCDMA (Wideband CDMA), HSDPA (High Speed ​​Downlink Packet Access), HSUPA (High Speed ​​Uplink Packet Access), LTE (Long Term Evolution), LTE-A (Long Term Evolution-Advanced), etc.). The wireless signal may include various types of data according to voice call signals, video call call signals, or text / multimedia message transmission and reception.

[0096] The wireless Internet module (523) refers to a module for wireless Internet access. The wireless Internet module (523) can be configured to transmit and receive wireless signals in a communication network according to wireless Internet technologies. Wireless Internet technologies include, for example, WLAN (Wireless LAN), Wi-Fi (Wireless-Fidelity), Wi-Fi (Wireless Fidelity) Direct, and DLNA (Digital Living Network Alliance).

[0097] The short-range communication module (524) is for short-range communication, and can support short-range communication using at least one of Bluetooth, RFID (Radio Frequency Identification), Infrared Data Association (IrDA), UWB (Ultra Wideband), ZigBee, NFC (Near Field Communication), Wi-Fi (Wireless-Fidelity), Wi-Fi Direct, and Wireless USB (Wireless Universal Serial Bus) technologies. The short-range communication module (524) can support wireless communication between an electronic device (1) and a wireless communication system, between an electronic device (1) and another electronic device, or between an electronic device (1) and a network where another electronic device (or an external server) is located through a short-range wireless communication network (Wireless Area Network). The short-range wireless communication network may be a short-range wireless personal area network (Wireless Personal Area Network). The other electronic device may be a wearable device capable of exchanging (or linking) data with the electronic device (1).

[0098] The location information module (525) is a module for obtaining the location (or current location) of the electronic device (1), and may include a GPS (Global Positioning System) module or a WiFi (Wireless Fidelity) module.

[0099] The input unit (530) may include a video input unit such as a camera device (531) for inputting a video signal, an audio input unit such as a microphone (532) for inputting an audio signal, an input device (533) for receiving information from a user, or a combination thereof.

[0100] The camera device (531) processes image frames, such as still images or moving images, obtained by an image sensor in video call mode or shooting mode. The processed image frames can be displayed on a display panel (10) or stored in a memory (570).

[0101] A microphone (532) processes external acoustic signals into electrical voice data. The processed voice data can be utilized in various ways depending on the function being performed (or the application being executed) by the electronic device (1).

[0102] The main processor (510) can control the operation of the electronic device (1) to correspond to information input through the input device (533). The input device (533) can include a mechanical input means or a touch input means, such as a button, a dome switch, a jog wheel, a jog switch, etc., located on the rear or side of the electronic device (1). The touch input means can be formed of a touch screen layer of the display panel (10).

[0103] The sensor unit (540) may include one or more sensors that sense at least one of information within the electronic device (1), information about the surrounding environment surrounding the electronic device (1), and user information, and generate a sensing signal corresponding thereto. Based on these sensing signals, the main processor (510) may control the operation or behavior of the electronic device (1), or perform data processing, functions, or operations related to an application installed in the electronic device (1). The sensor unit (540) may include at least one of a proximity sensor, an illumination sensor, an acceleration sensor, a magnetic sensor, a G-sensor, a gyroscope sensor, a motion sensor, an RGB sensor, an infrared sensor (IR sensor), a fingerprint recognition sensor, an ultrasonic sensor, an optical sensor, a battery gauge, an environmental sensor (e.g., a barometer, a hygrometer, a thermometer, a radiation detection sensor, a heat detection sensor, a gas detection sensor, etc.), a chemical sensor (e.g., an electronic nose, a healthcare sensor, a biometric recognition sensor, etc.), or a combination thereof.

[0104] The output unit (550) is for generating output related to visual, auditory, or tactile sensations, and may include at least one of a display panel (10), an audio output unit (551), a haptic module (552), and an optical output unit (553).

[0105] The display panel (10) displays (outputs) information processed in the electronic device (1). For example, the display panel (10) may display execution screen information of an application running in the electronic device (1), or UI (User Interface) or GUI (Graphical User Interface) information according to the execution screen information. The display panel (10) may include a display layer that displays an image and a touch screen layer that detects a user's touch input. Accordingly, the display panel (10) may function as one of the input devices (533) that provides an input interface between the electronic device (1) and the user, and at the same time, function as one of the output units (550) that provides an output interface between the electronic device (1) and the user.

[0106] The audio output unit (551) can output audio data received from the wireless communication unit (520) or stored in the memory (570) in a call signal reception mode, a call mode or a recording mode, a voice recognition mode, a broadcast reception mode, etc. The audio output unit (551) also outputs audio signals related to functions performed in the electronic device (1) (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit (551) may include a receiver and a speaker. At least one of the receiver and the speaker may be a sound generating device attached to the lower portion of the display panel (10) to vibrate the display panel (10) and output audio. The audio generating device may be a piezoelectric element or piezoelectric actuator that contracts and expands according to an electric signal, or an exciter that generates magnetic force using a voice coil to vibrate the display panel (10).

[0107] The haptic module (552) generates various tactile effects that can be felt by the user. The haptic module (552) can provide vibrations to the user as tactile effects. The haptic module (552) can not only deliver tactile effects through direct contact, but can also be implemented so that the user can feel the tactile effects through the kinesthetic senses of the fingers or arms.

[0108] The light output unit (553) outputs a signal to notify the occurrence of an event using light from a light source. Examples of events occurring in the electronic device (1) may include receiving a message, receiving a call signal, receiving a missed call, an alarm, a schedule reminder, receiving an email, receiving information through an application, or a combination thereof. The signal output by the light output unit (553) is implemented by the electronic device (1) emitting light of a single color or multiple colors from the front or rear. The signal output may be terminated when the electronic device (1) detects the user's confirmation of an event.

[0109] The interface unit (560) serves as a passageway for various types of external devices connected to the electronic device (1). The interface unit (560) may include at least one of a wired / wireless headset port, an external charger port, a wired / wireless data port, a memory card port, a port for connecting a device equipped with an identification module, an audio I / O (Input / Output) port, a video I / O (Input / Output) port, and an earphone port. The electronic device (1) may perform appropriate control related to the connected external device in response to the external device being connected to the interface unit (560).

[0110] The memory (570) stores data that supports various functions of the electronic device (1). The memory (570) can store a plurality of applications (application programs) running on the electronic device (1), data for the operation of the electronic device (1), and commands. At least some of the plurality of applications can be downloaded from an external server via wireless communication. The memory (570) can store applications for the operation of the main processor (510), and can also temporarily store input / output data, such as phone books, messages, still images, and moving images. In addition, the memory (570) can store haptic data for various patterns of vibration provided to the haptic module (552) and audio data regarding various sounds provided to the audio output unit (551). The memory (570) may include at least one type of storage medium among a flash memory type, a hard disk type, a solid state disk type, an SDD type, a multimedia card micro type, a card type memory (e.g., an SD or XD memory, etc.), a random access memory (RAM), a static random access memory (SRAM), a read-only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), a programmable read-only memory (PROM), a magnetic memory, a magnetic disk, and an optical disk, or a combination thereof.

[0111] The power supply unit (580) receives external power and internal power under the control of the main processor (510) and supplies power to each component included in the electronic device (1). The power supply unit (580) may include a battery (80). In addition, the power supply unit (580) is provided with a connection port, and the connection port may be configured as an example of an interface unit (560) to which an external charger that supplies power for charging the battery is electrically connected. Alternatively, the power supply unit (580) may be configured to charge the battery (80) wirelessly without using the connection port. The battery (80) may be arranged so as not to overlap the main circuit board (50) in the third direction (z direction). The battery (80) may overlap the battery hole (BH) of the bracket (60).

[0112] The lower cover (90) can be placed under the main circuit board (50) and the battery (80). The lower cover (90) can be fixed by being connected to the bracket (60). The lower cover (90) can form the lower exterior of the electronic device (1). The lower cover (90) can include plastic, metal, or both plastic and metal.

[0113] A second camera hole (CMH2) that exposes the lower surface of the camera device (531) may be formed in the lower cover (90). The position of the camera device (531) and the positions of the first and second camera holes (CMH1, CMH2) corresponding to the camera device (531) are not limited to the embodiments illustrated in FIGS. 1 and 2 and may be varied in various ways.

[0114] FIG. 4 is a plan view schematically illustrating a display panel (10) according to one embodiment of the present invention, and FIG. 5 is a side view schematically illustrating a display panel (10) according to one embodiment of the present invention.

[0115] The display panel (10) may include a display area (DA) and a peripheral area (PA) outside the display area (DA). The display area (DA) is a portion for displaying an image, and a plurality of pixels may be arranged. The display area (DA) may have various shapes, such as a circle, an oval, a polygon, or a shape of a specific shape. For example, FIG. 4 illustrates that the display area (DA) has a roughly rectangular shape with rounded corners.

[0116] A peripheral area (PA) may be arranged outside the display area (DA). The peripheral area (PA) may include a first peripheral area (PA1) arranged to surround at least a portion of the display area (DA) and a second peripheral area (PA2) adjacent to one side of the display area (DA) and extending in a negative second direction (e.g., -y direction). A width of the second peripheral area (PA2) along the first direction (e.g., x-axis direction) may be narrower than a width of the display area (DA). This structure may facilitate bending of at least a portion of the second peripheral area (PA2).

[0117] The shape of the plane of the display panel (10) illustrated in FIG. 4 may be substantially the same as the shape of the substrate (100) included in the display panel (10). When the display panel (10) is said to include a display area (DA) and a peripheral area (PA) outside the display area (DA), this may indicate that the substrate (100) includes the display area (DA) and a peripheral area (PA) outside the display area (DA). Hereinafter, for convenience, it will be described that the substrate (100) has a display area (DA) and a peripheral area (PA).

[0118] The display panel (10) may include a main region (MR), a bending region (BR) outside the main region (MR), and a sub-region (SR) spaced apart from the main region (MR) with the bending region (BR) therebetween. The main region (MR) may be arranged on one side of the bending region (BR), and the sub-region (SR) may be arranged on the other side of the bending region (BR). The display panel (10) may be bent in the bending region (BR), as illustrated in FIG. 5, and at least a portion of the sub-region (SR) may overlap the main region (MR) when viewed in a third direction (e.g., the z-direction). Although FIG. 5 illustrates the display panel (10) being bent, the present invention is not limited thereto. In another embodiment, the display panel (10) may be a foldable display panel, and the display region (DA) may be bent around a bending axis crossing the display region (DA). In yet another embodiment, the display panel (10) may not be bent. The sub-region (SR) may be a non-display area.

[0119] A data driver (20) may be placed in a sub-region (SR) of a display panel (10). The data driver (20) may be placed in the display panel (10) in the form of an integrated circuit (IC). For example, the data driver (20) may be a data driving integrated circuit that generates a data signal.

[0120] A display circuit board (30) may be attached to an end of a sub-area (SR) of a display panel (10). The display circuit board (30) may be electrically connected to a data driver (20) or the like through a pad of the sub-area (SR) of the display panel (10).

[0121] Figure 6 is a plan view schematically showing a display panel (10) according to one embodiment of the present invention.

[0122] Referring to FIG. 6, the display panel (10) may include a substrate (100). Various components constituting the display panel (10) may be arranged on the substrate (100).

[0123] The substrate (100) may include glass, metal, or a polymer resin. The substrate (100) may include a polymer resin such as, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate, or a combination thereof. The substrate (100) may have a multilayer structure including two layers including the aforementioned polymer resins and an inorganic layer interposed between the layers.

[0124] Pixels are arranged in a display area (DA), and the display area (DA) can provide an image using light emitted from the pixels. Each pixel can include a light-emitting diode (LED), and the light-emitting diode (LED) can be electrically connected to a pixel circuit (PC). The pixel circuit (PC) and the light-emitting diode (LED) can be arranged in the display area (DA).

[0125] A gate driving circuit (e.g., a first scan driving circuit (11), a second scan driving circuit (12), a light emission control driving circuit (13), a pad (14), a first power supply line (15), and a second power supply line (16)) may be arranged in the peripheral area (PA).

[0126] The first scan driving circuit (11) can provide a scan signal to the pixel circuit (PC) through the gate line (SL). The second scan driving circuit (12) can be arranged on the opposite side of the first scan driving circuit (11) with the display area (DA) therebetween. Some of the pixel circuits (PC) arranged in the display area (DA) can be electrically connected to the first scan driving circuit (11), and other pixel circuits (PC) arranged in the display area (DA) can be connected to the second scan driving circuit (12). In another embodiment, the second scan driving circuit (12) can be omitted.

[0127] The light emission control driving circuit (13) is arranged on the side of the first scan driving circuit (11) and can provide a light emission control signal to the pixel (P) through the light emission control line (EL). In Fig. 6, the light emission control driving circuit (13) is illustrated as being arranged only on one side of the display area (DA), but the present invention is not limited thereto. In another embodiment, the light emission control driving circuits (13) may be arranged on both sides of the display area (DA).

[0128] The pad (14) may be placed in the second peripheral area (PA2) of the substrate (100). The pad (14) may be exposed without being covered by an insulating layer and may be electrically connected to the display circuit board (30). The pad (34) of the display circuit board (30) may be electrically connected to the pad (14) of the display panel (10).

[0129] The display circuit board (30) transmits a signal or power of a control unit (not shown) to the display panel (10). The control signal generated by the control unit can be transmitted to each gate driving circuit through the display circuit board (30). In addition, the control unit can provide a first power voltage and a second power voltage (ELVDD, ELVSS, FIG. 8) to the first and second power supply lines (15, 16), respectively. The first power voltage (ELVDD, hereinafter referred to as driving voltage) is provided to each pixel circuit (PC) through a driving voltage line (PL) connected to the first power supply line (15), and the second power voltage (ELVSS, hereinafter referred to as common voltage) can be provided to an opposite electrode of a light emitting diode (LED) connected to the second power supply line (16). The first power supply line (15) can extend in a first direction (e.g., x-direction). The second power supply wiring (16) has a loop shape with one side open, so that it can partially surround the display area (DA).

[0130] The data signal of the data driver (20) can be transmitted to the pixel circuit (PC) through the data line (DL) electrically connected to the input line (IL) via the input line (IL).

[0131] FIG. 7a and FIG. 7b are schematic plan views each showing an enlarged portion of part VII of FIG. 6 as a part of a display panel (10) according to one embodiment of the present invention.

[0132] Referring to Fig. 7a, a data line (DL) extending along a second direction (e.g., y direction) is arranged in the display area (DA), and an input line (IL) is arranged in the outer area (PA). The input line (IL) can transmit a data signal of a data driver (20, Fig. 6) to the data line (DL). For convenience of explanation, Fig. 7 illustrates a case where the data line (DL) includes first to sixth data lines (DL1, DL2, DL3, DL4, DL5, DL6) and the input line (IL) includes first to sixth input lines (IL1, IL2, IL3, IL4, IL5, IL6), but the number of data lines (DL) and the number of input lines (IL) may be seven or more.

[0133] Some of the data lines (DL) may be directly connected to the input lines, while others of the data lines (DL) may be electrically connected via data transfer lines (DTL) between the input lines (IL) and the corresponding data lines (DL).

[0134] In one embodiment, the first, third, and fifth data lines (DL1, DL3, and DL5) can receive data signals from the first, third, and fifth input lines (IL1, IL3, and IL5), respectively. The first, third, and fifth input lines (IL1, IL3, and IL5) can be electrically connected to the first, third, and fifth data lines (DL1, DL3, and DL5), respectively. The first, third, and fifth input lines (IL1, IL3, and IL5) can be formed integrally with the first, third, and fifth data lines (DL1, DL3, and DL5), or can be connected through a first contact hole (CNT1) as shown in FIG. 7.

[0135] In one embodiment, the second, fourth, and sixth data lines (DL2, DL4, and DL6) can receive data signals from the second, fourth, and sixth input lines (IL2, IL4, and IL6), respectively, via the first to third data transmission lines (DTL1, DTL2, and DTL3). The second, fourth, and sixth input lines (IL2, IL4, and IL6) can be electrically connected to the second, fourth, and sixth data lines (DL2, DL4, and DL6), respectively, via the first to third data transmission lines (DTL1, DTL2, and DTL3).

[0136] The first to third data transmission lines (DTL1, DTL2, DTL3) can each be arranged in the display area (DA). The second input line (IL2) is electrically connected to the second data line (DL2) via the first data transmission line (DTL1), the fourth input line (IL4) is electrically connected to the fourth data line (DL4) via the second data transmission line (DTL2), and the sixth input line (IL6) is electrically connected to the sixth data line (DL6) via the third data transmission line (DTL3).

[0137] Each of the first to third data transmission lines (DTL1, DTL2, DTL3) has one end connected to the second, fourth, and sixth input lines (IL2, IL4, IL6) through the second contact hole (CNT2), and each of the other ends of the first to third data transmission lines (DTL1, DTL2, DTL3) can be connected to the second, fourth, and sixth data lines (DL2, DL4, DL6) through the third contact hole (CNT3). Although Fig. 7 illustrates that the second contact hole (CNT2) and the third contact hole (CNT3) are located in the peripheral area (PA), the present invention is not limited thereto. In another embodiment, the second contact hole (CNT2) and / or the third contact hole (CNT3) can be located in the display area (DA).

[0138] In one embodiment, the first to third data transmission lines (DTL1, DTL2, DTL3) may each include a first connection line (DH1, DH2, DH3), a second connection line (DV1, DV2, DV3), and a third connection line (DV1', DV2', DV3'). The first connection line (DH1, DH2, DH3) may extend in a first direction (e.g., x-direction), and the second connection line (DV1, DV2, DV3) and the third connection line (DV1', DV2', DV3') may extend in a second direction (e.g., y-direction) substantially parallel to the data line (DL).

[0139] Each of the second, fourth, and sixth input lines (IL2, IL4, and IL6) can be connected to the second connection lines (DV1, DV2, and DV3) through the second contact hole (CNT2), and each of the third connection lines (DV1', DV2', and DV3') can be connected to the second, fourth, and sixth data lines (DL2, DL4, and DL6) through the third contact hole (CNT3). Each of the first connection lines (DH1, DH2, and DH3) can be connected to the second connection lines (DV1, DV2, and DV3) and the third connection lines (DV1', DV2', and DV3') through the first connection contact hole (DH-CNT1) and the second connection contact hole (DH-CNT2).

[0140] In one embodiment, the second connection lines (DV1, DV2, DV3) and the third connection lines (DV1', DV2', DV3') may be arranged on the same layer, and the first connection lines (DH1, DH2, DH3) may be arranged on a different layer from the second connection lines (DV1, DV2, DV3) and the third connection lines (DV1', DV2', DV3'). In this case, being arranged on the same layer may mean that they are formed simultaneously through the same mask process and include the same material.

[0141] Although Fig. 7a illustrates that the first to third data transmission lines (DTL1, DTL2, DTL3) include first connection lines (DH1, DH2, DH3), second connection lines (DV1, DV2, DV3) and third connection lines (DV1', DV2', DV3'), respectively, the present invention is not limited thereto. In another embodiment, as illustrated in Fig. 7b, the first to third data transmission lines (DTL1, DTL2, DTL3) may include first connection lines (DH1, DH2, DH3) and second connection lines (DV1, DV2, DV3), respectively. In this case, the second connection lines (DV1, DV2, DV3) may be electrically connected to data lines, for example, the second, fourth and sixth data lines (DL2, DL4, DL6), through a second connection contact hole (DH-CNT2).

[0142] Although FIGS. 7A and 7B illustrate a structure in which one connection line extending in a second direction (e.g., y direction) is arranged between two adjacent data lines (DL), the present invention is not limited thereto. In another embodiment, two connection lines (e.g., data connection lines (DVL, FIG. 9)) may be arranged between two adjacent data lines (DL), as in the embodiment described with reference to FIG. 9.

[0143] FIG. 8 is a schematic equivalent circuit diagram of a light emitting diode (LED) and a pixel circuit (PC) of a display panel (10) according to one embodiment of the present invention.

[0144] Referring to FIG. 8, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. In one embodiment, the pixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, and T6), a storage capacitor (Cst), and a hold capacitor (Chd). The first transistor (T1) may be a driving transistor that outputs a driving current corresponding to a data signal, and the second to sixth transistors (T2, T3, T4, T5, and T6) may be switching transistors that transmit a signal. The first terminal (first electrode) of each of the first to sixth transistors (T1, T2, T3, T4, T5, and T6) may be a source or a drain, and the second terminal (second electrode) may be a terminal different from the first terminal. For example, when the first terminal is a drain, the second terminal may be a source.

[0145] In one embodiment, at least one of the first to sixth transistors (T1, T2, T3, T4, T5, T6) may be a p-channel MOSFET (PMOS), and the others may be n-channel MOSFETs (NMOS). For example, the fifth transistor (T5) may be a PMOS, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4 T6) may be NMOS. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may be PMOS, and the first, second, third, and fourth transistors (T1, T2, T3, T4) may be NMOS. Alternatively, the first to sixth transistors (T1, T2, T3, T4, T5, T6) may all be NMOS or all may be PMOS. Hereinafter, an embodiment will be described in which the fifth transistor (T5) is a PMOS (p-channel MOSFET) including a silicon semiconductor, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, and T6) are NMOS (n-channel MOSFETs) including an oxide semiconductor.

[0146] At least one of the plurality of transistors (T1, T2, T3, T4, T5, T6) may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer, and at least one of the plurality of transistors (T1, T2, T3, T4, T5, T6) may be a transistor having an oxide semiconductor layer. For example, the fifth transistor (T5) may include a semiconductor layer made of polycrystalline silicon having high reliability, and the first, second, third, fourth, and sixth transistors (T1, T2, T3, T4, T6) may include oxide semiconductor layers having high carrier mobility and low leakage current. The pixel circuit (PC) may be electrically connected to a gate line that transmits a signal to the gate of each of the first to sixth transistors (T1, T2, T3, T4, T5, T6). For example, a pixel circuit (PC) may be connected to a scan line (GWL) that transmits a scan signal (GW), an initialization gate line (GBL) that transmits an initialization signal (GB), a reference gate line (GRL) that transmits a reference signal (GR), a first emission control line (EML) that transmits a first emission control signal (EM), a second emission control line (EMBL) that transmits a second emission control signal (EMB), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel circuit (PC) may be connected to a driving voltage line (PL) that transmits a driving voltage (ELVDD), a reference voltage line (VRL) that transmits a reference voltage (VREF), and an initialization voltage line (VL) that transmits an initialization voltage (Vaint).

[0147] A first transistor (T1) may be electrically connected between a driving voltage line (PL) and a second node (N2). The first transistor (T1) may include a gate (G1) connected to the first node (N1), a first terminal connected to the driving voltage line (PL), and a second terminal connected to a second node (N2). The first terminal may be a drain (D) and the second terminal may be a source (S). The first transistor (T1) may have a dual gate structure. In addition to the gate (G1) connected to the first node, the first transistor (T1) may further include a lower gate electrode overlapping a channel region of the first transistor (T1). The lower gate electrode may be connected to a second node (N2) and a second hold electrode (CEh2) of a hold capacitor (Chd).

[0148] A first terminal of a first transistor (T1) is connected to a driving voltage line (PL) via a fifth transistor (T5), and a second terminal of the first transistor (T1) can be connected to a pixel electrode of a light-emitting diode (LED). The first transistor (T1) can receive a data signal (DATA) according to a switching operation of the second transistor (T2) and control the amount of driving current (Id) flowing to the light-emitting diode (LED).

[0149] The second transistor (T2) may be electrically connected between the data line (DL) and the first node (N1). The second transistor (T2) may include a gate connected to the scan line (GWL), a first terminal connected to the data line (DL), and a second terminal connected to the first node (N1). The second transistor (T2) may be turned on by a scan signal (GW) transmitted to the scan line (GWL) to electrically connect the data line (DL) and the first node (N1), and may transmit a data signal (DATA) transmitted to the data line (DL) to the first node (N1).

[0150] A third transistor (T3) may be electrically connected between a first node (N1) and a reference voltage line (VRL). The third transistor (T3) may include a gate connected to a reference gate line (GRL), a first terminal connected to a first node (N1), and a second terminal connected to the reference voltage line (VRL). The third transistor (T3) may be turned on by a reference signal (GR) transmitted to the reference gate line (GRL) and may transmit a reference voltage (Vref) transmitted to the reference voltage line (VRL) to the first node (N1).

[0151] The fourth transistor (T4) may be electrically connected between the first transistor (T1) and the initialization voltage line (VL). The fourth transistor (T4) may include a gate connected to the initialization gate line (GBL), a first terminal connected to the second terminal of the sixth transistor (T6) and a light-emitting diode (LED), and a second terminal connected to the initialization voltage line (VL). The fourth transistor (T4) may be turned on by the initialization signal (GB) transmitted to the initialization gate line (GBL) and may transmit the initialization voltage (Vaint) transmitted to the initialization voltage line (VL) to the pixel electrode of the light-emitting diode (LED).

[0152] The fifth transistor (T5) may be electrically connected between the driving voltage line (PL) and the first transistor (T1). The fifth transistor (T5) may include a gate connected to the first emission control line (EML), a first terminal connected to the driving voltage line (PL), and a second terminal connected to the first terminal of the first transistor (T1). The fifth transistor (T5) may be turned on or off according to the first emission control signal (EM) transmitted to the first emission control line (EML).

[0153] The sixth transistor (T6) may be connected between the first transistor (T1) and the light emitting diode (LED). The sixth transistor (T6) may include a gate connected to the second light emitting control line (EMBL), a first terminal connected to the second node (N2), and a second terminal connected to the light emitting diode (LED). The sixth transistor (T6) may be turned on by the second light emitting control signal (EMB) transmitted to the second light emitting control line (EMBL) to connect the second node (N2) and the pixel electrode of the light emitting diode (LED) to each other.

[0154] Although Fig. 8 illustrates that the fifth transistor (T5) and the sixth transistor (T6) operate in response to different light emission control signals (EM, EMB), the present invention is not limited thereto. In another embodiment, the fifth transistor (T5) and the sixth transistor (T6) may operate in response to the same light emission control signal.

[0155] In one embodiment, the reference signal (GR) may be substantially synchronized with the scan signal (GW) of the pixel circuit (PC) located in the previous row. The initialization signal (GB) may be substantially synchronized with the scan signal (GW). In another embodiment, the initialization signal (GB) may be substantially synchronized with the scan signal (GW) or the reference signal (GR) of the pixel circuit (PC) located in the next row.

[0156] The storage capacitor (Cst) may be connected between the first node (N1) and the second node (N2). In other words, the pixel circuit (PC) according to an embodiment of the present invention may be a source follower type circuit in which the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2). The first storage electrode (CEs1) of the storage capacitor (Cst) may be connected to the first node (N1), and the second storage electrode (CEs2) may be connected to the second node (N2). The storage capacitor (Cst) may store a threshold voltage of the first transistor (T1) and a voltage corresponding to a data signal (DATA).

[0157] In one embodiment, a hold capacitor (Chd) may be connected between a driving voltage line (PL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be connected to the driving voltage line (PL), and a second hold electrode (CEh2) may be connected to a second node (N2). The hold capacitor (Chd) allows the voltage of the lower gate electrode of the first transistor (T1) and the second node (N2) to remain constant and not fluctuate even when a peripheral signal fluctuates.

[0158] A light emitting diode (LED) includes a pixel electrode connected to a second node (N2) and a counter electrode on the pixel electrode, and the counter electrode can be supplied with a common voltage (ELVSS). The counter electrode can be a common electrode shared by a plurality of light emitting diodes (LEDs).

[0159] Although FIG. 8 illustrates that the pixel circuit (PC) includes six transistors and two capacitors, the present invention is not limited thereto. In another embodiment, the pixel circuit (PC) may include five transistors and two capacitors. In yet another embodiment, the pixel circuit (PC) may include seven transistors and two capacitors.

[0160] Fig. 9 is a plan view schematically illustrating pixel circuits of a display panel according to one embodiment of the present invention. For convenience of explanation, Fig. 9 illustrates two pixel circuits, for example, a first pixel circuit (PC1) and a second pixel circuit (PC2), arranged in the same row along a first direction (e.g., x direction), but the present invention is not limited thereto. The display panel (10) includes a plurality of pixel circuits arranged to form rows in the first direction (e.g., x direction) and columns in the second direction (e.g., y direction).

[0161] Referring to FIG. 9, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include transistors and capacitors. In one embodiment, each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first to sixth transistors (T1, T2, T3, T4, T5, T6), a storage capacitor (Cst), and a hold capacitor (Chd) described above with reference to FIG. 8.

[0162] The transistors and capacitors of the first pixel circuit (PC1) may be arranged symmetrically with the transistors and capacitors of the second pixel circuit (PC2), respectively. For example, the first transistor (T1) of the first pixel circuit (PC1) may be symmetrical with the first transistor (T1) of the second pixel circuit (PC2) with respect to an imaginary line (IML) passing between the first pixel circuit (PC1) and the second pixel circuit (PC2) along the second direction (e.g., the y direction). Similarly, the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the first pixel circuit (PC1) may be symmetrical with the second to sixth transistors (T2, T3, T4, T5, T6), the storage capacitor (Cst), and the hold capacitor (Chd) of the second pixel circuit (PC2), respectively, with respect to the imaginary line (IL).

[0163] Gate lines electrically connected to the first pixel circuit (PC1) and the second pixel circuit (PC2), such as a scan line (GWL), an initialization gate line (GBL), a reference gate line (GRL), a first emission control line (EML), and a second emission control line (EMBL), can extend in a first direction (e.g., an x-direction).

[0164] A first pixel circuit (PC1) may be electrically connected to a data line (DL) passing through the first pixel circuit (PC1), and a second pixel circuit (PC2) may be electrically connected to a data line (DL) passing through the second pixel circuit (PC2). The data line (DL) may extend along a second direction (e.g., y direction). The data line (DL) electrically connected to the first pixel circuit (PC1) and the data line (DL) electrically connected to the second pixel circuit (PC2) may be symmetrical with respect to the aforementioned virtual line (IML).

[0165] A first pixel circuit (PC1) may be electrically connected to a voltage line passing through the first pixel circuit (PC1), such as a reference voltage line (VRL) and an initialization voltage line (VL). A second pixel circuit (PC2) may be electrically connected to a voltage line passing through the second pixel circuit (PC2), such as a reference voltage line (VRL) and an initialization voltage line (VL). The reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the first pixel circuit (PC1) may be symmetrical with respect to the reference voltage line (VRL) and the initialization voltage line (VL) electrically connected to the second pixel circuit (PC2), respectively, and the aforementioned imaginary line (IML). The reference voltage line (VRL) and the initialization voltage line (VL) may each extend along a second direction (e.g., a y-direction).

[0166] In some embodiments, the data connection line (DVL) may extend along the second direction (e.g., the y direction). The data connection line (DVL) may be a signal line corresponding to a portion of the data transmission line (DTL) described above with reference to FIG. 7, for example, one of the second connection lines (DV1, DV2, DV3) and the third connection lines (DV1', DV2', DV3'). The data connection line (DVL) may be electrically connected to the data lines of pixel circuits arranged in a different column from the first and second pixel circuits (PC1, PC2) illustrated in FIG. 9, thereby transmitting data signals to pixel circuits arranged in a different column.

[0167] FIGS. 10 to 18 are plan views illustrating a process for forming a pixel circuit of a display panel according to an embodiment of the present invention. FIGS. 10 to 18 illustrate a process for forming components corresponding to the first pixel circuit (PC1) and the second pixel circuit (PC2) described with reference to FIG. 9. For convenience of explanation, the first pixel circuit (PC1) is described as being located in the (i)-th row and the (j)-th column, and the second pixel circuit (PC2) is described as being located in the (i)-th row and the (j+1)-th column.

[0168] Referring to FIG. 10, a lower metal layer (1110) may be disposed on a substrate. The lower metal layer (1110) may include a first portion (1111) extending along a second direction (e.g., y direction), and a second portion (1112) and a third portion (1113) connected to the first portion (1111) but extending along the first direction (e.g., x direction) as a whole.

[0169] In one embodiment, the first portion (1111) of the lower metal layer (1110) may be positioned on an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second portion (1112) and the third portion (1113) of the lower metal layer (1110) may be positioned on opposite sides with the first portion (1111) therebetween. The second portion (1112) and the third portion (1113) may extend generally along the first direction (e.g., the x-direction), but may be locally bent.

[0170] The lower metal layer (1110) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer (1110) may be a single layer including molybdenum, have a double layer structure in which a molybdenum layer and a titanium layer are stacked, or have a triple layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0171] The lower metal layer (1110) may have a voltage level of a constant voltage. For example, the lower metal layer (1110) may be electrically connected to the first power supply wire (15, FIG. 6) at the periphery of the display area (DA) of the display panel (10, FIG. 6).

[0172] Referring to FIG. 11, a silicon semiconductor layer (1200) may be disposed on a lower metal layer (1110). Specifically, the silicon semiconductor layer (1200) may include amorphous silicon or polysilicon. For example, the silicon semiconductor layer (1200) may include polysilicon crystallized at a low temperature. The silicon semiconductor layer (1200) may include a first silicon semiconductor pattern (1210) as shown in FIG. 11.

[0173] The first silicon semiconductor pattern (1210) may have an isolated shape and may extend along a first direction (e.g., x-direction). The first silicon semiconductor pattern (1210) may intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The first silicon semiconductor pattern (1210) may include a fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). In other words, the fifth semiconductor layer (A5) of the first pixel circuit (PC1) and the fifth semiconductor layer (A5) of the second pixel circuit (PC2) may be integrally connected.

[0174] The first silicon semiconductor pattern (1210) may overlap with the lower metal layer (1110). For example, the first silicon semiconductor pattern (1210) may overlap with the third portion (1113) of the lower metal layer (1110). The fifth semiconductor layer (A5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may overlap with the third portion (1113) of the lower metal layer (1110).

[0175] Referring to FIG. 12, a first conductive layer (1300) may be disposed on a silicon semiconductor layer (1200). The first conductive layer (1300) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0176] The first conductive layer (1300) may include an emission control line (EML), a first conductive pattern (1310), a second conductive pattern (1320), a third conductive pattern (1330), and a fourth conductive pattern (1340). The first emission control line (EML), the first conductive pattern (1310), the second conductive pattern (1320), the third conductive pattern (1330), and the fourth conductive pattern (1340) may be arranged to be spaced apart from each other.

[0177] The first emission control line (EML) can extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The first emission control line (EML) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0178] The first emission control line (EML) may include a fifth gate electrode (G5) of a fifth transistor (T5) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). A portion of the first emission control line (EML) may protrude to overlap with a fifth semiconductor layer (A5) of the fifth transistor (T5), and a portion of the protruding first emission control line (EML) may correspond to the fifth gate electrode (G5) of the fifth transistor (T5). The fifth semiconductor layer (A5, FIG. 11) of the fifth transistor (T5) may include a channel region (C5) overlapping with the fifth gate electrode (G5), and doped regions (S5, D5) disposed on both sides of the channel region (C5) and doped with impurities. One of the doped regions (S5, D5) may be a source region, and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source and drain regions can be interchanged depending on the properties of the transistor.

[0179] The first conductive pattern (1310), the second conductive pattern (1320), the third conductive pattern (1330), and the fourth conductive pattern (1340) may be arranged in the first pixel circuit (PC1) and the second pixel circuit (PC2), respectively. The first conductive pattern (1310), the second conductive pattern (1320), the third conductive pattern (1330), and the fourth conductive pattern (1340) may each have an isolated shape. The first conductive pattern (1310), the third conductive pattern (1330), and the fourth conductive pattern (1340) of the first pixel circuit (PC1) may be arranged symmetrically with respect to the first conductive pattern (1310), the third conductive pattern (1330), and the fourth conductive pattern (1340) of the second pixel circuit (PC2) with respect to the aforementioned virtual line (IML).

[0180] The second conductive pattern (1320) has an isolated shape and may extend in a first direction (e.g., x direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive layer (1320) may intersect a virtual line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2). The second conductive pattern (1320) may include a stem portion extending in the first direction (e.g., x direction) and a branch portion branching from the stem portion and protruding along a second direction (e.g., y direction). The branch portion of the first pixel circuit (PC1) and the branch portion of the second pixel circuit (PC2) may be symmetrically arranged with respect to the virtual line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0181] The second challenge pattern (1320) may include a first lower hold electrode (CEh1a), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd) described with reference to FIG. 8. In other words, the first lower hold electrode (CEh1a) of the first pixel circuit (PC1) may be integrally connected to the first lower hold electrode (CEh1a) of the second pixel circuit (PC2).

[0182] The third conductive pattern (1330) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include the first storage electrode (CEs1) of the storage capacitor (Cst) described with reference to FIG. 8.

[0183] Referring to FIG. 13, a second conductive layer (1400) may be disposed on a first conductive layer (1300). The second conductive layer (1400) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0184] The second conductive layer (1400) may include an initialization gate line (GBL), a reference gate line (GRL), and a fifth conductive pattern (1410). The initialization gate line (GBL), the reference gate line (GRL), and the fifth conductive pattern (1410) are arranged to be spaced apart from each other.

[0185] Each of the initialization gate line (GBL) and the reference gate line (GRL) may extend along a first direction (e.g., the x-direction) to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). Each of the initialization gate line (GBL) and the reference gate line (GRL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0186] The fifth conductive pattern (1410) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The fifth conductive pattern (1410) disposed in the first pixel circuit (PC1) and the fifth conductive pattern (1410) disposed in the second pixel circuit (PC2) may be spaced apart from each other and may be substantially symmetrically disposed with respect to the aforementioned virtual line (IML) as the center.

[0187] The fifth conductive pattern (1410) can overlap the third conductive pattern (1330) of the first pixel circuit (PC1), the third conductive pattern (1330) of the second pixel circuit (PC2), and the second conductive pattern (1320) passing through the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0188] The fifth challenge pattern (1410) may include a second hold electrode (CEh2) of a hold capacitor (Chd, FIG. 8) and a second storage electrode (CEs2) of a storage capacitor (Cst, FIG. 8). In other words, the second hold electrode (CEh2) of the hold capacitor (Chd, FIG. 8) and the second storage electrode (CEs2) of the storage capacitor (Cst, FIG. 8) may be formed integrally.

[0189] Referring to FIG. 14, an oxide semiconductor layer (1500) may be disposed on the second conductive layer (1400). Specifically, the oxide semiconductor layer (1500) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor layer (1500) may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0190] The oxide semiconductor layer (1500) may include a first oxide semiconductor pattern (1510), a second oxide semiconductor pattern (1520), a third oxide semiconductor pattern (1530), and a fourth oxide semiconductor pattern (1540). The first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may be arranged to be spaced apart from each other.

[0191] The first oxide semiconductor pattern (1510) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The first oxide semiconductor pattern (1510) may include a first semiconductor layer (A1), a fourth semiconductor layer (A4), and a sixth semiconductor layer (A6). In other words, the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the first pixel circuit (PC1) may be integrally connected, and the first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) of the second pixel circuit (PC2) may be integrally connected. The first oxide semiconductor pattern (1510) may have a shape that is folded several times.

[0192] The first semiconductor layer (A1), the fourth semiconductor layer (A4), and the sixth semiconductor layer (A6) may overlap with the fifth conductive pattern (1410) and the initialization gate line (GBL) described with reference to FIG. 13, and the fourth conductive pattern (1340) described with reference to FIG. 12, respectively.

[0193] In one embodiment, on a plane, the shapes of the first oxide semiconductor pattern (1510) of the first pixel circuit (PC1) and the first oxide semiconductor pattern (1510) of the second pixel circuit (PC2) may be different from each other. A part of the first semiconductor pattern (1510) of the first pixel circuit (PC1) may be arranged in a pixel circuit that is arranged in the same row as the first pixel circuit (PC) but in an adjacent column (e.g., the (i)th row and the (j-1)th column).

[0194] The second oxide semiconductor pattern (1520) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The second oxide semiconductor pattern (1520) may be bent to have an approximately "L" shape. The second oxide semiconductor pattern (1520) of the first pixel circuit (PC1) and the second oxide semiconductor pattern (1520) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML).

[0195] The second oxide semiconductor pattern (1520) may include a second semiconductor layer (A2) of the second transistor (T2) and a third semiconductor layer (A3) of the third transistor (T3). In other words, the second semiconductor layer (A2) of the second transistor (T2) and the third semiconductor layer (A3) of the third transistor (T3) may be connected integrally.

[0196] The second semiconductor layer (A2) and the third semiconductor layer (A3) may overlap with the first conductive pattern (1310) described with reference to FIG. 12 and the reference gate line (GRL) described with reference to FIG. 13, respectively.

[0197] The third oxide semiconductor pattern (1530) disposed in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The third oxide semiconductor pattern (1530) of the first pixel circuit (PC1) and the third oxide semiconductor pattern (1530) of the second pixel circuit (PC2) may be symmetrically disposed with respect to the aforementioned virtual line (IML).

[0198] The third oxide semiconductor pattern (1530) may overlap the fifth conductive pattern (1410) described with reference to FIG. 13 and the second conductive pattern (1320) described with reference to FIG. 12 along the third direction (e.g., z direction). The third oxide semiconductor pattern (1530) may include a first upper hold electrode (CEh1b) which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd, FIG. 8).

[0199] The fourth oxide semiconductor pattern (1540) may be arranged on the first pixel circuit (PC1). The fourth oxide semiconductor pattern (1540) may be arranged at a position corresponding to one end of the first semiconductor pattern (1510) of the second pixel circuit (PC1), and may correspond to a type of dummy electrode.

[0200] Each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540) may include at least a partially conductive region. For example, a conductive process using plasma or the like may be performed on at least a portion of each of the first oxide semiconductor pattern (1510), the second oxide semiconductor pattern (1520), the third oxide semiconductor pattern (1530), and the fourth oxide semiconductor pattern (1540). In one embodiment, the entire region of the third oxide semiconductor pattern (1530) including the first upper hold electrode (CEh1b) may be conductive to form a hold capacitor (Chd, FIG. 8).

[0201] Referring to FIG. 15, a third conductive layer (1600) may be disposed on an oxide semiconductor layer (1500). The third conductive layer (1600) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0202] The third conductive layer (1600) may include a horizontal initialization voltage line (VHL), a second emission control line (EMBL), a horizontal reference voltage line (VRHL), a sixth conductive pattern (1610), a seventh conductive pattern (1620), an eighth conductive pattern (1630), and a ninth conductive pattern (1640). The horizontal initialization voltage line (VHL), the second emission control line (EMBL), the horizontal reference voltage line (VRHL), the sixth conductive pattern (1610), the seventh conductive pattern (1620), the eighth conductive pattern (1630), and the ninth conductive pattern (1640) may be arranged to be spaced apart from each other.

[0203] The horizontal initialization voltage line (VHL) may extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The horizontal initialization voltage line (VHL) may be electrically connected to an initialization voltage line (VL) which will be described later with reference to FIG. 17.

[0204] The second emission control line (EMBL) may extend along the first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The second emission control line (EMBL) may pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0205] A horizontal reference voltage line (VRHL) may extend along a first direction (e.g., x-direction) so as to pass through a first pixel circuit (PC1) and a second pixel circuit (PC2). The horizontal reference voltage line (VRHL) may be electrically connected to a reference voltage line (VRL) which will be described later with reference to FIG. 17.

[0206] The sixth conductive pattern (1610), the seventh conductive pattern (1620), and the ninth conductive pattern (1640) arranged in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may each have an isolated shape. The sixth conductive pattern (1610), the seventh conductive pattern (1620), and the ninth conductive pattern (1640) of the first pixel circuit (PC1) may be arranged symmetrically with respect to the sixth conductive pattern (1610), the seventh conductive pattern (1620), and the ninth conductive pattern (1640) of the second pixel circuit (PC2) with respect to the aforementioned virtual line (IML).

[0207] The eighth conductive pattern (1630) may have an isolated shape and may extend along the first direction (e.g., the x-direction). The eighth conductive pattern (1630) may be arranged across the first pixel circuit (PC1) and the second pixel circuit (PC2). The eighth conductive pattern (1630) may intersect the aforementioned virtual line (IML).

[0208] The sixth conductive pattern (1610), the seventh conductive pattern (1620), the eighth conductive pattern (1630), the ninth conductive pattern (1640), and the second emission control line (EMBL) may include a gate electrode of the transistor.

[0209] Each of the sixth conductive patterns (1610) of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a first gate electrode (G1) of the first transistor (T1). Referring to FIGS. 14 and 15, the first semiconductor layer (A1) of the first transistor (T1) may include a channel region (C1) overlapping the sixth conductive pattern (1610) in a third direction (e.g., z direction) and conductive regions (S1, D1) arranged on both sides of the channel region (C1) in the first direction (e.g., x direction). One of the conductive regions (S1, D1) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor. At this time, a part of the fifth conductive pattern (1410, Fig. 13) and the first gate electrode (G1) may overlap each other in a third direction (e.g., z-direction) with the channel region (C1) therebetween. A part of the fifth conductive pattern (1410, Fig. 13) overlapping the channel region (C1) of the first transistor (T1) may correspond to the lower gate electrode of the first transistor (T1).

[0210] Each of the seventh conductive patterns (1620) of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a third gate electrode (G3) of the third transistor (T3). Referring to FIGS. 14 and 15, the third semiconductor layer (A3) of the third transistor (T3) may include a channel region (C3) overlapping the seventh conductive pattern (1620) in a third direction (e.g., z direction) and conductive regions (S3, D3) arranged on both sides of the channel region (C3) in a second direction (e.g., y direction). One of the conductive regions (S3, D3) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0211] The seventh conductive pattern (1620) may be electrically connected to a reference gate line (GRL) disposed below a third semiconductor layer (A3, FIG. 14) through a contact hole (CNT). The seventh conductive pattern (1620) and a portion of the reference gate line (GRL) may overlap each other in a third direction (e.g., z direction) with the channel region (C3) of the third transistor (T3) interposed therebetween. A portion of the reference gate line (GRL) overlapping the channel region (C3) of the third transistor (T3) in the third direction (e.g., z direction) may correspond to a lower gate electrode of the third transistor (T3), and the switching performance of the third transistor (T3) may be improved through such a dual gate structure.

[0212] The eighth conductive pattern (1630) may include a second gate electrode (G2) of the second transistor (T2). Referring to FIGS. 14 and 15, the second semiconductor layer (A2) of the second transistor (T2) may include a channel region (C2) overlapping with the third electrode layer (1630) in a third direction (e.g., z direction) and conductive regions (S2, D2) arranged on both sides of the channel region (C2) in a first direction (e.g., x direction). One of the conductive regions (S2, D2) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be changed depending on the properties of the transistor.

[0213] The eighth conductive pattern (1630) is electrically connected to a scan line (GWL) which will be described later with reference to FIG. 16. The eighth conductive pattern (1630) may be electrically connected to the first conductive pattern (1310) disposed below the second semiconductor layer (A2, FIG. 14) through a contact hole (CNT). The eighth conductive pattern (1630) and the first conductive pattern (1310) may overlap each other in a third direction (e.g., z-direction) with the channel region (C2) of the second transistor (T2) interposed therebetween. The first conductive pattern (1310) may correspond to the lower gate electrode of the second transistor (T2), and the switching performance of the second transistor (T2) may be improved through such a dual gate structure.

[0214] Each of the ninth conductive patterns (1640) of the first pixel circuit (PC1) and the second pixel circuit (PC2) may include a fourth gate electrode (G4) of the fourth transistor (T4). Referring to FIGS. 14 and 15, the fourth semiconductor layer (A4) of the fourth transistor (T4) may include a channel region (C4) overlapping the ninth conductive pattern (1640) in a third direction (e.g., z direction) and conductive regions (S4, D4) arranged on both sides of the channel region (C4). One of the conductive regions (S4, D4) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0215] The ninth conductive pattern (1640) may be electrically connected to an initialization gate line (GBL) disposed below the fourth semiconductor layer (A4, FIG. 14) through a contact hole (CNT). The ninth conductive pattern (1640) and a portion of the initialization gate line (GBL) may overlap each other in a third direction (e.g., z-direction) with the channel region (C4) of the fourth transistor (T4) interposed therebetween. A portion of the initialization gate line (GBL) overlapping the channel region (C4) of the fourth transistor (T4) may correspond to the lower gate electrode of the fourth transistor (T4), and the switching performance of the fourth transistor (T4) may be improved through such a dual gate structure.

[0216] The second emission control line (EMBL) may include the sixth gate electrode (G6) of the sixth transistor (T6). Referring to FIGS. 14 and 15, the sixth semiconductor layer (A6) of the sixth transistor (T6) may include a channel region (C6) overlapping the second emission control line (EMBL) in a third direction (e.g., z direction) and conductive regions (S6, D6) arranged on both sides of the channel region (C6) in a second direction (e.g., y direction). One of the conductive regions (S6, D6) may be a source region and the other may be a drain region. The source region and the drain region may correspond to a source electrode and a drain electrode, respectively. The positions of the source region and the drain region may be interchanged depending on the properties of the transistor.

[0217] The second light emission control line (EMBL) may be electrically connected to the fourth conductive pattern (1340) disposed below the sixth semiconductor layer (A6, FIG. 14) through a contact hole (CNT). A portion of the second light emission control line (EMBL) and the fourth conductive pattern (1340) may overlap each other in the third direction (e.g., z direction) with the channel region (C6) of the sixth transistor (T6) interposed therebetween. The fourth conductive pattern (1340) may correspond to the lower gate electrode of the sixth transistor (T6), and the switching performance of the fourth transistor (T4) may be improved through such a dual gate structure.

[0218] Referring to FIG. 16, a fourth conductive layer (1700) may be disposed on a third conductive layer (1600). The fourth conductive layer (1700) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0219] The fourth conductive layer (1700) may include a scan line (GWL) and tenth to seventeenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770, 1780). The scan line (GWL) and the tenth to seventeenth conductive patterns (1710, 1720, 1730, 1740, 1750, 1760, 1770, 1780) may be arranged to be spaced apart from each other.

[0220] The scan line (GWL) can extend along a first direction (e.g., the x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The scan line (GWL) can pass through pixel circuits arranged in the same row as the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0221] The tenth conductive pattern (1710) has an isolated shape and can extend along a first direction (e.g., x-direction) so as to pass through the first pixel circuit (PC1) and the second pixel circuit (PC2). The tenth conductive pattern (1710) can intersect an imaginary line (IML) between the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0222] The tenth conductive pattern (1710) may be electrically connected to the second conductive pattern (1320) and the third oxide semiconductor pattern (1530) through contact holes (CNT'). The tenth conductive pattern (1710) may be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5, FIG. 15) through the contact hole (CNT'). The tenth conductive pattern (1710) may be a connecting electrode that transmits the driving voltage (ELVDD, FIG. 8) of the driving voltage line (PL, FIG. 18) to be described later to the fifth transistor (T5, FIG. 15). Likewise, the 10th challenge pattern (1710) may be a connection electrode that is connected to the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b), respectively, and transmits the driving voltage of the driving voltage line (PL, FIG. 18) to the first hold electrode (CEh1, FIG. 8) of the hold capacitor (Chd, FIG. 8).

[0223] The 11th conductive pattern (1720) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 11th conductive pattern (1720) may electrically connect the first transistor (T1, FIG. 15) and the fifth transistor (T5, FIG. 15) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). The 11th conductive pattern (1720) may be electrically connected to the first semiconductor layer (A1) of the first transistor (T1, FIG. 15) through a contact hole (CNT') and may be electrically connected to the fifth semiconductor layer (A5) of the fifth transistor (T5, FIG. 15) through the contact hole (CNT'). For example, the 11th challenge pattern (1720) may be a connection electrode connecting the first transistor (T1, FIG. 15) and the fifth transistor (T5, FIG. 15).

[0224] The 12th conductive pattern (1730) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 12th conductive pattern (1730) may correspond to the first node described with reference to FIG. 8. The 12th conductive pattern (1730) may electrically connect the first transistor (T1, FIG. 15), the third transistor (T3, FIG. 15), and the first storage electrode (CEs1, FIG. 12) of the storage capacitor (Cst, FIG. 15) of each of the first pixel circuit (PC1) and the second pixel circuit (PC2). The 12th conductive pattern (1730) is electrically connected to the 6th conductive pattern (1610) corresponding to the first gate electrode of the first transistor (T1, FIG. 15) through a contact hole (CNT'), is electrically connected to the 3rd semiconductor layer (A3) through the contact hole (CNT'), and can be electrically connected to the 3rd conductive pattern (1330) through the contact hole (CNT').

[0225] The 13th conductive pattern (1740) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 13th conductive pattern (1740) may correspond to the second node described with reference to FIG. 8. The 13th conductive pattern (1740) may electrically connect the second storage electrode (CEs2, FIG. 13), the second hold electrode (CEh2, FIG. 13), the first transistor (T1, FIG. 15), and the sixth transistor (T6, FIG. 15). The 13th conductive pattern (1740) can be electrically connected to the 5th conductive pattern (1410) including the second storage electrode (CEs2, FIG. 13) and the second hold electrode (CEh2, FIG. 13) through a contact hole (CNT'), and can be electrically connected to the first oxide semiconductor pattern (1510) through the contact hole (CNT'). The connection point between the 13th conductive pattern (1740) and the first oxide semiconductor pattern (1510) can be located between an area corresponding to the first semiconductor layer (A1) of the first oxide semiconductor pattern (1510) and an area corresponding to the 6th semiconductor layer (A6, FIG. 15).

[0226] The 14th conductive pattern (1750) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 14th conductive pattern (1750) may be electrically connected to the third transistor (T3, FIG. 15). The 14th conductive pattern (1750) may be electrically connected to the third semiconductor layer (A3) through a contact hole (CNT'). The 14th conductive pattern (1750) may be a connection electrode that is connected to a reference voltage line (VRL, FIG. 17) to be described later and transmits a reference voltage (VREF, FIG. 8) to the third transistor (T3, FIG. 15).

[0227] The 15th conductive pattern (1760) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 15th conductive pattern (1760) may be electrically connected to the second transistor (T2, FIG. 15). The 15th conductive pattern (1760) may be electrically connected to the second transistor (T2, FIG. 15) through a contact hole (CNT'). The 15th conductive pattern (1760) may be a connection electrode that is connected to a data line (DL, FIG. 17) to be described later and transmits a data signal (DATA, FIG. 8) to the second transistor (T2, FIG. 15).

[0228] The 16th conductive pattern (1770) located in the second pixel circuit (PC2) may have an isolated shape. The 16th conductive pattern (1770) may electrically connect the fourth transistor (T4, FIG. 15) of the second pixel circuit (PC2) and the initialization voltage line (VL) described later with reference to FIG. 17. The 16th conductive pattern (1770) may be electrically connected to the fourth semiconductor layer (A4) of the fourth transistor (T4, FIG. 15) through a contact hole (CNT').

[0229] The fourth transistor (T4, FIG. 15) located in the first pixel circuit (PC1) may be electrically connected to an initialization voltage line (not shown) passing through the first pixel circuit (PC1) and an adjacent pixel circuit. For example, a part of the first semiconductor pattern (1510) of the first pixel circuit (PC1) may extend to an adjacent pixel circuit arranged in the (i)th row and the (j-1)th column, and the first semiconductor pattern (1510) of the first pixel circuit (PC1) may be electrically connected to an initialization voltage line passing through the adjacent pixel circuit.

[0230] The dummy conductive pattern (1770') located in the first pixel circuit (PC1) may have an isolated shape. The dummy conductive pattern (1770') may be electrically connected to the fourth oxide semiconductor pattern (1540) through a contact hole (CNT').

[0231] The 17th conductive pattern (1780) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may have an isolated shape. The 17th conductive pattern (1780) may be electrically connected to the 6th transistor (T6, FIG. 15). The 17th conductive pattern (1780) may be electrically connected to the 6th semiconductor layer (A6) and the 4th semiconductor layer (A4) through a contact hole (CNT'). The 17th conductive pattern (1780) may be electrically connected to the 1st oxide semiconductor pattern (1510) through the contact hole (CNT'), and the connection point between the 17th conductive pattern (1780) and the 1st oxide semiconductor pattern (1510) may be positioned between an area corresponding to the 6th semiconductor layer (A6) and an area corresponding to the 4th semiconductor layer (A4) among the 1st oxide semiconductor pattern (1510). The 17th challenge pattern (1780) may be a connection electrode connecting a pixel electrode of a light-emitting diode (LED, FIG. 8) and a fourth transistor (T4, FIG. 15) and a sixth transistor (T6, FIG. 15).

[0232] Referring to FIG. 17, a fifth conductive layer (1800) may be disposed on a fourth conductive layer (1700). The fifth conductive layer (1800) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials.

[0233] The fifth conductive layer (1800) may include a data line (DL), a data connection line (DVL), an initialization voltage line (VL), a reference voltage line (VRL), an eighteenth conductive pattern (1810), and a nineteenth conductive pattern (1820). The data line (DL), the data connection line (DVL), the initialization voltage line (VL), the reference voltage line (VRL), the eighteenth conductive pattern (1810), and the nineteenth conductive pattern (1820) may be arranged to be spaced apart from each other.

[0234] Referring to FIG. 17, each of the data line (DL), the data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) may extend along a second direction (e.g., the y direction). The data line (DL), the data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the first pixel circuit (PC1) and the data line (DL), the first data connection line (DVL), the initialization voltage line (VL), and the reference voltage line (VRL) passing through the second pixel circuit (PC2) may be substantially symmetrical with respect to the imaginary line (IML).

[0235] The data line (DL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the 15th conductive pattern (1760) described with reference to FIG. 16 through the first via contact hole (VCNT1), and can provide a data signal to the second transistor (T2, FIG. 15).

[0236] The data connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) can be electrically connected to pixel circuits arranged in different columns from the first pixel circuit (PC1) and the second pixel circuit (PC2).

[0237] An initialization voltage line (VL) passing through the second pixel circuit (PC2) is electrically connected to a 16th conductive pattern (1770, FIG. 16) located in the second pixel circuit (PC2) through a first via contact hole (VCNT1) to provide an initialization voltage to a 4th transistor (T4, FIG. 15) of the second pixel circuit (PC2).

[0238] An initialization voltage line (VL) passing through the first pixel circuit (PC1) can be electrically connected to a dummy conductive pattern (1770') described with reference to FIG. 16 through a first via contact hole (VCNT1). As described above with reference to FIG. 16, the fourth transistor (T4, FIG. 15) located in the first pixel circuit (PC1) can be electrically connected to an initialization voltage line (not shown) passing through an adjacent pixel circuit adjacent to the first pixel circuit (PC1).

[0239] A reference voltage line (VRL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2) is electrically connected to the 14th conductive pattern (1750) described with reference to FIG. 16 through the first via contact hole (VCNT1), and can provide a reference voltage to the third transistor (T3, FIG. 15).

[0240] The 18th conductive pattern (1810) and the 19th conductive pattern (1820) may have an isolated shape. The 18th conductive pattern (1810) located in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the 10th conductive pattern (1710) described with reference to FIG. 16 through the first via contact hole (VCNT1). The 10th conductive pattern (1710) and the 18th conductive pattern (1810) may be connection electrodes that transmit the driving voltage (ELVDD, FIG. 8) of the driving voltage line (PL, FIG. 18) to be described later to the hold capacitor (Chd, FIG. 8).

[0241] The 19th conductive pattern (1820) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the 17th conductive pattern (1780) described with reference to FIG. 16 through the first via contact hole (VCNT1). The 17th conductive pattern (1780) and the 19th conductive pattern (1820) may be connection electrodes that connect the pixel electrode of the light-emitting diode (LED, FIG. 8) to the fourth transistor (T4, FIG. 15) and the sixth transistor (T6, FIG. 15).

[0242] Referring to FIG. 18, a sixth conductive layer (1900) may be disposed on a fifth conductive layer (1800). The sixth conductive layer (1900) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu).

[0243] The sixth conductive layer (1900) may include a driving voltage line (PL) and a 20th conductive pattern (1955). The driving voltage line (PL) and the 20th conductive pattern (1955) may be arranged spaced apart from each other.

[0244] The driving voltage line (PL) may include main parts (1910) that are spaced apart from each other and bridge parts (1920, 1930) that connect the main parts (1910). The main parts (1910) and the bridge parts (1920, 1930) may be connected as one body. The connection structure of the main parts (1910) and the bridge parts (1920, 1930) may have a mesh shape on a plane.

[0245] The main portion (1910) may overlap with the voltage line or signal line below it in a third direction (e.g., z direction). In one embodiment, one of the main portions (1910) may be positioned on an imaginary line (IML) and may overlap with a data line (DL) and a data connection line (DVL) passing through each of the first pixel circuit (PC1) and the second pixel circuit (PC2). Another one of the main portions (1910) may overlap with a reference voltage line (VRL) passing through the first pixel circuit (PC1). Another one of the main portions (1910) may overlap with a reference voltage line (VRL) passing through the second pixel circuit (PC2). In one embodiment, the main portion (1910) may also overlap with a light-emitting area of ​​a light-emitting diode (LED, FIG. 8).

[0246] The bridge portions (1920, 1930) may extend along a first diagonal direction (OB1) and / or a second diagonal direction (OB2) intersecting a first direction (e.g., x-direction) and a second direction (e.g., y-direction). Each of the bridge portions (1920, 1930) may connect adjacent main portions (1910). In one embodiment, the first bridge portion (1920) of the bridge portions (1920, 1930) may extend along the first diagonal direction (OB1) to integrally connect two adjacent main portions (1910). The second bridge portion (1930) of the bridge portions (1920, 1930) may extend along the second diagonal direction (OB2) to integrally connect two adjacent main portions (1910).

[0247] In some embodiments, the driving voltage line (PL) may be electrically connected to a transistor or capacitor through a bridge portion (1920, 1930). For example, a second bridge portion (1930) passing through a first pixel circuit (PC1) may be electrically connected to an 18th conductive pattern (1810, FIG. 17) located in the first pixel circuit (PC1) through a second via contact hole (VCNT2). The 18th conductive pattern (1810, FIG. 17) may be electrically connected to a 10th conductive pattern (1710, FIG. 16) located in the first pixel circuit (PC1). The tenth conductive pattern (1710, FIG. 16) can be electrically connected to the second conductive pattern (1320, FIG. 12) including the first lower hold electrode (CEh1a, FIG. 12) of the hold capacitor (Chd, FIG. 8), the third oxide semiconductor pattern (1530, FIG. 14) including the first upper hold electrode (CEh1b, FIG. 14) of the hold capacitor (Chd, FIG. 8), and the fifth semiconductor layer (A5, FIG. 11) of the fifth transistor (T5, FIG. 12). Accordingly, the driving voltage of the driving voltage line (PL) can be transmitted to the fifth transistor (T5, FIG. 12) of the first pixel circuit (PC1) and the first hold electrode (CEh1, FIG. 8) of the hold capacitor (Chd, FIG. 8).

[0248] The 20th conductive pattern (1955) may have an isolated shape. The 20th conductive pattern (1955) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) may be electrically connected to the 19th conductive pattern (1820, FIG. 17) positioned in each of the first pixel circuit (PC1) and the second pixel circuit (PC2) through the second via contact hole (VCNT2). The 17th conductive pattern (1780, FIG. 16), the 19th conductive pattern (1820, FIG. 17), and the 20th conductive pattern (1955) may be connection electrodes that connect a pixel electrode of a light-emitting diode (LED, FIG. 8) to a fourth transistor (T4, FIG. 15) and a sixth transistor (T6, FIG. 15).

[0249] FIG. 19 is a schematic plan view of a portion of a display panel according to an embodiment of the present invention, which is an enlarged view of portion B of FIG. 9. FIG. 20 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention, which shows a cross-section taken along line I-I' of FIG. 19. For convenience of explanation, FIG. 19 illustrates a structure in which only a lower metal layer (1110, FIG. 10), a silicon semiconductor layer (1200, FIG. 11), a first conductive layer (1300, FIG. 12), a second conductive layer (1400, FIG. 13), an oxide semiconductor layer (1500, FIG. 14), a third conductive layer (1600, FIG. 15), and a fourth conductive layer (1700, FIG. 16) are accumulated.

[0250] First, referring to FIG. 20, the display panel (10) may include a pixel circuit layer (PCL) including transistors and capacitors arranged on a substrate (100), and a display element layer arranged on the pixel circuit layer (PCL) described above and including a light emitting diode (LED). The pixel circuit layer (PCL) may include the transistors and capacitors described above with reference to FIGS. 8 to 18, and FIG. 20 illustrates a first transistor (T1), a fifth transistor (T5), a storage capacitor (Cst), and a hold capacitor (Chd).

[0251] The substrate (100) may include a glass material, a ceramic material, a metal material, a plastic material, or a material having flexible or bendable properties. When the substrate (100) has flexible or bendable properties, the substrate (100) may include a polymer resin such as polyethersulfone (PES), polyacrylate, polyether imide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate, and cellulose acetate propionate (CAP).

[0252] The substrate (100) may have a single-layer or multi-layer structure of the above material, and in the case of a multi-layer structure, may further include an inorganic layer. For example, the substrate (100) may have a structure in which a layer including the aforementioned polymer resin and a barrier layer including an inorganic insulating material are alternately laminated.

[0253] A lower metal layer (1110) may be disposed on the substrate (100). As described above, the lower metal layer (1110) may include one or more materials selected from aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). In some embodiments, the lower metal layer (1110) may be a single layer including molybdenum, have a double layer structure in which a molybdenum layer and a titanium layer are stacked, or have a triple layer structure in which a titanium layer, an aluminum layer, and a titanium layer are stacked.

[0254] The lower metal layer (1110) may have a voltage level of a constant voltage. For example, the lower metal layer (1110) may have the same voltage level (e.g., driving voltage, ELVDD) as the driving voltage line (PL) described with reference to FIG. 8. The lower metal layer (1110) may shield light traveling to the fifth semiconductor layer (A5) of the fifth transistor (T5) and protect the fifth transistor (T5) from static electricity.

[0255] The lower metal layer (1110) may be electrically connected to a portion of the driving voltage line (PL, FIG. 6) or the first power supply wiring (15, FIG. 6) in an area other than the display area (DA, FIG. 6), for example, an outer area (PA, FIG. 6).

[0256] The buffer layer (101) may be disposed on the lower metal layer (1110). The buffer layer (101) may be an inorganic insulating layer including an inorganic insulating material such as silicon nitride and / or silicon oxide, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0257] A transistor including a silicon semiconductor layer may be arranged on the buffer layer (101). In this regard, FIG. 20 illustrates a fifth semiconductor layer (A5) of a fifth transistor (T5). The fifth semiconductor layer (A5) is a region included in the silicon semiconductor layer (1200, FIG. 11) and may be a silicon semiconductor layer including polysilicon. The fifth semiconductor layer (A5) may include a channel region (C5) and doped impurity regions (S5, D5) arranged on both sides of the channel region (C5). One of the doped regions (S5, D5) of the fifth semiconductor layer (A5) may be a source and the other may be a drain.

[0258] The first gate insulating layer (103) may be disposed on the fifth semiconductor layer (A5). The first gate insulating layer (103) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials.

[0259] The fifth gate electrode (G5) is disposed on the first gate insulating layer (103) and may overlap the channel region (C5) of the fifth semiconductor layer (A5) in the third direction (e.g., z direction). A sub-layer of the first storage electrode (CEs1) of the storage capacitor (Cst) and the first hold electrode (CEh1) of the hold capacitor (Chd), for example, a first lower hold electrode (CEh1a), may be disposed on the same layer as the fifth gate electrode (G5), for example, the first gate insulating layer (103). The fifth gate electrode (G5), the first storage electrode (CEs1), and the first lower hold electrode (CEh1a) may be a part of the first conductive layer (1300) described in FIG. 12.

[0260] The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include the same material. The fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-mentioned materials. In one embodiment, the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) may be a single layer including molybdenum.

[0261] The second gate insulating layer (105) may be disposed on the fifth gate electrode (G5), the first storage electrode (CEs1) of the storage capacitor (Cst), and the first lower hold electrode (CEh1a) of the hold capacitor (Chd). The second gate insulating layer (105) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second gate insulating layer (105) may include a different material from the first gate insulating layer (103). For example, the first gate insulating layer (103) may include silicon oxide, and the second gate insulating layer (105) may include silicon nitride.

[0262] The fifth conductive pattern (1410) may be disposed on the second gate insulating layer (105). The fifth conductive pattern (1410) may be a portion of the second conductive layer (1400) described in FIG. 13. The fifth conductive pattern (1410) may overlap the first storage electrode (CEs1) of the storage capacitor (Cst) and the first lower hold electrode (CEh1a) of the hold capacitor (Chd) in the third direction (e.g., the z direction). The fifth conductive pattern (1410) may include the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd). A portion of the fifth conductive pattern (1410) may be a second electrode (CEs2) of a storage capacitor (Cst), and another portion of the fifth conductive pattern (1410) may be a second hold electrode (CEh2) of a hold capacitor (Chd). In other words, the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd) may be connected integrally.

[0263] The fifth conductive pattern (1410), for example, the second storage electrode (CEs2) of the storage capacitor (Cst) and the second hold electrode (CEh2) of the hold capacitor (Chd), may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. In one embodiment, the fifth conductive pattern (1410) may be a single layer including molybdenum.

[0264] The first interlayer insulating layer (107) may be disposed on the fifth conductive pattern (1410). The first interlayer insulating layer (107) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. For example, the first interlayer insulating layer (107) may have a stacked structure of a layer including silicon oxide and a layer including silicon nitride.

[0265] The first semiconductor layer (A1) of the first transistor (T1) may be disposed on the first interlayer insulating layer (107). The first semiconductor layer (A1) of the first transistor (T1) may include an oxide semiconductor, and the oxide semiconductor may be an oxide semiconductor including at least one element selected from the group consisting of indium (In), gallium (Ga), stannum (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn). For example, the oxide semiconductor may include ITZO (InSnZnO) or IGZO (InGaZnO).

[0266] The first semiconductor layer (A1) may include a channel region (C1) and conductive regions (S1, D1) arranged on both sides of the channel region (C1). One of the conductive regions (S1, D1) may be a source and the other may be a drain. The first semiconductor layer (A1) may be arranged on a different layer from the fifth semiconductor layer (A5) described above. The vertical distance from the substrate (100) to the first semiconductor layer (A1) may be greater than the vertical distance from the substrate (100) to the fifth semiconductor layer (A5). The first semiconductor layer (A1) may be a portion of the first oxide semiconductor pattern (1510) described in FIG. 14.

[0267] The first upper hold electrode (CEh1b) of the hold capacitor (Chd) may be disposed on the same layer as the first semiconductor layer (A1) and may include the same material as the first semiconductor layer (A1). That is, the first upper hold electrode (CEh1b) of the hold capacitor (Chd) may be disposed on the first interlayer insulating layer (107). The first upper hold electrode (CEh1b) may be the third oxide semiconductor pattern (1530) described in FIG. 14. The entire area of ​​the third oxide semiconductor pattern (1530) may be conductive in order to function as the first upper hold electrode (CEh1b). For example, the entire area of ​​the third oxide semiconductor pattern (1530) may be a conductive area that has undergone plasma treatment.

[0268] Specifically, the oxide semiconductor layer (1500, FIG. 14) may have a property in which the conductive characteristics change depending on the oxygen content. In particular, a metal oxide semiconductor such as ITZO or IGZO may have the characteristics of a conductor or a semiconductor by appropriately controlling the oxygen content. The oxide semiconductor basically has the characteristics of a semiconductor, but if the oxygen content in the oxide semiconductor is reduced, the metallic properties are strengthened and the properties of a conductor can be obtained. A method for reducing the oxygen content of the oxide semiconductor may include the plasma treatment described above. When the plasma treatment is performed on the oxide semiconductor layer (1500, FIG. 14), the oxygen contained therein is removed, and the resistance of the oxide semiconductor is lowered, so that it can become a conductor. For example, the oxygen content of the conductive third oxide semiconductor pattern (1530) may be less than the oxygen content of the channel region (C1) of the first semiconductor layer (A1).

[0269] Referring to FIGS. 19 and 20, the storage capacitor (Cst) can be formed using a first conductive layer (1300, FIG. 12) and a second conductive layer (1400, FIG. 13). Specifically, the storage capacitor (Cst) can be formed in an area where the third conductive pattern (1330) of the first conductive layer (1300, FIG. 12) and the fifth conductive pattern (1410) of the second conductive layer (1400, FIG. 13) overlap in a third direction (e.g., z direction). At this time, the third conductive pattern (1330) can be a first storage electrode (CEs1) connected to a first node (N1, FIG. 8), and the fifth conductive pattern (1410) can be a second storage electrode (CEs2) connected to a second node (N2, FIG. 8).

[0270] In one embodiment, the hold capacitor (Chd) can be formed using a first conductive layer (1300, FIG. 12), a second conductive layer (1400, FIG. 13), and an oxide semiconductor layer (1500, FIG. 14). Specifically, the hold capacitor (Chd) can include a first sub-hold capacitor (Chd1) formed by overlapping the first conductive layer (1300, FIG. 12) and the second conductive layer (1400, FIG. 13) in a third direction (e.g., the z-direction), and a second sub-hold capacitor (Chd2) formed by overlapping the second conductive layer (1400, FIG. 13) and the oxide semiconductor layer (1500, FIG. 14) in a third direction (e.g., the z-direction). The first sub-hold capacitor (Chd1) may be formed in a region where the second conductive pattern (1320) of the first conductive layer (1300, FIG. 12) and the fifth conductive pattern (1410) of the second conductive layer (1400, FIG. 13) overlap in a third direction (e.g., z-direction). The second sub-hold capacitor (Chd2) may be formed in a region where the fifth conductive pattern (1410) of the second conductive layer (1400, FIG. 13) and the third oxide semiconductor pattern (1530) of the oxide semiconductor layer (1500, FIG. 14) overlap in a third direction (e.g., z-direction). At this time, the second conductive pattern (1320) may be a first lower hold electrode (CEh1a) which is a sub-layer of the first hold electrode (CEh1, FIG. 8), and the third oxide semiconductor pattern (1530) may be a first upper hold electrode (CEh1b) which is a sub-layer of the first hold electrode (CEh1, FIG. 8). The fifth conductive pattern (1410) may be a second hold electrode (CE2) which faces each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b). In conclusion, the second conductive pattern (1320), the fifth conductive pattern (1410), and the third oxide semiconductor pattern (1530) may be stacked to overlap each other to form a hold capacitor (Chd).

[0271] Meanwhile, the hold capacitor (Chd) is formed to stabilize the voltage of the second node (N2, FIG. 8), and a constant voltage can be applied to the first hold electrode (CEh1, FIG. 8) of the hold capacitor (Chd). That is, a constant voltage can be applied to each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b). In one embodiment, each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) can be electrically connected to the driving voltage line (PL). For example, the first upper hold electrode (CEh1b) can be electrically connected to the driving voltage line (PL) through the tenth conductive pattern (1710) and the eighteenth conductive pattern (1810, FIG. 10) to receive the driving voltage (ELVDD, FIG. 8). Likewise, the first lower hold electrode (CEh1a) is electrically connected to the driving voltage line (PL) through the tenth conductive pattern (1710) and the eighteenth conductive pattern (1810, FIG. 10) so that the driving voltage (ELVDD, FIG. 8) can be applied thereto. In other words, the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) are arranged on different layers, but are electrically connected to each other so that the same constant voltage can be applied thereto.

[0272] By forming the hold capacitor (Chd) with the structure described above, the hold capacitor (Chd) of the display device according to an embodiment of the present invention can have a high storage capacity. Specifically, compared to the case where only the first sub-hold capacitor (Chd1) is formed using the first conductive layer (1300, FIG. 12) and the second conductive layer (1400, FIG. 13), by additionally forming the second sub-hold capacitor (Chd2) using the second conductive layer (1400, FIG. 13) and the oxide semiconductor layer (1500, FIG. 14) in addition to the first sub-hold capacitor (Chd1), the capacity of the hold capacitor (Chd) can be significantly increased while using the same pixel circuit area. Accordingly, the display panel (10) according to one embodiment of the present invention can minimize the voltage change of the second node (N2, FIG. 8) and drive the pixel circuit (PC, FIG. 8) more stably while maintaining high resolution by increasing the capacity of the hold capacitor (Chd).

[0273] In addition, as described above, a second gate insulating layer (105) may be interposed between the first lower hold electrode (CEh1a) and the second hold electrode (CEh2), and a first interlayer insulating layer (107) may be interposed between the second hold electrode (CEh2) and the first upper hold electrode (CEh1b). In one embodiment, as the thickness of the second gate insulating layer (105) is reduced, the storage capacity of the first sub-hold capacitor (Chd1) may increase, and as the thickness of the first interlayer insulating layer (107) is reduced, the storage capacity of the second sub-hold capacitor (Chd2) may increase.

[0274] For example, when the hold capacitor (Chd) has a first sub-hold capacitor (Chd1) and a second sub-hold capacitor (Chd2), and the thicknesses of the second gate insulating layer (105) and the first interlayer insulating layer (107) are each 500 Å, the capacitance of the hold capacitor (Chd) can increase by 30 fF compared to the case where the hold capacitor (Chd) has only the first sub-hold capacitor (Chd1). When the hold capacitor (Chd) has a first sub-hold capacitor (Chd1) and a second sub-hold capacitor (Chd2), and the thicknesses of the second gate insulating layer (105) and the first interlayer insulating layer (107) are each 1000 Å, the capacitance of the hold capacitor (Chd) can increase by 15 fF compared to the case where the hold capacitor (Chd) has only the first sub-hold capacitor (Chd1). In conclusion, by additionally forming a second sub-hold capacitor (Chd2) using an oxide semiconductor layer (1500, FIG. 14) and minimizing the thickness of the insulating layers interposed between the hold capacitors (Chd), the storage capacity of the hold capacitor (Chd) can be significantly increased.

[0275] Referring again to FIG. 20, the third gate insulating layer (109) may be disposed on the first semiconductor layer (A1) and the first upper hold electrode (CEh1b) of the hold capacitor (Chd). The third gate insulating layer (109) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the third gate insulating layer (109) may be a single-layer including silicon oxide.

[0276] Although FIG. 20 illustrates that the third gate insulating layer (109) passes through the side surface of the first semiconductor layer (A1) and contacts the upper surface of the first interlayer insulating layer (107), the present invention is not limited thereto. In another embodiment, the third gate insulating layer (109) may be formed to have substantially the same pattern and / or the same width as the first gate electrode (G1) described later. In other words, the third gate insulating layer (109) may not pass through the side surface of the first semiconductor layer (A1) and contact the upper surface of the first interlayer insulating layer (107).

[0277] The first gate electrode (G1) may be disposed on the third gate insulating layer (109). The first gate electrode (G1) may overlap the channel region (C1) of the first semiconductor layer (A1) in a third direction (e.g., z direction). The first gate electrode (G1) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the first gate electrode (G1) may have a three-layer structure of titanium layer / aluminum layer / titanium layer.

[0278] The second interlayer insulating layer (111) may be disposed on the first gate electrode (G1). The second interlayer insulating layer (111) may be an inorganic insulating layer including an inorganic insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride, and may have a single-layer or multi-layer structure including the aforementioned materials. In one embodiment, the second interlayer insulating layer (111) may have a stacked structure of a layer including silicon nitride and a layer including silicon oxynitride.

[0279] The tenth conductive pattern (1710), the eleventh conductive pattern (1720), and the twelfth conductive pattern (1730) may be disposed on the same layer, for example, the second interlayer insulating layer (111). The tenth conductive pattern (1710), the eleventh conductive pattern (1720), and the twelfth conductive pattern (1730) may include the same material. The tenth conductive pattern (1710), the eleventh conductive pattern (1720), and the twelfth conductive pattern (1730) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the aforementioned materials. In one embodiment, the tenth conductive pattern (1710), the eleventh conductive pattern (1720), and the twelfth conductive pattern (1730) may have a three-layer structure of titanium layer / aluminum layer / titanium layer. The 10th challenge pattern (1710), the 11th challenge pattern (1720), and the 12th challenge pattern (1730) may be a portion of the 4th challenge layer (1700) described in FIG. 16.

[0280] The first organic insulating layer (113) may be disposed on the tenth conductive pattern (1710), the eleventh conductive pattern (1720), and the twelfth conductive pattern (1730). The first organic insulating layer (113) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0281] The data line (DL) and the initialization voltage line (VL) may be arranged on the first organic insulating layer (113). The data line (DL) and the initialization voltage line (VL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the data line (DL) and the initialization voltage line (VL) may have a three-layer structure of titanium layer / aluminum layer / titanium layer. The data line (DL) and the initialization voltage line (VL) may be a portion of the fifth conductive layer (1800) described in FIG. 17.

[0282] The second organic insulating layer (115) may be placed on the data line (DL) and the initialization voltage line (VL). The second organic insulating layer (115) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0283] The driving voltage line (PL) may be disposed on the second organic insulating layer (115). The driving voltage line (PL) may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and / or copper (Cu), and may be formed as a single layer or multiple layers including the above-described materials. In one embodiment, the driving voltage line (PL) may have a three-layer structure of titanium layer / aluminum layer / titanium layer. The driving voltage line (PL) may be a portion of the sixth conductive layer (1900) described in FIG. 18.

[0284] The third organic insulating layer (117) may be placed on the driving voltage line (PL). The third organic insulating layer (117) may include an organic insulating material such as acrylic, BCB (Benzocyclobutene), polyimide, or HMDSO (Hexamethyldisiloxane).

[0285] A light emitting diode (LED) may be disposed on the third organic insulating layer (117). The light emitting diode (LED) may include a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) on the third organic insulating layer (117).

[0286] An outer portion of the pixel electrode (210) may be covered in a third direction (e.g., z direction) by the bank layer (119), and an inner portion of the pixel electrode (210) may overlap an intermediate layer (220) in a third direction (e.g., z direction) through an opening (119OP) of the bank layer (119). The pixel electrode (210) may be arranged to correspond to each light emitting diode (LED), and the counter electrode (230) may be arranged to correspond to a plurality of light emitting diodes (LED). In other words, the counter electrode (230) may extend to overlap a plurality of pixel electrodes (210) in a third direction (e.g., z direction). A plurality of light emitting diodes (LEDs) may share a counter electrode (230), and a stacked structure of a pixel electrode (210), an intermediate layer (220), and a counter electrode (230) may correspond to a light emitting diode (LED).

[0287] The intermediate layer (220) may include an emission layer. In some embodiments, the intermediate layer (220) may further include an emission layer and a functional layer. The functional layer may include a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and / or an electron injection layer (EIL). In some further embodiments, the intermediate layer (220) may include a first stack including an emission layer and a functional layer, a second stack including an emission layer and a functional layer, and a charge generation layer between the first stack and the second stack. The charge generation layer may include a negative charge generation layer and a positive charge generation layer. The light emission efficiency of a tandem light emitting diode (LED) including a plurality of emission layers can be further increased by the negative charge generation layer and the positive charge generation layer.

[0288] The negative charge generation layer may be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material. The positive charge generation layer may be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer may include a host and a dopant. The host may include an organic material. The dopant may include a metallic material.

[0289] The counter electrode (230) may be formed of a conductive material having a low work function. The counter electrode (230) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the counter electrode (230) may further include a layer such as ITO, IZO, ZnO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0290] Although not shown, an encapsulation layer may be disposed on the light emitting diode (LED). The encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer therebetween.

[0291] Fig. 21 is a schematic equivalent circuit diagram of a light emitting diode and a pixel circuit of a display panel according to another embodiment of the present invention, and Fig. 22 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Referring to Figs. 21 and 22, except for the feature of the hold capacitor (Chd), other features are the same as those described with reference to Figs. 8 to 20. The same reference numerals among the components of Figs. 21 and 22 replace those described with reference to Figs. 8 to 20, and the following description focuses on the differences.

[0292] First, referring to FIG. 21, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. In one embodiment, the pixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, T6), a storage capacitor (Cst), and a hold capacitor (Chd).

[0293] In one embodiment, a hold capacitor (Chd) may be connected between a reference voltage line (VRL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be connected to the reference voltage line (VRL), and a second hold electrode (CEh2) may be connected to a second node (N2). The hold capacitor (Chd) may allow the voltage of the lower gate electrode of the first transistor (T1) and the second node (N2) to remain constant and have a constant voltage even when a peripheral signal fluctuates.

[0294] Next, referring to Fig. 22, a plurality of transistors and capacitors may be arranged on the substrate (100). For convenience of explanation, Fig. 22 only illustrates the first transistor (T1), the storage capacitor (Cst), and the hold capacitor (Chd).

[0295] A first lower hold electrode (CEh1a), which is a sub-layer of a first storage electrode (CEs1) of a storage capacitor (Cst) and a first hold electrode (CEh1) of a hold capacitor (Chd), may be disposed on a first gate insulating layer (103). A second gate insulating layer (105) may be disposed on the first storage electrode (CEs1) and the first lower hold electrode (CEh1a), and a second conductive layer (1400, FIG. 13) may be disposed on the second gate insulating layer (105). The second conductive layer (1400, FIG. 13) may include a second storage electrode (CEs2) overlapping the first storage electrode (CEs1) in a third direction (e.g., z direction) and a second hold electrode (CEh2) overlapping the first lower hold electrode (CEh1a) in a third direction (e.g., z direction). The second storage electrode (CEs2) and the second hold electrode (CEh2) can be connected as one body.

[0296] A first interlayer insulating layer (107) may be disposed on the second storage electrode (CEs2) and the second hold electrode (CEh2), and an oxide semiconductor layer (1500, FIG. 14) may be disposed on the first interlayer insulating layer (107). The oxide semiconductor layer (1500, FIG. 14) may include a channel region (C1) of the first transistor (T1) and conductive regions (S1, D1) on both sides of the channel region. In addition, the oxide semiconductor layer (1500, FIG. 14) may include a first upper hold electrode (CEh1b), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd). The first upper hold electrode (CEh1b) may overlap the second hold electrode (CEh2) in a third direction (e.g., z direction). The first upper hold electrode (CEh1b) may be a conductive portion of the oxide semiconductor layer (1500, FIG. 14).

[0297] To summarize, the storage capacitor (Cst) may be formed by overlapping a first storage electrode (CEs1) disposed on a first conductive layer (1300, FIG. 12) and a second storage electrode (CEs2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The hold capacitor (Chd) may include a first sub-hold capacitor (Chd1) and a second sub-hold capacitor (Chd2) disposed to overlap each other. The first sub-hold capacitor (Chd1) may be formed by overlapping a first lower hold electrode (CEh1a) disposed on a first conductive layer (1300, FIG. 12) and a second hold electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The second sub-hold capacitor (Chd2) can be formed by overlapping a second hold electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) and a first upper hold electrode (CEh1b) disposed on an oxide semiconductor layer (1500, FIG. 14) in a third direction (e.g., z direction).

[0298] Meanwhile, the hold capacitor (Chd) is formed to stabilize the voltage of the second node (N2), and a constant voltage can be applied to the first hold electrode (CEh1) of the hold capacitor (Chd). That is, a constant voltage can be applied to each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b). In one embodiment, each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) can be electrically connected to a reference voltage line (VRL). For example, as shown in FIG. 22, the first upper hold electrode (CEh1b) can be electrically connected to the reference voltage line (VRL) disposed on the fifth conductive layer (1800, FIG. 17) through the first bridge electrode (BE1), and can receive the reference voltage (VREF). In Fig. 22, the structure in which the first lower hold electrode (CEh1a) and the reference voltage line (VRL) are connected is not shown, but the first lower hold electrode (CEh1a) can also be connected to the reference voltage line (VRL) through a plurality of bridge electrodes and receive a reference voltage (Vref).

[0299] By forming the hold capacitor (Chd) with the above structure, the hold capacitor (Chd) of the display device according to an embodiment of the present invention can have a high storage capacity. Specifically, compared to the case where only the first sub-hold capacitor (Chd1) is formed using the first conductive layer (1300, FIG. 12) and the second conductive layer (1400, FIG. 13), by additionally forming the second sub-hold capacitor (Chd2) using the second conductive layer (1400, FIG. 13) and the oxide semiconductor layer (1500, FIG. 14) in addition to the first sub-hold capacitor (Chd1), the capacity of the hold capacitor (Chd) can be significantly increased while using the same pixel circuit area. Accordingly, the display panel (10) according to an embodiment of the present invention can maintain a high resolution while increasing the capacity of the hold capacitor (Chd), thereby minimizing the voltage change of the second node (N2), and driving the pixel circuit (PC) more stably.

[0300] Fig. 23 is a schematic equivalent circuit diagram of a light emitting diode and a pixel circuit of a display panel according to another embodiment of the present invention, and Fig. 24 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Referring to Figs. 23 and 24, except for the features of the hold capacitor (Chd) and the auxiliary hold capacitor (Chd'), other features are the same as those described with reference to Figs. 8 to 20. The same reference numerals among the components of Figs. 23 and 24 replace those described with reference to Figs. 8 to 20, and the following description focuses on the differences.

[0301] First, referring to FIG. 23, a pixel circuit (PC) connected to a light emitting diode (LED) may include a plurality of transistors and a plurality of capacitors. In one embodiment, the pixel circuit (PC) may include first to sixth transistors (T1, T2, T3, T4, T5, T6), a storage capacitor (Cst), a hold capacitor (Chd), and an auxiliary hold capacitor (Chd').

[0302] In one embodiment, a hold capacitor (Chd) may be connected between a driving voltage line (PL) and a second node (N2). A first hold electrode (CEh1) of the hold capacitor (Chd) may be connected to the driving voltage line (PL), and a second hold electrode (CEh2) may be connected to a second node (N2). In one embodiment, the pixel circuit (PC) may further include an auxiliary hold capacitor (Chd') in addition to the hold capacitor (Chd). The auxiliary hold capacitor (Chd') may be connected between a lower gate electrode of the first transistor (T1) and a reference voltage line (VRL). A third hold electrode (CEh3) of the auxiliary hold capacitor (Chd') may be connected to the reference voltage line (VRL), and a fourth hold electrode (CEh4) may be connected to a lower gate electrode of the first transistor (T1) and the second node (N2). The hold capacitor (Chd) and the auxiliary hold capacitor (Chd') ensure that the voltage of the lower gate electrode of the first transistor (T1) and the second node (N2) does not fluctuate and has a constant voltage even when the surrounding signal fluctuates.

[0303] Next, referring to Fig. 24, a plurality of transistors and capacitors may be arranged on the substrate (100). For convenience of explanation, Fig. 24 only illustrates the first transistor (T1), the storage capacitor (Cst), the hold capacitor (Chd), and the auxiliary hold capacitor (Chd').

[0304] On the first gate insulating layer (103), a first storage electrode (CEs1) of a storage capacitor (Cst), a first lower hold electrode (CEh1a) which is a sub-layer of a first hold electrode (CEh1) of a hold capacitor (Chd), and a third lower hold electrode (CEh3a) which is a sub-layer of a third hold electrode (CEh3) of an auxiliary hold capacitor (Chd') may be arranged. The first storage electrode (CEs1), the first lower hold electrode (CEh1a), and the third lower hold electrode (CEh3a) may be arranged on the same layer and may include the same material.

[0305] A second gate insulating layer (105) may be disposed on the first storage electrode (CEs1), the first lower hold electrode (CEh1a), and the third lower hold electrode (CEh3a), and a second conductive layer (1400, FIG. 13) may be disposed on the second gate insulating layer (105). The second conductive layer (1400, FIG. 13) may include a second storage electrode (CEs2) overlapping the first storage electrode (CEs1) in a third direction (e.g., z direction), a second hold electrode (CEh2) overlapping the first lower hold electrode (CEh1a), and a fourth hold electrode (CEh4) overlapping the third lower hold electrode (CEh3a) in a third direction (e.g., z direction). The second storage electrode (CEs2), the second hold electrode (CEh2), and the fourth hold electrode (CEh4) can be connected as one body.

[0306] A first interlayer insulating layer (107) may be disposed on the second storage electrode (CEs2), the second hold electrode (CEh2), and the fourth hold electrode (CEh4), and an oxide semiconductor layer (1500, FIG. 14) may be disposed on the first interlayer insulating layer (107). The oxide semiconductor layer (1500, FIG. 14) may include a channel region (C1) of the first transistor (T1) and conductive regions (S1, D1) on both sides of the channel region. In addition, the oxide semiconductor layer (1500, FIG. 14) may include a first upper hold electrode (CEh1b), which is a sublayer of the first hold electrode (CEh1) of the hold capacitor (Chd), and a third upper hold electrode (CEh3b), which is a sublayer of the third hold electrode (CEh3) of the auxiliary hold capacitor (Chd'). The first upper hold electrode (CEh1b) may overlap the second hold electrode (CEh2) in a third direction (e.g., z direction), and the third upper hold electrode (CEh3b) may overlap the fourth hold electrode (CEh4) in a third direction (e.g., z direction). The first upper hold electrode (CEh1b) and the third upper hold electrode (CEh3b) may be conductive portions of the oxide semiconductor layer (1500, FIG. 14).

[0307] To summarize, the storage capacitor (Cst) may be formed by overlapping a first storage electrode (CEs1) disposed on a first conductive layer (1300, FIG. 12) and a second storage electrode (CEs2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The hold capacitor (Chd) may include a first sub-hold capacitor (Chd1) and a second sub-hold capacitor (Chd2) disposed so as to overlap each other in a third direction (e.g., z direction). The first sub-hold capacitor (Chd1) may be formed by overlapping a first lower hold electrode (CEh1a) disposed on a first conductive layer (1300, FIG. 12) and a second hold electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The second hold capacitor (Chd2) can be formed by overlapping a second hold electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) and a first upper hold electrode (CEh1b) disposed on an oxide semiconductor layer (1500, FIG. 14) in a third direction (e.g., z direction).

[0308] The auxiliary hold capacitor (Chd') may include a third sub-hold capacitor (Chd3) and a fourth sub-hold capacitor (Chd4) arranged to overlap each other in a third direction (e.g., z-direction). The third sub-hold capacitor (Chd3) may be formed by overlapping a third lower hold electrode (CEh3a) arranged on a first conductive layer (1300, FIG. 12) and a fourth hold electrode (CEh4) arranged on a second conductive layer (1400, FIG. 13) in the third direction (e.g., z-direction). The fourth sub-hold capacitor (Chd4) may be formed by overlapping a fourth hold electrode (CEh4) arranged on a second conductive layer (1400, FIG. 13) and a third upper hold electrode (CEh3b) arranged on an oxide semiconductor layer (1500, FIG. 14).

[0309] Meanwhile, the hold capacitor (Chd) and the auxiliary hold capacitor (Chd') are formed to stabilize the voltage of the second node (N2), and a constant voltage can be applied to the first hold electrode (CEh1) of the hold capacitor (Chd) and the third hold electrode (CEh3) of the auxiliary hold capacitor (Chd'). That is, a constant voltage can be applied to each of the first lower hold electrode (CEh1a), the first upper hold electrode (CEh1b), the third lower hold electrode (CEh3a), and the third upper hold electrode (CEh3b).

[0310] In one embodiment, each of the first lower hold electrode (CEh1a) and the first upper hold electrode (CEh1b) may be electrically connected to a driving voltage line (PL). For example, as shown in FIG. 24, the first upper hold electrode (CEh1b) may be electrically connected to a driving voltage line (PL) disposed on the sixth conductive layer (1900, FIG. 18) through the first bridge electrode (BE1) and the second bridge electrode (BE2), and may receive a driving voltage (ELVDD). Although the structure in which the first lower hold electrode (CEh1b) and the driving voltage line (PL) are connected is not shown in FIG. 24, the first lower hold electrode (CEh1a) may also be connected to the driving voltage line (PL) through a plurality of bridge electrodes, and may receive a driving voltage (ELVDD).

[0311] Likewise, in one embodiment, each of the third lower hold electrode (CEh3a) and the third upper hold electrode (CEh3b) may be electrically connected to the reference voltage line (VRL). For example, as shown in FIG. 24, the third upper hold electrode (CEh3b) may be electrically connected to the reference voltage line (VRL) disposed on the fifth conductive layer (1800, FIG. 17) through the third bridge electrode (BE3) to receive the reference voltage (VREF). Although the structure in which the third lower hold electrode (CEh3a) and the reference voltage line (VRL) are connected is not shown in FIG. 24, the third lower hold electrode (CEh3a) may also be connected to the reference voltage line (VRL) through a plurality of bridge electrodes to receive the reference voltage (VREF).

[0312] By forming the hold capacitor (Chd) and the auxiliary hold capacitor (Chd') with the structure as described above, the hold capacitor (Chd) and the auxiliary hold capacitor (Chd') of the display device according to an embodiment of the present invention can have a high storage capacity. In the case of the display device as in Fig. 24, in addition to the hold capacitor (Chd) including the first sub-hold capacitor (Chd1) and the second sub-hold capacitor (Chd2), an auxiliary hold capacitor (Chd') including the third sub-hold capacitor (Chd3) and the fourth sub-hold capacitor (Chd4) is additionally arranged, so that the storage capacity of the capacitor can be significantly increased. Accordingly, the display panel (10) according to an embodiment of the present invention can maintain a high resolution while increasing the capacity of the capacitor, thereby minimizing the voltage change of the second node (N2), and driving the pixel circuit (PC) more stably.

[0313] Fig. 25 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Referring to Fig. 25, except for the characteristics of the storage capacitor (Cst) and the hold capacitor (Chd), the other characteristics are the same as those described with reference to Figs. 8 to 20. The same reference numerals among the components in Fig. 25 are replaced with those described with reference to Figs. 8 to 20, and the following description focuses on the differences.

[0314] Referring to Fig. 25, a plurality of transistors and capacitors may be arranged on the substrate (100). For convenience of explanation, Fig. 25 only illustrates the first transistor (T1), the storage capacitor (Cst), and the hold capacitor (Chd).

[0315] In one embodiment, the storage capacitor (Cst) may include a first sub-storage capacitor (Cst1) and a second sub-storage capacitor (Cst2). Specifically, a first lower storage electrode (CEs1a), which is a sub-layer of a first storage electrode (CEs1, FIG. 8) of the storage capacitor (Cst), and a first hold electrode (CEh1) of a hold capacitor (Chd) may be disposed on the first gate insulating layer (103). The first lower storage electrode (CEs1a) and the first hold electrode (CEh1) are portions of a first conductive layer (1300, FIG. 12) and may include the same material.

[0316] A second gate insulating layer (105) may be disposed on the first lower storage electrode (CEs1a) and the first hold electrode (CEh1), and a second conductive layer (1400, FIG. 13) may be disposed on the second gate insulating layer (105). The second conductive layer (1400, FIG. 13) may include a second storage electrode (CEs2) overlapping the first lower storage electrode (CEs1a) in a third direction (e.g., z direction) and a second hold electrode (CEh2) overlapping the first hold electrode (CEh1) in a third direction (e.g., z direction). The first hold electrode (CEh1) and the second hold electrode (CEh2) may be connected integrally.

[0317] A first interlayer insulating layer (107) may be disposed on the second storage electrode (CEs2) and the second hold electrode (CEh2), and an oxide semiconductor layer (1500, FIG. 14) may be disposed on the first interlayer insulating layer (107). The oxide semiconductor layer (1500, FIG. 14) may include a channel region (C1) of the first transistor (T1) and conductive regions (S1, D1) on both sides of the channel region. In addition, the oxide semiconductor layer (1500, FIG. 14) may include a first upper storage electrode (CEs1b), which is a sublayer of the first storage electrode (CEs1, FIG. 8) of the storage capacitor (Cst). The first upper storage electrode (CEs1b) may be a conductive portion of the oxide semiconductor layer (1500, FIG. 14). The region overlapping the first upper storage electrode (CEs1b) in the third direction (e.g., z direction) of the second challenge layer (1400, Fig. 13) can be another second storage electrode (CEs2).

[0318] To summarize, the hold capacitor (Chd) may be formed by overlapping a first hold electrode (CEh1) disposed on a first conductive layer (1300, FIG. 12) and a second hold electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The storage capacitor (Cst) may include a first sub-storage capacitor (Cst1) and a second sub-storage capacitor (Cst2). The first sub-storage capacitor (Cst1) may be formed by overlapping a first lower storage electrode (CEs1a) disposed on a first conductive layer (1300, FIG. 12) and a second storage electrode (CEh2) disposed on a second conductive layer (1400, FIG. 13) in a third direction (e.g., z direction). The second sub-storage capacitor (Chd2) can be formed by overlapping a second storage electrode (CEs2) disposed on a second conductive layer (1400, FIG. 13) and a first upper storage electrode (CEs1b) disposed on an oxide semiconductor layer (1500, FIG. 14) in a third direction (e.g., z direction).

[0319] At this time, the storage capacitor (Cst) is connected between the first node (N1) and the second node (N2), and the second storage electrode (CEs2) is connected to the second node (N2), so that each of the first lower storage electrode (CEs1a) and the first upper storage electrode (CEs1b) can be connected to the first node (N1). Specifically, each of the first lower storage electrode (CEs1a) and the first upper storage electrode (CEs1b) can be connected to the 12th conductive pattern (1730) corresponding to the first node (N1).

[0320] By forming the storage capacitor (Cst) with the above structure, the storage capacitor (Cst) of the display device according to an embodiment of the present invention can have a high storage capacity. Specifically, compared to the case where only the first sub-storage capacitor (Cst1) is formed using the first conductive layer (1300, FIG. 12) and the second conductive layer (1400, FIG. 13), by additionally forming the second sub-storage capacitor (Cst2) using the second conductive layer (1400, FIG. 13) and the oxide semiconductor layer (1500, FIG. 14) in addition to the first sub-storage capacitor (Cst1), the capacity of the storage capacitor (Cst) can be significantly increased while using the same pixel circuit area. Accordingly, the display panel (10) according to an embodiment of the present invention can maintain a high resolution while increasing the capacity of the storage capacitor (Cst), thereby minimizing the voltage change of the first node (N1, FIG. 8), and driving the pixel circuit (PC) more stably.

[0321] Embodiments have been disclosed herein, and the terms used are intended to be generic and descriptive rather than limiting. As will be apparent to those skilled in the art, features, characteristics, and / or components described in connection with any embodiment may be used alone or in combination with features, characteristics, and / or components described in connection with other embodiments, unless otherwise specified. Accordingly, it will be apparent to those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the present disclosure as set forth in the claims below.

Claims

1. Substrate; A pixel circuit layer disposed on the substrate and including a first pixel circuit; and A light emitting diode electrically connected to the first pixel circuit; The above pixel circuit layer is, A first conductive layer including a first conductive pattern disposed on the substrate; A second conductive layer disposed on the first conductive layer and including a second conductive pattern partially overlapping the first conductive pattern; and A first semiconductor layer including a first semiconductor pattern disposed on the second conductive layer and overlapping the second conductive pattern; The above first semiconductor pattern is a conductive display panel.

2. In paragraph 1, A display panel, wherein the first semiconductor layer includes an oxide semiconductor material.

3. In paragraph 1, A display panel in which a constant voltage is applied to the first conductive pattern and the first semiconductor pattern.

4. In paragraph 1, The above first pixel circuit, A first transistor connected between a driving voltage line and the light emitting diode; A storage capacitor connected between a first node to which the gate electrode of the first transistor is connected and a second node to which the first electrode of the first transistor is connected; and A display panel comprising a hold capacitor connected to the second node.

5. In paragraph 4, The first semiconductor layer further includes a second semiconductor pattern disposed on the same layer as the first semiconductor pattern and including a channel region of the first transistor, A display panel in which the first semiconductor pattern and the second semiconductor pattern are spaced apart from each other.

6. In paragraph 4, The above hold capacitor includes a first sub-hold capacitor and a second sub-hold capacitor that are formed to overlap each other, The first sub-hold capacitor is formed by overlapping a portion of the second conductive pattern with the first conductive pattern, A display panel in which the second sub-hold capacitor is formed by overlapping a portion of the second conductive pattern and the first semiconductor pattern.

7. In paragraph 4, The display panel, wherein the above-mentioned hold capacitor is connected between the second node and the driving voltage line.

8. In paragraph 4, A display panel in which the first conductive pattern and the first semiconductor pattern are electrically connected to the driving voltage line and receive the same driving voltage.

9. In paragraph 4, The above first pixel circuit, a second transistor connected between the data line and the first node; and A display panel further comprising a third transistor connected between a reference voltage line and the first node.

10. In paragraph 9, The above holding capacitor is connected between the second node and the driving voltage line, The first pixel circuit further includes an auxiliary hold capacitor connected between the lower gate electrode of the first transistor and the reference voltage line; The above auxiliary hold capacitor includes a third sub-hold capacitor and a fourth sub-hold capacitor that are formed to overlap each other, The first conductive layer further includes a third conductive pattern arranged spaced apart from the first conductive pattern, The first semiconductor layer is arranged to be spaced apart from the first semiconductor pattern, and further includes a conductive third semiconductor pattern, The third sub-hold capacitor is formed by overlapping a portion of the second conductive pattern and the third conductive pattern, A display panel in which the fourth sub-hold capacitor is formed by overlapping a portion of the second conductive pattern and the third semiconductor pattern.

11. In paragraph 4, The first conductive layer further includes a fourth conductive pattern disposed on the same layer as the first conductive pattern, but spaced apart from the first conductive pattern. A display panel in which the second challenge pattern is extended and partially overlaps with the fourth challenge pattern.

12. In paragraph 11, The above storage capacitor includes a first sub-storage capacitor and a second sub-storage capacitor, The first sub-storage capacitor is formed by overlapping a portion of the second conductive pattern and the fourth conductive pattern, The second sub-storage capacitor is formed by overlapping a portion of the second conductive pattern and the first semiconductor pattern, A display panel in which the first semiconductor pattern is electrically connected to an electrode corresponding to the first node.

13. In paragraph 4, The first pixel circuit further includes a fourth transistor connected between the driving voltage line and the first transistor; The pixel circuit layer further includes a second semiconductor layer including a channel region of the fourth transistor; The second semiconductor layer is disposed between the substrate and the first conductive layer, A display panel, wherein the second semiconductor layer comprises a silicon semiconductor material.

14. Display panel; and A lower cover forming an exterior and having an opening exposing a portion of the display panel on the front surface, The above display panel, substrate; A pixel circuit layer disposed on the substrate and including a first pixel circuit; and A light emitting diode electrically connected to the first pixel circuit; The above pixel circuit layer is, A first conductive layer including a first conductive pattern disposed on the substrate; A second conductive layer disposed on the first conductive layer and including a second conductive pattern partially overlapping the first conductive pattern; and A first semiconductor layer including a first semiconductor pattern disposed on the second conductive layer and overlapping the second conductive pattern; The above first semiconductor pattern is a conductive, electronic device.

15. In paragraph 14, An electronic device, wherein the first semiconductor layer comprises an oxide semiconductor material.

16. In paragraph 14, An electronic device in which a constant voltage is applied to the first conductive pattern and the first semiconductor pattern.

17. In paragraph 14, The above first pixel circuit, A first transistor connected between a driving voltage line and the light emitting diode; A storage capacitor connected between a first node to which the gate electrode of the first transistor is connected and a second node to which the first electrode of the first transistor is connected; and An electronic device comprising a hold capacitor connected to the second node.

18. In paragraph 17, The above hold capacitor includes a first sub-hold capacitor and a second sub-hold capacitor that are formed to overlap each other, The first sub-hold capacitor is formed by overlapping a portion of the second conductive pattern with the first conductive pattern, An electronic device in which the second sub-hold capacitor is formed by overlapping a portion of the second conductive pattern and the first semiconductor pattern.

19. In paragraph 17, An electronic device wherein the above-mentioned hold capacitor is connected between the second node and the driving voltage line.

20. In paragraph 17, An electronic device in which the first conductive pattern and the first semiconductor pattern are electrically connected to the driving voltage line and receive the same driving voltage.

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