Cholesteric liquid crystal display device and power recovery method thereof

Abstract

The present invention provides a cholesteric liquid crystal display device and a power recovery method thereof. The cholesteric liquid crystal display device comprises: a charging control circuit used for selecting an input power supply to generate output voltage; a boost circuit used for boosting the output voltage to generate a positive voltage signal and a negative voltage signal; a power management circuit used for generating multiple sets of positive voltage drive signals and multiple sets of negative voltage drive signals on the basis of the positive voltage signal and the negative voltage signal, wherein each of the positive voltage drive signals and each of the negative voltage drive signals are connected to a corresponding first bypass capacitor and second bypass capacitor; a power storage device; a cholesteric liquid crystal display panel; and a timing controller used for controlling the timing of display images on the cholesteric liquid crystal display panel. When a display image reset program or a display image update program of the cholesteric liquid crystal display panel executed by the timing controller is completed, the timing controller executes a power recovery mechanism to turn on a first switching circuit, such that each of the first bypass capacitors and each of the second bypass capacitors transmit stored charge to the power storage device through a first discharge path and a second discharge path, respectively, so as to charge the power storage device.

Description

Cholesterol Liquid Crystal Display Device and its Power Recovery Method Technical Field

[0001] This invention relates to display devices, and more particularly to a cholesterol liquid crystal display device and its power recovery method. Background Technology

[0002] Cholesteric liquid crystal displays (Ch-LCDs) possess bistable properties, allowing them to retain displayed content without consuming power. Cholesteric liquid crystal molecules are stable in both planar and focal conic states, meaning that when voltage is removed from the display, the molecular state and displayed image remain unchanged. Voltage is only applied when it is necessary to transition the liquid crystal molecules to different states or refresh the displayed image. Therefore, Ch-LCD devices are becoming increasingly popular in temperature-sensing displays, e-books, electronic paper, electronic whiteboards, and various other products.

[0003] Summary of the Invention

[0004] This invention provides a cholesterol liquid crystal display device, comprising: a charging control circuit for selecting an input power source to generate an output voltage; a boost circuit for boosting the output voltage to generate a positive voltage signal and a negative voltage signal; a power management circuit for generating multiple sets of positive voltage drive signals and multiple sets of negative voltage drive signals based on the positive voltage signal and the negative voltage signal, wherein each of the positive voltage drive signals and each of the negative voltage drive signals is connected to a corresponding first bypass capacitor and a second bypass capacitor; a power storage device; a cholesterol liquid crystal display panel; and a timing controller for controlling the timing of the display screen of the cholesterol liquid crystal display panel. When the timing controller finishes executing the display screen reset program or display screen update program of the cholesterol liquid crystal display panel, the timing controller executes a power recovery mechanism to activate a first switching circuit so that each of the first bypass capacitors and each of the second bypass capacitors transfers the stored charge to the power storage device through a first discharge path and a second discharge path, respectively, to charge the power storage device.

[0005] The present invention further provides a cholesterol liquid crystal display device, comprising: a charging control circuit for selecting an input power source to generate an output voltage; a boost circuit for boosting the output voltage to generate a positive voltage signal and a negative voltage signal; a power management circuit for generating multiple sets of positive voltage drive signals and multiple sets of negative voltage drive signals based on the positive voltage signal and the negative voltage signal, wherein each of the positive voltage drive signals and each of the negative voltage drive signals is connected to a corresponding first bypass capacitor and a second bypass capacitor; a power storage device; a cholesterol liquid crystal display panel; and a processor for executing a display screen reset program and a display screen update program of the cholesterol liquid crystal display panel. When the display screen reset program or the display screen update program ends, the processor executes a power recovery mechanism to activate a first switching circuit so that each of the first bypass capacitors and each of the second bypass capacitors transfers the stored charge to the power storage device through a first discharge path and a second discharge path, respectively, to charge the power storage device.

[0006] The present invention further provides a power recovery method for a cholesterol liquid crystal display device, wherein the cholesterol liquid crystal display device includes a power management circuit and a cholesterol liquid crystal display panel, the power management circuit is used to generate a positive voltage drive signal and a negative voltage drive signal, and each of the positive voltage drive signal and each of the negative voltage drive signals is connected to a corresponding first bypass capacitor and a second bypass capacitor, the method comprising: in response to a display screen update request signal, executing a display screen reset procedure and a display screen update procedure of the cholesterol liquid crystal display panel; when the display screen reset procedure or the display screen update procedure ends, executing a first stage of a power recovery mechanism to charge the power storage device by the charge stored in each of the first bypass capacitors and each of the second bypass capacitors in the display screen reset procedure or the display screen update procedure through a first discharge path and a second discharge path, respectively; and when it is detected that the voltage amplitude of the first voltage and the second voltage of each of the first bypass capacitors and each of the second bypass capacitors decreases to the voltage amplitude of the power supply voltage of the power storage device, executing a second stage of the power recovery mechanism to discharge the remaining charge stored in each of the first bypass capacitors and each of the second bypass capacitors to a ground terminal through a third discharge path and a fourth discharge path, respectively. Attached Figure Description

[0007] Figure 1A is a block diagram of a display device according to a first embodiment of the present invention.

[0008] Figure 1B is a schematic diagram of the first-stage discharge path of the display device according to the embodiment of Figure 1A.

[0009] Figure 1C is a schematic diagram of the second-stage discharge path of the display device according to the embodiment of Figure 1A.

[0010] Figure 2 is a block diagram of a display device according to a second embodiment of the present invention.

[0011] Figure 3 is a block diagram of a display device according to a third embodiment of the present invention.

[0012] Figure 4 is a flowchart of a power recovery method for a cholesterol liquid crystal display device according to an embodiment of the present invention.

[0013] Figures 5A and 5B are waveforms of the voltage and current signals of the bypass capacitor according to an embodiment of the present invention.

[0014] Figure 6 is a flowchart of an energy recovery mechanism according to an embodiment of the present invention. Detailed Implementation

[0015] The following disclosure provides numerous different embodiments or examples of various components for implementing the provided object. Specific examples of operation, components, and configurations are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, in the description, an operation performed before or after a second operation may include embodiments in which the first and second operations are performed together, and may also include embodiments in which additional operations can be performed between the first and second operations. For example, in the following description, forming a first component above, on, or in connection with a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which an additional component can be formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself define a relationship between the various embodiments and / or configurations discussed.

[0016] For ease of description, temporal relative terms such as "before," "after," "follow," and similar terms may be used herein to describe the relationship between one operation or component and another(s) of operation or component, as illustrated in the figures. Temporal relative terms are intended to cover different sequences of operations depicted in the figures. Furthermore, for ease of description, spatial relative terms such as "below," "under," "down," "above," and similar terms may be used herein to describe the relationship between one component or component and another(s) of component or component, as illustrated in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein may be interpreted accordingly. For ease of description, connection-related terms such as "connect," "via connection," "coupled," "in communication," and the like are used herein to describe an operational connection, coupling, or link between two components or elements. Connection-related terms are intended to cover different connections, couplings, or links between devices or components. Devices or components may be directly connected, coupled, or linked to each other, or indirectly through, for example, another component. Devices or components may be wired and / or wirelessly connected, coupled, or linked to each other.

[0017] As used herein, the singular terms “a,” “an,” and “the” may include multiple references unless the context clearly indicates otherwise. For example, a reference to an apparatus may include multiple apparatuses unless the context clearly indicates otherwise. The terms “comprising” and “including” may indicate the presence of described features, integers, steps, operations, elements, and / or components, but may not exclude the presence of combinations of one or more features, integers, steps, operations, elements, and / or components. The term “and / or” may include any or all combinations of one or more of the listed items.

[0018] Additionally, quantities, ratios, and other values ​​are sometimes presented in a range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include values ​​that are explicitly specified as a range, but also to include all individual values ​​or subranges covered within the range, as if each value and subrange were explicitly specified.

[0019] The nature and use of the embodiments are discussed in detail below. However, it should be understood that the present invention provides many applicable inventive concepts that can be embodied in various specific contexts. The specific embodiments discussed are merely illustrative of particular ways of embodying and using the invention and are not intended to limit its scope.

[0020] Figure 1A is a block diagram of a display device according to a first embodiment of the present invention. In some embodiments, the display device 100 is, for example, a cholesteric liquid crystal (ChLC) display device, which includes a charging control circuit 101, a boost circuit 102, a power management circuit 103, a common driver integrated circuit (COM-DV) 11, a segment driver integrated circuit (SEG-DV) 12, a cholesteric liquid crystal display panel (ChLC panel) 10, and a power recovery circuit 20.

[0021] The charging control circuit 101 may receive, for example, an input DC voltage 120 or a DC voltage 203 from the power storage device 202, and select one of the input DC voltages 120 and 203 as the input voltage 104 provided to the boost circuit 102. In some embodiments, the DC voltage range of the input DC voltage 120 is approximately 5V to 12V. The boost circuit 102 generates a positive voltage signal 105 and a negative voltage signal 106 based on the input voltage 104 and provides them to the power management circuit 103. In some embodiments, the positive voltage signal 105 and the negative voltage signal 106 are, for example, +24V and -24V, respectively, but the invention is not limited thereto.

[0022] In some embodiments, the power management circuit 103 generates various positive voltage drive signals 121 and negative voltage drive signals 122 (e.g., including multiple sets of voltage drive signals with different potentials up to ±21V) for driving the cholesteric liquid crystal display panel 10 based on the positive voltage signal 105 and the negative voltage signal 106, and provides the positive voltage drive signals 121 and negative voltage drive signals 122 to the common driver integrated circuit 11 and the segment driver integrated circuit 12 driving the cholesteric liquid crystal display panel 10. The common driver integrated circuit 11 is an integrated circuit for driving the horizontal line (scan line) side bus in the cholesteric liquid crystal display panel 10. The segment driver integrated circuit 12 is an integrated circuit for driving the segment side bus in the cholesteric liquid crystal display panel 10.

[0023] In some embodiments, the cholesteric liquid crystal display panel 10 includes multiple cholesteric liquid crystal layers for blue, green, and red pixel arrays, which may be referred to as blue display panel 10B, green display panel 10G, and red display panel 10R, respectively. In some embodiments, the common driver integrated circuit 11 and the segment driver integrated circuit 12 can apply corresponding common voltage (VCOM) and segment voltage (VSEG) to each pixel circuit (e.g., cholesteric liquid crystal pixel circuits located at each common electrode and each segment electrode) on the blue display panel 10B, green display panel 10G, and red display panel 10R based on a positive voltage drive signal 121 and a negative voltage drive signal 122, respectively. It should be noted that the common voltage (VCOM) and segment voltage (VSEG) are both alternating current (AC) voltages, and the AC voltage sensed by each pixel circuit is the segment voltage (VSEG) applied to each pixel circuit minus the common voltage (VCOM). In addition, the power management circuit 103 can be configured to drive the cholesteric liquid crystal display panel 10 using a dynamic driving scheme (DDS) or a pulse width modulation (PWM) mode.

[0024] In some embodiments, when the display device 100 receives a display screen update request signal to update the screen displayed on the cholesteric liquid crystal display panel 10 (including the blue display panel 10B, the green display panel 10G, and the red display panel 10R), the charging control circuit 101 can select either the input DC voltage 120 (e.g., 5-12V) or the DC voltage 203 as the input voltage 104 provided to the boost circuit 102 based on the potential monitoring signal of the power storage device 202 (not shown in FIG. 1). The boost circuit 102 then boosts the voltage amplitude of the input voltage 104 to generate a positive voltage signal 105 and a negative voltage signal 106. The amplitude and duration of the positive voltage drive signal 121 and the negative voltage drive signal 122 generated by the power management circuit 103 are determined according to the timing of different stages of the driving mode (e.g., PWM driving mode or DDS driving mode) used by the cholesteric liquid crystal display panel 10. For example, PWM driving modes include a reset stage, a selection stage, and a non-selection stage, while DDS driving modes include a preparation stage, a selection stage, an evolution stage, and a non-selection stage.

[0025] Furthermore, the positive voltage driving signal 121 includes multiple combinations of positive voltage signals (e.g., three or more) for the blue display panel 10B, green display panel 10G, and red display panel 10R, respectively, and the negative voltage driving signal 122 similarly includes multiple combinations of negative voltage signals (e.g., three or more) for the blue display panel 10B, green display panel 10G, and red display panel 10R, respectively. Therefore, the positive voltage driving signal 121 may include a total of nine or more combinations of positive voltage signals, and the negative voltage driving signal 122 may include a total of nine or more combinations of negative voltage signals. Each positive and negative voltage signal can be individually set to drive the cholesterol liquid crystal molecules in each pixel circuit of the blue display panel 10B, green display panel 10G, and red display panel 10R at different timings. For ease of explanation, Figures 1A to 1C only illustrate one set of positive voltage driving signal 121 and negative voltage driving signal 122 as representative examples.

[0026] In some embodiments, the power recovery circuit 20 includes a voltage conversion circuit 201, a power storage device 202, diodes 211-213 and 215-216, and switches 221-223. The power storage device 202 is, for example, a battery or a supercapacitor, but the invention is not limited thereto.

[0027] Figure 1B is a schematic diagram of the first-stage discharge path of the display device according to the embodiment of Figure 1A. Figure 1C is a schematic diagram of the second-stage discharge path of the display device according to the embodiment of Figure 1A.

[0028] In some embodiments, each positive voltage drive signal 121 has a corresponding bypass capacitor 111, and each negative voltage signal 122 has a corresponding bypass capacitor 112. Furthermore, each bypass capacitor 111 has corresponding discharge paths CP1 and DP1, and each bypass capacitor 112 has corresponding discharge paths CP2 and DP2, as shown in Figures 1B and 1C. Discharge paths CP1 and CP2 are used, for example, in the first stage of the power recovery mechanism of bypass capacitors 111 and 112, and can also be referred to as the first-stage discharge paths. Discharge paths DP1 and DP2 are used, for example, in the second stage of the power recovery mechanism of bypass capacitors 111 and 112, and can also be referred to as the second-stage discharge paths.

[0029] Taking the PWM drive mode as an example, when the display device 100 receives a screen update request signal to update the display screen of the cholesteric liquid crystal display panel 10, each positive voltage drive signal 121 and negative voltage drive signal 122 generated by the power management circuit 103 during the reset phase of the PWM drive mode has a high voltage amplitude and lasts for a predetermined period. The AC voltage difference (e.g., ±42V) between the common voltage VCOM and the segment voltage VSEG of all pixel circuits in the blue display panel 10B, green display panel 10G, and red display panel 10R applied by the common driver integrated circuit 11 and the segment driver integrated circuit 12 is sufficient to allow all cholesteric liquid crystal molecules in the blue display panel 10B, green display panel 10G, and red display panel 10R to enter the homeotropic state. Therefore, after the reset phase ends, the bypass capacitor 111 corresponding to each positive voltage drive signal 121 stores a positive potential at the corresponding node N1, and the bypass capacitor 112 corresponding to each negative voltage drive signal 122 stores a negative potential at the corresponding node N2. In addition, after the reset phase, there will be a rest period (or waiting period, interval period) during which the cholesteric liquid crystal molecules in the blue display panel 10B, green display panel 10G and red display panel 10R will not feel the AC voltage difference and will enter the planar state from the homeotropic state so that the display panel 10 displays a white image, wherein the planar state is a stable state.

[0030] After the rest period, the voltage amplitude of each positive voltage drive signal 121 and negative voltage drive signal 122 generated by the power management circuit 103 corresponds to the AC voltage value required by the common driver integrated circuit 11 and the segment driver integrated circuit 12 in the selection phase of the PWM drive mode, which is less than the AC voltage value used in the reset phase. Then, during the selection phase, the common driver integrated circuit 11 and the segment driver integrated circuit 12 can sequentially apply voltages to each common electrode (COM) to turn on each scan line in the blue display panel 10B, green display panel 10G, and red display panel 10R, and apply individual AC voltages to each segment electrode (SEG) to update the pixel values ​​of each pixel circuit on the turned-on common electrode. Therefore, if the charge stored in the bypass capacitors 111 and 112 is not fully discharged during the aforementioned rest period, the potential difference stored across the bypass capacitors 111 and 112 may affect the positive voltage drive signal 121 and negative voltage drive signal 122 during the selection phase. Similarly, in PWM drive mode, after the selection phase of all scan lines is completed, the bypass capacitor 111 corresponding to each positive voltage drive signal 121 will store a positive potential at the corresponding node N1, and the bypass capacitor 112 corresponding to each negative voltage drive signal 122 will store a negative potential at the corresponding node N2. Therefore, if the charge stored in the bypass capacitors 111 and 112 is not used to charge the power storage device after the selection phase of all scan lines is completed, power may be wasted.

[0031] In some embodiments, diodes 211, 212, and 213 are used for rectification and to prevent the power storage device 202 from reverse charging the bypass capacitors 111 and 112, wherein diodes 212 and 213 are configured in reverse. Similarly, diodes 215 and 216 can also be used for rectification and only allow the bypass capacitors 111 and 112 to discharge in the direction of rectification by diodes 215 and 216, wherein diodes 215 and 216 are configured in reverse.

[0032] In some embodiments, the discharge process of bypass capacitors 111 and 112 can be divided into a first stage and a second stage. In the first stage of the discharge process, the control signal SC2 on the control signal line 220 turns on the switch 223, causing discharge paths CP1 and CP2 to conduct, wherein discharge path CP2 includes discharge paths CP2a and CP2b. Bypass capacitors 111 and 112 can transfer the stored charge to the power storage device 202 through discharge paths CP1 and CP2, respectively, thereby charging the power storage device 202, as shown in FIG1B. For example, in the first stage, the switch 223 is turned on, so the bypass capacitor 111 can transfer the charge stored at node N1 to the power storage device 202 through the diode 211 and the switch 223 via the discharge path CP1, thereby charging the power storage device 202. Similarly, the bypass capacitor 112 can charge the power storage device 202 by transferring the charge stored at node N2 to the power storage device 202 via the internal energy storage component (not shown) of the voltage conversion circuit 201 through the diode 212, voltage conversion circuit 201, diode 213 and switch 223 via the discharge path CP2 (e.g., including discharge paths CP2a and CP2b).

[0033] In detail, the voltage conversion circuit 201, also known as a negative voltage to positive voltage conversion circuit, converts the negative voltage from the bypass capacitor 112 corresponding to each negative voltage drive signal 122 into a positive voltage, wherein both the negative and positive voltages are DC voltages. For example, the discharge path CP2a of the bypass capacitor 112 corresponding to each negative voltage drive signal 122 is from the ground terminal inside the voltage conversion circuit 201 through the voltage conversion circuit 201 and the diode 212 to the bypass capacitor 112. Therefore, the negative charge stored in the bypass capacitor 112 at node N2 can be transferred to the internal energy storage component (not shown) of the voltage conversion circuit 201 for energy storage through the discharge path CP2a. The voltage conversion circuit 201 can convert the negative voltage stored in the internal energy storage component into a positive voltage, and then through the discharge path CP2b and the diode 213, the converted positive voltage is used to charge the power storage device 202 via the switch 223 (e.g., when it is in the on state).

[0034] In some embodiments, when the voltage amplitudes of the positive and negative voltages of the bypass capacitors 111 and 112 at nodes N1 and N2, respectively, are equal to the power supply voltage of the power storage device 202 (e.g., V), BATWhen the discharge signal 121 is positive, the bypass capacitors 111 and 112 can no longer transfer the remaining charge to the power storage device 202 through the discharge paths CP1 and CP2. At this time, the discharge process enters the second stage, and the control signal SC1 on the control signal line 220 will turn on the switches 221 and 222 to conduct the discharge paths DP1 and DP2. The charge stored in the bypass capacitor 111 corresponding to each positive voltage drive signal 121 will be discharged to the ground terminal through the diode 215 and the switch 221 via the discharge path DP1. Similarly, the charge stored in the bypass capacitor 112 corresponding to each negative voltage drive signal 122 will be discharged to the ground terminal through the diode 216 and the switch 222 via the discharge path DP2, where the discharge path DP2 can also represent the current direction, as shown in Figure 1C. In some embodiments, when it is necessary to accelerate the discharge rate of bypass capacitors 111 and 112, the control signal SC1 on the control signal line 220 can directly turn on switches 221 and 222 to conduct discharge paths DP1 and DP2, without waiting for the voltage amplitudes of the positive and negative voltages of bypass capacitors 111 and 112 at nodes N1 and N2 to be equal to the power supply voltage of the power storage device 202 (e.g., V). BAT ).

[0035] Figure 2 is a block diagram of a display device according to a second embodiment of the present invention. In some embodiments, the display device 200 of Figure 2 is similar to the display device 100 shown in Figure 1A, except that the display device 200 of Figure 2 adds a timing controller (TCON) 21 and a processor 22 to construct a complete display system. In addition, the display device 200 also includes a voltage detection line 126 for detecting the potential difference (or residual potential) across bypass capacitors 111 and 112 and the power supply voltage (e.g., V) of the power storage device 202. BAT The timing controller 21 is, for example, a ChLC display panel timing controller, which can be used to control the display control timing of the display panel 10. The processor 22 is, for example, a central processing unit (CPU), a digital signal processor (DSP), a video signal processor (ISP), or a system-on-a-chip (SoC), but the present invention is not limited thereto.

[0036] Referring to Figure 2, the charging control circuit 101 can receive, for example, an input DC voltage 120 or a DC voltage 203 from the power storage device 202, select one of the input DC voltages 120 and 203, and convert the selected voltage appropriately to provide the input voltage 104 to the boost circuit 102, thereby meeting the voltage operation requirements of the various circuits and components in the display device 200. Furthermore, the charging control circuit 101 can also provide appropriate operating voltage to the timing controller 21 and the processor 22 via the power line 123.

[0037] In some embodiments, the timing controller 21 receives control signals and image signals from the processor 22, and controls the timing operation of the common driver integrated circuit 11 and the segment driver integrated circuit 12, starts / stops the boost circuit 102, sets the output voltage of the power management circuit 103, etc., through the timing control line 125, thereby executing the display screen reset procedure and the display screen refresh procedure of the display panel 10. In addition, the timing controller 21 can also control the components and switches in the power recovery circuit 20 through the control signal line 220. Taking PWM drive mode as an example, in the display screen reset procedure (or reset stage), the timing controller 21 can control the power management circuit 103 to generate a high-voltage amplitude positive voltage drive signal 121 and a negative voltage drive signal 122 through the control signal line 220 and continue for a predetermined period of time, so that the AC voltage difference (e.g. ±42V) between the common voltage VCOM and the segment voltage VSEG of all pixel circuits in the blue display panel 10B, green display panel 10G and red display panel 10R applied by the common driver integrated circuit 11 and the segment driver integrated circuit 12 is sufficient to allow all cholesteric liquid crystal molecules in each pixel circuit of the blue display panel 10B, green display panel 10G and red display panel 10R to enter the vertical state.

[0038] During the rest period after the display screen reset procedure, the timing controller 21 can control the power management circuit 103 to generate a positive voltage drive signal 121 and a negative voltage drive signal 122 with low voltage amplitude (e.g., 0V) through the control signal line 220. This makes the AC voltage difference between the common voltage VCOM and the segment voltage VSEG applied by the common driver integrated circuit 11 and the segment driver integrated circuit 12 to all pixel circuits in the blue display panel 10B, green display panel 10G, and red display panel 10R approximately 0V. As a result, the cholesteric liquid crystal molecules in each pixel circuit of the blue display panel 10B, green display panel 10G, and red display panel 10R do not sense the AC voltage difference and enter the planar state from the vertical state, so that the display panel 10 displays a white image (i.e., the screen reset has been performed).

[0039] Figure 3 is a block diagram of a display device according to a third embodiment of the present invention. In some embodiments, the display device 300 of Figure 3 is similar to the display device 200 shown in Figure 2, except that the control signal line 220 in the display device 300 of Figure 3 is controlled by the processor 22. Therefore, the processor 22 can be used with the timing controller 21 to more precisely control the operating timing of switches 221, 222 and 223, wherein the above operating timing will be described in detail with the flowchart of Figure 4 and the waveform diagrams of Figures 5A and 5B. For ease of explanation, in the embodiments described below, the processor 22 controls the charging control circuit 101 to select the input DC voltage 120 as the input voltage 104 of the boost circuit 102.

[0040] Figure 4 is a flowchart of a power recovery method for a cholesterol liquid crystal display device according to an embodiment of the present invention. Figures 5A and 5B are waveform diagrams of the voltage and current signals of the bypass capacitor according to an embodiment of the present invention. Please refer to Figures 2, 4, and 5A-5B simultaneously.

[0041] The flow 400 of the power recovery method in Figure 4 includes steps S401 to S430. In step S401, the display device 200 receives a display screen update request signal. For example, the processor (or single-chip system) 22 of the display device 200 may receive an external display screen update request signal, such as from a keyboard, touch panel, or USB controller (not shown in Figure 2) connected to the processor 22, and the timing controller 21 or the processor 22 may control the display device 200 to perform a display screen reset procedure and a display screen update procedure according to a control program (not shown) stored in the display device 200. The control program can be used to execute steps S410 to S430 in Figure 4. The display screen reset procedure includes steps S410 to S414, and the display screen update procedure includes steps S420 to S426. After the display screen reset procedure and the display screen update procedure, a power recovery mechanism is activated to transfer the charge stored in bypass circuits 111 and 112 to the power storage device 202 to charge the power storage device 202 or discharge it to the ground terminal. For ease of explanation, in steps S410 to S430, the timing controller 21 in FIG2 is used to control other circuits and switches in the display device 200 to execute the display screen reset procedure, the display screen update procedure, and the power recovery mechanism. It should be understood that the processor 22 in FIG3 can also be used to control other circuits and switches in the display device 300 to execute the display screen reset procedure, the display screen update procedure, and the power recovery mechanism.

[0042] First, at time t1, the timing controller 21 activates the boost circuit 102 (step S410). For example, the boost circuit 102 generates a positive voltage signal 105 and a negative voltage signal 106 based on the input voltage 104. Next, the output voltage of the power management circuit 103 is set (step S411). For example, the power management circuit 103 generates multiple sets of positive voltage drive signals 121 and multiple sets of negative voltage drive signals 122 for driving the cholesteric liquid crystal display panel 10 based on the positive voltage signal 105 and the negative voltage signal 106, and provides the positive voltage drive signals 121 and the negative voltage drive signals 122 to the common driver integrated circuit 11 and the segment driver integrated circuit 12 that drive the cholesteric liquid crystal display panel 10. Specifically, as shown in FIG5A, when the display device 200 has not yet received the display screen update request signal, the voltage V of the bypass capacitor 111 is V CP and current I CP and the voltage V of bypass capacitor 112 CN and I CN All are 0. When the display device 200 receives a display screen update request signal, the timing controller 21 can activate the boost circuit 102 and set the output voltage of the power management circuit 103 (i.e., steps S410 and S411). Therefore, at time t1, the positive voltage drive signal 121 and the negative voltage drive signal 122 will charge the bypass capacitors 111 and 112, so the voltage V of the bypass capacitors 111 and 112 is 0. CP and V CN The current I of the bypass capacitors 111 and 112 will be increased to the positive and negative high potentials respectively. CP and I CN The display screen reset procedure is then executed (step S412), which means that the timing controller 21 can control the common driver integrated circuit 11 and the segment driver integrated circuit 12 to apply an extremely high AC voltage difference (e.g., ±42V) to all pixel circuits in the blue display panel 10B, green display panel 10G and red display panel 10R so that all cholesteric liquid crystal molecules in each pixel circuit of the blue display panel 10B, green display panel 10G and red display panel 10R enter the vertical state.

[0043] At time t2, the output voltage of the power management circuit 103 is set (step S413) so that the AC voltage difference applied by the common driver integrated circuit 11 and the segment driver integrated circuit 12 to all pixel circuits in the blue display panel 10B, green display panel 10G, and red display panel 10R is 0V, and the timing controller 21 then shuts down the boost circuit 102 (step S414) to complete the display screen reset procedure and initiate the power recovery mechanism (step S415). Specifically, the display screen reset procedure occurs during time T1 between t1 and t2, for example, the positive voltage drive signal 121 and the negative voltage drive signal 122 have high voltage amplitudes at positive and negative potentials, respectively. The power recovery mechanism refers to the power recovery and / or discharge process of the bypass capacitors 111 and 112, which occurs during time T2 between t2 and t3.

[0044] It should be noted that because the voltage V across bypass capacitors 111 and 112 is... CP and V CN The positive voltage drive signal 121 and the negative voltage drive signal 122 in the display screen reset procedure have been charged to positive and negative potentials with high voltage amplitudes, respectively. Therefore, the timing controller 21 can turn on the switch 223 at time t2 via the signal SC2 of the control signal line 220 so that the bypass capacitors 111 and 112 can transfer the stored charge to the power storage device 202 through the discharge paths CP1 and CP2 (e.g., including discharge paths CP2a and CP2b) to charge the power storage device 202.

[0045] In some embodiments, the period between times t2 and t2a shown in FIG. 5B can be referred to as the first stage of the discharge process of bypass capacitors 111 and 112. For example, at time t2a shown in FIG. 5B, when the timing controller 21 detects the corresponding voltage V of bypass capacitors 111 and 112... CP and V CN The power supply voltage (e.g., V) of the power storage device 202 is close to or equal to that of the power storage device 202. BAT To accelerate discharge or reduce the load on the power management circuit 103, the timing controller 21 can turn on switches 221 and 222 via signal SC1 on control signal line 220, thereby turning on discharge paths DP1 and DP2. Therefore, bypass capacitors 111 and 112 can quickly discharge their stored residual charge to the ground terminal through discharge paths DP1 and DP2 respectively, resulting in a decrease in the corresponding voltage V of bypass capacitors 111 and 112. CP and V CN The ground voltage (0V) can be reached within a very short time after time t2a (e.g., at time t3 in Figure 5A), indicating that time t3 in Figure 5A is very close to time t2a in Figure 5B. The corresponding currents I of bypass capacitors 111 and 112 are... CPand I CN It will also change with the above discharge process. On the other hand, if the timing controller 21 does not turn on the switches 221 and 222 by the signal SC1 of the control signal line 220 at time t2a, the discharge process of the bypass capacitors 111 and 112 will be delayed until time t2b, and the discharge process during the period from time t2a to t2b may also put a burden on the power management circuit 103.

[0046] In some embodiments, when the corresponding voltage V of bypass capacitors 111 and 112 CP and V CN When the voltage is equal to the ground voltage (i.e., time t3), the timing controller 21 can control the common driver integrated circuit 11 and the segment driver integrated circuit 12 to apply an AC voltage difference of 0V to all pixel circuits in the blue display panel 10B, green display panel 10G and red display panel 10R. The T3 period between time t3 and t4 can be called the rest time (or interval time), so that the cholesteric liquid crystal molecules in each pixel circuit of the blue display panel 10B, green display panel 10G and red display panel 10R do not feel the AC voltage difference and enter the planar state from the vertical state, so that the display panel 10 displays a white image, indicating that the display screen of the display panel 10 has been reset.

[0047] In some embodiments, the display screen update procedure is, for example, during period T4 between time t4 and t5. At time t4, the timing controller 21 activates the boost circuit 102 (step S420), for example, the boost circuit 102 generates a positive voltage signal 105 and a negative voltage signal 106 based on the input voltage 104. Next, the output voltage of the power management circuit 103 is set (step S421), and the display screen update procedure is executed (step S422). For example, the power management circuit 103 generates various positive voltage drive signals 121 and negative voltage drive signals 122 for driving the cholesteric liquid crystal display panel 10 based on the positive voltage signal 105 and the negative voltage signal 106, and provides the positive voltage drive signals 121 and negative voltage drive signals 122 to the common driver integrated circuit 11 and the segment driver integrated circuit 12 that drive the cholesteric liquid crystal display panel 10. It should be noted that the voltage amplitudes of the positive voltage drive signal 121 and the negative voltage drive signal 122 generated by the display screen update program where the power management circuit 103 is located are lower than the voltage amplitudes of the positive voltage drive signal 121 and the negative voltage drive signal 122 generated in the display screen reset program.

[0048] Furthermore, the display screen update procedure of the display panel 10 updates the pixel values ​​of the pixel circuits on each scan line sequentially. Therefore, after each scan line's display screen update procedure is completed, the timing controller 21 determines whether the current scan line is the last scan line of the display screen. If it is not the last scan line, step S424 is executed to select the next scan line, and the process returns to step S421 to reset the output voltage of the power management circuit 103. If it is the last scan line, at time t5, the output voltage of the power management circuit 103 is set (step S425), for example, making both the positive voltage drive signal 121 and the negative voltage drive signal 122 0V. This causes the AC voltage difference applied by the common driver integrated circuit 11 and the segment driver integrated circuit 12 to all pixel circuits in the blue display panel 10B, green display panel 10G, and red display panel 10R to be 0V. The timing controller 21 then shuts down the boost circuit 102 (step S426) and starts the power recovery mechanism (step S427) to recover and / or discharge the charge stored in the bypass capacitors 111 and 112 during the display screen update process. At time t6, when the power recovery mechanism has finished executing, it indicates that the display screen has been updated (step S430).

[0049] It should be noted that the power recovery mechanism performed in step S427 is similar to the power recovery mechanism described in step S415, and the timing controller 21 can adjust the timing based on the detected voltage V of the bypass capacitors 111 and 112. CP and V CN and the power supply voltage (e.g., V) of the power storage device 202 BAT The requirements for accelerating discharge, etc., determine whether to transfer the charge stored in bypass capacitors 111 and 112 to the power storage device 202 through discharge paths CP1 and CP2 (e.g., including discharge paths CP2a and CP2b) and / or to discharge the charge stored in bypass capacitors 111 and 112 to the ground terminal through discharge paths DP1 and DP2. Therefore, the details will not be described in detail here.

[0050] In some embodiments, the display device 200 or 300 consumes approximately 600 mJ of power during the display screen reset procedure. For ease of explanation, the capacitance value of each bypass circuit 111 and 112 is 10 μF, and the positive voltage drive signal 121 and negative voltage drive signal 122 with the highest voltage amplitude during the display screen reset procedure are approximately 21V, which are supplied to the blue display panel 10B, green display panel 10G, and red display panel 10R. At this time, the total charge QP stored in the bypass capacitor 111 corresponding to the three sets of positive voltage drive signals 121 (e.g., +21V) for the blue display panel 10B, green display panel 10G, and red display panel 10R is 10 μF × 21V × 3 = 630 μC. Similarly, the total charge QN stored in the bypass capacitor 111 corresponding to the three sets of negative voltage drive signals 122 (e.g., -21V) for the blue display panel 10B, green display panel 10G, and red display panel 10R is also 630 μC. Therefore, the energy WP obtainable from the three sets of positive voltage drive signals 121 is WP = QP × V / 2 = 0.63 × 21 / 2 = 6.615 mJ. If the conversion efficiency of the voltage conversion circuit 201 in converting negative potential to positive potential is 90%, then the energy WN obtainable from the three sets of negative voltage drive signals 122 is WN = 6.615 × 0.9 = 5.954 mJ. Therefore, the total energy W charged to the power storage device 202 by the power recovery mechanism activated after each display screen reset procedure is completed is W = WP + WN = 6.615 + 5.954 = 12.57 mJ. Therefore, when the positive voltage drive signal 121 and the negative voltage drive signal 122 with the highest voltage amplitude are used on the corresponding bypass capacitors 111 and 112, executing the display screen reset procedure 48 times allows the power storage device 202 to store the energy required for one display screen reset procedure (e.g., 600 mJ). In other words, by incorporating the power recovery mechanism of this invention after the display screen reset procedure, approximately (12.57 / 600) × 100% = 2.095% of power can be saved. It should be noted that the above energy calculation uses a set of positive voltage drive signals 121 and negative voltage drive signals 122 for each of the blue display panel 10B, green display panel 10G, and red display panel 10R to illustrate the concept of the power recovery mechanism of this invention, and is not intended to limit the invention.

[0051] Figure 6 is a flowchart of an energy recovery mechanism according to an embodiment of the present invention. The energy recovery mechanism process 600 includes steps S602 to S608.

[0052] In step S602, the power recovery mechanism is activated. For example, the power recovery mechanism of the present invention has two activation times. The first activation time is after the display screen reset procedure ends and before the display screen update procedure begins, as shown in step S415 of FIG4. The second activation time is after the display screen update procedure for all scan lines of the display panel 10 is completed, as shown in step S427 of FIG4.

[0053] In step S604, the first stage of the power recovery mechanism is entered to transfer the charge stored in the first bypass capacitor 111 and the second bypass capacitor 112 of each positive voltage drive line 121 and each negative voltage drive line 122 to the power storage device 202 through the first discharge path CP1 and the second discharge path CP2 (e.g., including discharge paths CP2a and CP2b) to the power storage device 202 for charging.

[0054] In step S606, when the voltage amplitudes of the first voltage (e.g., the voltage at node N1) and the second voltage (e.g., the voltage at node N2) of the first bypass capacitor 111 and the second bypass capacitor 112 decrease to the power supply voltage (e.g., V) of the power storage device... BAT The voltage amplitude of the voltage wave enters the second stage of the power recovery mechanism.

[0055] In step S608, the remaining charge of the first bypass capacitor 111 and the second bypass capacitor 112 is discharged to the ground terminal through the third discharge path DP1 and the fourth discharge path DP2, respectively.

[0056] Therefore, through the circuit design of the present invention, the energy consumption of the cholesterol liquid crystal display device can be reduced, and unnecessary heat generation of the internal components of the cholesterol liquid crystal display device can be reduced, thereby improving the reliability and lifespan of the cholesterol liquid crystal display device.

[0057] The scope of this invention is not intended to be limited to the specific embodiments of the procedures, machines, articles, compositions of matter, means, methods, steps, and operations described in the specification. Those skilled in the art will readily understand from the disclosure of this invention that existing or potentially future-developed procedures, machines, articles, compositions of matter, means, methods, steps, or operations can be used to perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to encompass the stated procedures, machines, articles, compositions of matter, means, methods, steps, or operations within their scope. Furthermore, each technical solution constitutes a separate embodiment, and combinations of various claims and embodiments are within the scope of this invention.

[0058] While numerous features and advantages of the invention, as well as details of its structure and function, have been set forth in the foregoing description, this invention is merely illustrative. Within the scope of the principles of the invention, particularly regarding the shape, size, and arrangement of components, changes may be made to the details, which may fully conform to the broad general meaning indicated by the appended claims.

Claims

1. A cholesterol liquid crystal display device, comprising: The charging control circuit is used to select the input power supply to generate the output voltage; A boost circuit is used to boost the output voltage to generate positive and negative voltage signals; A power management circuit is used to generate multiple sets of positive voltage drive signals and multiple sets of negative voltage drive signals based on the positive voltage signal and the negative voltage signal, wherein each of the positive voltage drive signals and each of the negative voltage drive signals is connected to a corresponding first bypass capacitor and a second bypass capacitor. Power storage device; and Cholesterol LCD display panel; A timing controller is used to control the timing of the display screen of the cholesterol liquid crystal display panel; When the timing controller finishes executing the display screen reset program or display screen update program of the cholesterol liquid crystal display panel, the timing controller executes a power recovery mechanism to turn on the first switching circuit so that each of the first bypass capacitors and each of the second bypass capacitors transfers the stored charge to the power storage device through the first discharge path and the second discharge path respectively to charge the power storage device.

2. The cholesterol liquid crystal display device as claimed in claim 1, wherein the charging control circuit selects the input power source from the input DC voltage or the power supply voltage provided by the power storage device.

3. The cholesterol liquid crystal display device as claimed in claim 1, wherein the timing controller executes the display screen reset procedure and the display screen update procedure of the cholesterol liquid crystal display panel according to an external display screen update request.

4. The cholesteric liquid crystal display device as claimed in claim 3, wherein when the display screen reset procedure is completed, the cholesteric liquid crystal molecules in the cholesteric liquid crystal display panel enter the homeotropic state, and there is a rest period between the display screen reset procedure and the display screen update procedure to allow the cholesteric liquid crystal molecules to enter the planar state.

5. The cholesterol liquid crystal display device as claimed in claim 4, further comprising: The common driver integrated circuit and the segment driver integrated circuit apply a common voltage and a segment voltage to the common electrode and the segment electrode in the cholesterol liquid crystal display panel, respectively. During the rest period, the voltage difference between the segment voltage and the common voltage felt by each cholesterol-type liquid crystal molecule in the cholesterol liquid crystal display panel is 0V.

6. The cholesterol liquid crystal display device as claimed in claim 1, wherein: Each of the first bypass capacitors is coupled to a first terminal and a ground terminal, and its corresponding first discharge path is from the first terminal through a first diode and a corresponding first switching circuit to the power storage device. Each of the second bypass capacitors is coupled to a second terminal and a ground terminal, and its corresponding second discharge path extends from the second terminal through a second diode, a voltage conversion circuit, a third diode, and a corresponding first switching circuit to the power storage device; and The second diode and the third diode are configured in reverse.

7. The cholesterol liquid crystal display device of claim 6, wherein the voltage conversion circuit is used to convert the negative voltage stored in the second bypass capacitor at the second terminal into a positive voltage, and transmit the positive voltage to the power storage device through the third diode and the first switching circuit.

8. The cholesterol liquid crystal display device of claim 7, wherein when the timing controller detects that the voltage amplitudes of the first voltage and the second voltage of each of the first bypass capacitors and each of the second bypass capacitors decrease to the voltage amplitude of the power supply voltage of the power storage device, the timing controller activates the second switching circuit and the third switching circuit so that each of the first bypass capacitors and each of the second bypass capacitors discharges the remaining charge stored therein to the ground terminal through the third discharge path and the fourth discharge path, respectively.

9. The cholesterol liquid crystal display device as claimed in claim 8, wherein: The third discharge path corresponding to each of the first bypass capacitors is connected from the first endpoint to the ground terminal via a fourth diode; The corresponding fourth discharge path for each of the second bypass capacitors is connected to the ground terminal via the second terminal and the fifth diode; and The fourth diode and the fifth diode are configured in reverse.

10. A cholesterol liquid crystal display device, comprising: The charging control circuit is used to select the input power supply to generate the output voltage; A boost circuit is used to boost the output voltage to generate positive and negative voltage signals; A power management circuit is used to generate multiple sets of positive voltage drive signals and multiple sets of negative voltage drive signals based on the positive voltage signal and the negative voltage signal, wherein each of the positive voltage drive signals and each of the negative voltage drive signals is connected to a corresponding first bypass capacitor and a second bypass capacitor. Power storage device; Cholesterol LCD display panel; and The processor is used to execute the display screen reset program and the display screen update program of the cholesterol liquid crystal display panel; When the display screen reset procedure or the display screen update procedure ends, the processor executes a power recovery mechanism to activate the first switching circuit so that each of the first bypass capacitors and each of the second bypass capacitors transfers the stored charge to the power storage device through the first discharge path and the second discharge path respectively to charge the power storage device.

11. The cholesterol liquid crystal display device of claim 10, wherein the charging control circuit selects the input power source from the input DC voltage or the power supply voltage provided by the power storage device.

12. The cholesterol liquid crystal display device of claim 11, wherein the processor executes the display screen reset procedure and the display screen update procedure of the cholesterol liquid crystal display panel according to an external display screen update request.

13. The cholesteric liquid crystal display device as claimed in claim 12, wherein when the display screen reset procedure is completed, the cholesteric liquid crystal molecules in the cholesteric liquid crystal display panel enter the homeotropic state, and there is a rest period between the display screen reset procedure and the display screen update procedure to allow the cholesteric liquid crystal molecules to enter the planar state.

14. The cholesterol liquid crystal display device as claimed in claim 13, further comprising: The common driver integrated circuit and the segment driver integrated circuit apply a common voltage and a segment voltage to the common electrode and the segment electrode in the cholesterol liquid crystal display panel, respectively. During the rest period, the voltage difference between the segment voltage and the common voltage felt by each cholesterol-type liquid crystal molecule in the cholesterol liquid crystal display panel is 0V.

15. The cholesterol liquid crystal display device as claimed in claim 10, wherein: Each of the first bypass capacitors is coupled to a first terminal and a ground terminal, and its corresponding first discharge path is from the first terminal through a first diode and a corresponding first switching circuit to the power storage device. Each of the second bypass capacitors is coupled to a second terminal and a ground terminal, and its corresponding second discharge path extends from the second terminal through a second diode, a voltage conversion circuit, a third diode, and a corresponding first switching circuit to the power storage device; and The second diode and the third diode are configured in reverse.

16. The cholesterol liquid crystal display device of claim 15, wherein the voltage conversion circuit is used to convert the negative voltage stored in the second bypass capacitor at the second terminal into a positive voltage, and transmit the positive voltage to the power storage device through the third diode and the first switching circuit.

17. The cholesterol liquid crystal display device of claim 16, wherein when the processor detects that the voltage amplitudes of the first voltage and the second voltage of each of the first bypass capacitors and each of the second bypass capacitors decrease to the voltage amplitude of the power supply voltage of the power storage device, the processor activates the second switching circuit and the third switching circuit to discharge the remaining charge stored in each of the first bypass capacitors and each of the second bypass capacitors to the ground terminal through the third discharge path and the fourth discharge path, respectively.

18. The cholesterol liquid crystal display device as claimed in claim 16, wherein: The third discharge path corresponding to each of the first bypass capacitors is connected from the first endpoint to the ground terminal via a fourth diode; The corresponding fourth discharge path for each of the second bypass capacitors is connected to the ground terminal via the second terminal and the fifth diode; and The fourth diode and the fifth diode are configured in reverse.

19. A method for power recovery in a cholesterol liquid crystal display device, wherein the cholesterol liquid crystal display device includes a power management circuit and a cholesterol liquid crystal display panel, the power management circuit being configured to generate a positive voltage drive signal and a negative voltage drive signal, and each of the positive voltage drive signals and each of the negative voltage drive signals being connected to a corresponding first bypass capacitor and a second bypass capacitor, the method comprising: In response to a display screen update request signal, the display screen reset procedure and display screen update procedure of the cholesterol liquid crystal display panel are executed; When the display screen reset procedure or the display screen update procedure ends, the first stage of the power recovery mechanism is executed so that the charge stored in each of the first bypass capacitors and each of the second bypass capacitors in the display screen reset procedure or the display screen update procedure is charged to the power storage device through the first discharge path and the second discharge path, respectively. and When the voltage amplitudes of the first and second voltages of each of the first and second bypass capacitors are detected to decrease to the voltage amplitude of the power supply voltage of the power storage device, the second stage of the power recovery mechanism is executed so that each of the first and second bypass capacitors discharges the remaining charge stored therein to the ground terminal through the third and fourth discharge paths, respectively.

20. The method of claim 19, wherein when the display screen reset procedure is completed, the cholesteric liquid crystal molecules in the cholesteric liquid crystal display panel enter the homeotropic state, and there is a rest period between the display screen reset procedure and the display screen update procedure to allow the cholesteric liquid crystal molecules to enter the planar state.

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