Solar cell and manufacturing method therefor

Abstract

A solar cell and a manufacturing method therefor. The solar cell comprises a P region and an N region which are located on a back side; the P region comprises a heavily doped region and a lightly doped region; the back side of the N region is provided with a tunneling layer and an N-type doped polysilicon layer; the solar cell further comprises a first electrode located at the back side of the heavily doped region and a second electrode located at the back side of the N-type doped polysilicon layer. In the solar cell, the first electrode and the second electrode are both arranged on the back side, so that no metal electrode shields a front side, allowing for a large light-receiving area and high light conversion efficiency and thus improving cell efficiency. The P region is provided with an SE structure, increasing the open-circuit voltage and the short-circuit current of the cell. The N region is provided with a passivation contact structure for passivation of the surface of the N region, increasing the short-circuit current and thus improving the overall cell efficiency.

Description

Solar cells and their preparation methods

[0001] This application is based on and claims priority to Chinese Patent Application No. 202410917310.3, filed on July 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This invention relates to the field of photovoltaics, and more particularly to a solar cell and its preparation method. Background Technology

[0003] BC (Back Contact) batteries, also known as full back electrode contact batteries or full reverse electrode contact batteries, are a new type of solar cell technology.

[0004] BC cells employ a design different from traditional crystalline silicon photovoltaic cells. All of its electrodes are located on the back of the cell, while the front is fully exposed to sunlight, which improves light absorption efficiency. It also reduces the current transmission path, lowers resistance, and improves cell performance.

[0005] However, despite the significant advantages of BC batteries over other battery technologies, their efficiency still needs improvement.

[0006] In view of this, it is necessary to provide an improved solar cell and its fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0007] This invention provides a solar cell and its fabrication method, which improves carrier collection in the P-region and N-region on the back of the cell, thereby increasing the cell efficiency.

[0008] To achieve one of the above-mentioned objectives, the present invention adopts the following technical solution:

[0009] A solar cell, characterized in that it comprises:

[0010] The P-region located on the back side includes a heavily doped region and a lightly doped region;

[0011] The N region located on the back side is provided with a tunneling layer and an N-type doped polysilicon layer;

[0012] The first electrode is located on the back side of the heavily doped region;

[0013] The second electrode is located on the back side of the N-type doped polycrystalline silicon layer.

[0014] In one optional embodiment, the sheet resistance of the heavily doped region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the lightly doped region is 200 ohm / sq to 400 ohm / sq.

[0015] In one optional implementation, the diffusion depth of the P region is greater than the diffusion depth of the N region.

[0016] In one optional embodiment, the boron junction depth of the P region is 0.5 μm to 1.0 μm.

[0017] In one optional implementation, the doping concentration of the N-region is less than the doping concentration of the N-type doped polysilicon layer.

[0018] In an optional embodiment, the solar cell further includes an isolation region located between the P region and the N region, the width of the isolation region being no greater than 100 μm.

[0019] In an optional embodiment, the solar cell further includes: a back passivation layer and a back antireflection layer located on the back side; the first electrode passes through the back antireflection layer and the back passivation layer to contact the heavily doped region; the second electrode passes through the back antireflection layer and the back passivation layer to contact the N-type doped polycrystalline silicon layer; and a front passivation layer and a front antireflection layer are sequentially disposed on the front side of the silicon substrate.

[0020] A method for preparing a solar cell includes the following steps:

[0021] A boron diffusion layer and BSG are formed on the back side of a silicon substrate, wherein the gate line region of the P region is a heavily doped region and the region outside the gate line region is a lightly doped region.

[0022] Remove the BSG and boron junction outside the P region;

[0023] A tunneling layer, an N-type doped amorphous silicon layer, and a mask layer are formed on the entire back side of a silicon substrate.

[0024] Annealing transforms the N-type doped amorphous silicon layer into an N-type doped polycrystalline silicon layer, and the phosphorus extends into the silicon substrate to form an N-type doped region.

[0025] Remove the mask layer, N-type doped polysilicon layer, and tunneling layer outside the N region that is separated from the P region;

[0026] The first electrode and the second electrode were fabricated in the P region and the N region, respectively.

[0027] In an optional embodiment, "forming a boron diffusion layer and BSG" includes the following steps: forming a boron source on the entire back side of a silicon substrate; forming a heavily doped region by laser scanning in the gate region of the P-region; feeding the heavily doped silicon substrate into a tube furnace and introducing oxygen at a temperature of 950°C to 1000°C and an oxygen flow rate of 10 s / ml to 15 s / ml; forming a lightly doped region outside the gate region, while simultaneously introducing oxygen to form a BSG layer on the entire surface.

[0028] In one optional embodiment, the sheet resistance of the heavily doped region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the lightly doped region is 200 ohm / sq to 400 ohm / sq.

[0029] In an optional implementation, "removing the BSG and boron junction outside the P region" includes the following steps:

[0030] Laser ablation is used to remove the BSG layer outside the P region;

[0031] BSG on the front and side surfaces of the silicon substrate is removed by HF solution with a volume concentration of 5% to 20%.

[0032] Polishing process removes boron junctions outside the P region, and also removes boron junctions that have been expanded on the front side.

[0033] In one optional embodiment, the tunneling layer is SiOx with a thickness of 1.4 nm to 2.3 nm; or the tunneling layer is SiC with a thickness of 1 nm to 1.8 nm.

[0034] In one optional embodiment, the tunneling layer is silicon oxide with a thickness of 1.4 nm to 2.3 nm and an annealing temperature of 880 °C to 950 °C.

[0035] In one optional embodiment, the tunneling layer is a silicon carbide layer with a thickness of 1 nm to 1.8 nm and an annealing temperature of 850 °C to 900 °C.

[0036] In an optional implementation, "removing the mask layer, N-type doped polysilicon layer, and tunneling layer outside the N-region that are spaced apart from the P-region" includes the following steps:

[0037] Laser ablation removes the mask layer outside the N-region;

[0038] A chain machine is used to remove the mask layer that has been wrapped around the front side;

[0039] A trenching machine is used to remove the N-type doped polysilicon layer and tunneling layer outside the N-region on the back side, while forming a pyramid structure on the front side of the silicon substrate.

[0040] In an optional embodiment, before fabricating the first electrode and the second electrode, the method for fabricating the solar cell further includes the following steps:

[0041] Passivation layers are deposited on both the front and back sides. The passivation layers are aluminum oxide layers with a thickness of 3nm to 6nm.

[0042] Antireflection layers are deposited on both the front and back sides. The antireflection layers are selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the antireflection layers is 60 nm to 130 nm.

[0043] In one optional embodiment, after the first electrode and the second electrode are prepared, laser-assisted sintering technology is used to laser sinter the first electrode and the second electrode.

[0044] In one optional embodiment, the laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm to 2mm.

[0045] The beneficial effects of this invention are as follows: The solar cell of this invention, by placing both the first and second electrodes on the back side, eliminates the obstruction of the front side by metal electrodes, resulting in a large light-receiving area, high light conversion efficiency, and improved cell efficiency. Furthermore, by setting an SE structure in the P-region, the open-circuit voltage and short-circuit current of the cell are improved; and by setting a passivated contact structure in the N-region to passivate its surface, the short-circuit current is increased, thus improving the overall cell efficiency. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0047] Figure 2 is a flowchart of a method for preparing a solar cell according to an embodiment of the present invention.

[0048] Among them, 100-solar cell, 1-silicon substrate, 2-P region, 21-heavily doped region, 22-lightly doped region, 3-N region, 31-tunneling layer, 32-N-type doped polycrystalline silicon layer, 4-isolation region, 5-back passivation layer, 6-back antireflection layer, 7-front passivation layer, 8-front antireflection layer, 91-first electrode, 92-second electrode. Detailed Implementation

[0049] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0050] In the various figures of this invention, for ease of illustration, certain dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.

[0051] With the shortening of the BC battery process and breakthroughs in key manufacturing technologies, the mass production process is accelerating. In order to further improve the efficiency of solar cells, this invention optimizes the structure on the back of the battery by optimizing the N-region and P-region through different processes, thereby comprehensively improving the battery efficiency.

[0052] The present invention provides a solar cell 100, which includes a silicon substrate 1, a P region 2 and an N region 3 located on the back side of the silicon substrate 1, a first electrode 91 located on the back side of the P region 2, and a second electrode 92 located on the back side of the N region 3.

[0053] The solar cell 100 improves battery efficiency by placing both the first electrode 91 and the second electrode 92 on the back side, with no metal electrodes obstructing the front side, resulting in a large light-receiving area.

[0054] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 0.5 Ω·cm to 3.5 Ω·cm. In an optional embodiment, the front side of the silicon substrate 1 has a textured structure, which has a good light-limiting effect and can further improve the light utilization rate.

[0055] The P-region 2 and the N-region 3 are alternately arranged, and an isolation region 4 is provided between the P-region 2 and the N-region 3. The isolation region 4 completely isolates the P-region 2 and the N-region 3, preventing leakage problems caused by contact between them. In this invention, the width of the isolation region 4 is no greater than 100μm, preferably 10μm to 80μm; the smaller the width of the isolation region 4, the better, provided that the P-region 2 and the N-region 3 can be effectively isolated.

[0056] The P region 2 includes a plurality of first main gate regions extending along a first direction and a plurality of first sub-gate regions extending along a second direction. The plurality of first sub-gate regions are arranged along the first direction and are connected to the first main gate regions.

[0057] In an optional implementation, the P-region 2 includes a heavily doped region 21 and a lightly doped region 22, forming a selective emitter to reduce surface recombination.

[0058] The first electrode 91 is located in the heavily doped region 21. Specifically, the first electrode 91 includes a first main gate and a first sub-gate. The width of the first main gate is smaller than the width of the first main gate region, and the first main gate is located in the gate line region of the first main gate region. The width of the first sub-gate is smaller than the width of the first sub-gate region, and the first sub-gate is located in the gate line region of the first sub-gate region.

[0059] The gate region is a heavily doped region 21, forming an ohmic contact with the first electrode 91, reducing the series resistance of the battery and increasing the fill factor FF. The non-gate region outside the gate region is a lightly doped region 22, reducing the probability of carrier surface recombination and decreasing the reverse saturation current, thereby increasing the open-circuit voltage Voc and short-circuit current Isc. Furthermore, the heavily doped region 21 and the lightly doped region 22 can generate a P++ / P+ high-low junction laterally, which is beneficial for improving carrier collection and further increasing the short-circuit current Isc.

[0060] In an optional embodiment, the doping concentration of the heavily doped region 21 is 5E18cm⁻¹. -3 ~1E20cm -3The sheet resistance is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the lightly doped region 22 is 200 ohm / sq to 400 ohm / sq.

[0061] In this invention, the diffusion depth of P-region 2 is greater than that of N-region 3. In an optional embodiment, the boron junction depth of P-region 2 is 0.5 μm to 1.0 μm. This achieves the optimal passivation level for both P-region 2 and N-region 3, with the dark saturation current density J0 of P-region 2 being 2 to 4 fA / cm². 2 The dark saturation current density J0 in region N3 is between 1 and 3 fA / cm. 2 When this optimal passivation level is reached, a roughly fixed junction depth level will appear.

[0062] The N region 3 includes a plurality of second main gate regions extending along a first direction and a plurality of second sub-gate regions extending along a second direction. The sub-gate regions are arranged along the second direction and are connected to the second main gate regions. The first main gate regions and the second main gate regions are alternately arranged along the second direction, and the first sub-gate regions and the second sub-gate regions are alternately arranged along the first direction, so that the P region 2 and the N region 3 are arranged in a forked shape.

[0063] This invention optimizes the N-region 3 using TOPCon battery technology. A tunneling layer 31 and an N-type doped polysilicon layer 32 are formed on the back side of the N-region 3 to create a passivation contact structure. The second electrode 92 is located on the back side of the N-type doped polysilicon layer 32, which avoids direct contact between the second electrode 92 and the silicon substrate 1, thereby improving battery efficiency.

[0064] The tunneling layer 31 is selected from silicon oxide (SiOx) or silicon carbide (SiC), with a thickness of 1nm to 3nm, preferably 1nm to 2.5nm, more preferably 1nm to 2nm or 1.5nm to 2.5nm. The thickness of the tunneling layer 31 is optimized according to its density. When the tunneling layer 31 is SiOx, the thickness is between 1.4nm and 2.3nm; when the tunneling layer 31 is SiC, the film is more dense, with a thickness of 1nm to 1.8nm.

[0065] The N-type doped polysilicon layer 32 is a phosphorus-doped polysilicon layer, a carbon-doped polysilicon layer, or a nitrogen-doped polysilicon layer. The following explanation will use phosphorus doping as an example. The doping concentration is 1E19cm⁻¹. -3 ~1E21cm -3 1E20cm is preferred -3 ~9E20cm -3 The thickness is 80nm~120nm, and can be set to 90nm, 85nm, 100nm, 105nm, 110nm, or 115nm.

[0066] In this invention, the doping concentration of the N-region 3 is lower than that of the N-type doped polycrystalline silicon layer 32. Based on this design, when the phosphorus-doped amorphous silicon layer is annealed to transform into the N-type doped polycrystalline silicon layer 32, phosphorus diffuses inward, passes through the tunneling layer 31, and enters the silicon substrate 1 to form the N-region 3; phosphorus diffusion is not required separately in the N-region 3.

[0067] In an optional embodiment, the doping concentration of the N-region 3 is 1E19cm⁻¹. -3 ~1E20cm -3 The doping concentration of the N-type doped polycrystalline silicon layer 32 is 3E20cm³. -3 ~6E20cm -3 .

[0068] In addition, the back side of the solar cell 100 is provided with a back passivation layer 5 and a back anti-reflection layer 6. The first electrode 91 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the heavily doped region 21. The second electrode 92 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the N-type doped polycrystalline silicon layer 32.

[0069] The back passivation layer 5 is preferably an aluminum oxide layer, providing excellent field passivation for the P-region 2 and excellent interface passivation for the N-region 3. In this invention, the thickness of the back passivation layer 5 is preferably 3 nm to 6 nm.

[0070] The back antireflection layer 6 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm, which reduces reflectivity and improves light utilization.

[0071] In an optional embodiment, the solar cell 100 further includes a front passivation layer 7 and a front antireflection layer 8 sequentially disposed on the front side of the silicon substrate 1 to passivate surface defects on the front side. In this invention, the front passivation layer 7 and the back passivation layer 5 are made of the same material and have the same thickness, and can be deposited together; the front antireflection layer 8 and the back antireflection layer 6 are made of the same material and have the same thickness, and can also be deposited in the same process.

[0072] The present invention also provides a method for preparing a solar cell, comprising the following steps:

[0073] A boron diffusion layer and BSG (borosilicate glass) are formed on the back side of silicon substrate 1, wherein the gate line region of P region 2 is a heavily doped region 21, and the region outside the gate line region is a lightly doped region 22.

[0074] Remove the BSG and boron junction outside of region P2;

[0075] The back side is deposited with a tunneling layer 31, a phosphorus-doped amorphous silicon layer, and a mask layer.

[0076] Annealing transforms the doped amorphous silicon layer into an N-type doped polycrystalline silicon layer 32, and the phosphorus extends into the silicon substrate 1 to form a phosphorus-doped region.

[0077] Remove the mask layer, N-type doped polysilicon layer 32 and tunneling layer 31 outside of the N-region 3 which is spaced apart from the P-region 2;

[0078] The first electrode 91 and the second electrode 92 are fabricated in P region 2 and N region 3, respectively.

[0079] For ease of description, the method for preparing the solar cell of the present invention will be described in detail below.

[0080] S1 forms a boron diffusion layer and a BSG on the back side of the silicon substrate 1, wherein the boron diffusion layer has an SE structure, the gate region of P region 2 is a heavily doped region 21, and the other regions outside the gate region of P region 2 are lightly doped regions 22. Specifically, the steps include the following:

[0081] S11 First, a boron source is formed on the entire back side of the silicon substrate 1. Optionally, the silicon substrate 1 is fixed in a quartz boat, placed in a tube furnace, and a boron source and oxygen are introduced to deposit a layer of boron source (or a source transfer layer) on the back side of the silicon substrate 1. The boron source is boron trichloride (BCl3), with a flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BCl3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer; or, the boron source is boron tribromide (BBr3), with a boron trichloride flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BBr3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer.

[0082] S12 laser processing forms the heavily doped region 21. Specifically, the heavily doped region 21 is formed by laser scanning in the gate line region of P region 2. Laser parameters: laser gas power is 120W, using 63% power for wafer fabrication; laser frequency is 100kHz, and scan speed is 25m / s.

[0083] S13 then forms a lightly doped region 22 outside the gate line region, while simultaneously oxidizing the entire surface to form a layer of BSG.

[0084] In one optional embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen is introduced into the tube furnace at a temperature of 950°C to 1000°C and an oxygen flow rate of 10 s / ml to 15 s / ml. At the high temperature, the boron source in the non-gate region diffuses inward to form a lightly doped region 22, while BSG is formed on the entire surface.

[0085] In one optional embodiment, the sheet resistance after depositing the boron source is 120 ohm / sq to 170 ohm / sq; after laser scanning, the doping concentration of the heavily doped region 21 is 5E18cm⁻¹. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; after high-temperature oxidation, the sheet resistance of the lightly doped region 22 is 200 ohm / sq to 400 ohm / sq.

[0086] S2 “Removing BSG and boron junctions outside of P region 2” includes the following steps:

[0087] S21 Removes the BSG layer outside P region 2. Optionally, laser ablation is performed outside P region 2 to remove the BSG layer. The laser power is 50W~120W, preferably ultraviolet picosecond or green picosecond lasers, which have low damage and low cost; femtosecond lasers can also be used.

[0088] S22 removes the boron junction outside P-region 2. Specifically, it includes the following steps:

[0089] First, the BSG on the front and sides of the silicon substrate 1 is removed using an HF solution with a concentration of 5% to 20% (volume concentration). In an optional embodiment, this step is performed in a chain machine.

[0090] The process then involves polishing to remove the boron junctions outside region P2, as well as the boron junctions extending from the front side. The boron junctions in region P2 and the BSG are retained. In an optional embodiment, this step is performed in a trough mill.

[0091] This step removes the boron junction outside P region 2, as well as the BSG on the front and sides, and the boron junction expanded on the front. The process is simple and lays a good foundation for subsequent processes.

[0092] S3 "Backside Deposition of Tunneling Layer 31, Doped Amorphous Silicon Layer and Mask Layer" includes: growing tunneling layer 31 and phosphorus-doped amorphous silicon layer on the entire backside using PECVD in-situ doping, and then growing a mask layer on the outermost side.

[0093] In one embodiment, the tunneling layer 31 is SiOx, and its thickness is preferably 1.4 nm to 2.3 nm.

[0094] In another embodiment, the tunneling layer 31 is SiC, which is more dense and preferably has a thickness of 1 nm to 1.8 nm.

[0095] The thickness of the N-poly layer is preferably 80nm~120nm.

[0096] The mask layer is preferably a silicon oxide layer, with a thickness controlled in the range of 10nm to 50nm.

[0097] S4 uses a high-temperature annealing furnace, and the annealing temperature can be matched according to the tunneling conditions. The tunneling layer 31 has a large thickness, requiring a high annealing temperature. In an optional embodiment, the annealing temperature is 850℃~950℃, which can be optimally matched with conventional tunneling layers 31, ensuring a doping concentration of 1E19cm⁻¹ in the n-poly region electrochemical doping concentration test (ECV test). -3 ~1E21cm -3 .

[0098] During this process, a BSG layer is retained in the tunneling layer 31 of the P region 2 to prevent the inward diffusion of phosphorus; while outside the P region 2, phosphorus diffuses through the tunneling layer 31 into the silicon substrate 1 to form a phosphorus-doped region.

[0099] The annealing temperature is related to the density and thickness of the tunneling layer 31. In one optional embodiment, when the tunneling layer 31 is silicon oxide, the thickness is 1.4 nm to 2.3 nm and the annealing temperature is 880 °C to 950 °C; when the tunneling layer 31 is silicon carbide, the thickness is 1 nm to 1.8 nm and the annealing temperature is 850 °C to 900 °C, so as to ensure that phosphorus outside the P region 2 diffuses inward to the silicon substrate 1.

[0100] S5 "Removing the mask layer, N-type doped polysilicon layer 32, and tunneling layer 31 outside of the N-region 3 which is spaced apart from the P-region 2" includes the following steps:

[0101] S51 uses a laser process to remove the mask layer outside the N-region 3, exposing the underlying N-type doped polysilicon layer 32. Laser parameters: laser power 50W~120W, preferably ultraviolet picosecond or green picosecond laser; the less damaging the laser, the better for film opening.

[0102] The S52 uses a chain machine and HF solution to remove the mask layer that has been wrapped around the front side.

[0103] S53 then uses a tank machine and alkaline solution (such as NaOH solution) to remove the N-type doped polysilicon layer 32 and tunneling layer 31 outside the N region 3 on the back side; at the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a pyramid structure on the exposed silicon substrate 1, and finally it is cleaned.

[0104] Compared to related technologies that "first form a textured structure on the surface of silicon substrate 1 and then prepare other films", this invention forms a pyramid structure on the front side after the important structures and films of P region 2 and N region 3 are prepared. On the one hand, there is no need to polish the back side before boron diffusion; on the other hand, step S53 removes the N-type doped polysilicon layer 32 and tunneling layer 31 on the back side while forming a pyramid structure on the front side, achieving multiple benefits at once; furthermore, when the front side is flat, it is more conducive to the deposition and cleaning of films in the above steps.

[0105] Furthermore, the boron junction, tunneling layer 31, and N-type doped polysilicon layer 32 between P-region 2 and N-region 3 have all been removed to form isolation region 4, preventing leakage between P-region 2 and N-region 3. In this invention, the width of isolation region 4 is no greater than 100 μm, preferably 10 μm to 80 μm. Under the premise of preventing leakage, the narrower the width of isolation region 4, the less recombination of charge carriers in that region, and the higher the battery efficiency.

[0106] S6 Double-sided passivation. Using the ALD process, aluminum oxide is deposited on both the front and back sides, with a preferred thickness of 3nm~6nm. Al2O3 provides excellent field passivation for P-region 2 and excellent interface passivation for N-region 3. In this invention, the double-sided passivation layer is not a mandatory process step.

[0107] S7 Double-sided antireflective layer: can be a stacked film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm. In this invention, the double-sided antireflective layer is not a necessary process step.

[0108] S8 electrode fabrication: Electrode fabrication is carried out by screen printing and sintering, including the fabrication of the back main gate electrode and the fabrication of the back P region 2 and N region 3 sub-gate electrodes.

[0109] The S9 uses laser-assisted contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, which can improve the contact between silver and silicon in the electrodes, thereby increasing the battery efficiency by more than 0.2% to 0.3%. It can also change the electrode paste, such as using silver-coated copper paste with low silver content, to save costs.

[0110] The laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm~2mm.

[0111] In summary, the solar cell 100 of the present invention improves cell efficiency by placing both the first electrode 91 and the second electrode 92 on the back side, eliminating metal electrode obstruction on the front side, resulting in a large light-receiving area and high light conversion efficiency. Furthermore, by setting an SE structure in the P-region 2, the open-circuit voltage and short-circuit current of the cell are improved; and by setting a passivated contact structure in the N-region 3 to passivate its surface, the short-circuit current is increased, thus improving overall cell efficiency.

[0112] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0113] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, include: The P-region located on the back side includes a heavily doped region and a lightly doped region; The N region located on the back side is provided with a tunneling layer and an N-type doped polysilicon layer; The first electrode is located on the back side of the heavily doped region; The second electrode is located on the back side of the N-type doped polycrystalline silicon layer.

2. The solar cell according to claim 1, characterized in that: The sheet resistance of the heavily doped region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the lightly doped region is 200 ohm / sq to 400 ohm / sq.

3. The solar cell according to claim 1, characterized in that: The diffusion depth of region P is greater than that of region N.

4. The solar cell according to claim 1, characterized in that: The boron junction depth in the P region is 0.5 μm to 1.0 μm.

5. The solar cell according to claim 1, characterized in that: The doping concentration of the N-region is less than the doping concentration of the N-type doped polysilicon layer.

6. The solar cell according to claim 1, characterized in that: The solar cell also includes an isolation region located between the P region and the N region, the width of which is no greater than 100 μm.

7. The solar cell according to claim 1, characterized in that: The solar cell also includes: A back passivation layer and a back anti-reflection layer are located on the back side. The first electrode passes through the back anti-reflection layer and the back passivation layer to contact the heavily doped region. The second electrode passes through the back anti-reflection layer and the back passivation layer to contact the N-type doped polysilicon layer. A passivation layer and an antireflection layer are sequentially disposed on the front side of the silicon substrate.

8. A method for preparing a solar cell, characterized in that: Includes the following steps: A boron diffusion layer and BSG are formed on the back side of a silicon substrate, wherein the gate line region of the P region is a heavily doped region and the region outside the gate line region is a lightly doped region. Remove the BSG and boron junction outside the P region; A tunneling layer, an N-type doped amorphous silicon layer, and a mask layer are formed on the entire back side of a silicon substrate. Annealing transforms the N-type doped amorphous silicon layer into an N-type doped polycrystalline silicon layer, and the phosphorus extends into the silicon substrate to form an N-type doped region. Remove the mask layer, N-type doped polysilicon layer, and tunneling layer outside the N region that is separated from the P region; The first electrode and the second electrode were fabricated in the P region and the N region, respectively.

9. The method for preparing a solar cell according to claim 8, characterized in that: The process of "forming a boron diffusion layer and BSG" includes the following steps: A boron source is formed on the entire back side of the silicon substrate; Laser scanning is used to form heavily doped regions in the gate line region of the P region; The heavily doped silicon substrate is fed into a tube furnace and oxygen is introduced at a temperature of 950℃~1000℃ and an oxygen flow rate of 10sml~15sml. A lightly doped region is formed outside the gate region, and oxygen is introduced at the same time to form a layer of BSG on the entire surface.

10. The method for preparing a solar cell according to claim 9, characterized in that: The sheet resistance of the heavily doped region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the lightly doped region is 200 ohm / sq to 400 ohm / sq.

11. The method for preparing a solar cell according to claim 8, characterized in that: "Removing BSG and boron junctions outside the P region" includes the following steps: Laser ablation is used to remove the BSG layer outside the P region; BSG on the front and side surfaces of the silicon substrate is removed by HF solution with a volume concentration of 5% to 20%. Polishing process removes boron junctions outside the P region, and also removes boron junctions that have been expanded on the front side.

12. The method for preparing a solar cell according to claim 8, characterized in that: The tunneling layer is SiOx with a thickness of 1.4 nm to 2.3 nm; or the tunneling layer is SiC with a thickness of 1 nm to 1.8 nm.

13. The method for preparing a solar cell according to claim 8, characterized in that: The tunneling layer is silicon oxide with a thickness of 1.4 nm to 2.3 nm and an annealing temperature of 880°C to 950°C; or The tunneling layer is a silicon carbide layer with a thickness of 1nm~1.8nm and an annealing temperature of 850℃~900℃.

14. The method for preparing a solar cell according to claim 8, characterized in that: "Removing the mask layer, N-type doped polysilicon layer, and tunneling layer outside the N-region that is separated from the P-region" includes the following steps: Laser ablation removes the mask layer outside the N-region; A chain machine is used to remove the mask layer that has been wrapped around the front side; A trenching machine is used to remove the N-type doped polysilicon layer and tunneling layer outside the N-region on the back side, while forming a pyramid structure on the front side of the silicon substrate.

15. The method for preparing a solar cell according to claim 8, characterized in that: Before fabricating the first and second electrodes, the method for fabricating a solar cell also includes the following steps: Passivation layers are deposited on both the front and back sides. The passivation layers are aluminum oxide layers with a thickness of 3nm to 6nm. Antireflection layers are deposited on both the front and back sides. The antireflection layers are selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the antireflection layers is 60 nm to 130 nm.

16. The method for preparing a solar cell according to any one of claims 8 to 15, characterized in that: After the first electrode and the second electrode are prepared, laser-assisted sintering technology is used to laser sinter the first electrode and the second electrode.

17. The method for preparing a solar cell according to claim 16, characterized in that: The laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm~2mm.

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