Iii-v tandem cell and preparation method therefor

Abstract

A III-V tandem cell and a preparation method therefor, relating to the technical field of solar cells. The preparation method for the III-V tandem cell comprises the following steps: using an XBC cell as a substrate, and sequentially depositing a substrate layer, a tunnel junction layer, a back surface field layer, a body layer, a window layer and an antireflection layer on the front surface of the XBC cell, wherein the tunnel junction layer comprises a GaInP layer and an AlGaAs layer which are sequentially deposited. The method for preparing the III-V tandem cell uses a multi-tunnel junction structure to enhance the passivation effect, thereby improving the cell efficiency.

Description

III-V group tandem solar cells and their preparation methods

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410939839.5, filed on July 12, 2024, entitled “Method for preparing a III-V tandem battery and a III-V tandem battery”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the technical field of solar cells, and more specifically, to a III-V tandem solar cell and its fabrication method. Background Technology

[0004] Group III-V compound solar cells are solar cells made using materials composed of Group III-V elements (nitrogen, phosphorus, arsenic, gallium, and indium). Compared to silicon solar cells, these cells have a wider spectral response range and perform better in high-temperature and low-light-intensity environments. However, existing Group III-V cells suffer from low cell conversion efficiency due to lattice matching issues.

[0005] In view of this, this disclosure is hereby made.

[0006] Public content

[0007] This disclosure provides a III-V tandem solar cell and a method for its fabrication, thereby alleviating at least one technical problem present in the prior art.

[0008] In order to achieve at least one of the above-mentioned objectives of this disclosure, the following technical solution is adopted:

[0009] In a first aspect, this disclosure provides a III-V tandem solar cell, including an XBC cell, wherein the front side of the XBC cell includes a substrate layer, a tunneling junction layer, a back field layer, a bulk region layer, a window layer, and an antireflection layer deposited sequentially; wherein the tunneling junction layer includes a GaInP layer and an AlGaAs layer deposited sequentially.

[0010] In a second aspect, this disclosure provides a method for preparing a III-V tandem solar cell according to the first aspect, the method comprising:

[0011] Using an XBC cell as a substrate, a substrate layer, a tunnel junction layer, a back field layer, a bulk region layer, a window layer, and an anti-reflection layer are sequentially deposited on the front side of the XBC cell.

[0012] The tunneling junction layer comprises a GaInP layer and an AlGaAs layer deposited sequentially.

[0013] Compared with the prior art, the beneficial effects of this disclosure include:

[0014] The method for fabricating a III-V tandem solar cell disclosed herein uses an XBC solar cell as a substrate to fabricate a III-V solar cell on top of it, forming a tandem solar cell, i.e., a series of solar cells. Simultaneously, the multi-tunneling junction structure effectively forms a PN junction. Under illumination, the electron-hole pairs formed in the PN junction are separated by an electric field, thereby generating current, which enhances the passivation effect and thus improves the cell efficiency. Furthermore, a buffer layer is first deposited on the XBC solar cell to avoid lattice distortion of the substrate cell. Then, a tunneling junction layer, a back surface layer, a bulk layer, a window layer, and an anti-reflection layer are deposited, ultimately forming a III-V tandem solar cell based on the XBC solar cell substrate. The III-V tandem solar cell fabricated using this method has high cell efficiency. Attached Figure Description

[0015] Figure 1 is a schematic diagram of the structure of the III-V tandem battery described in this disclosure.

[0016] Among them, 1 is the XBC cell, 2 is the substrate layer, 3 is the GaInP layer, 4 is the AlGaAs layer, 5 is the back field layer, 6 is the bulk layer, 7 is the window layer, and 8 is the anti-reflection layer.

[0017] Figure 2 is a flowchart of the method for preparing the III-V tandem solar cell described in this disclosure. Detailed Implementation

[0018] The embodiments of this disclosure will be described in detail below with reference to examples. However, those skilled in the art will understand that the following examples are for illustrative purposes only and should not be considered as limiting the scope of this disclosure. Unless otherwise specified in the examples, conventional conditions or conditions recommended by the manufacturer shall apply.

[0019] In a first aspect, as shown in Figure 1, this disclosure provides a III-V tandem solar cell, including an XBC cell 1. The front side of the XBC cell 1 includes a substrate layer 2, a tunneling junction layer, a back field layer 5, a bulk region layer 6, a window layer 7, and an anti-reflection layer 8 deposited sequentially. The tunneling junction layer includes a GaInP layer 3 and an AlGaAs layer 4 deposited sequentially.

[0020] In this disclosure, XBC cells are used as a substrate to prepare group III-V cells to form a superimposed cell. At the same time, a PN junction is effectively formed. Under illumination, the electron-hole pairs formed in the PN junction are separated by an electric field, thereby generating current, which can enhance the passivation effect and thus improve the cell efficiency.

[0021] In optional embodiments of this disclosure, the GaInP layer thickness is 50-100nm, for example, it can be 50nm, 55nm, 60nm, 65nm, 70nm, 75nm, 80nm, 850nm, 90nm, 95nm and 100nm.

[0022] In optional embodiments of this disclosure, the thickness of the AlGaAs layer is 40-90 nm, for example, it can be 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm and 90 nm.

[0023] In this disclosure, the GaInP layer and the AlGaAs layer form a tunneling layer structure. Since the band structure of the GaInP and AlGaAs layers is mainly located at the conduction band edge, they can reflect minority carriers, passivate the emitter surface, and reduce surface recombination. Therefore, they serve to connect the top and bottom cells, thereby improving cell efficiency. Simultaneously, both the GaInP and AlGaAs layers have specific thickness ranges to improve cell efficiency. If the GaInP and AlGaAs layers are too thin, it will affect the series connection between the top and bottom cells, thus impacting their performance and leading to lower yield and efficiency. If the thickness is too thick, it will result in a large series resistance connecting the top and bottom cells, reducing cell efficiency.

[0024] In optional embodiments of this disclosure, the XBC battery includes one of a TBC battery, an IBC battery, and an HBC battery.

[0025] In an optional embodiment of this disclosure, the substrate layer is a GaAs substrate layer.

[0026] In optional embodiments of this disclosure, the thickness of the GaAs substrate layer is 2-5 μm, for example, it can be 2 μm, 3 μm, 4 μm and 5 μm.

[0027] In this disclosure, the GaAs substrate layer serves as a buffer layer; without it, lattice distortion occurs in the solar cell. Simultaneously, the GaAs substrate layer has a specific thickness range, which improves cell efficiency. If the GaAs substrate layer is too thin, it reduces carrier transport capacity and leads to decreased crystal quality, resulting in lower cell yield and efficiency. If the GaAs substrate layer is too thick, it lengthens the growth cycle of the outer film, increasing material and time costs. Furthermore, an excessively thick buffer layer introduces significant thermal resistance, affecting the overall performance of the cell.

[0028] In an optional embodiment of this disclosure, the back field layer includes an N+AlGaInP back field layer and / or an N+AlGaAs back field layer.

[0029] In optional embodiments of this disclosure, the thickness of the back field layer is 50-90 nm, for example, it can be 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm and 90 nm.

[0030] In this disclosure, the back field layer can reduce the probability of minority carrier recombination on the back side, thereby increasing the photoelectric conversion efficiency of the cell. Simultaneously, the back field layer has a specific thickness range, which can improve the cell efficiency. If the back field layer is too thin, it will affect its passivation performance, increase the probability of carrier recombination, and reduce the cell efficiency; if the back field layer is too thick, it will increase the absorption of long-wavelength light, affecting the light absorption of the bottom cell and reducing the overall cell yield and efficiency.

[0031] In optional embodiments of this disclosure, the bulk layer includes any one or a combination of at least two of the following: an N-type GaInP bulk layer, an N-type GaAs bulk layer, or an N-type GaInAsP bulk layer.

[0032] In optional embodiments of this disclosure, the thickness of the body layer is 400-800nm, for example, it can be 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, etc.

[0033] In this disclosure, the body layer is the main body of the tandem battery. The body layer has a specific thickness range, which can improve the efficiency of the battery cells. If the body layer is too thin, the long-wavelength light utilization rate of the tandem battery is low, and the overall passivation performance of the battery is reduced. If the body layer is too thick, the short-wavelength light utilization rate of the tandem battery is low, which affects the overall efficiency of the battery.

[0034] In an optional embodiment of this disclosure, the window layer includes a P-type AlInP window layer and / or a P-type GaInP window layer.

[0035] In optional embodiments of this disclosure, the thickness of the window layer is 20-40 nm, for example, it can be 20 nm, 25 nm, 30 nm, 35 nm and 40 nm.

[0036] In this disclosure, the window layer has a larger band gap, which can reflect minority carriers, reduce surface recombination, and increase light absorption and utilization while reducing photon absorption loss. Simultaneously, the window layer has a specific thickness range, which can improve the cell efficiency. If the window layer is too thin, the passivation effect is poor, and minority carrier recombination is severe; if the window layer is too thick, parasitic absorption is severe, affecting the utilization rate of short-wavelength light.

[0037] In optional embodiments of this disclosure, the antireflection layer includes any one or a combination of at least two of ZnS antireflection layer, MgF2 antireflection layer or SiNX antireflection layer.

[0038] In optional embodiments of this disclosure, the thickness of the antireflection layer is 50-90 nm, for example, it can be 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm and 90 nm.

[0039] In this disclosure, the antireflective layer can increase the incident light, thereby improving the photocurrent and efficiency of the solar cell. In particular, the ZnS antireflective layer, due to its high optical transmittance and good crystallinity in the infrared band (2-14 micrometers), possesses a stronger antireflective effect. Simultaneously, the antireflective layer has a specific thickness range, which can improve the antireflective effect of the solar cell and increase light utilization. If the antireflective layer is too thin, it will result in high light reflectivity and poor antireflective effect; if it is too thick, it will increase parasitic light absorption and reduce light utilization.

[0040] In a second aspect, this disclosure provides a method for preparing a III-V tandem solar cell as described in the first aspect, as shown in Figure 2, the method comprising:

[0041] Using an XBC cell as a substrate, a substrate layer, a tunnel junction layer, a back field layer, a bulk region layer, a window layer, and an anti-reflection layer are sequentially deposited on the front side of the XBC cell.

[0042] The tunneling junction layer comprises a GaInP layer and an AlGaAs layer deposited sequentially.

[0043] In an optional embodiment of this disclosure, the GaInP layer is prepared by the following steps:

[0044] PH3, TMGa, and TMIn are introduced into an MOCVD (Metal-Organic Chemical Vapor Deposition) apparatus to deposit the GaInP layer on the substrate.

[0045] In an optional embodiment of this disclosure, preferably, the gas flow rate ratio of PH3, TMGa, and TMIn is (8-17):(2-7):(1-3), wherein "8-17" can be, for example, 8, 9, 10, 11, 12, 13, 14, 15, 16, and 17, etc.; "2-7" can be, for example, 2, 3, 4, 5, 6, and 7, etc.; "1-3" can be, for example, 1, 2, and 3, etc.; and the deposition temperature is 450-600℃, for example, it can be... Temperatures range from 450℃, 500℃, 550℃, and 600℃, with reaction times of 150-250s (e.g., 150s, 160s, 170s, 180s, 190s, 200s, 210s, 220s, 230s, 240s, and 250s) and pressures of 20-50 torr (e.g., 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr).

[0046] In an optional embodiment of this disclosure, the AlGaAs layer is prepared by the following steps:

[0047] AsH3, TMAL, and TMGa are introduced into the MOCVD apparatus to deposit the AlGaAs layer on the GaInP layer.

[0048] In an optional embodiment of this disclosure, the gas flow rate ratio of AsH3, TMAL, and TMGa is (15-30):(3-8):(1-5), where "15-30" can be, for example, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, and 30; "3-8" can be, for example, 3, 4, 5, 6, 7, and 8; "1-5" can be, for example, 1, 2, 3, 4, and 5; the deposition temperature is 450-600℃, for example, 450℃, 500℃, 550℃, and 600℃; and the reaction time is 150-250s. For example, the duration could be 150s, 160s, 170s, 180s, 190s, 200s, 210s, 220s, 230s, 240s, and 250s, with a pressure of 20-50 torr, such as 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr.

[0049] In an optional embodiment of this disclosure, the substrate layer is prepared by the following steps:

[0050] TMGa and AsH3 are introduced into an MOCVD apparatus to deposit the GaAs substrate layer.

[0051] In an optional embodiment of this disclosure, the gas flow rate ratio of TMGa to AsH3 is (30-50):1, where "30-50" can be, for example, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, and 50, etc., and the deposition temperature is 600-700℃, for example, 600℃, 610℃, 620℃, 630℃, 640℃, and 650℃. Temperatures range from 660℃, 670℃, 680℃, 690℃, and 700℃, with reaction times of 300-400s (e.g., 300s, 310s, 320s, 330s, 340s, 350s, 360s, 370s, 380s, 390s, and 400s), and pressures of 20-50 torr (e.g., 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr).

[0052] In an optional embodiment of this disclosure, the back field layer is prepared by the following steps:

[0053] PH3, TMAL, TMGa and TMIn are introduced into the MOCVD equipment to deposit the N+AlGaInP back field layer.

[0054] In an optional embodiment of this disclosure, the gas flow rate ratio of PH3, TMAL, TMGa, and TMIn is (5-10):(4-9):(1-3):(1-2), where "5-10" can be, for example, 5, 6, 7, 8, 9, and 10; "4-9" can be, for example, 4, 5, 6, 7, 8, and 9; "1-3" can be, for example, 1, 2, and 3; the deposition temperature is 450-600℃, for example, 450℃, 500℃, 550℃, and 600℃; the reaction time is 200-300s, for example, 200s, 210s, 220s, 230s, 240s, 250s, and 300s; and the pressure is 20-50 torr, for example, 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr.

[0055] In an optional embodiment of this disclosure, the volumetric layer is prepared by the following steps:

[0056] PH3, TMGa, and TMIn are introduced into the MOCVD equipment to deposit the N-type GaInP bulk layer.

[0057] In an optional embodiment of this disclosure, the gas flow rate ratio of PH3, TMGa, and TMIn is (6-15):(5-10):(1-5), where "6-15" can be, for example, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15, "5-10" can be, for example, 5, 6, 7, 8, 9, and 10, and "1-10" can be, for example, 1, 2, 3, 4, and 5. The deposition temperature is 450-600℃, for example, it can be... Temperatures range from 450℃, 500℃, 550℃, and 600℃, with reaction times of 500-1000s (e.g., 500s, 550s, 600s, 650s, 700s, 750s, 800s, 850s, 600s, 950s, and 1000s). Pressures range from 20-50 torr (e.g., 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr).

[0058] In an optional embodiment of this disclosure, the window layer is prepared by the following steps:

[0059] PH3, TMAl, and TMIn are introduced into the MOCVD apparatus to deposit the P-type AlInP window layer.

[0060] In an optional embodiment of this disclosure, the gas flow rate ratio of PH3, TMAl, and TMIn is (3-8):(2-7):(1-3), where "3-8" can be, for example, 3, 4, 5, 6, 7, and 8; "2-7" can be, for example, 2, 3, 4, 5, 6, and 7; "1-3" can be, for example, 1, 2, and 3; and the deposition temperature is 450-600℃, for example, 450℃, 500℃, 5... Temperatures such as 50℃ and 600℃, reaction times of 100-200s (e.g., 100s, 110s, 120s, 130s, 140s, 150s, 160s, 170s, 180s, 190s, and 200s), and pressures of 20-50 torr (e.g., 20 torr, 25 torr, 30 torr, 35 torr, 40 torr, 45 torr, and 50 torr).

[0061] In an optional embodiment of this disclosure, the antireflective layer is prepared by the following steps:

[0062] A ZnS antireflection layer was deposited using a sputtering process.

[0063] In optional embodiments of this disclosure, the sputtering power is 6-15 kW, for example, it can be 6 kW, 7 kW, 8 kW, 9 kW, 10 kW, 11 kW, 12 kW, 13 kW, 14 kW and 15 kW.

[0064] In an optional embodiment of this disclosure, the fabrication steps of the III-V tandem solar cell fabrication method further include:

[0065] After depositing the antireflective layer, the positive electrode and the back electrode are printed on the back of the XBC cell, followed by sintering and annealing.

[0066] In an optional embodiment of this disclosure, the method for fabricating the III-V tandem solar cell includes the following steps:

[0067] a. Using MOCVD process, a GaAs substrate layer with a thickness of 2-5 μm is deposited on the front side of the XBC battery substrate. TMGa and AsH3 with a gas flow rate ratio of (30-50):1 are introduced. The deposition temperature is 600-700℃, the reaction time is 300-400s, and the pressure is 20-50 torr.

[0068] b. Using MOCVD process, GaInP layer and AlGaAs layer are sequentially deposited on GaAs substrate, forming a tunneling layer structure. The thickness of GaInP layer is 50-100nm. The gas flow rate ratio of PH3, TMGa and TMIn is (8-17):(2-7):(1-3) to deposit GaInP layer on substrate. The deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50torr. The thickness of AlGaAs layer is 40-90nm. The gas flow rate ratio of AsH3, TMAL and TMGa is (15-30):(3-8):(1-5) to deposit AlGaAs layer on GaInP layer. The deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50torr.

[0069] c. An N+AlGaInP back field layer with a thickness of 50-90 nm was deposited on the tunnel junction using MOCVD process. The gas flow rate ratio of PH3, TMAL, TMGa and TMIn was (5-10):(4-9):(1-3):(1-2). The deposition temperature was 450-600℃, the reaction time was 200-300s, and the pressure was 20-50 torr.

[0070] d. An N-type GaInP bulk region with a thickness of 400-800 nm was deposited on the back field layer using MOCVD process. The gas flow rate ratio of PH3, TMGa and TMIn was (6-15):(5-10):(1-5). The deposition temperature was 450-600℃, the reaction time was 500-1000s, and the pressure was 20-50 torr.

[0071] e. A 20-40 nm thick P-type AlInP window layer is deposited on the bulk layer using MOCVD process, with a gas flow rate ratio of (3-8):(2-7):(1-3) of PH3, TMAl and TMIn, a deposition temperature of 450-600℃, a reaction time of 100-200 s, and a pressure of 20-50 torr;

[0072] f. A ZnS antireflection layer with a thickness of 50-90 nm is deposited on the window layer using a sputtering process with a sputtering power of 6-15 kW;

[0073] g. Print the positive electrode and back electrode on the back of the XBC battery and perform sintering annealing to form a complete battery cell.

[0074] Example 1

[0075] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0076] a. Using MOCVD process, a GaAs substrate layer with a thickness of 2 μm was deposited on the front side of the TBC battery substrate. TMGa and AsH3 were introduced at a gas flow rate ratio of 50:1. The deposition temperature was 600℃, the reaction time was 400 s, and the pressure was 20 torr.

[0077] b. Using MOCVD process, GaInP layer and AlGaAs layer are sequentially deposited on GaAs substrate, forming a tunneling layer structure. The GaInP layer is 100 nm thick. PH3, TMGa and TMIn are introduced in a gas flow rate ratio of 8:7:1 to deposit the GaInP layer on the substrate. The deposition temperature is 600℃, the reaction time is 150 s, and the pressure is 50 torr. The AlGaAs layer is 40 nm thick. AsH3, TMAL and TMGa are introduced in a gas flow rate ratio of 30:3:5 to deposit the AlGaAs layer on the GaInP layer. The deposition temperature is 600℃, the reaction time is 150 s, and the pressure is 50 torr.

[0078] c. A 50 nm thick N+AlGaInP back field layer was deposited on the tunnel junction using MOCVD process. The gas flow rate ratio of PH3, TMAL, TMGa and TMIn was 10:4:3:1. The deposition temperature was 600℃, the reaction time was 200s, and the pressure was 50 torr.

[0079] d. An N-type GaInP bulk region with a thickness of 400 nm was deposited on the back field layer using MOCVD process. PH3, TMGa and TMIn were introduced in a gas flow ratio of 15:5:5. The deposition temperature was 600℃, the reaction time was 500s, and the pressure was 50 torr.

[0080] e. A 20 nm thick P-type AlInP window layer was deposited on the bulk layer using MOCVD process, with PH3, TMAl and TMIn gas flow rates of 8:2:3, deposition temperature of 450℃, reaction time of 200 s and pressure of 20 torr.

[0081] f. A 90 nm thick ZnS antireflection layer is deposited on the window layer using a sputtering process with a sputtering power of 6 kW;

[0082] g. Print the positive electrode and back electrode on the back of the TBC battery and perform sintering annealing to form a complete battery cell.

[0083] Example 2

[0084] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0085] a. Using MOCVD process, a GaAs substrate layer with a thickness of 5 μm was deposited on the front side of the TBC battery substrate. TMGa and AsH3 were introduced at a gas flow rate ratio of 30:1. The deposition temperature was 700℃, the reaction time was 300s, and the pressure was 50 torr.

[0086] b. Using MOCVD process, GaInP layer and AlGaAs layer are sequentially deposited on GaAs substrate, forming a tunneling layer structure. The GaInP layer is 50 nm thick. PH3, TMGa and TMIn are introduced in a gas flow ratio of 17:2:3 to deposit the GaInP layer on the substrate. The deposition temperature is 450℃, the reaction time is 250 s, and the pressure is 20 torr. The AlGaAs layer is 90 nm thick. AsH3, TMAL and TMGa are introduced in a gas flow ratio of 15:8:1 to deposit the AlGaAs layer on the GaInP layer. The deposition temperature is 450℃, the reaction time is 250 s, and the pressure is 20 torr.

[0087] c. A 90 nm thick N+AlGaInP back field layer was deposited on the tunnel junction using MOCVD process. The gas flow rate ratio of PH3, TMAL, TMGa and TMIn was 5:9:1:2. The deposition temperature was 450℃, the reaction time was 300s, and the pressure was 20 torr.

[0088] d. An 800 nm thick N-type GaInP bulk region was deposited on the back field layer using MOCVD process. PH3, TMGa and TMIn were introduced in a gas flow ratio of 6:10:1. The deposition temperature was 450 °C, the reaction time was 1000 s, and the pressure was 20 torr.

[0089] e. A 40 nm thick P-type AlInP window layer was deposited on the bulk layer using MOCVD process, with PH3, TMAl and TMIn gas flow rates of 3:7:1, deposition temperature of 600℃, reaction time of 100s and pressure of 50 torr.

[0090] f. A 50 nm thick ZnS antireflection layer is deposited on the window layer using a sputtering process with a sputtering power of 15 kW;

[0091] g. Print the positive electrode and back electrode on the back of the TBC battery and perform sintering annealing to form a complete battery cell.

[0092] Example 3

[0093] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0094] a. Using MOCVD process, a GaAs substrate layer with a thickness of 4 μm was deposited on the front side of the TBC battery substrate. TMGa and AsH3 were introduced at a gas flow rate ratio of 40:1. The deposition temperature was 650℃, the reaction time was 350s, and the pressure was 35 torr.

[0095] b. Using MOCVD process, GaInP layer and AlGaAs layer are sequentially deposited on GaAs substrate, forming a tunneling layer structure. The GaInP layer is 75 nm thick. PH3, TMGa and TMIn are introduced in a gas flow ratio of 13:4:2 to deposit the GaInP layer on the substrate. The deposition temperature is 500℃, the reaction time is 200 s, and the pressure is 35 torr. The AlGaAs layer is 75 nm thick. AsH3, TMAL and TMGa are introduced in a gas flow ratio of 25:6:3 to deposit the AlGaAs layer on the GaInP layer. The deposition temperature is 500℃, the reaction time is 200 s, and the pressure is 35 torr.

[0096] c. A 70 nm thick N+AlGaInP back field layer was deposited on the tunnel junction using MOCVD process. The gas flow rate ratio of PH3, TMAL, TMGa and TMIn was 8:7:2:2. The deposition temperature was 500℃, the reaction time was 150s, and the pressure was 35 torr.

[0097] d. An N-type GaInP bulk region with a thickness of 600 nm was deposited on the back field layer using MOCVD process. PH3, TMGa and TMIn were introduced in a gas flow ratio of 12:8:3. The deposition temperature was 500℃, the reaction time was 7500s, and the pressure was 35 torr.

[0098] e. A 30 nm thick P-type AlInP window layer was deposited on the bulk layer using MOCVD process, with PH3, TMAl and TMIn gas flow rates of 6:4:2, deposition temperature of 500℃, reaction time of 150 s and pressure of 35 torr.

[0099] f. A 70 nm thick ZnS antireflection layer is deposited on the window layer using a sputtering process with a sputtering power of 10 kW;

[0100] g. Print the positive electrode and back electrode on the back of the TBC battery and perform sintering annealing to form a complete battery cell.

[0101] Example 4

[0102] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0103] The thickness of the GaAs substrate layer in step a is 1 μm, and the remaining steps are the same as in Example 3.

[0104] Example 5

[0105] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0106] The thickness of the GaAs substrate layer in step a is 7 μm, and the remaining steps are the same as in Example 3.

[0107] Example 6

[0108] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0109] The GaInP layer thickness in step b is 30 nm, and the remaining steps are the same as in Example 3.

[0110] Example 7

[0111] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0112] The GaInP layer thickness in step b is 120 nm, and the remaining steps are the same as in Example 3.

[0113] Example 8

[0114] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0115] The AlGaAs layer thickness in step b is 20 nm, and the remaining steps are the same as in Example 3.

[0116] Example 9

[0117] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0118] The AlGaAs layer thickness in step b is 110 nm, and the remaining steps are the same as in Example 3.

[0119] Example 10

[0120] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0121] The thickness of the N+AlGaInP back field layer in step c is 30 nm, and the remaining steps are the same as in Example 3.

[0122] Example 11

[0123] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0124] The thickness of the N+AlGaInP back field layer in step c is 110 nm, and the remaining steps are the same as in Example 3.

[0125] Example 12

[0126] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0127] The thickness of the N-type GaInP bulk layer in step d is 350 nm, and the remaining steps are the same as in Example 3.

[0128] Example 13

[0129] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0130] The thickness of the N-type GaInP bulk layer in step d is 850 nm, and the remaining steps are the same as in Example 3.

[0131] Example 14

[0132] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0133] In step e, the thickness of the P-type AlInP window layer is 10 nm, and the remaining steps are the same as in Example 3.

[0134] Example 15

[0135] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0136] In step e, the thickness of the P-type AlInP window layer is 50 nm, and the remaining steps are the same as in Example 3.

[0137] Example 16

[0138] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0139] In step f, the thickness of the ZnS antireflection layer is 40 nm, and the remaining steps are the same as in Example 3.

[0140] Example 17

[0141] This embodiment provides a method for fabricating a III-V tandem solar cell, including the following steps:

[0142] In step f, the thickness of the ZnS antireflection layer is 100 nm, and the remaining steps are the same as in Example 3.

[0143] Example 18

[0144] This embodiment provides a III-V group stack, which differs from Embodiment 1 only in that the back field layer is replaced with an N+AlGaAs back field layer of equal thickness.

[0145] Example 19

[0146] This embodiment provides a type III-V stack, which differs from Embodiment 1 only in that the bulk layer is replaced with an N-type GaAs bulk layer of equal thickness.

[0147] Example 20

[0148] This embodiment provides a 3-5 family stack, which differs from Embodiment 1 only in that the bulk layer is replaced with an N-type GaInAsP bulk layer of equal thickness.

[0149] Example 21

[0150] This embodiment provides a 3-5 family stack, which differs from Embodiment 1 only in that the window layer is replaced with a P-type GaInP window layer of equal thickness.

[0151] Example 22

[0152] This embodiment provides a 3-5 group stacked layer, which differs from Embodiment 1 only in that the antireflection layer is replaced with an antireflection layer of equal thickness MgF2.

[0153] Example 23

[0154] This embodiment provides a 3-5 family stacked layer, the only difference from Embodiment 1 is that the antireflection layer is replaced with SiN of equal thickness. X Anti-reflective layer.

[0155] Comparative Example 1

[0156] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0157] Step a is skipped; instead, the GaInP and AlGaAs layers from step b are deposited directly on the front side of the TBC cell. The remaining steps are the same as in Example 3.

[0158] Comparative Example 2

[0159] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0160] Step b is omitted; instead, an N+AlGaInP back field layer is deposited on the substrate, and the remaining steps are the same as in Example 3.

[0161] Comparative Example 3

[0162] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0163] In step b, no GaInP layer is deposited; the remaining steps are the same as in Example 3.

[0164] Comparative Example 4

[0165] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0166] In step b, no AlGaAs layer is deposited; the remaining steps are the same as in Example 3.

[0167] Comparative Example 5

[0168] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0169] Step c is omitted; instead, an N-type GaInP bulk layer is deposited on the tunneling layer, and the remaining steps are the same as in Example 3.

[0170] Comparative Example 6

[0171] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0172] Step d is omitted; instead, a P-type AlInP window layer is deposited on the back field layer, and the remaining steps are the same as in Example 3.

[0173] Comparative Example 7

[0174] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0175] Step e is omitted; a ZnS antireflection layer is deposited on the N-type GaInP bulk layer, and the remaining steps are the same as in Example 3.

[0176] Comparative Example 8

[0177] This comparative example provides a method for preparing a III-V tandem solar cell, including the following steps:

[0178] Step f is omitted; the remaining steps are the same as in Example 3.

[0179] Test case

[0180] Test samples: III-V tandem solar cells prepared in Examples 1-23 and III-V tandem solar cells prepared in Comparative Examples 1-8.

[0181] Test method: The Eff of the solar cell was measured using a Halm meter.

[0182] The test results are shown in Table 1 below:

[0183] Table 1

[0184] As shown in Table 1, compared with Example 3, Comparative Examples 1-8 are III-V tandem solar cells lacking the substrate layer, tunneling junction layer, GaInP layer, AlGaAs layer, back field layer, bulk layer, window layer, and antireflection layer, respectively. The cell efficiency of Example 3 is higher than that of Comparative Examples 1-8. Examples 4-17 are III-V tandem solar cells with layer thicknesses not within a specific range. It can be seen that the cell efficiency can only be improved if the layer thicknesses are within a specific range. Examples 18-23 replace the back field layer, bulk layer, window layer, and antireflection layer with materials within the preferred range of this application based on Example 1, and it is found that the cell efficiency can be improved.

[0185] This disclosure also provides the following notes:

[0186] 1. A method for fabricating a III-V tandem solar cell, comprising:

[0187] Using an XBC cell as a substrate, a substrate layer, a tunnel junction layer, a back field layer, a bulk region layer, a window layer, and an anti-reflection layer are sequentially deposited on the front side of the XBC cell.

[0188] The tunneling junction layer comprises a GaInP layer and an AlGaAs layer deposited sequentially.

[0189] 2. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the GaInP layer has a thickness of 50-100 nm;

[0190] Preferably, PH3, TMGa and TMIn are introduced into the MOCVD equipment to deposit the GaInP layer on the substrate layer;

[0191] Preferably, the gas flow rate ratio of PH3, TMGa and TMIn is (8-17):(2-7):(1-3), the deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50 torr;

[0192] Preferably, the AlGaAs layer has a thickness of 40-90 nm;

[0193] Preferably, AsH3, TMAL and TMGa are introduced into the MOCVD equipment to deposit the AlGaAs layer on the GaInP layer;

[0194] Preferably, the gas flow rate ratio of AsH3, TMAL and TMGa is (15-30):(3-8):(1-5), the deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50 torr.

[0195] 3. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the deposition of the substrate layer includes: depositing a GaAs substrate layer on the substrate;

[0196] Preferably, TMGa and AsH3 are introduced into the MOCVD equipment to deposit the GaAs substrate layer;

[0197] Preferably, the thickness of the GaAs substrate layer is 2-5 μm;

[0198] Preferably, the gas flow rate ratio of TMGa to AsH3 is (30-50):1, the deposition temperature is 600-700℃, the reaction time is 300-400s, and the pressure is 20-50 torr.

[0199] 4. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the deposition of the back field layer includes: depositing an N+AlGaInP back field layer on the tunnel junction layer;

[0200] Preferably, PH3, TMAL, TMGa and TMIn are introduced into the MOCVD equipment to deposit the N+AlGaInP back field layer;

[0201] Preferably, the thickness of the N+AlGaInP back field layer is 50-90 nm;

[0202] Preferably, the gas flow rate ratio of PH3, TMAL, TMGa and TMIn is (5-10):(4-9):(1-3):(1-2), the deposition temperature is 450-600℃, the reaction time is 200-300s, and the pressure is 20-50 torr.

[0203] 5. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the deposition body layer includes: depositing an N-type GaInP body layer on the back field layer;

[0204] Preferably, PH3, TMGa and TMIn are introduced into the MOCVD equipment to deposit the N-type GaInP bulk layer;

[0205] Preferably, the thickness of the N-type GaInP bulk layer is 400-800 nm;

[0206] Preferably, the gas flow rate ratio of PH3, TMGa and TMIn is (6-15):(5-10):(1-5), the deposition temperature is 450-600℃, the reaction time is 500-1000s, and the pressure is 20-50 torr.

[0207] 6. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the deposition window layer comprises: depositing a P-type AlInP window layer on the bulk region layer;

[0208] Preferably, PH3, TMAl, and TMIn are introduced into the MOCVD equipment to deposit the P-type AlInP window layer;

[0209] Preferably, the thickness of the P-type AlInP window layer is 20-40 nm;

[0210] Preferably, the gas flow rate ratio of PH3, TMAl and TMIn is (3-8):(2-7):(1-3), the deposition temperature is 450-600℃, the reaction time is 100-200s, and the pressure is 20-50 torr.

[0211] 7. The method for fabricating a III-V tandem solar cell according to Appendix 1, wherein the deposition of the antireflection layer includes: depositing a ZnS antireflection layer on the window layer;

[0212] Preferably, a ZnS antireflection layer is deposited using a sputtering process;

[0213] Preferably, the thickness of the ZnS antireflection layer is 50-90 nm;

[0214] Preferably, the sputtering power is 6-15 kW.

[0215] 8. The method for preparing a III-V tandem solar cell according to Appendix 1, wherein the preparation steps of the method further include:

[0216] After depositing the antireflective layer, the positive electrode and the back electrode are printed on the back of the XBC cell, followed by sintering and annealing.

[0217] 9. The method for preparing a III-V tandem battery according to Appendix 1, wherein,

[0218] The XBC battery includes one of the following: TBC battery, IBC battery, and HBC battery.

[0219] 10. A III-V tandem battery prepared by the method described in any one of Appendices 1-9.

[0220] Although this disclosure has been illustrated and described with reference to specific embodiments, it should be understood that many other changes and modifications can be made without departing from the spirit and scope of this disclosure. Therefore, it is intended that all such changes and modifications falling within the scope of this disclosure be included in the appended claims.

Claims

1. A type of III-V tandem battery, characterized in that, The XBC cell includes a substrate layer, a tunneling junction layer, a back field layer, a bulk region layer, a window layer, and an antireflection layer deposited sequentially on its front side; wherein the tunneling junction layer includes a GaInP layer and an AlGaAs layer deposited sequentially.

2. The III-V group tandem battery according to claim 1, characterized in that, The thickness of the GaInP layer is 50-100 nm; And / or, the thickness of the AlGaAs layer is 40-90 nm.

3. The III-V group tandem battery according to claim 1, characterized in that, The XBC battery includes one of the following: TBC battery, IBC battery, and HBC battery.

4. The III-V tandem battery according to claim 1, characterized in that, The substrate layer is a GaAs substrate layer; And / or, the thickness of the substrate layer is 2-5 μm.

5. The III-V group tandem battery according to claim 1, characterized in that, The back field layer includes an N+AlGaInP back field layer and / or an N+AlGaAs back field layer. And / or, the thickness of the back field layer is 50-90 nm.

6. The III-V tandem battery according to claim 1, characterized in that, The bulk region layer includes any one or a combination of at least two of the following: N-type GaInP bulk region layer, N-type GaAs bulk region layer, or N-type GaInAsP bulk region layer. And / or, the thickness of the body layer is 400-800 nm.

7. The III-V group tandem battery according to claim 1, characterized in that, The window layer includes a P-type AlInP window layer and / or a P-type GaInP window layer; And / or, the thickness of the window layer is 20-40 nm.

8. The III-V group tandem battery according to claim 1, characterized in that, The antireflection layer includes a ZnS antireflection layer, a MgF2 antireflection layer, or a SiN antireflection layer. X Any one or at least two of the antireflective layers; And / or, the thickness of the antireflective layer is 50-90 nm.

9. A method for preparing a III-V tandem battery according to any one of claims 1-8, characterized in that, The preparation method includes: Using an XBC cell as a substrate, a substrate layer, a tunnel junction layer, a back field layer, a bulk region layer, a window layer, and an anti-reflection layer are sequentially deposited on the front side of the XBC cell. The tunneling junction layer comprises a GaInP layer and an AlGaAs layer deposited sequentially.

10. The preparation method according to claim 9, characterized in that, The GaInP layer is prepared by the following steps: PH3, TMGa and TMIn are introduced into the MOCVD equipment to deposit the GaInP layer on the substrate layer; And / or, the gas flow rate ratio of PH3, TMGa and TMIn is (8-17):(2-7):(1-3), the deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50 torr.

11. The preparation method according to claim 9, characterized in that, The AlGaAs layer is prepared by the following steps: AsH3, TMAL and TMGa are introduced into the MOCVD equipment to deposit the AlGaAs layer on the GaInP layer; And / or, the gas flow rate ratio of AsH3, TMAL and TMGa is (15-30):(3-8):(1-5), the deposition temperature is 450-600℃, the reaction time is 150-250s, and the pressure is 20-50 torr.

12. The preparation method according to claim 9, characterized in that, The substrate layer is prepared by the following steps: TMGa and AsH3 are introduced into an MOCVD apparatus to deposit the GaAs substrate layer; And / or, the gas flow rate ratio of TMGa to AsH3 is (30-50):1, the deposition temperature is 600-700℃, the reaction time is 300-400s, and the pressure is 20-50 torr.

13. The preparation method according to claim 9, characterized in that, The back field layer is prepared by the following steps: PH3, TMAL, TMGa and TMIn are introduced into the MOCVD equipment to deposit the N+AlGaInP back field layer; And / or, the gas flow rate ratio of PH3, TMAL, TMGa and TMIn is (5-10):(4-9):(1-3):(1-2), the deposition temperature is 450-600℃, the reaction time is 200-300s, and the pressure is 20-50 torr.

14. The preparation method according to claim 9, characterized in that, The volumetric layer is prepared by the following steps: PH3, TMGa and TMIn are introduced into the MOCVD equipment to deposit the N-type GaInP bulk layer; And / or, the gas flow rate ratio of PH3, TMGa and TMIn is (6-15):(5-10):(1-5), the deposition temperature is 450-600℃, the reaction time is 500-1000s, and the pressure is 20-50 torr.

15. The preparation method according to claim 9, characterized in that, The window layer is prepared by the following steps: PH3, TMAl, and TMIn are introduced into the MOCVD equipment to deposit the P-type AlInP window layer; And / or, the gas flow rate ratio of PH3, TMAl and TMIn is (3-8):(2-7):(1-3), the deposition temperature is 450-600℃, the reaction time is 100-200s, and the pressure is 20-50 torr.

16. The preparation method according to claim 9, characterized in that, The antireflective layer is prepared by the following steps: A ZnS antireflection layer was deposited using a sputtering process; And / or, the sputtering power is 6-15 kW.

17. The preparation method according to claim 9, characterized in that, The preparation steps of the method for preparing the III-V tandem solar cell also include: After depositing the antireflective layer, the positive electrode and the back electrode are printed on the back of the XBC cell, followed by sintering and annealing.

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