Method for reducing bus load, CXL module, processing system, and processor chip

Abstract

A method for reducing the bus load, a CXL module, a processing system, and a processor chip, applied to the field of computers. In the processing system comprising a plurality of processing units, each processing unit acquires configuration information of a coherence cache area by means of a configuration interface having cache coherence, and a partial area of a cache of a current processing unit is configured as a coherence cache area, so as to use the coherence cache area to cache data in shared memories of a plurality of processing units. The CXL module can acquire configuration information of the shared memories by means of a shared memory configuration instruction at configuration interfaces of the shared memories, and configure partial memory areas in memory mediums as the shared memories.

Description

Methods to reduce bus load, CXL module, processing system and processor chip

[0001] This application claims priority to Chinese patent application No. 202410925305.7, filed on July 10, 2024, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of computers, and particularly to a method for reducing bus load, a CXL module, a processing system, and a processor chip. Background Technology

[0003] In some multiprocessor architectures, multiple processor chips are connected via a bus. Each processor chip contains a processor and memory. Memory connected to the processor via a high-bandwidth interface can be used as a cache to provide high-performance computing capabilities. Multiprocessor architectures can use cache coherency protocols to ensure that modifications made by one processor are visible to all other processors, preventing situations where one processor modifies data but other processors still see outdated data. Simultaneously, it's necessary to ensure that the order in which different processors access shared data conforms to a predefined operation order to prevent data inconsistencies caused by out-of-order execution or concurrent access. This mechanism can improve system performance and concurrent access efficiency while guaranteeing data integrity.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] This disclosure provides a CXL module, which includes a CXL controller and a memory medium connected to the CXL controller. The CXL controller is configured to perform the following processes:

[0007] The system receives and parses shared memory configuration instructions to obtain shared memory configuration information; wherein, the shared memory is a memory region shared by multiple processing units connected to the CXL module.

[0008] The address range of the shared memory is determined based on the configuration information of the shared memory;

[0009] Based on the address range of the shared memory, a portion of the memory region in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0010] This disclosure also provides a shared memory configuration method applied to a CXL module, the CXL module including a CXL controller and a memory medium connected to the CXL controller, the method including:

[0011] The system receives and parses shared memory configuration instructions to obtain shared memory configuration information; wherein, the shared memory is a memory region shared by multiple processing units connected to the CXL module.

[0012] The address range of the shared memory is determined based on the configuration information of the shared memory;

[0013] Based on the address range of the shared memory, a portion of the memory region in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0014] The embodiments disclosed herein extend the CXL protocol by adding an interface for shared memory configuration. The CXL module parses the shared memory configuration information according to the shared memory configuration instructions defined by this interface; then, based on the shared memory configuration information, it determines the address range of the shared memory, thereby configuring a portion of the memory region in the memory medium as the shared memory, and only maintaining cache consistency for the data in the shared memory. That is, the size of the shared memory in the CXL module can be limited by configuration, and the CXL module only maintains cache consistency for the data in the shared memory. By limiting the size of the shared memory in the CXL module to a set range through configuration, the embodiments of this disclosure can prevent excessively frequent cache consistency maintenance operations from causing excessive bus load.

[0015] This disclosure also provides a processing system, including a bus and multiple processing units connected via the bus. Each processing unit is equipped with a cache and has a cache consistency configuration interface. The processing unit is configured to:

[0016] The configuration information of the consistent cache region is obtained through the configuration interface of the cache consistency, and the address range of the consistent cache region is determined based on the configuration information of the consistent cache region.

[0017] Based on the address range of the consistency cache region, a portion of the cache of this processing unit is configured as a consistency cache region to cache data in the shared memory of multiple processing units using the consistency cache region.

[0018] This disclosure also provides a method for reducing bus load, applied to a system including multiple processing units connected via a bus, wherein each processing unit is configured with a cache and has a cache consistency configuration interface, the method comprising:

[0019] The processing unit obtains the configuration information of the consistency cache region through the configuration interface of the cache consistency, and determines the address range of the consistency cache region based on the configuration information of the consistency cache region;

[0020] The processing unit configures a portion of its cache as a consistency cache region based on the address range of the consistency cache region, so as to use the consistency cache region to cache data in the shared memory of multiple processing units.

[0021] This disclosure also provides a processor chip including a processor core and a cache, the processor core being configured to perform a method for reducing bus load as described in any embodiment of this disclosure, executed by a processing unit.

[0022] This disclosure also provides a non-transient computer storage medium storing a computer program, which, when executed by a processor, can implement the method for reducing bus load described in any embodiment of this disclosure.

[0023] This disclosure also provides a computer product that, when executed by a processor, can implement the method for reducing bus load described in any embodiment of this disclosure.

[0024] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0026] Overview of the attached figures

[0027] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0028] Figure 1 is a schematic diagram of a multiprocessor architecture according to an embodiment of the present disclosure;

[0029] Figure 2 is a flowchart of a method for reducing bus load according to an embodiment of the present disclosure;

[0030] Figure 3 is a schematic diagram of the cache region division of a processing unit according to an embodiment of the present disclosure;

[0031] Figure 4 is a schematic diagram of the memory region division in a CXL module according to an embodiment of this disclosure;

[0032] Figure 5 is a schematic diagram of the address mapping between the coherence cache region in a processor chip and the shared memory in multiple CXL modules according to an embodiment of the present disclosure;

[0033] Figure 6 is a schematic diagram of a method for finding cached data based on an address according to an embodiment of the present disclosure;

[0034] Figure 7 is a flowchart of a shared memory configuration method according to an embodiment of the present disclosure.

[0035] Detailed Explanation

[0036] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0037] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form an inventive scheme protected by this disclosure. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another inventive scheme protected by this disclosure. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0038] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0039] Figure 1 illustrates an exemplary multiprocessor architecture according to an embodiment of this disclosure. This architecture includes multiple processors interconnected via a bus. The processors reside in different processor chips, which provide CXL interfaces and are interconnected via a CXL bus. Each processor chip may include one or more processor cores (only one is shown in the figure). The processors in the multiprocessor architecture can also be connected via other types of buses, such as the Peripheral Component Interconnect Express (PCIe) bus. Multiple processors can be connected via an interconnect network. The buses between the processors can be shared or independent, depending on the system design. The bus connections shown in the figure are merely illustrative.

[0040] The processor in this embodiment can be a Graphics Processing Unit (GPU), a Central Processing Unit (CPU), or other types of processors. A single processor chip can also integrate one or more processor cores, which can be of the same or different types. The processor chip encapsulates memory media and processor cores, which are connected via a high-bandwidth interface. This high-bandwidth interface has a capacity and bandwidth far exceeding that of general-purpose Double Data Rate Synchronous Dynamic Random Access Memory (DDR). In the illustrated example, this memory media is embedded Dynamic Random Access Memory (DRAM) integrated into the processor chip, such as High Bandwidth Memory (HBM) or GDDR6X. This memory media can be used as a processor cache to provide high-performance computing capabilities. The processor chip may also include other memory interfaces (such as a DDR interface, not shown in the figure) for connecting external memory devices, as well as clock circuitry, memory management components, etc.

[0041] In a multiprocessor architecture, multiple processors can access the same memory region, known as shared memory. Multiple processors can have one or more shared memory regions, which can be regions within the processor's local memory, regions within the memory of external devices such as CXL modules, or regions encompassing both local and external memory. In a multiprocessor architecture, each processor can have its own cache. To ensure consistent access to shared data across different processors, a cache coherence protocol is needed to maintain the consistency of data in shared memory across the caches of each processor (cache coherence) to improve system performance and concurrent access efficiency.

[0042] Operations related to maintaining cache coherency in multiprocessor architectures may include:

[0043] The processor needs to constantly monitor operations related to cache lines on the bus. Operations on cache lines by other processors will trigger bus broadcast events, thereby increasing the bus load.

[0044] After receiving a bus sniffing event, the processor needs to compare it with the cache line in the corresponding cache area of ​​the processor to decide whether to modify the state of the current cache line.

[0045] Furthermore, when the processor core (such as x64) uses a store buffer, the latency will increase significantly when writing data from the store buffer back to main memory via the CXL interface. This will also affect the communication overhead of the bus and increase the bus load.

[0046] CXL is developed based on PCIe 5.0 and runs on top of the PCIe physical layer. Based on the characteristics of memory access, CXL is divided into three sub-protocols: CXL.io, CXL.mem, and CXL.cache. Correspondingly, CXL devices are divided into three types: Type 1 CXL device, Type 2 CXL device, and Type 3 CXL device. Both Type 2 and Type 3 devices have dedicated device memory, which can be DDR, HBM, etc. Taking Type 2 devices as an example, they can be accelerator cards (such as GPUs) in real-world applications, with the host providing data and the accelerator card handling computation. The Host Direct Management (HDM) model allows the host to directly manage and control the storage space on the Type 2 device, dynamically allocating and configuring device memory according to application needs and performing direct read and write operations. Type 3 devices can provide the host with large-capacity DRAM and can also support persistent media (i.e., non-volatile media, including flash memory chips).

[0047] Optionally, as shown in Figure 1, multiple processors in a multiprocessor architecture can also be connected to the CXL module via a CXL bus. The CXL module disclosed herein refers to a CXL device including memory media, such as a Type 2 device, a Type 3 device, etc. As shown in the figure, the CXL module includes a control chip and one or more memory media connected to the control chip, wherein the memory media in the illustrated example is a DRAM chip. The memory in this CXL module can serve as extended memory for the processors connected to it. This extended memory can be used to store data shared by multiple processors or multiple processing cores, such as storing global variables and other types of data as shared memory.

[0048] In the multiprocessor architecture of this embodiment, the processor chip uses a large-capacity and high-bandwidth memory medium, thus increasing the available cache space; the processor chips are connected based on the CXL bus, and the memory usage range can be expanded based on the CXL module, thus increasing the available memory range as well. However, this also introduces the following problems:

[0049] 1) The increase in data cached by each processor leads to an increase in the overhead of maintaining cache coherency on the bus; in extreme cases, if only one cacheline is maintained for maintaining cache coherency, the related signaling interactions will be minimized.

[0050] 2) CXL access latency is longer compared to local DDR access latency. After the current CPU broadcasts an event on the bus, the broadcast event may trigger other processors to access CXL memory first (e.g., refresh the current processor's cache data) before responding to the current CPU with the broadcast event feedback, increasing processing latency and leading to increased bus load. One possible cause is a local write operation by the host CPU. If a cache line at the same location in the CXL device is in a modified state, the data needs to be written back to main memory and its state modified. Simultaneously, the state of the current host CPU's cache line is modified (the latency of writing data back to main memory by the CXL device is relatively long). The long data feedback time results in slow control information exchange, and excessive access latency also leads to bus congestion. Each cache line contributes to the bus interaction load, and these problems are exacerbated when the number of caches requiring cache consistency maintenance is large (i.e., a large number of cache lines).

[0051] 3) The high latency of CXL is determined by the CXL path. When cache coherency information arrives at the CXL device, the algorithm for finding a specific cacheline based on a specific address also introduces latency. With a large cache, the load on the processor chip to locate the cacheline increases, leading to low cacheline location efficiency and indirectly increasing feedback latency. In other words, latency increases with the number of cachelines. Cacheline location can occur at either the host (e.g., processor) or the CXL device.

[0052] Therefore, bus load is related to the number of cachelines used to maintain consistency and the latency of consistency signaling interactions, the latter of which is related to the efficiency of the device and host in locating cachelines.

[0053] While the above examples use multi-processor architectures, other systems with multiple processing units also exhibit these issues. For instance, in some multi-core chipsets, there are problems with shared memory and maintaining cache coherency among the multiple processor cores. If the cache size of a processor core is too large, it can lead to excessive bus load across multiple processor cores. Similarly, distributed systems or other systems involving large-scale parallel computing that include multiple processors and require cache coherency maintenance also face similar problems.

[0054] In practical applications, the scope of shared memory for multi-core processes is relatively small. For example, in the training process based on AI or large language models, there is less data interaction between layers. From the perspective of CPU or GPU parallelism, this means that there are fewer scenarios with large-scale data interaction between cores. In other words, in some scenarios, it is not necessary to maintain cache consistency for all caches and external memory.

[0055] For systems with large cache spaces (such as processors or processor cores) that require cache coherency maintenance, some embodiments of this disclosure add a cache coherency configuration interface (e.g., defining corresponding configuration instructions) to configure the cache region for cache coherency in the processing unit, reducing the number of cachelines for cache coherency and thus reducing the bus overhead for maintaining system coherency. In some embodiments of this disclosure, a cache coherency configuration interface is added to configure a region of shared memory for multiple processing units, reducing the capacity of shared memory and thus reducing the bus overhead for maintaining system coherency. In some embodiments of this disclosure, the cacheline search algorithm in the cache is improved to increase cacheline location efficiency, reducing feedback latency and thus reducing the bus overhead for maintaining system coherency.

[0056] It should be noted that although the embodiments of this disclosure are more effective when applied to processing units with larger cache spaces, the application of the embodiments of this disclosure is not limited to the size of the cache space. They can also be applied to systems that require maintaining cache consistency, including processing units with smaller cache spaces, and can also reduce the load on the bus.

[0057] One embodiment of this disclosure provides a method for reducing bus load, applied to a system including multiple processing units connected via a bus, wherein each processing unit is equipped with a cache and has a configuration interface for cache consistency, as shown in FIG2. The method includes:

[0058] Step 110: The processing unit obtains the configuration information of the consistency cache region through the configuration interface of the cache consistency, and determines the address range of the consistency cache region based on the configuration information of the consistency cache region;

[0059] Step 120: The processing unit configures a portion of its cache as a consistency cache region based on the address range of the consistency cache region, so as to use the consistency cache region to cache data in the shared memory of multiple processing units.

[0060] The method in this embodiment divides the processing unit's cache into two parts, as shown in Figure 3: a coherence area and other cache areas, marked as non-coherence areas in the figure. The processing unit uses the coherence area to cache data in the shared memory of multiple processing units. This means that when a processing unit caches data in the shared memory of multiple processing units, it caches it in the coherence area configured for that processing unit and not in the non-coherence area. This embodiment can set a cache consistency configuration interface for one or more processing units in the system. When setting a cache consistency configuration interface for multiple processing units, the configuration interfaces for multiple processing units can be independent of each other or a unified interface can be used. The types of configuration interfaces for different processing units can be the same or different.

[0061] The non-uniform cache region in Figure 3 can be further subdivided into multiple regions of different natures to meet actual needs. In one example, embedded DRAM (such as HBM) in the processor chip can be used as a cache for the processing unit, and the capacity of this cache is much larger than that of traditional caches, reaching the GB level.

[0062] The relevant technologies do not have an interface for partitioning the cache into the aforementioned regions. This embodiment adds a configuration interface for cache consistency, which allows a portion of the processing unit's cache to be designated as a consistency cache region for that processing unit. This allows for configuration to limit the size of the consistency cache region for that processing unit, instead of using all of the processing unit's cache space to cache data in the shared memory of multiple processing units. Because the data in the shared memory of multiple processing units is only cached in the consistency cache region of each individual processing unit, limiting the size of the consistency cache region within a set range prevents excessive bus load caused by maintaining cache consistency when the number of cache lines in the consistency cache region is too large.

[0063] In this embodiment, the processing unit is a processor or a processor core. The types of multiple processing units in the system can be the same or different. In one example, all multiple processing units are processors, and the system including multiple processing units can be a system with a multi-processor architecture; in another example, all multiple processing units are processor cores, and the system including multiple processing units can include a multi-core processor architecture; in yet another example, some of the multiple processing units are processors, and others are processor cores, then the system includes both multi-core processors and single-core processors. The processor core can be a CPU core, but is not limited to this. It should also be noted that the system to which this method is applied only needs to have multiple processing units connected via a bus and equipped with caches; it is not required that all processing units in the system be connected via a bus, nor that all processing units have their own caches.

[0064] In one exemplary embodiment of this disclosure, the cache capacity of at least one of the processing units is greater than or equal to 128M, or greater than or equal to 256M. The cache space can be provided by an embedded high-bandwidth memory integrated into the processor chip. However, this disclosure is not limited to this; it is also possible for the cache capacity of multiple processing units to be less than 128M.

[0065] In an exemplary embodiment of this disclosure, the configuration information of the consistency cache region includes the size of the consistency cache region, and may also include the location information of the consistency cache region, such as the starting position.

[0066] In an exemplary embodiment of this disclosure, the processing unit obtains configuration information of the consistency cache region through the cache consistency configuration interface, including: the processing unit receiving a cache region configuration instruction issued by the central control hardware unit of the system, parsing the cache region configuration instruction, and obtaining the configuration information of the consistency cache region; or, the processing unit obtains the configuration information of the consistency cache region according to the programming interface provided by the system software; wherein, in this embodiment, the size of the consistency cache region configured by different processing units among the multiple processing units may be the same or different.

[0067] In one example of this embodiment, the processing unit receives a cache region configuration instruction from the central control hardware unit, parses the instruction, and obtains the configuration information of the consistency cache region. When the system includes a server with multiple processing units, the central control hardware unit may be, for example, the server's Basic Input / Output System (BIOS), which initiates the configuration of the consistency cache region. In one case, the configuration information of the consistency cache region may include the size and location of the consistency cache region, and the processing unit can determine the address range of the consistency cache region based on this configuration information. In another case, the configuration information includes the size of the consistency cache region, and the processing unit, in conjunction with the default location of the locally stored consistency cache region or the location obtained through other means, determines the address range of the consistency cache region. In this document, a server with multiple processing units refers to an entity in the system capable of configuring and managing multiple processing units, such as, but not limited to, the server's BIOS hardware unit or server firmware.

[0068] In another example of this embodiment, the processing unit can obtain the configuration information of the coherent cache region based on the programming interface provided by the system software. The operating system manages all hardware resources of the computer device, and the processing unit can obtain the configuration information of the coherent cache region based on the application programming interface (API) provided by the operating system. For example, the CPU can provide a graphical interface to determine the size of the coherent cache region based on user input. For example, for the cache, two fields with configurable sizes are provided: Coherence and Non-Coherence. The size of the Coherence field set by the user is used as the size of the user-configured coherent cache region, and the size of the Non-Coherence field set by the user is used as the size of the user-configured non-coherent cache region. The graphical interface can also allow the user to configure the location of the coherent cache region. In this case, the configuration information of the coherent cache region obtained by the processing unit through the graphical interface includes the size and location of the coherent cache region. If the graphical interface only allows the user to configure the size of the coherent cache region, the location of the coherent cache region can be obtained using a pre-stored default location or other methods. The processing unit can determine the address range of the coherent cache region in the cache based on the size of the coherent cache region in the configuration information and its location.

[0069] In one example of this embodiment, there are different types of processing units in the system, such as GPUs and CPUs. The cache sizes of different processing units are not necessarily the same, and the sizes of the consistency cache regions configured for different processing units can also be the same or different.

[0070] In an exemplary embodiment of this disclosure, the system further includes an external device connected to the plurality of processing units via a bus, the external device being provided with a memory medium; the method further includes:

[0071] The external device receives and parses the shared memory configuration command to obtain the configuration information of the shared memory, and determines the address information of the shared memory based on the configuration information of the shared memory;

[0072] The external device configures a portion of its memory area as shared memory for multiple processing units based on the address range of the shared memory. In this document, this shared memory can also be referred to as a shared memory region, that is, a memory region accessible to the multiple processing units.

[0073] The aforementioned external device refers to a device located outside the processor chip, not a device outside the system. Although this embodiment uses a portion of the memory medium in the external device as shared memory, this disclosure is not limited to this. In other embodiments, a portion of the memory medium embedded in the processor chip can also be configured as shared memory. In this case, the processing unit can complete the configuration of the shared memory according to the shared memory configuration instruction; that is, the processing unit receives and parses the shared memory configuration instruction to obtain the configuration information of the shared memory, and determines the address information of the shared memory according to the configuration information of the shared memory; and the processing unit configures a portion of the memory region in this device as shared memory for multiple processing units according to the address range of the shared memory.

[0074] In one example, the shared memory configuration instruction carries configuration information including the size and location (e.g., starting location) of the shared memory. The external device can determine the address information of the shared memory based on the configuration information obtained by parsing the shared memory configuration instruction. In another example, the shared memory instruction carries configuration information including the size of the shared memory. The external device needs to parse the shared memory configuration instruction to obtain the size of the shared memory, and then combine it with the default location preset for the shared memory or the location of the shared memory obtained through other means to obtain the configuration information of the shared memory, and then determine the address information of the shared memory.

[0075] In an exemplary embodiment of this disclosure, the external device includes a CXL module that communicates with multiple processing units via a CXL interface. The CXL module includes a controller (such as a control chip or control chipset) and a set of memory chips connected to the controller. The shared memory configuration command is issued by the system's Fabric Manager to the CXL module via the CXL interface. The Fabric Manager (FM) refers to an entity used to configure and manage CXL devices. This embodiment adds a shared memory configuration function to the CXL interface, allowing shared memory configuration of the CXL module via shared memory configuration commands. The Fabric Manager can be integrated into a processing unit in the system or can be independent of any processing unit in the system, located in a different position from multiple processing units in the system, such as using an external processing unit.

[0076] In the examples shown in Figures 1 and 4, the CXL module includes three DRAM chips. When configuring shared memory, the control chip in the CXL module can configure one DRAM chip as shared memory for multiple processing units. The other memory areas, i.e., the other two DRAM chips, can be referred to as non-shared memory or non-shared memory regions. It's easy to understand that the diagrammatic division is merely illustrative; shared memory can be a portion of a single DRAM chip or a combination of regions from multiple DRAM chips. In a module composed of multiple DRAM chips, shared memory and non-shared memory are presented externally as address ranges (logical concepts).

[0077] Although this embodiment uses the CXL module as an example of an external device, in other embodiments, the external device may also be a memory chip, such as a DDR chip, that is connected to the processor chip via a memory interface.

[0078] In one exemplary embodiment of this disclosure, the Internet Manager further sends the shared memory configuration information to multiple processing units respectively. In another exemplary embodiment of this disclosure, the Internet Manager further sends the shared memory configuration information to a server of the multiple processing units, and the server then sends the shared memory configuration information to the multiple processing units respectively to complete the entire configuration process. In this case, the server can determine the configuration information of the consistency cache region in the multiple processing units based on the shared memory configuration information, and carry the configuration information of the multiple consistency cache regions in multiple cache region configuration instructions, which are then issued to the multiple processing units respectively through the system's central control hardware unit. The shared memory configuration information includes the size of the shared memory, and the consistency cache region configuration information includes the size of the consistency cache region. The server determines the size of the consistency cache region in each of the multiple processing units by combining the shared memory configuration information. For example, the configured consistency cache region size can be positively correlated with the shared memory size, thereby coordinating the sizes of shared memory and the consistency cache region to achieve better efficiency. (If the sizes of shared memory and the consistency cache region differ significantly, such as a large shared memory and a small consistency cache region, searching for data in shared memory will be too slow; conversely, if the shared memory is small and the consistency cache region is too large, it will waste resources.) After configuration, the server can issue cache region configuration instructions to each of the multiple processing units through a central control hardware unit. The central control hardware unit can be part of the server, or it can be independent of the server but capable of communicating with it.

[0079] In an exemplary embodiment of this disclosure, the method further includes: the processing unit establishing a first address mapping relationship between the shared memory and the consistency cache region based on the address range of the shared memory and the address range of the consistency cache region. In this embodiment, a consistency cache region can establish an address mapping relationship with one or more shared memories, and the first address mapping relationship between the shared memory and the consistency cache region can use methods such as direct associative mapping, group-associative mapping, or full associative mapping. After configuring the consistency cache region according to its address range, the processing unit, combined with the previously obtained address range of the shared memory, can establish the first address mapping relationship between the consistency cache region and the shared memory using any of the three mapping methods.

[0080] Figure 5 illustrates the address mapping relationship between the coherent cache region in a processor chip and the shared memory of the memory media in multiple CXL modules under a multiprocessor architecture.

[0081] The aforementioned first address mapping reflects the relationship between the storage location of data in shared memory and its cache location in the coherent cache region. Based on this, the processing unit can generate a physical or virtual address to access the data in the shared memory, thereby locating the data in the coherent cache region. The processor's Memory Management Unit (MMU) can participate in address management, such as generating addresses for accessing data in shared memory. These generated addresses can serve as input addresses for the cache. When the relative positions of the MMU and the cache differ, the input address can be a virtual address (with the cache located between the CPU and the MMU) or a physical address (with the MMU located between the cache and the CPU).

[0082] In one example of this embodiment, the processing unit can also establish a second address mapping relationship between other cache regions of the processing unit (excluding the consistent cache region) and other memory regions of the external device (excluding the shared memory) based on the address range of the shared memory and the address range of the consistent cache region. Referring to Figures 3 and 4, this second address mapping relationship establishes an address mapping relationship between the non-consistent cache regions in the cache and the non-shared memory in the CXL module. This address mapping relationship can be established using direct associative mapping, group-associative mapping, or full associative mapping. In another example of this embodiment, the processing unit only establishes an address mapping relationship between a portion of the non-consistent cache regions of the processing unit and a portion of the non-shared memory of the external device; that is, a portion of the memory regions in the external device do not need to be mapped to the cache.

[0083] In an exemplary embodiment of this disclosure, the consistency cache region is divided into multiple cache groups, each cache group including multiple cache lines; the address used by the processing unit when accessing data in the shared memory includes the following fields: Tagmeta, Tagdata, and Offset; or includes the following fields: Tagmeta, Indexmeta, Tagdata, and Offset;

[0084] in:

[0085] Tagmeta is a field used to identify the consistency cache region;

[0086] Indexmeta is a field used to identify the cache group in the consistent cache region;

[0087] Tagdata is a field used to identify cache rows in the cache group of the consistent cache region;

[0088] Offset is a field used to identify data offset.

[0089] Building upon the existing configuration interface that divides the cache into consistent and inconsistent cache regions, this embodiment further improves the data access address by adding a Tagmeta field to distinguish between consistent and inconsistent cache regions. For example, a 1-bit value can be used: Tagmeta = 0 indicates that the data to be accessed may be cached in the inconsistent cache region, while Tagmeta = 1 indicates that the data to be accessed may be cached in the consistent cache region. This eliminates the need for searching across the entire cache range, improving location efficiency. Furthermore, the Indexmeta field can be set to target the search range to cache groups within the consistent cache region, further enhancing location efficiency. Improved cache line location efficiency reduces latency when accessing data in shared memory, which helps avoid bus congestion.

[0090] Although the fields included in the address in this embodiment are not limited to Tagmeta, Tagdata, and Offset, or even include Tagmeta, Indexmeta, Tagdata, and Offset, other fields may also be included. For example, if the address includes the fields Tagmeta, Indexmeta, Tagdata, and Offset, it may also include a field Indexdata for locating a cache subgroup within the cache group identified by Indexmeta.

[0091] In an exemplary embodiment of this disclosure, the system is configured with multiple shared memories, each belonging to a memory medium with different characteristics. The coherence cache region is divided into multiple cache groups, each corresponding one-to-one with one of the shared memories. The characteristics of the memory medium include any one or more of latency and bandwidth. Dividing the cache groups in the coherence cache region according to the characteristics of the shared memory's memory medium allows for a unified standard, facilitating interconnection between devices from different manufacturers. In this embodiment, the Indexmeta can define sharing among several CXL DRAMs, grouping the CXL DRAMs in the system and thus dividing them into different cache groups based on the latency, bandwidth, and other characteristics of the external memory medium. For example, some cache groups can be mapped to slower memory media (e.g., CXL-based shared SSDs), while others can be mapped to faster memory media (e.g., CXL-based DRAMs). CXL modules within the same cache group have the same access latency and corresponding Indexmeta, facilitating the use of the same cacheline access strategy by the processing units.

[0092] In an exemplary embodiment of this disclosure, the method further includes: when the processing unit searches for data in the shared cache region in the cache, it determines a cache group in the consistent cache region based on Tagmeta and Indexmeta in the address, and then searches for a cache line containing the data in the determined cache group based on Tagdata in the address.

[0093] In one example of the embodiment, Tagmeta has multiple values, one of which indicates that the data cache area is the consistent cache area; Indexmeta represents the index of the cache group in the consistent cache area;

[0094] The processing unit first determines the cache group in the consistent cache region based on the Tagmeta and Indexmeta in the address, and then searches for the cache line containing the data in the determined cache group based on the Tagdata in the address, including:

[0095] The metadata table of the consistent cache region is searched based on the value of Tagmeta in the address. Each record in the metadata table includes the following fields: Tagmeta and cache group offset; wherein, the value of Tagmeta indicates that the cache region of the data is the consistent cache region, and the value of cache group offset indicates the position offset of the cache group in the record in the consistent cache region.

[0096] The corresponding record in the metadata table is found based on the value of Indexmeta in the address, and the search range in the consistent cache area is determined based on the cache group offset in the corresponding record; and the corresponding cache line is searched in the search range based on the value of Tagdata in the address to determine whether a cache hit occurs.

[0097] In one example of this embodiment, the size of the cache group in the consistent cache region can be fixed. In another example, the size of the cache group in the consistent cache region can vary, such as being calculated based on the size of its corresponding shared memory using a preset algorithm. The size of the cache group can be represented by the data of the cache lines included in the cache group, but is not limited to this. When the size of the cache group can vary, a "cache group size" field can be added to the metadata table to record it, or it can be calculated based on other metadata (such as the corresponding shared memory size), or determined based on the cache group offset in the next record. Other fields can also be set in the metadata table of the consistent cache region, such as a replacement flag to indicate the replacement mechanism of cache lines in the cache group.

[0098] The metadata table for the aforementioned consistent cache region can be created during the setup of the cache consistency region, and the values ​​of fields such as cache group offset in the records can be generated during the configuration process.

[0099] As shown in the example in Figure 6, the address generated by the processor (CPU or GPU) (taking the physical address as an example) includes four fields: region flag (Tagmeta), cache group flag (Indexmeta), tag (Tagdata), and offset (Offset). In the metadata table of the consistent cache region, each record corresponds to a cache group within the consistent cache region and includes the following fields: region flag (Tagmeta), replacement flag (Ctrl flag), and cache line area offset (Cacheline Area Offset). When accessing data in shared memory, the value of Tagmeta in the input address of the cache access is the same as the value of Tagmeta in the metadata table. Since Indexmeta can be considered an index of the record in the metadata table of the consistent cache region, a record in the metadata table can be located based on the values ​​of Tagmeta and Indexmeta in the address. Searching for the Ctrl flag and Cacheline Area Offset fields of this record determines the cache group replacement mechanism and finds the corresponding cache group's offset within the consistent cache region. Each cache line in the consistent cache region includes a Tagdata field and the cached data. Within the scope of this cache group, it is searched to see if the value of Tagdata in the cache line is equal to the value of Tagdata at the address. If found, it means a cache hit, and the required data can be retrieved based on the Offset value at the address. If not found, it means a cache miss, and the corresponding data can be read by accessing the shared memory based on the address.

[0100] The aforementioned metadata tables and other information related to cache consistency maintenance can be maintained using a designated processor in the system, such as the main processor. This main processor can manage and control the consistency cache regions of all processing units in the system, or the consistency cache regions of all processing units in the system and the system's shared memory, including controlling the ownership of cache lines.

[0101] This embodiment improves cacheline location efficiency by adding a Meta region to the Coherence Area to describe the location information of the corresponding cacheline. Based on the physical address generated by the processor, relevant metadata fields, such as TagMeta and IndexMeta, are defined. By introducing Meta-related fields, cachelines in the coherence cache area can be further grouped (e.g., according to external memory characteristics), reducing the number of cachelines within a group and decreasing the number of comparisons within the group when searching for a specific cacheline. Existing solutions compare the tag value with all cachelines within a specific group (identified by an index), which is suitable when the cache space is small; however, it is inefficient when the cache space is large. This embodiment improves the efficiency of cacheline location.

[0102] The size of the CPU's internal cache typically depends on the CPU manufacturer's implementation. The CPU only provides static information about the cache, without offering an interface for modification or configuration. To address this, the embodiments described above propose configuration interfaces for setting coherent cache regions and shared memory. These interfaces allow configuration of the CPU's internal cache and shared memory, setting the size of the coherent cache region and the shared memory. This solves the problem of high bus load caused by coherence maintenance between multiple processors or cores when the processor chip's internal cache space is too large, and also improves cache line location efficiency.

[0103] An embodiment of this disclosure also provides a processing system, referring to Figures 1 and 5. The processing system includes a bus and multiple processing units connected via the bus. Each processing unit is equipped with a cache and has a cache consistency configuration interface. The processing unit is configured to:

[0104] The configuration information of the consistent cache region is obtained through the configuration interface of the cache consistency, and the address range of the consistent cache region is determined based on the configuration information of the consistent cache region.

[0105] Based on the address range of the consistency cache region, a portion of the cache of this processing unit is configured as a consistency cache region to cache data in the shared memory of multiple processing units using the consistency cache region.

[0106] In an exemplary embodiment of this disclosure, the processing unit is a processor or a processor core; the cache capacity of at least one of the processing units is greater than or equal to 128M, or greater than or equal to 256M; the configuration information of the consistency cache region includes the size of the consistency cache region.

[0107] In one exemplary embodiment of this disclosure,

[0108] The processing system further includes: a central control hardware unit, configured to issue a cache region configuration instruction to the processing unit, carrying the configuration information of the consistent cache region;

[0109] The processing unit obtains the configuration information of the consistent cache region through the cache consistency configuration interface, including: receiving the cache region configuration instruction issued by the central control hardware unit, parsing the cache region configuration instruction, and obtaining the configuration information of the consistent cache region;

[0110] The size of the consistency cache area configured for different processing units may be the same or different.

[0111] In an exemplary embodiment of this disclosure, the processing unit obtains configuration information of the consistency cache region through the cache consistency configuration interface, including: the processing unit obtains the configuration information of the consistency cache region based on the programming interface provided by the system software.

[0112] In one exemplary embodiment of this disclosure,

[0113] The system also includes an external device connected to the plurality of processing units via a bus, the external device being provided with a memory medium;

[0114] The external device is configured as follows:

[0115] Receive and parse the shared memory configuration instruction to obtain the configuration information of the shared memory, and determine the address information of the shared memory based on the configuration information of the shared memory;

[0116] Based on the address range of the shared memory, a portion of the memory region in this device is configured as shared memory for multiple processing units.

[0117] In an exemplary embodiment of this disclosure, the external device includes a CXL module that communicates with a plurality of the processing units via a CXL interface. The CXL module includes a controller and a set of memory chips connected to the controller. The processing system further includes an Internetwork Manager configured to issue the shared memory configuration command to the CXL module via the CXL interface.

[0118] In an exemplary embodiment of this disclosure, the Internet Manager is further configured to send the configuration information of the shared memory to a plurality of the processing units respectively; wherein the configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistency cache region includes the size of the consistency cache region.

[0119] In one exemplary embodiment of this disclosure,

[0120] The processing system also includes servers and a central control hardware unit for multiple processing units;

[0121] The network manager is also configured to send the configuration information of the shared memory to the server;

[0122] The server is configured to send the configuration information of the shared memory to multiple processing units respectively; and to determine the configuration information of the consistency cache region in the multiple processing units based on the configuration information of the shared memory, and to carry the configuration information of the multiple consistency cache regions in multiple cache region configuration instructions respectively, and to send them to the multiple processing units respectively through the central control hardware unit.

[0123] The configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistency cache region includes the size of the consistency cache region.

[0124] The aforementioned network manager, server, and central control hardware unit can be physically integrated together or set up separately.

[0125] In an exemplary embodiment of this disclosure, the processing unit is further configured to: establish a first address mapping relationship between the shared memory and the consistency cache region based on the address range of the shared memory and the address range of the consistency cache region.

[0126] In one exemplary embodiment of this disclosure, the consistency cache region is divided into multiple cache groups, and each cache group includes multiple cache lines;

[0127] The address used by the processing unit when accessing data in the shared memory includes the following fields: Tagmeta, Tagdata, and Offset; or includes the following fields: Tagmeta, Indexmeta, Tagdata, and Offset; wherein:

[0128] Tagmeta is a field used to identify the consistency cache region;

[0129] Indexmeta is a field used to identify the cache group in the consistent cache region;

[0130] Tagdata is a field used to identify cache rows in the cache group of the consistent cache region;

[0131] Offset is a field used to identify data offset.

[0132] In an exemplary embodiment of this disclosure, the system is configured with multiple shared memories, and the memory media to which the different shared memories belong have different characteristics; the multiple cache groups divided by the consistency cache region correspond one-to-one with the multiple shared memories; wherein, the characteristics of the memory media include any one or more of latency and bandwidth.

[0133] In an exemplary embodiment of this disclosure, the method further includes: when the processing unit searches for data in the shared cache region in the cache, it first determines the cache group in the consistent cache region based on Tagmeta and Indexmeta in the address, and then searches for the cache line containing the data in the determined cache group based on Tagdata in the address.

[0134] In one exemplary embodiment of this disclosure,

[0135] Tagmeta has multiple values, one of which indicates that the data cache area is the consistent cache area; Indexmeta represents the index of the cache group in the consistent cache area;

[0136] The processing unit determines the cache group in the consistent cache region based on the Tagmeta and Indexmeta in the address, and then searches for the cache line containing the data in the determined cache group based on the Tagdata in the address, including:

[0137] The metadata table of the consistent cache region is searched based on the value of Tagmeta in the address. Each record in the metadata table includes the following fields: Tagmeta and cache group offset; wherein, the value of Tagmeta indicates that the cache region of the data is the consistent cache region, and the value of cache group offset indicates the position offset of the cache group in the record in the consistent cache region.

[0138] The corresponding record in the metadata table is found based on the value of Indexmeta in the address, and the search range in the consistent cache area is determined based on the cache group offset in the corresponding record; and the corresponding cache line is searched in the search range based on the value of Tagdata in the address to determine whether a cache hit occurs.

[0139] An embodiment of this disclosure also provides a processor chip, including a processor and a cache, as shown in FIG1, wherein the processor is configured to perform a method for reducing bus load as described in any embodiment of this disclosure.

[0140] An embodiment of this disclosure also provides a non-transient computer storage medium storing a computer program, which, when executed by a processor, can implement the bus load reduction method or shared memory configuration method described in any embodiment of this disclosure.

[0141] An embodiment of this disclosure also provides a CXL module, as shown in FIG1. ​​The CXL module includes a CXL controller (in the example of a control chip in the figure) and a memory medium (in the example of a DRAM chip in the figure) connected to the CXL controller. The CXL controller is configured to perform the following processes:

[0142] The system receives and parses shared memory configuration instructions to obtain shared memory configuration information; wherein, the shared memory is a memory region shared by multiple processing units connected to the CXL module.

[0143] The address range of the shared memory is determined based on the configuration information of the shared memory;

[0144] Based on the address range of the shared memory, a portion of the memory region in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

[0145] In an exemplary embodiment of this disclosure, the controller receiving a shared memory configuration instruction includes: the controller receiving a shared memory configuration instruction issued by the Internet Manager in the system through a shared memory configuration interface. The Internet Manager refers to an entity in the system including the CXL device that can be used to configure and manage the CXL device.

[0146] This disclosure also provides a shared memory configuration method in an embodiment, applied to a CXL module, the CXL module including a CXL controller and a memory medium connected to the CXL controller, the method including:

[0147] Step 210: Receive and parse the shared memory configuration instruction to obtain the configuration information of the shared memory; wherein, the shared memory is a memory area shared by multiple processing units connected to the CXL module;

[0148] Step 220: Determine the address range of the shared memory based on the configuration information of the shared memory;

[0149] Step 230: Based on the address range of the shared memory, configure a portion of the memory region in the memory medium as the shared memory, and only maintain cache consistency for the data in the shared memory.

[0150] In this embodiment, when a host sends a memory read / write request, it can use the metadata table of the device's shared memory. If the request sent by the host contains an address within the shared memory address range, consistency maintenance is performed; otherwise, if the address falls within the non-shared memory address range, consistency maintenance is not required. Shared memory consistency maintenance can be implemented in two ways: First, through device-side hardware maintenance (HDM-DB), multiple hosts first request cacheline ownership and then begin access; second, the device exposes content in an HDM-H manner, maintained by the host, such as the central processing unit handling cacheline ownership among multiple hosts.

[0151] The embodiments disclosed herein extend the CXL protocol by adding an interface for shared memory configuration. The CXL module parses the shared memory configuration information according to the shared memory configuration instructions defined by this interface; then, based on the shared memory configuration information, it determines the address range of the shared memory, thereby configuring a portion of the memory region in the memory medium as the shared memory, and only maintaining cache consistency for the data in the shared memory. That is, the size of the shared memory in the CXL module can be limited by configuration, and the CXL module only maintains cache consistency for the data in the shared memory. By limiting the size of the shared memory in the CXL module to a set range through configuration, the embodiments of this disclosure can prevent excessively frequent cache consistency maintenance operations from causing excessive bus load.

[0152] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A CXL module, the CXL module comprising a CXL controller and a memory medium connected to the CXL controller, the CXL controller being configured to perform the following processes: It receives and parses shared memory configuration commands to obtain shared memory configuration information; among which, The shared memory is a memory region shared by multiple processing units connected to the CXL module; The address range of the shared memory is determined based on the configuration information of the shared memory; Based on the address range of the shared memory, a portion of the memory region in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

2. The CXL module as described in claim 1, wherein: The controller receiving shared memory configuration instructions includes: the controller receiving shared memory configuration instructions issued by the Internet Manager in the system through the shared memory configuration interface.

3. A shared memory configuration method applied to a CXL module, the CXL module including a CXL controller and a memory medium connected to the CXL controller, the method comprising: The system receives and parses shared memory configuration instructions to obtain shared memory configuration information; wherein, the shared memory is a memory region shared by multiple processing units connected to the CXL module. The address range of the shared memory is determined based on the configuration information of the shared memory; Based on the address range of the shared memory, a portion of the memory region in the memory medium is configured as the shared memory, and cache consistency maintenance is performed only on the data in the shared memory.

4. A processing system, comprising a bus and a plurality of processing units, wherein the plurality of processing units are connected via the bus, each processing unit is provided with a cache and has a configuration interface for cache consistency, and the processing unit is configured to: The configuration information of the consistent cache region is obtained through the configuration interface of the cache consistency, and the address range of the consistent cache region is determined based on the configuration information of the consistent cache region. Based on the address range of the consistency cache region, a portion of the cache of this processing unit is configured as a consistency cache region to cache data in the shared memory of multiple processing units using the consistency cache region.

5. The processing system as described in claim 4, wherein: The processing unit is a processor or a processor core; the cache capacity of at least one of the processing units is greater than or equal to 128M, or greater than or equal to 256M; the configuration information of the consistency cache region includes the size of the consistency cache region.

6. The processing system as claimed in claim 4, wherein: The processing system further includes: a central control hardware unit, configured to issue a cache region configuration instruction to the processing unit, carrying the configuration information of the consistent cache region; The processing unit obtains the configuration information of the consistent cache region through the cache consistency configuration interface, including: receiving the cache region configuration instruction issued by the central control hardware unit, parsing the cache region configuration instruction, and obtaining the configuration information of the consistent cache region; The size of the consistency cache area configured for different processing units may be the same or different.

7. The processing system of claim 4, wherein: The processing unit obtains the configuration information of the consistency cache region through the configuration interface of the cache consistency, including: the processing unit obtains the configuration information of the consistency cache region based on the programming interface provided by the system software.

8. The processing system as claimed in claim 4, wherein: The system also includes an external device connected to the plurality of processing units via a bus, the external device being provided with a memory medium; The external device is configured as follows: Receive and parse the shared memory configuration instruction to obtain the configuration information of the shared memory, and determine the address information of the shared memory based on the configuration information of the shared memory; Based on the address range of the shared memory, a portion of the memory region in this device is configured as shared memory for multiple processing units.

9. The processing system of claim 8, wherein: The external device includes a CXL module that communicates with multiple processing units via a CXL interface. The CXL module includes a controller and a set of memory chips connected to the controller. The processing system further includes an Internet Manager configured to send the shared memory configuration command to the CXL module via the CXL interface.

10. The processing system of claim 9, wherein: The network manager is further configured to send the configuration information of the shared memory to multiple processing units respectively; wherein the configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistency cache region includes the size of the consistency cache region.

11. The processing system of claim 9, wherein: The processing system also includes servers and a central control hardware unit for multiple processing units; The network manager is also configured to send the configuration information of the shared memory to the server; The server is configured to send the configuration information of the shared memory to multiple processing units respectively; and to determine the configuration information of the consistency cache region in the multiple processing units based on the configuration information of the shared memory, and to carry the configuration information of the multiple consistency cache regions in multiple cache region configuration instructions respectively, and to send them to the multiple processing units respectively through the central control hardware unit. The configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistency cache region includes the size of the consistency cache region.

12. The processing system of claim 8, wherein: The processing unit is further configured to: establish a first address mapping relationship between the shared memory and the consistency cache region based on the address range of the shared memory and the address range of the consistency cache region.

13. The processing system of claim 4, wherein: The consistency cache region is divided into multiple cache groups, and each cache group includes multiple cache lines; The address used by the processing unit when accessing data in the shared memory includes the following fields: Tagmeta, Tagdata, and Offset; or Includes the following fields: Tagmeta, Indexmeta, Tagdata, and Offset; where: Tagmeta is a field used to identify the consistency cache region; Indexmeta is a field used to identify the cache group in the consistent cache region; Tagdata is a field used to identify cache rows in the cache group of the consistent cache region; Offset is a field used to identify data offset.

14. The processing system of claim 13, wherein: The system is configured with multiple types of shared memory, and the memory media of different shared memory have different characteristics; The various cache groups divided by the consistency cache region correspond one-to-one with the various shared memory types; wherein, the characteristics of the memory medium include any one or more of latency and bandwidth.

15. A method for reducing bus load, applied to a system comprising multiple processing units connected via a bus, wherein each processing unit is provided with a cache and has a configuration interface for cache consistency, the method comprising: The processing unit obtains the configuration information of the consistency cache region through the configuration interface of the cache consistency, and determines the address range of the consistency cache region based on the configuration information of the consistency cache region; The processing unit configures a portion of its cache as a consistency cache region based on the address range of the consistency cache region, so as to use the consistency cache region to cache data in the shared memory of multiple processing units.

16. The method of claim 15, wherein: The processing unit is a processor or a processor core; The configuration information of the consistency cache region includes the size of the consistency cache region; the cache capacity of at least one of the processing units is greater than or equal to 128M, or greater than or equal to 256M.

17. The method of claim 15, wherein: The processing unit obtains the configuration information of the consistent cache region through the cache consistency configuration interface, including: the processing unit receives a cache region configuration instruction issued by the central control hardware unit of the system, parses the cache region configuration instruction, and obtains the configuration information of the consistent cache region; or, the processing unit obtains the configuration information of the consistent cache region based on the programming interface provided by the system software. The size of the consistency cache area configured for different processing units may be the same or different.

18. The method of claim 15, wherein: The system further includes an external device connected to the plurality of processing units via a bus, the external device being provided with a memory medium; the method further includes: The external device receives and parses the shared memory configuration command to obtain the configuration information of the shared memory, and determines the address information of the shared memory based on the configuration information of the shared memory; The external device configures a portion of the memory region in this device as shared memory for multiple processing units based on the address range of the shared memory.

19. The method of claim 18, wherein: The external device includes a CXL module that communicates with multiple processing units via a CXL interface. The CXL module includes a controller and a set of memory chips connected to the controller. The shared memory configuration command is sent from the system's Internet Manager to the CXL module via the CXL interface.

20. The method of claim 19, wherein: The network manager also sends the configuration information of the shared memory to multiple processing units respectively; or, The Internet Manager also sends the configuration information of the shared memory to the servers of the multiple processing units, and the servers send the configuration information of the shared memory to the multiple processing units respectively; Furthermore, the server also determines the configuration of the consistent cache region among the multiple processing units based on the configuration information of the shared memory. The information carries the configuration information of the multiple consistent cache regions in multiple cache region configuration instructions, and sends them to the multiple processing units through the central control hardware unit of the system. The configuration information of the shared memory includes the size of the shared memory, and the configuration information of the consistency cache region includes the size of the consistency cache region.

21. The method of claim 18, wherein: The method further includes: the processing unit establishing a first address mapping relationship between the shared memory and the consistency cache region based on the address range of the shared memory and the address range of the consistency cache region.

22. The method of claim 15, wherein: The consistency cache region is divided into multiple cache groups, and each cache group includes multiple cache lines; the address used by the processing unit to access data in the shared memory includes the following fields: Tagmeta, Tagdata, and Offset; or Includes the following fields: Tagmeta, Indexmeta, Tagdata, and Offset; where: Tagmeta is a field used to identify the consistency cache region; Indexmeta is a field used to identify the cache group in the consistent cache region; Tagdata is a field used to identify cache rows in the cache group of the consistent cache region; Offset is a field used to identify data offset.

23. The method of claim 22, wherein: The system is configured with multiple types of shared memory, and the memory media to which the different shared memory belong have different characteristics; the multiple cache groups divided by the consistency cache region correspond one-to-one with the multiple types of shared memory; wherein, the characteristics of the memory media include any one or more of latency and bandwidth.

24. The method of claim 22, wherein: The method further includes: when the processing unit searches for data in the shared cache region in the cache, it first determines the cache group in the consistent cache region based on the Tagmeta and Indexmeta in the address, and then searches for the cache line containing the data in the determined cache group based on the Tagdata in the address.

25. The method of claim 24, wherein: Tagmeta has multiple values, one of which indicates that the data cache area is the consistent cache area; Indexmeta represents the index of the cache group in the consistent cache area; The processing unit determines the cache group in the consistent cache region based on the Tagmeta and Indexmeta in the address, and then searches for the cache line containing the data in the determined cache group based on the Tagdata in the address, including: The metadata table of the consistent cache region is searched based on the value of Tagmeta in the address. Each record in the metadata table includes the following fields: Tagmeta and cache group offset; wherein, the value of Tagmeta indicates that the cache region of the data is the consistent cache region, and the value of cache group offset indicates the position offset of the cache group in the record in the consistent cache region. The corresponding record in the metadata table is found based on the value of Indexmeta in the address, and the search range in the consistent cache area is determined based on the cache group offset in the corresponding record; and the corresponding cache line is searched in the search range based on the value of Tagdata in the address to determine whether a cache hit occurs.

26. A processor chip including a processor core and a cache, the processor core being configured to perform the method as claimed in any one of claims 15 to 17, 21 to 25.

27. A non-transient computer storage medium storing a computer program, which, when executed by a processor, can implement the method as described in any one of claims 15 to 25.

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